Display panel and display device comprising the same

Abstract

A display panel and a display device including the same are disclosed. The display panel includes a display area in which a plurality of sub-pixels are arranged, each sub-pixel including a pixel circuit connected to a light emitting element; a non-display area in which a plurality of dummy pixels are arranged, each dummy pixel including a dummy pixel circuit; at least one repair line extending across the display area and the non-display area; and a first compensation capacitor connected between the repair line and an anode electrode of the light emitting element.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0174501, filed on November 29, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to display panels and display devices including such display panels. Background Technology

[0004] Electroluminescent display devices include self-emissive elements, such as organic light-emitting diodes (OLEDs), arranged in individual sub-pixels, and possess advantages such as fast response speed, high luminous efficiency, high brightness, and wide viewing angle. Electroluminescent display devices not only have fast response speed and excellent luminous efficiency, brightness, and viewing angle, but can also represent black gradients as full black, thus exhibiting excellent contrast and color reproduction. Such electroluminescent display devices do not require a backlight unit and can be implemented on flexible materials such as plastic substrates, thin glass substrates, and metal substrates.

[0005] Depending on the pixel structure of the electroluminescent display device, the brightness of the pixels can vary. For example, when the pixel brightness is low, the brightness may change sensitively with temperature. Summary of the Invention

[0006] The purpose of this disclosure is to address the aforementioned necessity and / or issues.

[0007] This disclosure provides a display panel capable of improving image quality and a display device including the display panel.

[0008] The purpose of this disclosure is not limited to the foregoing, and other purposes not expressly mentioned will be clearly understood by those skilled in the art from the following description.

[0009] A display panel according to one embodiment includes: a display area having a plurality of sub-pixels arranged therein, each sub-pixel including a pixel circuit connected to a light-emitting element; a non-display area having a plurality of virtual pixels arranged therein, each virtual pixel including a virtual pixel circuit; at least one repair line extending across the display area and the non-display area; and a first compensation capacitor connected between the repair line and the anode electrode of the light-emitting element.

[0010] The pixel circuitry arranged in the display area may include internal compensation circuitry based on diode connections or internal compensation circuitry based on source followers.

[0011] The pixel circuitry for each sub-pixel arranged in the display area may include: a driving transistor comprising a first electrode connected to a first node of the sub-pixel, a gate electrode connected to a second node of the sub-pixel, and a second electrode connected to a third node of the sub-pixel; a first switching transistor connected between a constant voltage node to which a reference voltage is applied and the second node of the sub-pixel, and turned on in response to a second scan signal; a second switching transistor connected between a constant voltage node to which an anode reset voltage is applied and a fourth node of the sub-pixel, and turned on in response to a third scan signal; a third switching transistor connected between a data line to which a data voltage is applied and the second node of the sub-pixel, and turned on in response to a first scan signal; a fourth switching transistor connected between a constant voltage node to which a pixel driving voltage is applied and the first node of the sub-pixel, and turned on in response to a first light emission signal; and a fifth switching transistor connected between the third node and the fourth node of the sub-pixel, and turned on in response to a second light emission signal.

[0012] The pixel circuit of each sub-pixel arranged in the display area may further include: a first capacitor connected between a second node and a third node of the sub-pixel; and a second capacitor connected between a constant voltage node to which a pixel driving voltage is applied and the third node of the sub-pixel. The anode electrode of the light-emitting element may be connected to a fourth node of the sub-pixel, and the cathode electrode of the light-emitting element may be connected to a constant voltage node to which a pixel ground voltage is applied.

[0013] The virtual pixel circuit may include: a driving transistor for the virtual pixel, the driving transistor including a first electrode connected to a first node of the virtual pixel to which a pixel driving voltage is applied, a gate electrode connected to a second node of the virtual pixel, and a second electrode connected to a third node of the virtual pixel; a first switching transistor for the virtual pixel connected between a constant voltage node to which a reference voltage is applied and the second node of the virtual pixel, and turned on in response to a second scan signal; a second switching transistor for the virtual pixel connected between a constant voltage node to which an anode reset voltage is applied and a fourth node of the virtual pixel, and turned on in response to a third scan signal; a third switching transistor for the virtual pixel connected between a virtual data line and the second node of the virtual pixel, and turned on in response to a first scan signal; and a fourth switching transistor for the virtual pixel connected between the third node and the fourth node of the virtual pixel, and turned on in response to a second light emission signal.

[0014] The virtual pixel circuit may further include: a first capacitor for the virtual pixel connected between a second node and a third node of the virtual pixel; and a second capacitor for the virtual pixel connected between the first node and the third node of the virtual pixel.

[0015] The virtual pixel may also include: a light-emitting element of the virtual pixel, which is connected between the fourth node of the virtual pixel and a constant voltage node to which a pixel ground voltage is applied.

[0016] The virtual pixel circuit may further include a second compensation capacitor connected between the gate line to which the first light-emitting signal is applied and the fourth node of the virtual pixel. Optionally, the capacitance of the second compensation capacitor may be 10% to 100% of the capacitance of the first capacitor.

[0017] The repair line can be connected to the fourth node of the virtual pixel. The first compensation capacitor can be connected between the repair line and the fourth node of the sub-pixel.

[0018] The maximum voltage that can be applied to the virtual data line is the data voltage.

[0019] The display area may include a second sub-pixel. The pixel circuitry of the second sub-pixel may be electrically disconnected from the anode electrode of the light-emitting element disposed in the second sub-pixel. The anode electrode of the light-emitting element disposed in the second sub-pixel may be connected to a repair line.

[0020] One of the following can be applied to the virtual data line: the maximum data voltage, the data voltage to be applied to the second sub-pixel, and the preset voltage.

[0021] A display device according to one embodiment includes: a display panel, the display panel including: a display area having a plurality of sub-pixels arranged therein, each sub-pixel including a pixel circuit connected to a light-emitting element; a non-display area having a plurality of virtual pixels arranged therein, each virtual pixel including a virtual pixel circuit; at least one repair line extending across the display area and the non-display area; a first compensation capacitor connected between the repair line and the anode electrode of the light-emitting element; and a display panel driving circuit configured to drive the sub-pixels and the virtual pixels.

[0022] The display panel may also include: multiple data lines connected to sub-pixels, virtual data lines connected to virtual pixels, multiple gate lines intersecting the data lines and virtual data lines, and multiple power lines connected to the sub-pixels and virtual pixels. Sub-pixels and virtual pixels may share the gate lines and power lines.

[0023] The display panel driving circuit may include: a gate driving circuit disposed in a non-display area of ​​the display panel and configured to supply gate signals to gate lines; and a data driving circuit configured to supply data voltages to data lines and dummy data lines.

[0024] This disclosure reduces power consumption without degrading image quality and improves the temperature-sensitive emission (TLS) characteristics of pixels by using virtual pixels to rapidly charge the anode electrode of the light-emitting element. Therefore, this disclosure can enhance image quality.

[0025] This disclosure can optimize processing and increase the yield of display panels by using virtual pixels to enable defective subpixels to be driven normally.

[0026] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand other effects not explicitly mentioned in the claims. Attached Figure Description

[0027] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the exemplary embodiments described in detail with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a block diagram illustrating a display device according to one embodiment of the present disclosure;

[0029] Figure 2 This is a diagram showing an example of a repair line;

[0030] Figure 3A and Figure 3B This is a diagram used to illustrate a comparison of TLS features between embodiments of the present disclosure and comparative examples;

[0031] Figure 4 This is a circuit diagram showing a pixel circuit in a display area according to one embodiment of the present disclosure;

[0032] Figure 5 This is a circuit diagram illustrating pixel circuitry in a display area according to another embodiment of the present disclosure;

[0033] Figure 6 This is a circuit diagram illustrating a pixel circuit of a virtual pixel according to one embodiment of the present disclosure;

[0034] Figure 7 This is a circuit diagram illustrating a pixel circuit of a virtual pixel according to another embodiment of the present disclosure;

[0035] Figure 8It is shown Figure 6 The pixel circuit shown is electrically connected via a repair line and a capacitor. Figure 4 The circuit diagram of an example pixel circuit is shown;

[0036] Figure 9 It is shown Figure 7 The pixel circuit shown is electrically connected via a repair line and a capacitor. Figure 4 The circuit diagram of an example pixel circuit is shown;

[0037] Figure 10 It is shown Figure 7 The pixel circuit shown is electrically connected via a repair line and a capacitor. Figure 5 The circuit diagram of an example pixel circuit is shown;

[0038] Figure 11 It shows that it is applied to Figure 8 The waveforms of the gate signal and the voltage of the main nodes of the pixel circuit are shown.

[0039] Figure 12 It shows that it is applied to Figure 9 The waveforms of the gate signal and the voltage of the main nodes of the pixel circuit are shown.

[0040] Figure 13 It shows the combination Figure 8 The illustrated pixel circuit diagram shows an example circuit where a defective sub-pixel is connected to a virtual pixel via a repair line; and

[0041] Figure 14 It shows the combination Figure 9 The illustrated pixel circuit diagram shows an example of a circuit that connects a defective sub-pixel to a virtual pixel via a repair line. Detailed Implementation

[0042] The advantages and features of this disclosure, as well as the methods for implementing it, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and allow those skilled in the art to fully understand its scope.

[0043] The shapes, sizes, proportions, angles, and numbers shown in the accompanying drawings to illustrate embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, similar reference numerals generally denote similar elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0044] Terms such as “including,” “comprising,” “having,” and “consisting of” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0045] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0046] When describing the location or interconnection between two components, such as “on top of”, “above”, “below”, “near”, “connected to or coupled to”, “cross”, “intersect”, etc., unless “immediately adjacent” or “directly” is used, one or more other components may be inserted between them.

[0047] When describing time precedence relationships, such as "after", "following", "immediately following", "before", etc., it may not be sequential on a time basis unless "immediately" or "directly" is used.

[0048] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or name preceding the component.

[0049] The following implementations can be combined or integrated with each other in part or in whole, and can be linked and operated in various technical ways. The implementations can be performed independently or in conjunction with each other.

[0050] The pixel circuit and gate drive circuit of the display device may include multiple transistors. The transistors may be implemented as thin-film transistors (TFTs). The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon TFTs (LTPS TFTs) including low-temperature polycrystalline silicon, etc.

[0051] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide-semiconductor), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0052] The gate signal oscillates between the gate on-voltage and the gate off-voltage. The transistor turns on in response to the gate on-voltage and turns off in response to the gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be the gate high voltage VGH, and the gate off-voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate on-voltage can be the gate low voltage VGL, and the gate off-voltage can be the gate high voltage VGH.

[0053] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0055] Reference Figure 1 According to one embodiment of the present disclosure, a display device includes a display panel 100, a display panel driving circuit (including a data driver 110 and a gate driver 120) for writing image data to pixels P of the display panel 100, and a power circuit 140 for generating power required to drive the pixels P and the display panel driving circuit.

[0056] The display panel 100 may be, but is not limited to, a rectangular panel having a width in the X-axis direction (first direction), a length in the Y-axis direction (second direction), and a thickness in the Z-axis direction (third direction). For example, at least a portion of the display panel 100 may have a curved periphery. The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. Transmissive display panels can be applied to transparent display devices in which an image is displayed on a screen and the actual object in the background is visible. The display panel 100 may be implemented as a flexible display panel.

[0057] Panel 100 may include a display area AA and a non-display area NA outside the display area AA. The display area AA of the display panel 100 may include a pixel array for displaying images thereon. The pixel array may include multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels P arranged in a matrix. The non-display area NA may also include virtual pixels 160 and virtual data lines 104 connecting the virtual channels of the data driver 110 to the virtual pixels 160. Gate lines 103 intersect with virtual data lines 104. The display panel 100 may also include multiple power lines that are commonly connected to the pixel circuitry of pixel P and the pixel circuitry of virtual pixels 160. Each of the power lines includes a constant voltage node connected to the pixel circuitry.

[0058] A pixel P may include two or more sub-pixels for color implementation. For example, each of pixel P may be divided into red, green, and blue sub-pixels. Each of pixel P may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element.

[0059] Each subpixel of pixel P can be connected to data line 102, gate line 103, and power line. Virtual pixel 160 can be connected to virtual data line 104, gate line 103, and power line.

[0060] The pixel array of the display area AA may include multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln may include a row of pixels P arranged along the X-axis direction in the pixel array of the display panel 100. Pixels P arranged in a pixel line may share gate line 103. Pixels arranged along the column direction (Y-axis direction) along the data line direction may share data line 102. A horizontal time period is the time obtained by dividing a frame time period by the total number of pixel lines L1 to Ln.

[0061] A virtual pixel 160 can be disposed between pixel P in the display area AA of the display panel 100 and gate driver 120 in the non-display area NA. The virtual pixel 160 may include multiple virtual pixel circuits arranged in the non-display area NA to correspond to pixel lines L1 to Ln. For example, a first virtual pixel circuit can be disposed in the non-display area NA on an extension of the first pixel line L1. A pixel circuit for a second virtual pixel can be disposed in the non-display area NA on an extension of the second pixel line L2. A virtual data line 104 is connected to the virtual channel of the data driver 110 to apply a data voltage output from the virtual channel to the virtual pixel circuit.

[0062] The driving circuit of the display panel 100 (including the data driver 110 and the gate driver 120) writes the pixel data of the input image into the pixels under the control of the timing controller 130.

[0063] The timing controller 130 can receive pixel data of the input image and timing signals synchronized with the pixel data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, and a data enable signal DE. One period of the vertical synchronization signal Vsync can be a frame period. One period of the horizontal synchronization signal Hsync and the data enable signal DE can be a horizontal period 1H. The pulse of the data enable signal DE can be synchronized with a line of data of pixel P to be written to a pixel line. Since the frame period and horizontal period can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The timing controller 130 can transmit the pixel data of the input image to the data driver 110 and control the operating timing of the data driver 110 and the gate driver 120. The gate timing control signal generated from the timing controller 130 can be input to the gate driver 120 through a level shifter 150.

[0064] Level shifter 150 can receive gate timing control signals to output start pulses and shift clocks. The input signal to level shifter 150 can be a digital signal voltage level signal, and the output signal from level shifter 150 can be an analog voltage signal oscillating between a gate high voltage VGH and a gate low voltage VGL. Level shifter 150 can convert a low-level voltage of the gate timing signal output from timing controller 130 to a gate low voltage (VGL) and a high-level voltage to a gate high voltage (VGH).

[0065] Data driver 110 can receive pixel data of an input image received as a digital signal from timing controller 130 and output a data voltage. Data driver 110 can use a digital-to-analog converter (hereinafter referred to as "DAC") to convert the pixel data of the input image into a gamma-compensated voltage and output the data voltage. The gamma reference voltage output from power circuit 140 can be divided into gamma-compensated voltages for each grayscale by a voltage divider circuit in data driver 110 and supplied to the DAC. The DAC can generate a data voltage as a gamma-compensated voltage corresponding to the grayscale value of the pixel data. The data voltage from the DAC can be output from the respective channels of data driver 110 to data line 102 and virtual data line 104 via an output buffer. The data voltage output from data driver 110 can vary according to the grayscale value of the pixel data. The data voltage can be determined based on the pixel data within a dynamic range between a maximum and a minimum voltage determined based on the gamma reference voltage.

[0066] The circuitry of the data driver 110 can be integrated into the driver IC (integrated circuit). The driver IC can be bonded to the display panel 100 using a chip-on-glass (COG) process, or it can be implemented as a chip-on-film (COF) and bonded to the display panel 100 and electrically connected to the data lines 102 and 104.

[0067] Gate driver 120 can be disposed on display panel 100. Gate driver 120 can be disposed in non-display area NA outside display area AA in display panel 100, or it can be partially disposed in display area AA. Gate driver 120 can supply gate signal to gate line 103 in a single-feed method. In the single-feed method, the gate signal can be applied at one end of gate line 103. In the dual-feed method, gate signals can be applied simultaneously at opposite ends of gate line 103. Gate signal output from gate driver 120 can be applied to pixel P in display area AA and virtual pixel 160 in non-display area NA.

[0068] Multiple gate signals can be applied to the pixel circuitry of pixel P and virtual pixel 160. In this case, multiple gate lines 103 are connected to the pixel circuitry, allowing gate signals of different waveforms to be applied. Gate driver 120 may include multiple gate drivers that output different gate signals. Each of the gate drivers may include circuitry such as shift registers, edge triggers, etc., to shift the pulses of the gate signals.

[0069] The power circuit 140 may include, but is not limited to, a charge pump, regulator, buck converter, boost converter, etc. The power circuit 140 can receive a DC input voltage from the host system 200 to generate the power required to drive the drive circuitry (including data driver 110 and gate driver 120) of the display panel 100 and the pixels P of the display panel 100. The power circuit 140 can output a constant voltage (or DC voltage), such as a gamma reference voltage, gate high voltage, gate low voltage, etc. Additionally, the power circuit 140 can output a constant voltage to be supplied to the pixel P. The gamma reference voltage can be supplied to the data driver 110. The gate high voltage VGH and gate low voltage VGL can be supplied to the level shifter 150 and the gate driver 120. The constant voltage input to the pixel circuitry, such as the pixel drive voltage, pixel ground voltage, etc., can be applied to the pixel P and the virtual pixel 160 via a power line commonly connected to the pixel P. The pixel ground voltage EVSS can be a cathode voltage. The power circuit 140 can be implemented as a power IC, such as a power management integrated circuit (PMIC), an electronic integrated circuit (ELIC), etc., but is not limited to these.

[0070] The drive circuitry of the display panel 100 (including the data driver 110 and the gate driver 120) can be driven at a variable refresh rate (VRR) under the control of the timing controller 130. For example, the timing controller 130 can reduce the power consumption of the display device by analyzing the input image and reducing the refresh rate when the input image does not change within a preset time period. In this case, when a still image is input for a specific time period or longer under the control of the timing controller 130, the drive circuitry of the display panel 100 can reduce the refresh rate of pixel P to control the data writing period of pixel P to be longer, thereby reducing the power consumption of the display device. The drive circuitry of the display panel 100 can reduce the refresh rate when the display device is operating in standby mode or in response to a user command. In addition, the refresh rate can be reduced in an always-on display (AOD) screen. An AOD screen is a small pixel area in the display area AA in which preset information, such as brief information such as remaining battery power and time, is displayed in standby mode.

[0071] The host system 200 can scale the image signal from the video source to match the resolution of the display panel 100, and can transmit it to the timing controller 130 along with the timing control signal.

[0072] exist Figures 4 to 7In the case of the pixel circuit shown, the gate signal may include a first scan signal SC1, a second scan signal SC2, a third scan signal SC3, and a light emission signal (hereinafter referred to as the "EM signal"). In this case, the gate driver 120 may include a first gate driver that outputs the first scan signal SC1, a second gate driver that outputs the second scan signal SC2, a third gate driver that outputs the third scan signal SC3, and a fourth gate driver that outputs the EM signal. Each of the first to fourth gate drivers may start outputting a pulse corresponding to the gate signal in response to a start pulse, and the pulse may be shifted according to a shift clock timing sequence.

[0073] During the manufacturing process of the display panel 100, defective sub-pixels may occur. For example, the pixel circuit used to drive the light-emitting element EL may be driven normally, and the defective sub-pixel may appear as a bright spot. To repair such defective sub-pixels, the repair process can electrically connect the defective sub-pixel to a dummy pixel to drive the light-emitting element of the defective sub-pixel. For this purpose, the display panel 100 may also include multiple repair lines WDR, for example... Figure 2 Those shown.

[0074] This disclosure improves the temperature luminous sensitivity (TLS) characteristics of a pixel by rapidly charging the anode voltage of the light-emitting element in the pixel of the display area AA using a gate signal (e.g., the voltage of the EM signal) applied to the dummy pixel via the repair line WDR. Here, the pixel with improved TLS characteristics in the display area AA refers to all pixels in the display area AA, including normally driven pixels and defective sub-pixels.

[0075] Figure 2 This is a diagram showing an example of a repair line. In Figure 2 In Chinese, "DPXL" indicates Figure 1 The virtual pixel is shown as one of the sub-pixels, and "PXL1" represents any sub-pixel present in the display area AA. "DPC" represents the virtual pixel circuit, and "APC" represents the pixel circuit of sub-pixel PXL1 located in the display area AA.

[0076] Reference Figure 2 The repair line WDR can be formed as a long wiring that extends across the non-display area NA and the display area AA in the Y-axis direction (second direction) of each pixel line in the display panel 100. The repair line WDR can be parallel to the gate line 103 and can intersect with the data lines 102 and 104, all of which are in Figure 1 As shown in the image.

[0077] To improve the TLS (Temperature-to-Light Emission Sensitivity) characteristics, the virtual pixel circuit DPC formed in the virtual pixel DPXL and the pixel circuit APC of the display area AA can be electrically connected via the repair line WDR and the first compensation capacitor COV. When the light-emitting period of sub-pixel PXL1 begins, the voltage applied by the virtual pixel circuit DPC through the virtual pixel DPXL can charge the anode electrode of the light-emitting element EL formed in sub-pixel PXL1 via the repair line WDR and the capacitor COV. The first compensation capacitor COV can be formed by overlapping metal layers at the intersection of the repair line WDR and the node connected to the anode electrode of the light-emitting element EL, wherein an insulating layer (dielectric layer) is inserted between the metal layers.

[0078] The light-emitting element (EL) can be implemented as an OLED or an inorganic LED, such as a micro-LED. The EL may include a capacitor positioned between an anode and a cathode electrode. An OLED comprises an anode electrode, a cathode electrode, and an organic compound layer interposed between these electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode electrodes of the EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML) to form excitons. Visible light is then emitted from the emissive layer (EML). An OLED can be implemented as an OLED with a tandem structure in which multiple emissive layers are stacked. OLEDs with a tandem structure can improve pixel brightness and lifetime.

[0079] The virtual pixel DPXL may also include a second compensation capacitor CB for improving the TLS (temperature luminescence sensitivity) characteristics of the sub-pixel PXL1 by transmitting the voltage of the EM signal EM1 to the repair line WDR.

[0080] The virtual pixel DPXL does not require a light-emitting element, but may include a light-emitting element omitted in the figure. The light-emitting element formed in the virtual pixel DPXL may have a structure that is substantially the same as the light-emitting element in the sub-pixel PXL1 located in the display area AA, and may be covered by a black matrix.

[0081] Figure 3A and Figure 3B This is a graph used to illustrate a comparison of the TLS (Temperature Emission Sensitivity) characteristics between embodiments and comparative examples of the present disclosure. TLS describes the degree of brightness change under specific temperature conditions. TLS refers to the sensitivity of the light-emitting element to brightness changes when the temperature of a pixel changes. When TLS is improved, the brightness change of the light-emitting element according to temperature fluctuations is reduced.

[0082] Figure 3A This is a waveform diagram showing the EM signal EM1 and anode voltage VAND of the light-emitting element in a comparative example with poor TLS characteristics. Figure 3B This is a waveform diagram showing the EM signal EM1 and anode voltage VAND of the light-emitting element in an embodiment with improved TLS characteristics. In the VGH segment of the EM signal EM1, the anode voltage of the light-emitting element EL can begin to charge, and light emission can occur. Figure 3A The comparison examples shown are Figure 3B In the embodiments shown, it is assumed that the amount of charge in the anode electrode of the light-emitting element is the same.

[0083] like Figure 3A As shown, the anode electrode of the light-emitting element can begin charging to the high data voltage Vdata after a certain delay following the start of the light-emitting period. In this case, the slope of the anode voltage is large during charging, which makes the brightness of the light-emitting element EL change sensitively with temperature variations.

[0084] like Figure 3B As shown, the anode electrode of the light-emitting element can be rapidly charged to a low data voltage Vdata immediately after the start of the light-emitting period, and can be charged by an amount equal to that of the comparative example. In this case, the slope of the anode voltage during charging is small. When the slope of the anode voltage is small, the brightness of the light-emitting element does not change sensitively with temperature, and thus the TLS characteristics are improved.

[0085] In such Figure 3A In a comparative example, when the brightness control value limiting pixel brightness is low, the TLS (Temperature Emissivity to Light) characteristic may deteriorate. The brightness control value can be DBV (Digital Brightness Value, Display Brightness Value, or Display Brightness Voltage). The host system can control the brightness of pixel P by updating DBV in response to ambient illuminance (brightness) in response to brightness adjustment input data input via a user interface or in response to the output of an illuminance sensor. Power circuit 140 can adjust the gamma reference voltage in association with DBV. For example, power circuit 140 can output a gamma reference voltage of the gamma band indicated by DBV in the gamma band classified by brightness in association with DBV input to a programmable gamma circuit, and can supply the gamma reference voltage to data driver 110. Since the data voltage output from data driver 110 is determined based on the gamma reference voltage, the brightness of the pixel can change in association with changes in DBV.

[0086] This disclosure allows the anode electrode of the light-emitting element (EL) to be charged immediately after the start of the light-emitting period by using virtual pixels and repair lines (e.g., Figure 3B(As shown) to improve TLS features and enhance image quality, even at low DBV.

[0087] The pixel circuitry of the display area can be implemented using either a diode-based internal compensation circuit or a source follower-based internal compensation circuit.

[0088] Figure 4 This is a circuit diagram illustrating pixel circuitry in a display area according to one embodiment of the present disclosure. Figure 4 An example of a pixel circuit using an internal compensation circuit based on diode connections is shown, but the implementation of this disclosure is not limited thereto.

[0089] Reference Figure 4 The sub-pixel PXL1 of the display area AA includes a pixel circuit APC that drives the light-emitting element EL. The pixel circuit APC includes a driving element M6, multiple switching elements M1 to M5, a first capacitor CST, and a second capacitor CA. The driving element M6 and the switching elements M1 to M5 can be implemented as an n-channel oxide TFT, but are not limited thereto.

[0090] The pixel circuit APC is connected to the data line DL, which receives the data voltage Vdata for applying pixel data, and the gate lines SC1, SC2, SC3, EM1, and EM2, for which gate signals SC1, SC2, SC3, EM1, and EM2 are applied. The pixel circuit APC is also connected to the first constant voltage node PL1, which receives the pixel drive voltage EVDD; the second constant voltage node PL2, which receives the pixel ground voltage EVSS; the third constant voltage node PL3, which receives the reference voltage Vref; and the fourth constant voltage node PL4, which receives the anode reset voltage VAR. These constant voltage nodes can be connected to their corresponding power lines.

[0091] The voltage levels of each of the constant voltages EVDD, EVSS, Vref, and VAR applied to the pixel circuit APC can be set by considering the voltage margin of saturation operation. The voltage levels of the constant voltages EVDD, EVSS, Vref, and VAR can be set under the condition that EVDD > Vref > VAR > EVSS. The gate high voltage VGH can be set higher than the pixel drive voltage EVDD, and the gate low voltage VGL can be set lower than the pixel ground voltage EVSS. The data voltage Vdata output from the data driver 110 has a dynamic range set between the reference voltage Vref and the pixel drive voltage EVDD. In one example, the minimum value of the data voltage Vdata can be set close to the reference voltage Vref, and the maximum value of the data voltage Vdata can be set close to the pixel drive voltage EVDD. In the following, the gate high voltage VGH will be referred to as the gate turn-on voltage, and the gate low voltage VGL will be referred to as the gate turn-off voltage.

[0092] Gate signals SC1, SC2, SC3, EM1, and EM2 consist of pulses that oscillate between the gate on-voltage VGH and the gate off-voltage VGL.

[0093] During a frame period, the sequence can be: initialization period (INI), sensing period (SEN), sampling period (SAM), anode reset period (AR), and emission period (EMI) (e.g.) Figure 11 and Figure 12 (As shown) drive Figure 4 The pixel circuit is shown. The initialization period INI, sensing period SEN, sampling period SAM, anode reset period AR, and emission period EMI can be defined by the waveforms of gate signals SC1, SC2, SC3, EM1, and EM2. After the voltage at the third node n3 and the anode voltage of the light-emitting element EL rise at the beginning of the emission period EMI, the light-emitting element EL can emit light.

[0094] exist Figure 11 and Figure 12 In the diagram, "AA timing (6T2C)" represents the waveforms of the gate signal and the major node, which sequentially show the waveforms when using... Figure 4 The pixel circuit APC shown implements the internal compensation operation of the pixel circuit APC when the pixels of the display area AA are displayed.

[0095] Reference Figure 4 , Figure 11 and Figure 12 The voltage of the first EM signal EM1 is the gate on-state voltage VGH during the sensing period SEN and the emission period EMI, and the gate off-state voltage VGL during the initialization period INI, the sampling period SAM, and the anode reset period AR. The fourth switching element M4 is turned on in response to the gate on-state voltage VGH of the first EM signal EM1, and turned off in response to the gate off-state voltage VGL of the first EM signal EM1.

[0096] The voltage of the second EM signal EM2 is the gate on-state voltage VGH during the initialization period INI, the anode reset period AR, and the emission period EMI, and the gate off-state voltage VGL during the sensing period SEN and the sampling period SAM. The fifth switching element M5 turns on in response to the gate on-state voltage VGH of the second EM signal EM2, and turns off in response to the gate off-state voltage VGL of the second EM signal EM2.

[0097] The voltage of the first scan signal SC1 is generated as a pulse of gate-on voltage VGH synchronized with the data voltage Vdata of the pixel data during the sampling period SAM, and is a gate-off voltage VGL during other periods INI, SEN, AR, and EMI. The third switching element M3 is turned on in response to the gate-on voltage VGH of the first scan signal SC1, and turned off in response to the gate-off voltage VGL of the first scan signal SC1.

[0098] The voltage of the second scan signal SC2 is generated as a pulse of gate on-state voltage VGH during the initialization period INI and the sensing period SEN, and as a gate off-state voltage VGL during other periods SAM, AR, and EMI. The first switching element M1 is turned on in response to the gate on-state voltage VGH of the second scan signal SC2, and turned off in response to the gate off-state voltage VGL of the second scan signal SC2.

[0099] The voltage of the third scan signal SC3 is the gate on-state voltage VGH during the initialization period INI, the sensing period SEN, the sampling period SAM, and the anode reset period AR, and is the gate off-state voltage VGL during the emission period EMI. The second switching element M2 turns on in response to the gate on-state voltage VGH of the third scan signal SC3, and turns off in response to the gate off-state voltage VGL of the third scan signal SC3.

[0100] The driving element M6 generates a current based on the gate-to-source voltage Vgs to drive the light-emitting element EL. The gate-to-source voltage Vgs of the driving element M6 can be a voltage applied between the second node n2 and the third node n3. The driving element M6 includes a first electrode connected to the first node n1, a gate electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0101] The anode electrode of the light-emitting element EL can be connected to a fourth node n4, and its cathode electrode can be connected to a second constant-voltage node PL2 to which the pixel ground voltage EVSS is applied. The light-emitting element EL includes a capacitor formed between the anode electrode and the cathode electrode.

[0102] The first capacitor CST is connected between the second node n2 and the third node n3. The first capacitor CST is initialized during the initialization period INI and then stores the threshold voltage Vth of the driving element M6 during the sensing period SEN. The first capacitor CST stores the data voltage Vdata of the pixel data compensated by the threshold voltage Vth of the driving element M6 during the sampling period SAM, and then maintains the gate-to-source voltage Vgs of the driving element M6 during the anode reset period AR and the emission period EMI.

[0103] The second capacitor CA can be connected between the first constant voltage node PL1 and the third node n3. The second capacitor CA prevents the loss of data voltage Vdata. The data voltage Vdata transmission rate (Data DR) is expressed by the following Equation 1:

[0104] [Equation 1]

[0105]

[0106] Here, C DTS_par It is the parasitic capacitance connected to the third node n3. With C DTShold As the value increases, the data voltage Vdata is transmitted more completely, and the loss of data voltage Vdata is reduced.

[0107] A first switching element M1 is connected between a third constant-voltage node PL3, to which a reference voltage Vref is applied, and a second node n2, and is turned on in response to the gate turn-on voltage VGH of the second scan signal SC2. When the first switching element M1 is on, the reference voltage Vref is applied to the second node n2. When the voltage of the second scan signal SC2 is the gate turn-off voltage VGL, the first switching element M1 is in the off state. The first switching element M1 includes a first electrode connected to the third constant-voltage node PL3, a gate electrode connected to the gate line to which the second scan signal SC2 is applied, and a second electrode connected to the second node n2.

[0108] The second switching element M2 is connected between the fourth constant-voltage node PL4 and the fourth node n4, where the anode reset voltage VAR is applied, and is turned on in response to the gate turn-on voltage VGH of the third scan signal SC3. When the second switching element M2 is on, the anode reset voltage VAR is applied to the fourth node n4. When the voltage of the third scan signal SC3 is the gate turn-off voltage VGL, the second switching element M2 is in the off state. The second switching element M2 includes a first electrode connected to the fourth constant-voltage node PL4, a gate electrode connected to the gate line to which the third scan signal SC3 is applied, and a second electrode connected to the fourth node n4.

[0109] A third switching element M3 is connected between the data line DL, where the pixel data data voltage Vdata is applied, and the second node n2, and is turned on in response to the gate turn-on voltage VGH of the first scan signal SC1. When the third switching element M3 is on, the data voltage Vdata is applied to the second node n2. When the voltage of the first scan signal SC1 is the gate turn-off voltage VGL, the third switching element M3 is in the off state. The third switching element M3 includes a first electrode connected to the data line DL, a gate electrode connected to the gate line where the first scan signal SC1 is applied, and a second electrode connected to the second node n2.

[0110] A fourth switching element M4 is connected between the first constant voltage node PL1, to which the pixel driving voltage EVDD is applied, and the first node n1, and is turned on in response to the gate on-state voltage VGH of the first EM signal EM1. When the fourth switching element M4 is turned on, the pixel driving voltage EVDD can be applied to the first node n1. The fourth switching element M4 includes a first electrode connected to the first constant voltage node PL1, a gate electrode connected to the gate line to which the first EM signal EM1 is applied, and a second electrode connected to the first node n1.

[0111] A fifth switching element M5 is connected between the third node n3 and the fourth node n4, and is turned on in response to the gate on-state voltage VGH of the second EM signal EM2. When the fifth switching element M5 is turned on, the third node n3 can be electrically connected to the fourth node n4. The fifth switching element M5 includes a first electrode connected to the third node n3, a gate electrode connected to the gate line to which the second EM signal EM2 is applied, and a second electrode connected to the fourth node n4.

[0112] Figure 5 This is a circuit diagram illustrating pixel circuitry in a display area according to another embodiment of the present disclosure. Figure 5 An example of a pixel circuit applying an internal compensation circuit based on a source follower is shown, but the implementation of this disclosure is not limited thereto.

[0113] Reference Figure 5 The pixel circuit APC includes a driving element M28, multiple switching elements M21 to M27, a first capacitor C1, and a second capacitor C2. The driving element M28 and the switching elements M21 to M27 can be implemented as an n-channel oxide TFT, but are not limited thereto.

[0114] The pixel circuit APC is supplied with a data voltage Vdata for pixel data, gate signals SC1, SC2, SC3, EM1 and EM2, and DC voltages such as the pixel drive voltage EVDD, the pixel ground voltage EVSS, the reference voltage Vref2, and the initialization voltage Vinit. The voltages applied to the pixel circuit APC can be set such that EVDD > Vref2 > Vinit > EVSS, but are not limited to this.

[0115] The pixel circuit APC can be driven in the following sequence: an initialization period for initializing the pixel circuit APC; a sampling period for sampling the threshold voltage Vth of the driving element M28; an addressing period for charging the data voltage Vdata and writing pixel data; and an emission period for emitting light from the light-emitting element EL. Each period can be defined by gate signals SC1, SC2, SC3, EM1, and EM2.

[0116] The anode electrode of the light-emitting element EL is connected to the fourth node n4, and the cathode electrode of the light-emitting element EL can be connected to the second constant voltage node PL2, to which the pixel ground voltage EVSS is applied. A first capacitor C1 is connected between the second node n2 and the fifth node n5. A second capacitor C2 is connected between the third node n3 and the fifth node n5.

[0117] The driving element M28 can be a transistor with a dual-gate structure. The driving element M28 includes a first gate electrode connected to the second node n2, a second gate electrode connected to the fourth node n4, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0118] Switching elements M21 to M27 are turned on in response to a gate turn-on voltage applied to their respective gate electrodes, and are turned off in response to a gate turn-off voltage.

[0119] The first switching element M21 is turned on in response to the gate on-state voltage VGH of the second scan signal SC2 during the initialization and sampling periods, and can electrically connect the first node n1 to the second node n2. The first switching element M21 includes a first electrode connected to the first node n1, a second electrode connected to the second node n2, and a gate electrode connected to the gate line to which the second scan signal SC2 is applied.

[0120] The second switching element M22 is turned on in response to the gate turn-on voltage VGH of the second EM signal EM2 during the light-emitting period, and can form a current path between the driving element M28 and the light-emitting element EL. The second switching element M22 includes a first electrode connected to the third node n3, a second electrode connected to the fourth node n4, and a gate electrode connected to the gate line to which the second EM signal EM2 is applied.

[0121] The third switching element M23 is turned on in response to the gate on-state voltage VGH of the second scan signal SC2 during the initialization and sampling periods, and can supply the initialization voltage Vinit to the fifth node n5. The third switching element M23 includes a first electrode connected to the third constant voltage node PL3 to which the initialization voltage Vinit is applied, a second electrode connected to the fifth node n5, and a gate electrode connected to the gate line to which the second scan signal SC2 is applied.

[0122] The fourth switching element M24 is turned on during the addressing period in response to the gate on-state voltage VGH of the first scan signal SC1, and can supply the data voltage Vdata to the fifth node n5. The fourth switching element M24 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a second electrode connected to the fifth node n5, and a gate electrode connected to the gate line to which the first scan signal SC1 is applied.

[0123] The fifth switching element M25 is turned on in response to the gate on-state voltage VGH of the first EM signal EM1 during the initialization and emission periods, and can supply the pixel driving voltage EVDD to the first node n1. The fifth switching element M25 includes a first electrode connected to the first constant voltage node PL1 to which the pixel driving voltage EVDD is applied, a second electrode connected to the first node n1, and a gate electrode connected to the gate line to which the first EM signal EM1 is applied.

[0124] The sixth switching element M26 is turned on in response to the gate on-state voltage VGH of the third scan signal SC3 during the sampling and addressing periods, and can supply the reference voltage Vref2 to the third node n3. The sixth switching element M26 includes a first electrode connected to the third node n3, a second electrode connected to the fourth constant voltage node PL4 to which the reference voltage Vref2 is applied, and a gate electrode connected to the gate line to which the third scan signal SC3 is applied.

[0125] The seventh switching element M27 is turned on in response to the gate turn-on voltage VGH of the third scan signal SC3 during the sampling and addressing periods, and can supply the initialization voltage Vinit to the fourth node n4. The seventh switching element M27 includes a first electrode connected to the third constant voltage node PL3 to which the initialization voltage Vinit is applied, a second electrode connected to the fourth node n4, and a gate electrode connected to the gate line to which the third scan signal SC3 is applied.

[0126] The virtual pixel DPXL includes pixel circuitry that supplies voltage to the repair line WDR during the illumination period of the sub-pixels in the display area AA. For example... Figure 6 and Figure 7 As shown, the virtual pixel DPXL can be implemented as the following pixel circuit, in which, from Figure 4 The fourth switching element M4 has been removed from the pixel circuit of the display area AA shown, so that the anode electrode of the third node n3 and the light-emitting element EL can be charged quickly.

[0127] Figure 6 This is a circuit diagram illustrating the virtual pixel circuit DPC of the virtual pixel DPXL according to one embodiment of the present disclosure. Figure 6 In the middle, the part with is omitted. Figure 4 The redundant description related to the pixel circuit is shown.

[0128] Reference Figure 6 The virtual pixel circuit DPC shares the gate signals SC1, SC2, SC3 and EM2 except for the first EM signal EM1, and shares the constant voltages EVDD, EVSS, Vref and VAR.

[0129] The virtual pixel circuit (DPC) includes a driving element T5, multiple switching elements T1 to T4, a first capacitor CST, and a second capacitor CA. The driving element T5 and the switching elements T1 to T4 can be implemented as n-channel oxide TFTs, but are not limited thereto. The switching elements T1 to T4 can be turned on in response to the gate on-state voltage VGH of the corresponding gate signals SC1, SC2, SC3, and EM2, and can be turned off in response to the gate off-state voltage VGL.

[0130] The virtual pixel circuit DPC is connected to the virtual data line DDL, which receives the data voltage Vdata to which pixel data is applied, and the gate lines to which gate signals SC1, SC2, SC3, and EM2 are applied. Although Figure 4 The pixel circuit shown requires a switching element for applying the first EM signal EM1, but this switching element is removed from the pixel circuit of the virtual pixel. This is to improve TLS characteristics by rapidly charging the anode electrode of the third node n3 and the light-emitting element EL during the light-emitting period.

[0131] During a frame period, with Figure 4 The pixel circuit shown is similar to APC. Figure 6 The virtual pixel circuit DPC shown can be configured in the following order: initialization period INI, sensing period SEN, sampling period SAM, anode reset period AR, and emission period EMI (e.g., Figure 11 (As shown) drive. The initialization period INI, sensing period SEN, sampling period SAM, anode reset period AR, and emission period EMI can be defined by the waveforms of gate signals SC1, SC2, SC3, and EM2.

[0132] exist Figure 11 In this context, "virtual timing (5T2C)" represents the waveforms of the gate signal and the major node, which are sequentially shown when using... Figure 6 The virtual pixel circuit DPC shown implements the internal compensation operation of the virtual pixel circuit DPC when the virtual pixel DPXL is used.

[0133] Reference Figure 6 and Figure 11 The driving element T5 includes a first electrode connected to a first node n1, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3. The first node n1 is directly connected to a first constant voltage node PL1. The pixel driving voltage EVDD is directly applied to the first node n1.

[0134] The anode electrode of the light-emitting element EL can be connected to a fourth node n4, and its cathode electrode can be connected to a second constant-voltage node PL2 to which the pixel ground voltage EVSS is applied. The light-emitting element EL includes a capacitor formed between the anode electrode and the cathode electrode.

[0135] The first capacitor CST is connected between the second node n2 and the third node n3. The second capacitor CA is connected between the first constant voltage node PL1 and the third node n3.

[0136] A first switching element T1 is connected between a third constant-voltage node PL3 and a second node n2, and is turned on in response to the gate turn-on voltage VGH of the second scan signal SC2 during the initialization period INI and the sensing period SEN. When the first switching element T1 is turned on, a reference voltage Vref is applied to the second node n2. The first switching element T1 is turned off during the sampling period SAM, the anode reset period AR, and the emission period EMI, wherein the voltage of the second scan signal SC2 is the gate turn-off voltage VGL. The first switching element T1 includes a first electrode connected to the third constant-voltage node PL3, a gate electrode connected to the gate line to which the second scan signal SC2 is applied, and a second electrode connected to the second node n2.

[0137] The second switching element T2 is connected between the fourth constant voltage node PL4 and the fourth node n4, and is turned on in response to the gate turn-on voltage VGH of the third scan signal SC3 during the initialization period INI, the sensing period SEN, the sampling period SAM, and the anode reset period AR. When the second switching element T2 is turned on, the anode reset voltage VAR is applied to the fourth node n4. The second switching element T2 is in the off state during the emission period EMI, where the voltage of the third scan signal SC3 is the gate turn-off voltage VGL. The second switching element T2 includes a first electrode connected to the fourth constant voltage node PL4, a gate electrode connected to the gate line to which the third scan signal SC3 is applied, and a second electrode connected to the fourth node n4.

[0138] A third switching element T3 is connected between the virtual data line DDL, to which the data voltage Vdata is applied, and the second node n2. The third switching element T3 is turned on during the sampling period SAM in response to the gate turn-on voltage VGH of the first scan signal SC1. When the third switching element T3 is on, the data voltage Vdata is applied to the second node n2. The third switching element T3 is in a turned-off state during the initialization period INI, the sensing period SEN, the anode reset period AR, and the emission period EMI, where the voltage of the first scan signal SC1 is the gate turn-off voltage VGL. The third switching element T3 includes a first electrode connected to the virtual data line DDL, a gate electrode connected to the gate line to which the first scan signal SC1 is applied, and a second electrode connected to the second node n2.

[0139] A fourth switching element T4 is connected between the third node n3 and the fourth node n4, and is turned on in response to the gate turn-on voltage VGH of the second EM signal EM2 during the initialization period INI, the anode reset period AR, and the emission period EMI. When the fourth switching element T4 is turned on, the third node n3 can be electrically connected to the fourth node n4. The fourth switching element T4 is in the off state during the sensing period SEN and the sampling period SAM, wherein the voltage of the second EM signal EM2 is the gate turn-off voltage VGL. The fourth switching element T4 includes a first electrode connected to the third node n3, a gate electrode connected to the gate line to which the second EM signal EM2 is applied, and a second electrode connected to the fourth node n4.

[0140] Figure 7 This is a circuit diagram illustrating the virtual pixel circuit DPC of the virtual pixel DPXL according to another embodiment of the present disclosure. Figure 7 In the middle, the part with is omitted. Figure 4 and Figure 6 The redundant description related to the pixel circuit is shown.

[0141] Figure 7 The virtual pixel circuit DPC shown also includes a second compensation capacitor CB.

[0142] The second compensation capacitor CB is connected between the gate line to which the first EM signal EM1 is applied and the fourth node n4 of the virtual pixel circuit DPC. For example... Figure 9 As shown, the fourth node n4 is connected to the repair line WDR. Therefore, the second compensation capacitor CB is connected to the repair line WDR via capacitor coupling. The second compensation capacitor CB can transmit the voltage of the first EM signal EM1 to the pixel P of the display area through the repair line WDR to quickly charge the anode electrode of the light-emitting element EL and improve the TLS characteristics. The first EM signal EM1 is applied to the pixel circuit APC of the display area AA and the virtual pixel circuit DPC of the virtual pixel DPXL with the same waveform. Therefore, as Figure 7 and Figure 11 As shown, the voltage of the first EM signal EM1 is activated to the gate turn-on voltage VGH during the sensing period SEN and the emission period EMI, and is deactivated to the gate turn-off voltage VGL during the initialization period INI, the sampling period SAM, and the anode reset period AR.

[0143] The second compensation capacitor CB can be determined experimentally. The capacitance of the second compensation capacitor CB can be approximately 10% to 100% of the capacitance of the first capacitor CST. The second compensation capacitor CB can have approximately 10% of the capacitance of the first capacitor CST, but is not limited to this. When the capacitance of the first capacitor CST is in the range of 100fF to 300fF, the capacitance of the second compensation capacitor CB can be in the range of 10fF to 30fF.

[0144] The data voltage Vdata applied to the virtual pixel circuit DPC of the virtual pixel DPXL can be set by considering both the TLS feature improvement effect and the presence of defective sub-pixels. When the virtual pixel DPXL is connected to a defective sub-pixel via the repair line WDR, the data voltage Vdata applied to the defective sub-pixel can be applied to the virtual pixel circuit DPC of the virtual pixel DPXL.

[0145] In the absence of defective sub-pixels in the pixel line, the data voltage Vdata need not be applied to the virtual pixel DPXL, because the voltage of the first EM signal EM1 can be applied to... Figure 7 The repair line WDR in the virtual pixel circuit DPC shown.

[0146] In another embodiment of the pixel line without defective sub-pixels, the data voltage Vdata can be applied to... Figure 6 and Figure 7 The virtual pixel circuit DPC is shown. Due to the resistance of the repair line WDR and the first compensation capacitor COV, the RC load in the pixels of the display area AA may increase, thereby increasing the RC delay. Taking this into consideration, the data voltage Vdata applied to the virtual pixel circuit DPC can be set to the maximum voltage of the dynamic range, for example, set to the peak white-grayscale voltage, to reduce the RC delay, but is not limited thereto. For example, the data voltage Vdata applied to the virtual pixel DPXL (which is electrically connected via a capacitor to a pixel line without defective sub-pixels) can be the maximum voltage, average voltage, or experimentally determined voltage of the data voltage applied to the corresponding pixel line's sub-pixel.

[0147] Figure 8 It is shown Figure 6 The virtual pixel circuit DPC shown is electrically connected to the repair line WDR and the first compensation capacitor COV via the repair line WDR. Figure 4 The circuit diagram shown is an example of an APC pixel circuit. Figure 9 It is shown Figure 7 The virtual pixel circuit DPC shown is electrically connected to the repair line WDR and the first compensation capacitor COV via the repair line WDR. Figure 4 The circuit diagram shown is an example of an APC pixel circuit. Figure 8 and Figure 9 In this context, "PXL1" refers to any subpixel that can be driven normally within the display area AA. In the following text, "PXL1" will be referred to as the "first subpixel".

[0148] Reference Figure 8 and Figure 9 The first sub-pixel PXL1 and the virtual pixel DPXL can be driven by sharing the same gate line and power line.

[0149] The repair line WDR is connected to the fourth node n4 of the virtual pixel DPXL. The fourth node n4 of the first sub-pixel PXL1 is connected to the repair line WDR through the first compensation capacitor COV. The fourth node n4 of the first sub-pixel PXL1 is not directly connected to the repair line WDR.

[0150] The third node n3 of the virtual pixel DPXL is pre-charged by the current flowing through the driving element T5 before the light-emitting period, and the fourth node n4 is rapidly charged by the fourth switching element T4, which is turned on at the beginning of the light-emitting period. The voltage charged in the fourth node n4 of the virtual pixel DPXL is applied to the fourth node n4 of the first sub-pixel PXL1 through the first compensation capacitor COV. Therefore, since the anode voltage of the light-emitting element EL in the first sub-pixel PXL1 begins to charge rapidly at the beginning of the light-emitting period, the TLS characteristics are improved.

[0151] like Figure 9 As shown, when the voltage of the first EM signal EM1 is applied to the repair line WDR through the second compensation capacitor CB in the virtual pixel DPXL, the anode voltage of the first sub-pixel PXL1 can rise more rapidly at the beginning of the light emission period, as... Figure 12 As shown.

[0152] Figure 10 It is shown Figure 7 The virtual pixel circuit DPC shown is electrically connected to the repair line WDR and the first compensation capacitor COV via the repair line WDR. Figure 5 The circuit diagram shows an example of the pixel circuit APC. In this embodiment, since the internal compensation drive timings of the virtual pixel DPXL and the first sub-pixel PXL1 can be different, the gate line does not need to be shared between the first sub-pixel PXL1 and the virtual pixel DPXL, and a separate gate driver can be designed. Figure 10 The connection structure of the virtual pixel DPXL and the first sub-pixel PXL1 shown in the figure is such that the voltage charged in the fourth node n4 of the virtual pixel DPXL is applied to the fourth node n4 of the first sub-pixel PXL1 through the first compensation capacitor COV at the beginning of the light emission period, so that the anode voltage of the light-emitting element EL is charged quickly and the TLS characteristics are improved.

[0153] Figure 11 It shows that it is applied to Figure 8 The waveforms of the gate signal and the voltage of the main node in the pixel circuit are shown. Figure 12 It shows that it is applied to Figure 9 The diagram shows the waveforms of the gate signal and the voltage of the main nodes in the pixel circuit. Figure 11 and Figure 12 In the diagram, "DTG" represents the voltage of the second node n2, "DTS" represents the voltage of the third node n3, and "VAND" represents the anode voltage of the light-emitting element EL. The waveform of the third node voltage DTS is shown as a solid line, and the waveform of the anode voltage VAND is shown as a dashed line.

[0154] Reference Figure 8 , Figure 9 , Figure 11 and Figure 12 When EMI begins during the emission period, EM signals EM1 and EM2 rise to the gate turn-on voltage VGH, thereby turning on switching elements M4, M5, and T4 between the pixel drive voltage EVDD and the pixel ground voltage EVSS. At this time, current from drive element M6 is applied to the anode electrode of the light-emitting element EL formed in the first sub-pixel PXL1, and simultaneously, current from virtual pixel DPXL is applied through the repair line WDR, causing the anode voltage VAND of the light-emitting element EL to rise rapidly immediately after the start of EMI during the emission period. Therefore, compared to the comparative example indicated by the dashed line, the anode voltage VAND can rise more rapidly with a smaller slope, thereby improving TLS characteristics.

[0155] In the repair process of the display panel, the pixel circuit APC of the defective sub-pixel can be disconnected from the anode electrode of the light-emitting element EL, and the virtual pixel DPXL can be connected to the anode electrode of the light-emitting element EL formed in the defective sub-pixel through the repair line WDR. Therefore, the light-emitting element of the defective sub-pixel can be normally driven by the current generated from the virtual pixel DPXL.

[0156] Figure 13 It shows the combination Figure 8 The illustrated pixel circuit diagram shows an example of a circuit that connects a defective sub-pixel to a virtual pixel via a repair line. Figure 14 It shows the combination Figure 9 The illustrated pixel circuit diagram shows an example circuit where a defective sub-pixel is connected to a virtual pixel via a repair line. Figure 13 and Figure 14In this text, "PXL1" represents the first sub-pixel located in display area AA and normally driven, and "PXL2" represents the defective sub-pixel located in display area AA (hereinafter referred to as the "second sub-pixel"). The dashed line indicated in the second sub-pixel PXL2 represents the break point where the wiring is cut by a laser beam during the repair process. In the repair process, a laser beam of a preset wavelength can be irradiated at the desired location in the defective sub-pixel to break the wiring (or node) by cutting or short-circuiting it by soldering.

[0157] Reference Figure 13 and Figure 14 The light-emitting element EL of the second sub-pixel PXL2 is electrically disconnected from the second switching element M2 and the fifth switching element M5. The fourth node n4 of the second sub-pixel PXL2 is connected to the repair line WDR.

[0158] When driving the virtual pixel DPXL, the current generated from the driving element T5 can flow through the repair line WDR to the light-emitting element EL formed in the second sub-pixel PXL2, thus driving the light-emitting element EL. The data voltage Vdata applied to the virtual pixel DPXL is the data voltage to be applied to the second sub-pixel PXL2.

[0159] According to one or more embodiments of this disclosure, the display device can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop computers, laptop computers, netbook computers, workstations, navigation systems, vehicle navigation systems, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptops, monitors, camera devices, camcorders, and home appliances, etc. Furthermore, the display device according to one or more embodiments of this disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0160] The purpose, means, and effects of this disclosure do not specify the basic features of the claims, and therefore the scope of the claims is not limited to the content of this disclosure.

[0161] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display panel, comprising: A display area is provided, in which a plurality of sub-pixels are arranged, each sub-pixel including a pixel circuit connected to a light-emitting element; A non-display area, in which multiple virtual pixels are arranged, each virtual pixel including a virtual pixel circuit; At least one repair line extends across the display area and the non-display area; as well as A first compensation capacitor is connected between the repair line and the anode electrode of the light-emitting element.

2. The display panel according to claim 1, wherein, The pixel circuitry arranged in the display area includes either a diode-based internal compensation circuit or a source follower-based internal compensation circuit.

3. The display panel according to claim 1, wherein, The pixel circuitry arranged in each of the sub-pixels in the display area includes: A driving transistor includes a first electrode connected to a first node of the sub-pixel, a gate electrode connected to a second node of the sub-pixel, and a second electrode connected to a third node of the sub-pixel; A first switching transistor is connected between a constant voltage node to which a reference voltage is applied and a second node of the sub-pixel, and is turned on in response to a second scan signal; The second switching transistor is connected between the constant voltage node to which the anode reset voltage is applied and the fourth node of the sub-pixel, and is turned on in response to the third scan signal; A third switching transistor is connected between the data line to which the data voltage is applied and the second node of the sub-pixel, and is turned on in response to the first scan signal; A fourth switching transistor is connected between a constant voltage node to which a pixel driving voltage is applied and a first node of the sub-pixel, and is turned on in response to a first light-emitting signal; and A fifth switching transistor is connected between the third node and the fourth node of the sub-pixel, and is turned on in response to the second light emission signal.

4. The display panel according to claim 3, wherein, The pixel circuitry arranged in each of the sub-pixels in the display area further includes: A first capacitor is connected between the second node and the third node of the sub-pixel; and A second capacitor is connected between the constant voltage node to which the pixel driving voltage is applied and the third node of the sub-pixel, and The anode electrode of the light-emitting element is connected to the fourth node of the sub-pixel, and the cathode electrode of the light-emitting element is connected to a constant voltage node to which a pixel ground voltage is applied.

5. The display panel according to claim 3, wherein, The virtual pixel circuit includes: The driving transistor of the virtual pixel includes a first electrode connected to a first node of the virtual pixel to which the pixel driving voltage is applied, a gate electrode connected to a second node of the virtual pixel, and a second electrode connected to a third node of the virtual pixel. The first switching transistor of the virtual pixel is connected between the constant voltage node to which the reference voltage is applied and the second node of the virtual pixel, and is turned on in response to the second scan signal; The second switching transistor of the virtual pixel is connected between the constant voltage node to which the anode reset voltage is applied and the fourth node of the virtual pixel, and is turned on in response to the third scan signal; The third switching transistor of the virtual pixel is connected between the virtual data line and the second node of the virtual pixel, and is turned on in response to the first scan signal; and The fourth switching transistor of the virtual pixel is connected between the third node and the fourth node of the virtual pixel, and is turned on in response to the second light emission signal.

6. The display panel according to claim 5, wherein, The virtual pixel circuit also includes: The first capacitor of the virtual pixel is connected between the second node and the third node of the virtual pixel; and The second capacitor of the virtual pixel is connected between the first node and the third node of the virtual pixel.

7. The display panel according to claim 6, wherein, The virtual pixel also includes: The light-emitting element of the virtual pixel is connected between the fourth node of the virtual pixel and the constant voltage node to which the pixel ground voltage is applied.

8. The display panel according to claim 5, wherein, The virtual pixel circuit also includes: A second compensation capacitor is connected between the gate line to which the first light-emitting signal is applied and the fourth node of the virtual pixel.

9. The display panel according to claim 8, wherein, The capacitance of the second compensation capacitor is 10% to 100% of the capacitance of the first capacitor.

10. The display panel according to claim 5, wherein: The repair line is connected to the fourth node of the virtual pixel, and The first compensation capacitor is connected between the repair line and the fourth node of the sub-pixel.

11. The display panel according to claim 5, wherein, The maximum voltage of the data voltage is applied to the virtual data line.

12. The display panel according to claim 11, wherein: The display area includes a second sub-pixel. The pixel circuit of the second sub-pixel is electrically disconnected from the anode electrode of the light-emitting element arranged in the second sub-pixel, and The anode electrode of the light-emitting element arranged in the second sub-pixel is connected to the repair line.

13. The display panel according to claim 12, wherein, One of the maximum voltage of the data voltage, the data voltage to be applied to the second sub-pixel, and the preset voltage is applied to the virtual data line.

14. A display device, comprising: Display panel according to any one of claims 1 to 11; as well as A display panel driving circuit is configured to drive the sub-pixels and the virtual pixels of the display panel.

15. The display device according to claim 14, wherein, The display panel also includes: Multiple data lines connected to the sub-pixel, virtual data lines connected to the virtual pixel, multiple gate lines intersecting the data lines and the virtual data lines, and multiple power lines connected to the sub-pixel and the virtual pixel, and The sub-pixel and the virtual pixel share the gate line and the power line.

16. The display device according to claim 15, wherein, The display panel driving circuit includes: A gate driving circuit, disposed in the non-display area of ​​the display panel, and configured to supply a gate signal to the gate line; and A data driving circuit is configured to supply data voltage to the data line and the virtual data line.

Images