Method of forming phase change memory and phase change memory

Abstract

The application discloses a forming method of a phase change memory and the phase change memory. An insulating layer is formed on a first contact, the insulating layer is etched to form a groove, and a first conductive line connected with the first contact is formed in the groove. Therefore, the forming method of the first conductive line does not need to etch tungsten, so that the morphology of the first conductive line can be improved, the width consistency and the hole phenomenon of the first conductive line can be improved, the over-etching of the first contact can be improved to reduce the damage of the first contact, and the resistance can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for forming a phase-change memory and the phase-change memory itself. Background Technology

[0002] Phase-change memory (PCM) is a new type of non-volatile memory. To improve storage density, PCM often uses cross-array storage of three-dimensional stacked storage cells, such as two-layer, four-layer, and eight-layer stacks.

[0003] Taking a two-layer stacked three-dimensional phase-change memory as an example, different stacked layers of the phase-change memory often share the same word line (WL), while the two bit lines are located at the top and bottom ends of the stacked structure, respectively, and are called the top bit line (TBL) and the bottom bit line (BBL).

[0004] To improve the electrical performance of phase-change memory (PCM), a top-only flow process is currently used to fabricate PCM. This process eliminates the bottom layer of memory cells and directly fabricates word lines and top layer memory cells on the word line contacts (instead of forming intermediate word lines on the bottom layer of memory cells). However, in this top-only flow process, a conductive tungsten layer is deposited first, and then the tungsten is etched to form the word lines. This etching process often results in poor word line morphology and can also cause over-etching of the top of the word line contacts, leading to damage to the word line contacts. Summary of the Invention

[0005] This application provides a method for forming a phase-change memory, which aims to improve the morphology of word lines and reduce over-etching of word line contacts to reduce word line contact damage.

[0006] This application provides a method for forming a phase-change memory, comprising: providing a substrate; forming a first contact and an insulating layer on the first contact on the substrate; etching the insulating layer to form a groove exposing the first contact; and forming a first conductive line connected to the first contact in the groove.

[0007] In some embodiments, the method further includes forming a stop layer on the first contact before forming the insulating layer; the method of forming the groove includes: etching the insulating layer, the etching process stopping on the stop layer; etching the stop layer exposed by the groove to form the groove penetrating the insulating layer and the stop layer.

[0008] In some embodiments, the method of forming the first conductive line includes: forming a first conductive layer in the groove and on the surface of the insulating layer; planarizing the first conductive layer until the surface of the insulating layer is exposed to form the first conductive line located in the groove.

[0009] In some embodiments, the method further includes: forming a barrier layer on the surface of the groove and the surface of the insulating layer before forming the first conductive layer; and planarizing the barrier layer in a process of planarizing the first conductive layer until the surface of the insulating layer is exposed.

[0010] In some embodiments, the materials of both the barrier layer and the first conductive layer include tungsten; the formation process of the barrier layer includes a first deposition process, and the precursor used in the first deposition process is fluorine-free; the formation process of the first conductive layer includes a second deposition process, and the precursor of the second deposition process is fluorine-containing.

[0011] In some embodiments, the first deposition process includes atomic layer deposition, and the second deposition process includes at least one of chemical vapor deposition and physical vapor deposition.

[0012] In some embodiments, the method further includes: forming a memory stack on the insulating layer and the first conductive line; etching the memory stack to form a memory cell layer connected to the first conductive line; forming a second conductive layer on the memory cell layer; etching the second conductive layer and the memory cell layer to form a plurality of second conductive lines and a plurality of memory cells; wherein the thickness of the insulating layer is 1.5 to 2.5 times the thickness of the second conductive layer.

[0013] In some embodiments, the phase change memory includes an array region and a contact region, and the method of forming the phase change memory further includes: removing the memory cell layer and the first conductive line located in the contact region before forming the second conductive layer; forming a second contact in the contact region, the second contact being connected to a first contact located in the contact region; wherein, after forming the second conductive layer, the second conductive layer is connected to the second contact.

[0014] In some embodiments, the first conductive lines extend along a first direction and are spaced apart along a second direction, both the first and second directions being parallel to the surface of the substrate, and the first and second directions intersecting each other; the dimension of the first conductive line along the second direction is greater than the spacing between two adjacent first conductive lines.

[0015] This application also provides a phase-change memory, formed by the phase-change memory formation method in any of the above embodiments.

[0016] In the phase-change memory formation method of this application embodiment, an insulating layer is first formed on the first contact, then the insulating layer is etched to form a groove, and finally a first conductive line connected to the first contact is formed in the groove. Therefore, the method of forming the first conductive line in this application does not require etching of tungsten, so the morphology of the first conductive line can be improved, the width uniformity of the first conductive line can be increased and the void phenomenon can be reduced; at the same time, the over-etching of the first contact point can be improved to reduce the damage to the first contact point, thereby improving the resistance.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a cross-sectional structural schematic diagram of a phase-change memory provided in one embodiment of this application; Figure 2 This is a cross-sectional structural schematic diagram of a phase-change memory provided in another embodiment of this application; Figures 3 to 5 yes Figure 2 A cross-sectional structural diagram of the phase change memory during its fabrication process; Figure 6 This is a schematic flowchart of a method for forming a phase-change memory provided in some embodiments of this application; Figures 7 to 13 This is a cross-sectional structural diagram of the phase change memory provided in some embodiments of this application during its formation process. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] Please see Figure 1 , Figure 1This is a cross-sectional structural diagram of a phase-change memory provided in one embodiment of this application.

[0022] This phase-change memory (PCM) comprises two stacked memory cells. Each cell consists of a first electrode E1, a gate layer OTS, a second electrode E2, a storage layer PCM, and a third electrode E3, stacked sequentially (from bottom to top). The upper-layer memory cell C2 and the lower-layer memory cell C1 share a single word line (WL), which consists of two layers of conductive lines (including the first sub-conductive line of the lower layer and the second sub-conductive line of the upper layer). Two bit lines (BLs) are located at the top and bottom ends of the stacked structure, respectively, and are called the top bit line (TBL) and the bottom bit line (BBL). When an electrical signal is applied, WL is loaded with a high level, while BBL and TBL are loaded with a low level. The layer where current flows from WL to BBL is defined as the lower layer, and the layer where current flows from WL to TBL is defined as the upper layer. Therefore, the thickness of the word line is approximately twice the thickness of either the top or bottom bit line.

[0023] Three-dimensional stacked phase-change memories exhibit structural asymmetry. Specifically, for two or more stacked memory layers, the current entering from the WL layer flows in opposite directions into the upper and lower memory cells. This asymmetry between the two memory cells results in a difference in the threshold voltage Vt of the OTS (Optical Switching Layer) between the upper and lower layers. This prevents the application of the same current to the upper and lower layers, complicating the electrical signal design and reducing device reliability.

[0024] Electrical testing revealed that the upper-level memory cell C2 has better electrical performance than the lower-level memory cell C1. Therefore, by separating the upper-level memory stack D2 (including the upper-level memory cell C2, word line WL, and top bit line BBL) as a separate storage device, the problem of inconsistent electrical performance between the upper and lower memory layers in multi-layer stacked memory can be solved. Furthermore, compared to the traditional single-layer memory cell structure (e.g., ...), ... Figure 1 The lower storage stack D1 shown includes, from bottom to top, the bottom bit line BBL, the lower storage cell C1, and the word line WL. In contrast, treating the upper storage stack D2 in the two-layer stacked structure as a separate memory provides better electrical performance.

[0025] Therefore, this application provides a phase-change memory. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a cross-sectional structural schematic diagram of a phase-change memory provided in another embodiment of this application. This phase-change memory is related to... Figure 1 The difference in this embodiment is that the structure of the phase-change memory is as follows: Figure 1 The upper-middle storage stack D2 serves as Figure 2The structure of the phase-change memory is such that it has only one layer of storage cells. In other words, Figure 2 The phase-change memory in the model is formed by directly forming the upper storage stack D2 on the substrate.

[0026] The phase change memory includes a substrate 10, a dielectric layer 20, a first contact 31, multiple first sub-conductive lines 41, multiple second sub-conductive lines 42, a storage cell 60, and multiple second conductive lines 70.

[0027] The substrate 10 may include a substrate and a complementary metal-oxide-semiconductor (CMOS) located on the substrate. A dielectric layer 20 is located on the CMOS, a first contact 31 is located within the dielectric layer 20, and the bottom of the first contact 31 is connected to the CMOS.

[0028] Multiple first sub-conductive lines 41 are located on the dielectric layer 20. The first sub-conductive lines 41 are arranged along the first direction X and extend along the second direction Y. Multiple second sub-conductive lines 42 are connected to the multiple first sub-conductive lines 41 in a one-to-one correspondence. The second sub-conductive lines 42 and the first sub-conductive lines 41 are overlapped and together serve as word lines.

[0029] The first contact 31 is located within the dielectric layer 20 and is connected between the CMOS and the first sub-conducting line 41. The first contact 31 is located in the array region 101 and the contact region 102.

[0030] The phase-change memory also includes an insulating layer 90 located between adjacent first sub-conducting lines 41 to achieve electrical isolation.

[0031] Multiple second conductive lines 70 extend along the second direction Y and are arranged along the first direction X. The second conductive lines 70 serve as top bit lines, and the memory cell 60 is located at the intersection of the word line and the bit line. It should be noted that the word line and bit line in this application are interchangeable.

[0032] For the specific structure of storage unit 60, please refer to Figure 1 As can be understood from the relevant descriptions in the document, the specific storage unit 60 in this application is not limited to this.

[0033] The phase-change memory also includes a second contact 32 located on the periphery of the memory cell 60 (i.e., contact area 102), for example, on one side of the memory cell 60 along the first direction X. One end of the second contact 32 is connected to the CMOS via the first contact 31, and the other end of the second contact 32 is connected to the second conductive line 70.

[0034] Please see Figures 3 to 5 , Figures 3 to 5 yes Figure 2A cross-sectional structural diagram of the phase change memory during its fabrication process.

[0035] See Figure 3 A substrate 10 is provided, on which a plurality of first contacts 31 and a first sub-conductive layer 41a are formed; a mask layer 81 and a mask pattern 82 are formed on the first sub-conductive layer 41a.

[0036] An exemplary material for the first contact 31 includes tungsten, and an exemplary material for the first sub-conductive layer 41a includes tungsten. The material of the mask layer 81 may include a stacked silicon nitride layer, a diamond layer, and a silicon oxynitride layer. The formation process of the first sub-conductive layer 41a includes a deposition process.

[0037] See Figure 4 Using the mask pattern 82 as a mask, the mask layer 81 is etched to form a patterned mask layer; using the patterned mask layer as a mask, the first sub-conductive layer 41a is etched to form multiple first sub-conductive lines 41; the residue of the patterned mask layer is removed by a wet etching process; and an insulating layer 90 is filled between adjacent first sub-conductive lines 41. The formation process of the insulating layer 90 includes a deposition process and a polishing process (e.g., chemical mechanical polishing), and the material of the insulating layer 90 includes silicon oxide.

[0038] See Figure 5 A second sub-conductive layer 42a and a storage stack 60a are formed on the insulating layer 90.

[0039] See Figure 2 The storage stack 60a and the second sub-conductive layer 42a are etched to form a storage cell layer and a second sub-conductive line 42; a second conductive layer is formed on the storage cell layer; the second conductive layer and the storage cell layer are etched to form multiple second conductive lines 70 and multiple storage cells 60; and a heat insulation layer 61 is filled between adjacent second conductive lines 70 and adjacent storage cells 60.

[0040] It should be noted that the insulating layer filling the spaces between the first sub-conductive lines 41 and the material filling the spaces between the second sub-conductive lines 42 are the same as the material filling the spaces between the memory cell layers, both being heat insulation layers 61. The insulating layer is made of silicon oxide, while the heat insulation layer 61 is made of organosiloxane; their functions are different.

[0041] exist Figure 1 In this embodiment, the first sub-conductive line is formed in the fabrication process of the lower storage cell C1, and the second sub-conductive line is formed in the fabrication process of the upper storage cell C2.

[0042] exist Figures 3 to 5 In the process, in order to be compatible with Figure 1The fabrication process of the phase change memory is compatible. The first sub-conductive line 41 is fabricated separately, and the second sub-conductive line 42 is fabricated together with the memory cell layer. However, the following technical defects exist: 1) Due to the similar etching choices of the patterned mask layer (including silicon nitride) and the first sub-conductive layer 41a (tungsten), the etching process results in poor morphology of the first sub-conductive line 41 formed by the etching process because the etching rate of silicon nitride is relatively fast in both the lateral and longitudinal directions. Furthermore, the subsequent deposition of the insulating layer 90 between the first sub-conductive lines 41 and the polishing process can easily lead to voids between the first sub-conductive lines 41; 2) Since the material of the first contact 31 is also tungsten, the top of the first contact 31 is easily over-etched and damaged during the etching process of the first conductive layer 41a; 3) During the etching process of the second conductive layer, alignment errors between the second sub-conductive line 42 and the first sub-conductive line 41 can easily occur, leading to leakage; 4) The process of forming the insulating layer 90 can easily cause oxidation of the first sub-conductive line 41; 5) When removing the residue of the patterned mask layer by wet etching, the first sub-conductive line is easily damaged because the etching choices of silicon nitride and tungsten are relatively similar.

[0043] Based on this, embodiments of this application provide a method for forming a phase-change memory. Please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for forming a phase-change memory (PCM) according to some embodiments of this application. The method for forming the PCM includes: Step S1: Provide a substrate; Step S2: Form a first contact and an insulating layer on the first contact on the substrate; Step S3: Etch the insulating layer to form a groove that exposes the first contact point; Step S4: A first conductive line connected to the first contact is formed in the groove.

[0044] In the phase-change memory formation method of this application embodiment, an insulating layer is first formed on the first contact, then the insulating layer is etched to form a groove, and finally a first conductive line connected to the first contact is formed in the groove. Therefore, the method of forming the first conductive line in this application does not require etching of tungsten, so the morphology of the first conductive line can be improved, the width uniformity of the first conductive line can be increased, and voids can be reduced; at the same time, the over-etching of the first contact point can be improved to reduce damage to the first contact point, thereby improving the resistance.

[0045] In addition, by forming the first conductive line within the groove, it is possible to simultaneously form Figure 2In this embodiment, there is no alignment issue between the first and second sub-conductive wires, thus resolving the leakage problem. Furthermore, since the insulating layer is formed before the first conductive wire, the insulation layer formation process does not cause oxidation to the first conductive wire.

[0046] Furthermore, since the mask layer is formed on the insulating layer, the first conductive line will not be damaged when the patterned mask layer is removed by wet etching process.

[0047] The following combination Figures 7 to 13 The method for forming a phase-change memory provided in the embodiments of this application will be described. Figures 7 to 13 This is a cross-sectional structural diagram of the phase change memory provided in some embodiments of this application during its formation process.

[0048] Step S1: Provide substrate 10. See [link / reference] Figure 7 .

[0049] Substrate 10 may include a substrate and a complementary metal oxide semiconductor (CMOS) located on the substrate. The CMOS may include an interconnect metal layer M, and an exemplary material for the interconnect metal layer M includes copper.

[0050] Step S2: A first contact 31 and an insulating layer 90 located on the first contact 31 are formed on the substrate 10. See also Figure 7 and Figure 8 .

[0051] In some embodiments, in order to be consistent with Figure 1 The upper storage stack D2 in the two-layer stacked structure is compatible with the process. The first contact 31 includes a first contact segment 311 and a second contact segment 312. The second contact segment 312 is connected to the first contact segment 311 in the thickness direction of the substrate 10. The first contact segment 311 is located between the interconnect metal layer M and the second contact segment 312.

[0052] The method for forming the first contact 31 includes: forming a first sub-dielectric layer on the substrate 10; etching the first sub-dielectric layer to form a first sub-contact hole; forming a first contact segment 311 within the first sub-contact hole; forming a second sub-dielectric layer on the first contact segment 311 and the first sub-dielectric layer; etching the second sub-dielectric layer to form a second sub-contact hole; and forming a second contact segment 312 within the second sub-contact hole that connects to the first contact segment 311. In other words, the first contact 31 is formed through two etching processes to connect with... Figure 1The contact process of the WL character line is compatible. The first and second sub-dielectric layers together form dielectric layer 20.

[0053] The formation processes of the first and second sub-dielectric layers can include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) methods such as thermal oxidation, evaporation, sputtering, and other methods. The exemplary materials for the first and second sub-dielectric layers include silicon oxide.

[0054] The insulating layer 90 is formed on the dielectric layer 20, and the process of the insulating layer 90 includes any of the above-described deposition processes.

[0055] Step S3: Etch the insulating layer 90 to form a groove 91 exposing the first contact 31. See also Figures 8 to 10 .

[0056] See Figure 8 A mask layer 81 and a mask pattern 82 located on the mask layer 81 are formed on the insulating layer 90.

[0057] In some embodiments, the mask pattern 82 includes a photoresist pattern or a dielectric block, wherein the photoresist pattern may be formed by a photolithography process, the dielectric block may be formed by a self-aligned double patterning (SADP) process, and the material of the dielectric block may include silicon oxide.

[0058] In some embodiments, the mask layer 81 may include a diamond layer and a silicon oxynitride layer on the diamond layer. This multilayer structure of the mask layer 81 can improve the conformality of pattern transfer.

[0059] See Figure 9 Using the mask pattern 82 as a mask, the mask layer 81 and the insulating layer 90 are etched to form a patterned mask layer and a groove 91; the residual patterned mask layer on the insulating layer 90 is removed.

[0060] It should be noted that the opening in the mask pattern 82 is aligned with the first contact 31, so the first conductive line formed subsequently can be aligned and connected with the first contact 31.

[0061] In some embodiments, such as Figure 8As shown, the method for forming the phase-change memory further includes forming a stop layer 83 on the first contact 31 before forming the insulating layer 90. In this embodiment, the method for forming the groove 91 includes the following steps.

[0062] See Figure 9 The insulating layer 90 is etched, and the etching process stops on the stop layer 83. Specifically, stopping the etching process to form the groove 91 on the stop layer 83 improves the consistency of the groove 91 depth, thereby improving the consistency of the first conductive line thickness.

[0063] The material of the stop layer 83 may include silicon nitride, because silicon nitride has a large etching selectivity ratio with the silicon oxide of the insulating layer 90. During the etching process of the insulating layer 90, the etching process can stop well on the stop layer 83. Furthermore, the stop layer 83 can also prevent the etching process that forms the groove 91 from affecting the first contact 31.

[0064] See Figure 10 The stop layer 83 exposed by the groove 91 is etched to form the groove 91 that penetrates the insulating layer 90 and the stop layer 83.

[0065] In some embodiments, phosphoric acid can be used for wet cleaning because phosphoric acid has a high etching selectivity for the first contact 31 (tungsten) and the insulating layer 90 (silicon oxide), thus reducing damage to the first contact 31 and the insulating layer 90.

[0066] Step S4: A first conductive line 40, connected to the first contact 31, is formed within the groove 91. (See also...) Figure 11 and Figure 12 .

[0067] It should be noted that, since the groove 91 in the insulating layer 90 is used to fill the first conductive line 40, the thickness of the insulating layer 90 is basically equal to the thickness required for the subsequent first conductive line 40.

[0068] See Figure 12 A first conductive layer is formed in the groove 91 and on the surface of the insulating layer 90; the first conductive layer is planarized until the surface of the insulating layer 90 is exposed to form the first conductive line 40 located in the groove 91.

[0069] In some embodiments, see Figure 11 The method for forming the phase-change memory further includes: forming a barrier layer 43 on the surface of the groove 91 and the surface of the insulating layer 90 before forming the first conductive layer; see also Figure 12In the process of planarizing the first conductive layer, the barrier layer 43 is planarized until the surface of the insulating layer 90 is exposed.

[0070] The barrier layer 43 is located between the first conductive line 40 and the insulating layer 90, and can prevent tungsten in the first conductive line 40 from diffusing into the insulating layer 90. The barrier layer 43 is also located between the first contact 31 and the first conductive line 40, so the barrier layer 43 is a conductive material.

[0071] In some embodiments, the material of the barrier layer 43 may include metal nitrides such as titanium nitride.

[0072] In other embodiments, both the barrier layer 43 and the first conductive layer are made of tungsten. This avoids the barrier layer 43 affecting the conductivity between the first contact 31 and the first conductive line 40, i.e., it does not affect the overall resistance value. In this case, the barrier layer 43 and the first conductive line 40 together serve as word lines, and the sum of the thicknesses of the insulating layer 90 and the barrier layer 43 is equal to the required thickness of the word lines.

[0073] Research has revealed that the diffusion of tungsten in the first conductive wire 40 is caused by fluorine, so fluorine-free tungsten can be used as the barrier layer 43.

[0074] In some embodiments, the formation process of the barrier layer 43 includes a first deposition process, and the precursor used in the first deposition process is fluorine-free. The formation process of the first conductive layer includes a second deposition process, and the precursor used in the second deposition process is fluorine-containing. Thus, the material of the formed barrier layer 43 includes tungsten but is fluorine-free, so it can block tungsten diffusion caused by fluorine in the first conductive line 40.

[0075] In some embodiments, the first deposition process includes atomic layer deposition (ALD), and the second deposition process includes at least one of chemical vapor deposition (CVD) and physical vapor deposition (PVD). Since ALD produces denser tungsten with fewer defects, it improves the barrier performance of the barrier layer 43. Furthermore, the CVD and PVD processes for forming the first conductive line 40 are less expensive, thus reducing process costs.

[0076] In some embodiments, the first conductive lines 40 extend along a first direction X and are spaced apart along a second direction Y. Both the first direction X and the second direction Y are parallel to the surface of the substrate 10, and the first direction X and the second direction Y intersect. The dimension W1 of the first conductive line 40 along the second direction Y is greater than the spacing W2 between two adjacent first conductive lines 40.

[0077] Because in Figure 8 and Figure 9In the etching process, the opening in the mask pattern 82 is pre-aligned with the position of the first conductive line 40, so the size of the opening in the mask pattern 82 is the same as that of W1. And... Figure 3 and Figure 4 In the etching process, the opening in the mask pattern 82 is pre-aligned with the adjacent first conductive line 40, so the opening size in the mask pattern 82 is the same as W2. Since W1 > W2, therefore... Figure 8 and Figure 9 The etching process reduces the aspect ratio and increases the etching window, thus lowering the difficulty of the etching process.

[0078] See Figure 13 The method for forming the phase-change memory further includes: forming a memory stack 60a on the insulating layer 90 and the first conductive line 40; etching the memory stack 60a to form a memory cell layer connected to the first conductive line 40; forming a second conductive layer on the memory cell layer; and etching the second conductive layer and the memory cell layer to form multiple second conductive lines 70 and multiple memory cells 60.

[0079] The memory stack 60a may include a first electrode layer, an initial gate layer, a second electrode layer, an initial memory layer, and a third electrode layer stacked (from bottom to top). The extension direction of the memory cell layer is the same as the extension direction of the first conductive line 40. After the second conductive layer is formed, etching is performed in another direction, thereby etching the second conductive layer into multiple second conductive lines 70 and etching the multiple memory cell layers into multiple memory cells 60. The extension direction of the second conductive lines 70 intersects the extension direction of the first conductive lines 40, for example, they are perpendicular to each other. The first conductive line 40 serves as a word line, and the second conductive line 70 serves as a bit line.

[0080] In some embodiments, the phase-change memory includes an array region 101 and a contact region 102. The method for forming the phase-change memory further includes: removing the memory cell layer and the first conductive line 40 located in the contact region 102 before forming the second conductive layer; forming a second contact 32 within the contact region 102, the second contact 32 being connected to a first contact 31 located in the contact region 102. After forming the second conductive layer, the second conductive layer is connected to the second contact 32; after forming the second conductive line 70, the second conductive line 70 is connected to the second contact 32.

[0081] In some embodiments, the thickness of the insulating layer 90 is 1.5 to 2.5 times the thickness of the second conductive layer.

[0082] Since the word line thickness in the top-only architecture of this application is approximately twice the bit line thickness, i.e., the sum of the thicknesses of the first and second sub-conductive lines is approximately twice the thickness of the second conductive line 70, the thickness of the insulating layer 90 is 1.5 to 2.5 times, for example, twice, the thickness of the second conductive layer. This ensures that the storage cell 60 of the phase-change memory achieves... Figure 1 Electrical performance of the upper-middle layer storage unit C2.

[0083] This application also provides a phase change memory, which is formed by the phase change memory formation method in any of the above embodiments.

[0084] Please see Figure 13 The phase-change memory 100 includes a first conductive line 40, a storage unit 60, and a second conductive line 70. The first conductive line 40 and the second conductive line 70 intersect in opposite directions. The storage unit 60 is located between the first conductive line 40 and the second conductive line 70, and at the intersection of the first conductive line 40 and the second conductive line 70. The first conductive line 40 includes overlapping first and second sub-conductive lines.

[0085] The phase-change memory 100 further includes an insulating layer 90 located between adjacent first conductive lines 40, that is, between adjacent first sub-conductive lines and between adjacent second sub-conductive lines. The insulating layer 90 is made of silicon oxide and is used to electrically isolate the adjacent first conductive lines 40.

[0086] In some embodiments, when the first conductive line 40 is a word line, the second conductive line 70 is a bit line; when the first conductive line 40 is a bit line, the second conductive line 70 is a word line.

[0087] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0088] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0089] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0090] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for forming a phase-change memory, characterized in that, include: Provide substrate; A first contact and an insulating layer located on the first contact are formed on the substrate; The insulating layer is etched to form a groove that exposes the first contact point; A first conductive line is formed within the groove to connect with the first contact.

2. The method for forming a phase-change memory according to claim 1, characterized in that, It also includes forming a stop layer on the first contact point before forming the insulating layer; the method for forming the groove includes: The insulating layer is etched, and the etching process stops at the stop layer; The stop layer exposed by the groove is etched to form the groove that penetrates the insulating layer and the stop layer.

3. The method for forming a phase-change memory according to claim 1, characterized in that, The method for forming the first conductive line includes: A first conductive layer is formed within the groove and on the surface of the insulating layer; The first conductive layer is planarized until the surface of the insulating layer is exposed to form the first conductive line located within the groove.

4. The method for forming a phase-change memory according to claim 3, characterized in that, Also includes: Before forming the first conductive layer, a barrier layer is formed on the surface of the groove and the surface of the insulating layer; In the process of planarizing the first conductive layer, the barrier layer is planarized until the surface of the insulating layer is exposed.

5. The method for forming a phase-change memory according to claim 4, characterized in that, Both the barrier layer and the first conductive layer are made of tungsten. The process for forming the barrier layer includes a first deposition process, and the precursor used in the first deposition process is fluorine-free. The formation process of the first conductive layer includes a second deposition process, and the precursor of the second deposition process contains fluorine.

6. The method for forming a phase-change memory according to claim 5, characterized in that, The first deposition process includes atomic layer deposition, and the second deposition process includes at least one of chemical vapor deposition and physical vapor deposition.

7. The method for forming a phase-change memory according to claim 3, characterized in that, Also includes: A storage stack is formed on the insulating layer and the first conductive line; The memory stack is etched to form a memory cell layer connected to the first conductive line; A second conductive layer is formed on the memory cell layer; The second conductive layer and the memory cell layer are etched to form multiple second conductive lines and multiple memory cells; The thickness of the insulating layer is 1.5 to 2.5 times the thickness of the second conductive layer.

8. The method for forming a phase-change memory according to claim 7, characterized in that, The phase-change memory includes an array region and a contact region, and the method for forming the phase-change memory further includes: Before forming the second conductive layer, the memory cell layer and the first conductive line located in the contact area are removed; A second contact is formed within the contact area, and the second contact is connected to the first contact located in the contact area; After the second conductive layer is formed, the second conductive layer is connected to the second contact.

9. The method for forming a phase-change memory according to claim 1, characterized in that, The first conductive line extends along a first direction and is spaced apart along a second direction. Both the first direction and the second direction are parallel to the surface of the substrate, and the first direction intersects the second direction. The dimension of the first conductive line along the second direction is greater than the spacing between two adjacent first conductive lines.

10. A phase-change memory, characterized in that, It is formed by the method of forming a phase change memory according to any one of claims 1 to 9.

Images