Integrated circuit for modifying address bits for fluid ejection devices

Abstract

An integrated circuit can include a first contact to receive first address bits from a host controller and a second contact to transmit second address bits to a fluid ejection device, the second address bits based on the first address bits.

Description

Background Technology

[0001] A fluid jetting device deposits a printing fluid (such as ink, resin, biomaterials, or other substances) onto a substrate (such as paper, powder, support structure, etc.) for printing in two or three dimensions. A print die dispenses the printing fluid for printing. An integrated circuit can connect to both the printer control interface and the print die interface to receive and transmit signals to both.

[0002] Certain ink cartridges and / or fluid jet units (also known as printheads) can be compatible with certain host printers through certain coding or configurations. Furthermore, the cartridges may be configured with memory for updated printing materials (e.g., reagents, liquids, ink levels). Providing additional or alternative memory functionality associated with the ink cartridges and / or fluid jet units may be advantageous. Providing alternative solutions for certain functions (such as the aforementioned coding, configuration, and / or printing material levels) may also be advantageous. Attached Figure Description

[0003] Figure 1A This is a block diagram of an example integrated circuit.

[0004] Figure 1B It includes control logic. Figure 1A A block diagram of an integrated circuit.

[0005] Figure 2 It includes host-side contact arrays and device-side contact arrays. Figure 1B A block diagram of an integrated circuit.

[0006] Figure 3 The diagram shows Figure 2 The host-side contact array.

[0007] Figure 4 The diagram shows Figure 2 The device side contact array.

[0008] Figure 5 An example fluid structure assembly is illustrated, which includes a fluid structure, a fluid jet device having a fluid jet core, and interconnecting circuitry.

[0009] Figure 6A The illustration shows an example printed part, which includes... Figure 5 Fluid structure components.

[0010] Figure 6B The diagram shows Figure 6A Example printed parts and Figure 2 Integrated circuits.

[0011] Figure 7This is a block diagram illustrating a data packet used to transmit information to a fluid jetting device.

[0012] Figure 8 It's a diagram. Figure 7 A block diagram of an example repeating address sequence of data packets.

[0013] Figure 9 The diagram illustrates the modifications and Figure 8 An example of generating a second data packet associated with a second repeating address sequence.

[0014] Figure 10 The diagram illustrates the modifications. Figure 7 An example of a data packet used to remove random data.

[0015] Figure 11 The illustration shows the identification based on clock idle time or a predetermined amount of time between non-random data in subsequent data packets. Figure 7 An example of the end of a data packet.

[0016] Figure 12 The diagram illustrates the use of predefined bits for identification. Figure 7 The non-random data of the package.

[0017] Figure 13 The illustration shows the use of a mask for identification. Figure 7 Example methods for generating non-random data packets.

[0018] Figure 14 This is a flowchart of the example method access protocol.

[0019] Figure 15 The illustration shows an example configuration register write protocol.

[0020] Figure 16 The illustration shows an example status register access protocol.

[0021] Figure 17 An example integrated circuit is illustrated, which enables the host to treat a fluid jet device with a second address offset as if it were a fluid jet device with a first address offset.

[0022] Figure 18 The illustration shows an example integrated circuit that maps bits of a fluid jet device to other bits of that fluid jet device.

[0023] Figure 19 The figure illustrates an example response curve for incremental programming of non-volatile memory bits.

[0024] Figure 20 The illustration shows an example integrated circuit that responds to incremental write and read signals from the host.

[0025] Figure 21 The figure illustrates an example voltage response curve used for parallel bit reads.

[0026] Figure 22 The figure illustrates an example current response curve used for parallel bit reads.

[0027] Figure 23 The illustration shows an example integrated circuit that responds to parallel bit reads from the host.

[0028] The foregoing and other features of this disclosure will become clear from the accompanying drawings, the following description, and the appended claims. It should be understood that these drawings depict only a few examples according to this disclosure and are therefore not intended to limit the scope of the disclosure, which will be described more specifically and in detail using the accompanying drawings. Detailed Implementation

[0029] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description. In the drawings, like symbols typically identify like parts unless the context otherwise requires. The illustrative examples set forth in the detailed description, drawings, and claims are not intended to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter set forth herein. It will be readily understood that, as generally described herein and illustrated in the drawings, aspects of this disclosure can be arranged, substituted, combined, and designed in a variety of different configurations, all of which are explicitly considered and are part of this disclosure.

[0030] This disclosure relates to printing components. A printing component may include a reservoir to supply ink to a printhead. A printing component may be a printhead. A printing component may be a print cartridge. A printing component may include an integrated circuit for communication with a host printer. The integrated circuit may be part of the printhead or may be separate from the printhead. A printhead may include at least one fluid jetting die.

[0031] The printing component can be any part of a printing system, such as a replaceable print cartridge, or a component of an ink cartridge, such as a fluid jetting device (e.g., a printhead) or other integrated circuit associated with the ink cartridge. The printing component can include printing elements for dispensing printing fluid and reservoirs for storing the printing fluid. The printing fluid can include any 2D or 3D printing agent comprising ink for printing on a medium such as paper (2D) or (e.g., powdered) building material (3D). The printing fluid can include a dispensable fluid to be dispensed with relatively high precision (in terms of volume and / or position) for applications beyond 2D or 3D imaging, including but not limited to forensic, laboratory, or pharmaceutical applications.

[0032] In one example of this disclosure, an integrated circuit is an intermediate circuit configured to detect and / or respond to and / or transmit certain host printer signals. These integrated circuits can be used to modify, add to, or update certain functions relating to an associated fluid jet device or cartridge. It should be noted that the functions disclosed in this disclosure can also be implemented within the fluid jet device, rather than separately. The integrated circuit can be implemented as part of the fluid jet die or printhead. The integrated circuit can be part of the original OEM printhead or part of a third-party alternative printhead that is not an OEM. Unless otherwise disclosed, the integrated circuits disclosed herein can be part of a fluid jet device or printhead.

[0033] In cases where the integrated circuit (IC) is separate from the fluid jetting device, signals can be transmitted to the individual fluid jetting device. The IC can be attached to or is attachable to the ink cartridge, whereby the cartridge may include a plastic body (e.g., including a memory), a fluid jetting device, and interconnect circuitry for routing signals between the host and the fluid jetting device. The IC can be communicatively connected to the ink cartridge's interconnect circuitry and / or the fluid jetting device. It may include thin circuitry such as a thin PCB or flexible circuitry to allow it to be attached over the ink cartridge's interconnect circuitry, located between the interconnect circuitry and the printer-side (carriage) interconnect circuitry. In other examples, the IC may be part of the fluid jetting device.

[0034] In one example, the integrated circuit (IC) can receive signals from a host controller (such as an ASIC print controller for a printer) and respond to the host controller with response signals, for example, replacing the associated fluid jet device memory. In another example, the IC attached to the print cartridge can receive signals from the host controller and modify these signals for transmission to the fluid jet device of the print cartridge. The IC can modify signals from the fluid jet device and modify these signals for transmission to the host controller. The IC can allow some signals to pass between the host controller and the printing components without alteration. The IC can be a thin circuit attached to the print cartridge, having a device-side contact array connected to the fluid jet device and a host-side contact array connected to the host controller when the print cartridge is in the mounted state.

[0035] An integrated circuit (IC) can be attached to the print cartridge to modify signals from the host controller and / or host (such as a printer) to the fluid jet device, thereby modifying the output from the fluid jet device to the host; or, it can directly output signals generated and / or stored by the IC to the host. Different types of fluid jet devices may be compatible with certain host families but incompatible with others. Furthermore, the fluid jet device may include memory bits indicating the usage status of the fluid jet device, such as indicating the consumed and / or remaining fluid level. An IC attached to the print cartridge can provide and / or modify signals to / from the host, causing the host to perceive the cartridge as compatible and / or full. Additionally, a host, such as a printer, can be configured to analyze signals from the fluid jet device to verify that the cartridge is in good condition and / or operating as expected and / or compatible. An IC attached to the print cartridge can provide and / or modify signals to / from the host, causing the host to perceive the cartridge with the IC as the same as a compatible and / or full cartridge, or a cartridge in good condition and / or operating as expected. In the example, the printer may indicate a low ink level based on the printer's estimate of the ink level in the print cartridge. In this example, if the original fluid jet device is associated with a low-fill original print cartridge, but that cartridge has been refilled to the level associated with a high-fill print cartridge, the integrated circuit can modify the signal between the fluid jet device and the host, causing the host to treat the fluid jet device as a high-fill print cartridge.

[0036] Figure 1A This is a block diagram of an example integrated circuit 100. The integrated circuit 100 may have a first contact 101 and a second contact 102. The first contact 101 is used to electrically connect the integrated circuit 100 to a host controller. The first contact 101 corresponds to a contact on the host controller. The first contact 101 is used to transmit signals between the integrated circuit 100 and the host controller. The second contact 102 is used to electrically connect the integrated circuit 100 to a fluid injection device. The second contact 102 corresponds to a contact on the interconnect circuit of the fluid injection device. The second contact 102 is used to transmit signals between the integrated circuit 100 and the fluid injection device.

[0037] Figure 1B It includes control logic. Figure 1A A block diagram of the integrated circuit 100. Control logic 105 controls the signals transmitted by the integrated circuit 100. Control logic 105 receives signals from a first contact 101 and / or a second contact 102. In some embodiments, control logic 105 analyzes the signals received at the first contact 101 and / or the second contact 102. In some embodiments, control logic 105 modifies the signals received at the first contact 101 and / or the second contact 102. In some embodiments, control logic generates signals to be transmitted at the first contact 101 and / or the second contact 102.

[0038] Note that it is possible that the first contact 101 and the second contact 102 form a single integral contact, whereby, as controlled by logic 105, the same integral contact is used on the one hand to transmit signals to / from the host, and on the other hand to transmit signals to / from the fluid jetting device. Certain other examples of the integrated circuits of this disclosure can intercept signals from the host and communicate with the host without receiving or transmitting signals to or from the fluid jetting device, thus effectively eliminating the need for a device-side contact array 120.

[0039] Figure 2 It includes a host-side contact array 110 and a device-side contact array 120. Figure 1B A block diagram of an integrated circuit. In some embodiments, the host-side contact array 110 includes a first contact 101. In some embodiments, the device-side contact array 120 includes a second contact 102. The host-side contact array 110 is used to electrically connect the integrated circuit 100 to a host controller. The host-side contact array 110 corresponds to a contact array on the host controller. The host-side contact array 110 is used to transmit signals between the integrated circuit 100 and the host controller. The host-side contact array 110 includes a plurality of contacts, each contact being used to receive and / or transmit different electrical signals. In some embodiments, the host-side contact array 110 receives and / or transmits combinations of signals on the plurality of contacts. The device-side contact array 120 is used to electrically connect the integrated circuit 100 to a fluid jetting device. The device-side contact array 120 corresponds to a contact array on the interconnect circuitry of the fluid jetting device. The device-side contact array 120 is used to transmit signals between the integrated circuit 100 and the fluid jetting device. The device-side contact array 120 includes a plurality of contacts, each for receiving and / or transmitting different electrical signals. In some embodiments, the device-side contact array 120 receives and / or transmits combinations of signals on the plurality of contacts.

[0040] Integrated circuit 100 can receive signals at host-side contact array 110 and allow the received signals to be transmitted to the fluid jetting device at device-side contact array 120. In this way, the integrated circuit allows signals from the host controller to pass through to the fluid jetting device. Integrated circuit 100 can receive signals at host-side contact array 110 and modify the received signals and / or generate different signals for transmission at the device-side contact array. In this way, integrated circuit 100 intercepts signals from the host controller intended for use with the fluid jetting device. Integrated circuit 100 can allow signals received at host-side contact array 110 to be transmitted at device-side contact array 120 and generate additional signals in parallel at the device-side contact array. In this way, integrated circuit overwrites signals from the host controller to the fluid jetting device. Similarly, integrated circuits can process signals by allowing signals from the fluid jetting device intended for use with the host controller to pass through, intercepting them, and / or overwriting them.

[0041] Note that it is possible that certain relative contacts of contact arrays 110, 120 form integral contacts for transmitting signals to / from the host and to / from the fluid jetting device as controlled by logic 105. Certain other examples of the integrated circuits of this disclosure may intercept signals from the host and communicate with the host without receiving or transmitting signals to or from the fluid jetting device, thus effectively eliminating the need for a second contact 102.

[0042] Integrated circuit 100 can be a thin circuit. In some embodiments, integrated circuit 100 is a thin printed circuit board (PCB). Integrated circuit 100 can be thin enough to fit between the host controller contact array and the cartridge interconnect circuit contact array without interfering with the relative positions of the host controller contacts and the interconnect circuit contacts. Without integrated circuit in between, the host controller contacts and the cartridge interconnect circuit contacts are in permanent contact in the cartridge's mounted state. The interconnect portion of integrated circuit 100 can be thin enough to be placed between the host controller and the interconnect circuit in the mounted state. In some embodiments, the interconnect portion of integrated circuit 100 (including routing and support / insulating substrate) has a maximum thickness of less than two millimeters or less than one millimeter.

[0043] As discussed herein, integrated circuit 100 can be used to modify the signal between the host controller and the fluid jetting device, such that the host controller recognizes the fluid jetting device as a compatible and / or unused (or less frequently used) fluid jetting device in good condition and / or operating as intended. Therefore, integrated circuit 100 may need to be thin enough to fit between the host controller and the fluid jetting device without requiring modification to the host structure or host signals. The integrated circuit may include flexible circuitry with contacts on both sides, one on the host side and the other on the device side, thereby allowing an insulating layer between some host-side and device-side circuitry (e.g., contacts).

[0044] Figure 3 The diagram shows Figure 2 The host-side contact array 110 may include contacts 112a-112k. The host-side contact array 110 may include a first contact 112a, a second contact 112b, a third contact 112c, a fourth contact 112d, a fifth contact 112e, a sixth contact 112f, a seventh contact 112g, an eighth contact 112h, a ninth contact 112i, a tenth contact 112j, and an eleventh contact 112k. Each of contacts 112a-112k may correspond to a host controller contact on the host controller contact array.

[0045] The first contact 112a can be a pen detection contact, engaging pen detection logic (e.g., a pull-down device with a transistor). In use, the first contact 112a can have a voltage from 0 V to 3.3 V. The second contact 112b can be a sensing and / or analog read signal contact, a low-voltage input / output contact for temperature measurement, strain gauge sensing, and / or non-volatile memory reads. The second contact 112b can provide an analog data signal in response to a data read signal from the host. The second contact can be connected to the memory of an integrated circuit. In operation, the second contact 112b can have a voltage from 0 V to 3.3 V. In operation, the second contact 112b can transmit and / or receive analog signal values ​​between 0 V and 3.3 V. The third contact 112c can be a mode contact, providing a low-voltage input signal for selecting between a data loading mode and a register access mode. The third contact 112c can be connected to control logic 105. In operation, the third contact 112c can have a voltage from 0 V to 3.3 V. In operation, the third contact 112c can transmit and / or receive logic low and logic high signals. In some examples, the logic low signal can be approximately 0 V and the logic high signal can be approximately 3.3 V. In some examples, the logic low signal can be approximately 3.3 V and the logic high signal can be approximately 0 V. The fourth contact 112d can be a clock contact, which is a low-voltage input signal used to provide a clock signal, to load transmit pulse group data, and for register access. The fourth contact 112d can be connected to control logic 105. In operation, the fourth contact 112d can have a voltage from 0 V to 3.3 V. The fifth contact 112e can be a data select contact. The data select contact can be a low-voltage input / output signal contact used to receive input to load pulse data packets and configure register data. The fifth contact 112e can be connected to control logic 105. In operation, the data selection contact can be used to send an output from integrated circuit 100 to the host controller contact array when serially shifting out status register data. In operation, the fifth contact 112e can have a voltage from 0 V to 3.3 V. In operation, the fifth contact 112e can transmit and / or receive logic low and logic high signals. In some examples, the logic low signal can be approximately 0 V, and the logic high signal can be approximately 3.3 V. In some examples, the logic low signal can be approximately 3.3 V, and the logic high signal can be approximately 0 V.

[0046] The sixth contact 112f can be a low-voltage ground contact. The seventh contact 112g can be a high-voltage power input contact. In operation, the seventh contact 112g can have a voltage from 0 volts to 35 volts. The eighth contact 112h can be a high-voltage ground contact. The seventh contact 112g and / or the eighth contact 112h can be connected to the fluid ejection device to transmit a power signal, at least when assembled into the cartridge. The ninth contact 112i can be a low-voltage power input contact. In operation, the ninth contact 112i can have a voltage from 0 volts to 5.7 volts (±3%). The sixth contact 112f and / or the ninth contact 112i can be connected to control logic 105, and / or at least when assembled into the cartridge, selectively transmit signals to the fluid ejection device as controlled by control logic 105. The tenth contact 112j can be a transmitting contact. In operation, the tenth contact 112j can transmit and / or receive logic low and logic high signals of approximately 0 V and approximately 3.3 V, respectively. The tenth contact 112j can be connected to control logic 105. The eleventh contact 112k can be a reset contact. The eleventh contact 112k can transmit and / or receive logic low and logic high signals of approximately 0 V and approximately 3.3 V, respectively. The eleventh contact 112k can be connected to control logic 105 and / or, when assembled to a cartridge, connected to a fluid ejection device.

[0047] The voltages discussed herein can be DC voltages. Furthermore, the voltages discussed herein can be approximate values. The voltages described in conjunction with the individual contacts 112a-112k can be the voltages applied to contacts 112a-112k during operation. The voltages described herein can be analog or digital voltages, such as the aforementioned logic high and logic low voltages. Furthermore, the voltages used for logic high and logic low can depend on the voltages used by the host controller. In one example, the host controller may use approximately 0 V for logic low and approximately 3.3 V for logic high. In another example, the host controller may use approximately 3.3 V for logic low and approximately 0 V for logic high.

[0048] The first to fifth contacts 112a-112e can be in the first column of the host-side contact array 110. The sixth to eleventh contacts 112f-112k can be in the second column of the host-side contact array 110. The first and second columns can correspond to the contact columns on the interconnection circuit for the fluid injection device and / or the contact columns on the host controller contact array. The first and second contact columns can be arranged along straight parallel lines.

[0049] In some implementations, the host-side contact array 110 does not include all contacts 112a-112k. In one example, the integrated circuit includes... Figure 3The contact array 110 comprises a subset of the contacts. In some embodiments, the host-side contact array 110 includes only contacts corresponding to signals that the integrated circuit 100 needs to receive and / or transmit. On the other hand, the integrated circuit 100 may include all indicated contacts, thereby potentially including contacts that do not require further processing by the integrated circuit 100 (i.e., switching, modification, calculation, data storage, response, etc.), which will directly allow signals to pass in either direction between the host and the fluid injection device. The integrated circuit 100 may be configured to "use" (i.e. process) signals from only a portion of the contacts 112a-112k. The integrated circuit 100 may require a first subset of contacts 112a-112k for a first function and a second subset of contacts 112a-112k for a second function. Therefore, the host-side contact array 110 may include or "use" some of the contacts 112a-112k depending on the function performed by the integrated circuit 100, as discussed herein. In this example, the host-side contact array 110 includes only the second to fifth contacts 112b-112e and the tenth contact 112j, because these contacts are required to receive signals for the memory access protocol, as discussed herein. In this example, the host-side contact array 110 does not include the seventh contact 112g, because the integrated circuit can receive power through different contacts.

[0050] In some implementations, the host-side contact array 110 may include additional contacts. An example of the host-side contact array 110 shown includes eleven contacts, with the fifth contact 112e corresponding to a single data contact. A single data contact can be used in a fluid jetting apparatus having a single fluid jetting die (such as a black ink fluid jetting die). However, a fluid jetting apparatus for color printing may include multiple fluid jetting dies, such as three fluid jetting dies, thus requiring three different data contacts. The host-side contact array 110 may include additional contacts corresponding to additional fluid jetting dies. In the example, the host-side contact array 110 may include thirteen contacts, three of which correspond to data contacts.

[0051] Figure 4 The diagram shows Figure 2The device-side contact array 120 may include contacts 122a-122k. The device-side contact array 120 may include a first contact 122a, a second contact 122b, a third contact 122c, a fourth contact 122d, a fifth contact 122e, a sixth contact 122f, a seventh contact 122g, an eighth contact 122h, a ninth contact 122i, a tenth contact 122j, and an eleventh contact 122k. Each of contacts 122a-122k may correspond to an interconnect circuit contact on an interconnect circuit contact array. The device-side contact array 120 may be a mirror image of the host-side contact array 110, because the interconnect circuit contact array is a mirror image of the host controller contact array.

[0052] The first contact 122a can be a pen detection contact, engaging pen detection logic (e.g., a pull-down device with a transistor). In operation, the first contact 122a can have a voltage from 0 V to 3.3 V. The second contact 122b can be a sensing and / or analog read signal contact, a low-voltage input / output contact for temperature measurement, strain gauge sensing, and non-volatile memory reads. The second contact 122b can provide an analog data signal in response to a data read signal from the host. The second contact can be connected to the memory of an integrated circuit. In operation, the second contact 122b can have a voltage from 0 V to 3.3 V. In operation, the second contact 122b can transmit and / or receive analog signal values ​​between 0 V and 3.3 V. The third contact 122c can be a mode contact, transmitting and / or receiving a low-voltage input signal for selecting between a data loading mode and a register access mode. The third contact 122c can be connected to control logic 105. In operation, the third contact 122c can have a voltage from 0 V to 3.3 V. In operation, the third contact 122c can transmit and / or receive logic low and logic high signals. In some examples, the logic low signal can be approximately 0 V and the logic high signal can be approximately 3.3 V. In some examples, the logic low signal can be approximately 3.3 V and the logic high signal can be approximately 0 V. The fourth contact 122d can be a clock contact, which is a low-voltage input signal used to provide a clock signal, load transmit pulse group data, and access registers. The fourth contact 122d can be connected to control logic 105. In operation, the fourth contact 122d can have a voltage from 0 V to 3.3 V. The fifth contact 122e can be a data select contact. The data select contact can be a low-voltage input / output signal contact used to receive input to load pulse data packets and configure register data. The fifth contact 122e can be connected to control logic 105. The data selection contact can be used to send an output from integrated circuit 100 to the host controller contact array when serially shifting out status register data. In operation, the fifth contact 122e can have a voltage from 0 V to 3.3 V. In operation, the fifth contact 122e can transmit and / or receive logic low and logic high signals. In some examples, the logic low signal can be approximately 0 V and the logic high signal can be approximately 3.3 V. In some examples, the logic low signal can be approximately 3.3 V and the logic high signal can be approximately 0 V.

[0053] The sixth contact 122f can be a low-voltage ground contact. The seventh contact 122g can be a high-voltage power input contact. In operation, the seventh contact 122g can have a voltage from 0 volts to 35 volts. The eighth contact 122h can be a high-voltage ground contact. The seventh contact 122g and / or the eighth contact 122hh can be connected to the fluid ejection device to transmit a power signal, at least when assembled into the cartridge. The ninth contact 122i can be a low-voltage power input contact. In operation, the ninth contact 122i can have a voltage from 0 volts to 5.7 volts (±3%). The sixth contact 122f and / or the ninth contact 122i can be connected to control logic 105, and / or at least when assembled into the cartridge, selectively transmit signals to the fluid ejection device as controlled by control logic 105. The tenth contact 122j can be a transmitting contact. In operation, the tenth contact 122j can transmit and / or receive logic low and logic high signals of approximately 0 V and approximately 3.3 V, respectively. The tenth contact 122j can be connected to control logic 105. The eleventh contact 122k can be a reset contact. In operation, the eleventh contact 122k can transmit and / or receive logic low and logic high signals of approximately 0 V and approximately 3.3 V, respectively. The eleventh contact 122k can be connected to control logic 105 and / or, when assembled into a cartridge, connected to a fluid ejection device.

[0054] The voltages discussed herein can be DC voltages. Furthermore, the voltages discussed herein can be approximate values. The voltages described in conjunction with the individual contacts 112a-112k can be the voltages applied to contacts 112a-112k during operation. The voltages described herein can be analog or digital voltages, such as the aforementioned logic high and logic low voltages. Furthermore, the voltages used for logic high and logic low can depend on the voltages used by the host controller. In one example, the host controller may use approximately 0 V for logic low and approximately 3.3 V for logic high. In another example, the host controller may use approximately 3.3 V for logic low and approximately 0 V for logic high.

[0055] The first to fifth contacts 122a-122e can be in the first column of the device-side contact array 120. The sixth to eleventh contacts 122f-122k can be in the second column of the device-side contact array 120. The first and second columns can correspond to the contact columns on the interconnection circuit for the fluid injection device and / or the contact columns on the host controller contact array. The first and second contact columns can be arranged along straight parallel lines.

[0056] In some implementations, the device-side contact array 120 does not include all contacts 122a-122k. In one example, the integrated circuit includes... Figure 3The contact array 110 comprises a subset of the contacts. In some embodiments, the device-side contact array 120 includes only contacts corresponding to signals that the integrated circuit 100 needs to receive and / or transmit. On the other hand, the integrated circuit 100 may include all indicated contacts, thereby potentially including contacts that do not require further processing by the integrated circuit 100 (i.e., switching, modification, calculation, data storage, response, etc.), which will directly allow signals to pass in either direction between the host and the fluid jetting device. The integrated circuit 100 may be configured to "use" (i.e. process) signals from only a portion of contacts 112a-112k. The integrated circuit 100 may require a first subset of contacts 122a-122k for a first function and a second subset of contacts 122a-122k for a second function. Therefore, the device-side contact array 120 may include or "use" some of contacts 122a-122k depending on the function performed by the integrated circuit 100, as discussed herein. In this example, the device-side contact array 120 includes only the second to fifth contacts 122b-122e and the tenth contact 122j, because these contacts are required to transmit signals for the memory access protocol, as discussed herein. In this example, the device-side contact array 120 does not include the seventh contact 122g, because the interconnect circuitry can receive power directly from the host controller.

[0057] In some implementations, the device-side contact array 120 may include additional contacts. An example of the device-side contact array 120 shown includes eleven contacts, with the fifth contact 122e corresponding to a single data contact. A single data contact can be used in a fluid jetting apparatus having a single fluid jetting die (such as a black ink fluid jetting die). However, a fluid jetting apparatus for color printing may include multiple fluid jetting dies, such as three fluid jetting dies, thus requiring three different data contacts. The device-side contact array 120 may include additional contacts corresponding to additional fluid jetting dies. In the example, the device-side contact array 120 may include thirteen contacts, three of which correspond to data contacts.

[0058] Figure 5An example fluid structure assembly is illustrated, comprising a fluid structure 140, a fluid injection device 142, and interconnecting circuitry 130. Interconnecting circuitry 130 may include an interconnecting circuit contact array 132. The contacts of interconnecting circuit contact array 132 may be arranged on both sides of a central axis of interconnecting circuit contact array 132. The contacts of interconnecting circuit contact array 132 may correspond to contacts 122a-122k of device-side contact array 120 and / or contacts of host controller contact array. The contacts of interconnecting circuit contact array 132 may be arranged in two columns, one column on a first side of the central axis of interconnecting circuit contact array 132 and a second column on a second side of the central axis of interconnecting circuit contact array 132. The two columns may extend substantially parallel to each other and parallel to the central axis of interconnecting circuit contact array 132. The central axis of the interconnect circuit contact array 132 can be aligned with the fluid jet dies 144 in the mounted state, or aligned with the central fluid jet die of the fluid jet device 142 if the fluid jet device 142 includes multiple fluid jet dies. In the example shown, the contacts of the interconnect circuit contact array 132 are arranged in no more than two columns.

[0059] Figure 6A The illustration shows an example printed part 160, which includes... Figure 5 The printing component 160 may include a molding body 150, interconnect circuitry 130, and a fluid jetting device 140. The molding body 150 may include a reservoir for storing printing fluid. The reservoir may be fluidly connected to the fluid jetting device 140, enabling the fluid jetting device 140 to output printing fluid based on signals received via the interconnect circuitry 130. The printing component 160, in its mounted state, may be positioned relative to its... Figure 6A The illustration is flipped vertically so that the fluid jet device 140 faces downwards (e.g., toward the printing surface).

[0060] Figure 6B The diagram shows the attachment. Figure 6A Printed part 160 Figures 2 to 4Any one of the integrated circuits 100. Interconnect circuits 130 may be stacked on top of integrated circuits 100. Integrated circuits 100 may be stacked on top of interconnect circuits 130 such that the integrated circuit covers the interconnect circuit contact array 132. Integrated circuits 100 may be stacked on top of interconnect circuit contact array 132 such that host-side contact array 110 occupies the position of interconnect circuit contact array 132. In this way, when the print unit 160 is mounted, host-side contact array 110 can contact host controller contact array because interconnect circuit contact array 132 is configured to contact host controller contact array when print unit 160 is mounted. The contacts of host controller contact array can contact host-side contact array 110 and / or interconnect circuit array 132 depending on which contacts are included in host-side contact array 110. As described above, in some cases, certain contacts of host-side contact array 110 can directly contact cartridge contacts 132 to allow signal passage. For example, in some cases, it may be more advantageous to transmit signals directly through the contacts than to leave an opening for the original contacts 132 of the cartridge to contact the host. Therefore, in some embodiments, one or more contacts in the host-side contact array 110 are replaced with holes to allow the contacts of the host controller contact array to directly contact the corresponding contacts of the interconnect circuit contact array 132, and / or one or more contacts in the host-side contact array 110 are replaced with conductive pads to allow the contacts of the host controller contact array to directly contact the corresponding contacts of the interconnect circuit contact array 132.

[0061] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, when integrated circuit 100 is connected to the fluid jetting device and the fluid jetting device is installed in the host device, the first contact 101 can receive a first address bit from the host controller. The second contact 102 can transmit a second address bit to the fluid jetting device. The second address bit can be based on the first address bit. In one example, the second address bit can be obtained by performing a mathematical operation on the first address bit. In another example, the second address bit can be obtained by using a lookup table to map the first address bit to the second address bit.

[0062] The first address bit may include a first address code, and the second address bit may include a second address code. The first address code is used to select a first nozzle circuit of the fluid jetting device, and the second address code is used to select a second nozzle circuit of the fluid jetting device. The first nozzle circuit may be located at a first position on the fluid jetting device, and the second nozzle circuit may be located at a second position on the fluid jetting device. The integrated circuit 100 may receive a first data packet from the host controller at a first contact 101 and transmit a second data packet to the fluid jetting device at a second contact 102. The first data packet and the second data packet respectively include the first address code and the second address code.

[0063] Integrated circuit 100 may include control logic that maps a first address code to a second address code. This control logic may determine a second address bit associated with a second address bit sequence based on a first address bit sequence received from a host controller. The control logic may include at least one of mathematical operations and a lookup table. A second data packet may include a header, a middle portion, and a tail, the header including a first subset of address bits, the tail including a second subset of address bits, and the first and second subsets of address bits including a second address code. The middle portion may include primitive data. Primitives may include a group of nozzle circuits. The primitive data may indicate which primitives the second address code should be applied to. In this way, the second data packet may include information for transmitting instructions for each nozzle circuit. The fluid jetting device may include an array of nozzle circuits to jet droplets from each nozzle circuit in the array, the second address bit being used to select a second nozzle circuit for jetting droplets. The tail may include control bits. The control bits may control the operation of the fluid jetting device, such as heating the fluid jetting device.

[0064] In some implementations, the first data packet and the second data packet include the same primitive bits. The second data packet may be based on the first data packet to include the same primitive bits. Integrated circuit 100 may modify the address bits of the first data packet to generate the second data packet. In some implementations, integrated circuit 100 modifies a first portion of the first packet containing address bits and does not modify a second portion of the packet. In some implementations, integrated circuit 100 modifies the address bits but does not modify the primitive bits.

[0065] In some embodiments, the integrated circuit 100 includes a host-side contact array including a first contact and at least one contact column to contact a corresponding contact column of a host controller for transmitting signals between the integrated circuit and a host printer. The integrated circuit 100 may include a device-side contact array including a second contact. The integrated circuit 100 may include a first clock contact to receive a first clock signal from the host controller and a second clock contact to output a second clock signal to the fluid jetting device. The second clock signal may be the same as the first clock signal. The second clock signal may have a higher frequency than the first clock signal. The integrated circuit 100 may include a first transmit contact to receive a first transmit signal from the host controller and a second transmit contact to output a second transmit signal to the fluid jetting device. The first transmit signal may be in phase with a first address bit based on the first clock signal, and the second transmit signal may be in phase with a second address bit based on the second clock signal.

[0066] In some embodiments, integrated circuit 100 is attached to a print cartridge that includes a fluid jet device. The print cartridge can be configured to be inserted into a printer that includes a host controller. Integrated circuit 100 can receive, analyze, and / or modify signals from the host controller to the fluid jet device. Integrated circuit 100 can modify print instructions from the host controller to the fluid jet device to accommodate a mismatch between the print cartridge type for which the printer supplies instructions and the print cartridge type of the print cartridge that includes the fluid jet device.

[0067] In this example, the fluid jetting device is integrated into the low-fill print cartridge, and the fluid jetting device is configured to receive print data according to a low-fill address sequence of the nozzle circuitry on the fluid jetting device. The low-fill address sequence can be associated with the low-fill print cartridge. In this example, the integrated circuit 100 attached to the low-fill print cartridge (low-fill fluid jetting device) modifies the signal between the host controller and the fluid jetting device, causing the host controller to recognize and process the fluid jetting device as a fluid jetting device integrated into the high-fill print cartridge (high-fill fluid jetting device). In this way, the integrated circuit 100 causes the host controller to estimate the fill level of the low-fill print cartridge based on the fill level of the high-fill print cartridge. In this way, the low-fill print cartridge can be filled to the fill level of the high-fill print cartridge. However, the high-fill fluid jetting device is associated with a high-fill address sequence of the nozzle circuitry. Therefore, when the host controller recognizes the low-fill fluid jetting device as a high-fill fluid jetting device, the host controller provides print data with an address sequence incompatible with the low-fill fluid jetting device. To address this issue, integrated circuit 100 modifies the print data (e.g., a data packet containing print data) from the host controller to switch between high-fill and low-fill address sequences. In this way, integrated circuit 100 causes the host controller to treat the low-fill print cartridge as a high-fill print cartridge, while simultaneously ensuring the low-fill print cartridge prints correctly by modifying the print data from the host controller.

[0068] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, when the integrated circuit 100 is coupled to the fluid jetting device and the fluid jetting device is installed in the host device, the integrated circuit 100 may include a host-side contact array 110 and a device-side contact array 120. The host-side contact array includes host-side data contacts for receiving a first data packet from a host controller, and the device-side contact array includes device-side data contacts for outputting a second data packet to the fluid jetting device, each second data packet corresponding to a received first data packet. The integrated circuit is configured to transmit a second data packet modified relative to the corresponding first data packet, such that the fluid jetting device prints based on the second data packet.

[0069] The host-side contact array 110 may include a host-side clock contact for receiving a first clock signal from the host controller and a host-side transmit contact for receiving a first transmit signal from the host controller. The device-side contact array includes a device-side clock contact for outputting a second clock signal to the fluid jetting device and a device-side transmit contact for outputting a second transmit signal to the fluid jetting device. A first address bit in a first data packet may include a first address code, and a second address bit in a second data packet may include a second address code. The first address code selects a first nozzle circuit of the fluid jetting device, and the second address code selects a second nozzle circuit of the fluid jetting device. The first nozzle circuit may be located at a first position on the fluid jetting device, and the second nozzle circuit may be located at a second position on the fluid jetting device. Therefore, if the integrated circuit 100 does not modify the first data packet, the fluid jetting device will jet fluid at the first position, resulting in a printing error.

[0070] Control logic 105 can map a first address code to a second address code. The control logic can determine the second address code based on a first address bit sequence received from the host controller, whereby the second address bits are associated with the second address bit sequence. The control logic can determine the second address bit as the next address bit in the second address bit sequence. Control logic 105 can include at least one of mathematical operations and lookup tables. Mathematical operations and / or lookup tables can be used to map the first address code to the second address code.

[0071] In some embodiments, the second data packet includes a header, a middle portion, and a tail. The header includes a first subset of address bits, and the tail includes a second subset of address bits. The first and second subsets of address bits include a second address code. The middle portion may include primitive data. The tail may include control bits. The first and second data packets may include the same primitive bits. In some embodiments, the fluid jetting device includes a nozzle circuit array to jet droplets from each nozzle circuit in the array. The second address bits are used to select a second nozzle circuit for jetting droplets. The primitive data, along with the address bits, can select a second nozzle circuit for jetting droplets.

[0072] In some embodiments, the host-side contact array 110 includes a first contact column and a second contact column, the first contact column including host-side transmit contacts, and the second contact column including host-side clock contacts and host-side data contacts; and the device-side contact array includes a first contact column and a second contact column, the first contact column including device-side transmit contacts, and the second contact column including device-side clock contacts and device-side data contacts.

[0073] Integrated circuit 100 can modify the first packet such that a first portion of the first packet, including address bits, is modified, while a second portion of the first packet remains unchanged. This second portion may include metadata.

[0074] In some implementations, the first transmit signal is in phase with a first address bit based on a first clock signal, and the second transmit signal is in phase with a second address bit based on a second clock signal. Integrated circuit 100 can modify the first clock signal to obtain the second clock signal. The second clock signal may have the same frequency as the first clock signal or a higher frequency than the first clock signal.

[0075] In some implementations, the integrated circuit is attached to a print cartridge that includes a fluid jetting device, which will be inserted into a printer that includes a host controller.

[0076] Figure 7 The illustration shows a device for transmitting information to a fluid jetting apparatus (such as...). Figure 5 A block diagram of a data packet 710 for a fluid jetting device 142. Data packet 710 is used to transmit fluid jetting instructions to the fluid jetting device. The fluid jetting instructions may correspond to a portion of a print job. In this example, the data packet may include instructions for printing a portion of a print job (e.g., droplets from a nozzle).

[0077] Fluid jetting core (such as Figure 5 The fluid jetting die 144 may include a nozzle array. The nozzle array may include rows of nozzles arranged along the fluid jetting die. Each nozzle row includes multiple nozzles arranged to dispense fluid onto a substrate, such as a sheet of paper or a 3D printed surface. The nozzles may be arranged into groups referred to as “primitives.” Primitives may be further arranged into groups referred to as “virtual primitives.” The number and arrangement of nozzles in the primitives and / or virtual primitives may vary depending on the desired print density. The fluid jetting die may include a fluid jetting controller connected to the nozzle array. The fluid jetting controller may receive a data packet 710 from the host controller and / or integrated circuit 100 for controlling fluid jetting by the nozzles of the nozzle array. The fluid jetting array controller may generate jetting control data for the nozzles of the nozzle array based on the contents of the data packet 710.

[0078] Data packet 710 may include a first data packet 710a, a second data packet 710b, a third data packet 710c, a fourth data packet 710d, a fifth data packet 710e, and any number of additional data packets. In some embodiments, each of the data packets 710 has the same structure, and contains different or similar information within the same structure.

[0079] The third data packet 710c may include random data 711c, zero-padding data 712c, a header 713c, basic data 714c, and a tail 715c. The random data 711c may include pseudo-random data. The random data 711c may include a random or pseudo-random number of bits. In the example, the random data 711c includes zero, two, four, six, or eight random bits. The length of the third packet 710c may vary based on the length of the random data 711c. The fluid injection device may include a shift register corresponding to the length of the third packet 710c minus the random data 711c. The random data 711c is fed into the shift register first, and is discarded as the remainder of the third packet 710c is loaded into the shift register.

[0080] Data packet 710 may include random data 711 to determine that the fluid injection device is operating as intended. Random data 711 may include a random number of random bits. As described above, and as used herein, the term "random" includes pseudo-random data. A host device, including a host controller, may generate random data 711 to ensure correct operation of the fluid injection device. The host device may generate random data 711 to obfuscate the beginning of the header 713 of data packet 710. In this way, the host device may force integrated circuit 100 to introduce delays into the transmission of the modified data packet and / or use probabilistic methods to identify which bits to modify when modifying data packet 710, as discussed herein. The examples discussed herein regarding the identification of random data 711, non-random data, and / or the end of data packet 710 are intended to overcome and / or mitigate this security feature of data packet 710.

[0081] exist Figure 7 In the diagram, the timing of data packet 710 and its components is shown as time progressing from left to right, causing the packets to be transmitted from left to right. Arrows between the tail 715b of the second data packet 710b and the random data 711c, and between the tail 715c and the random data 711d of the fourth data packet 710d, illustrate the sequence in which data packet 710 and its components are transmitted to integrated circuit 100 and / or the fluid injection device.

[0082] Zero-padding data 712c may include one or more zeros. Zero-padding data 712c may have the same length in all data packets 710. Header 713c may include a first subset of address bits. Tail 715c may include a second subset of address bits and control bits. The first and second subsets of address bits may be address codes corresponding to the addresses of nozzle circuits on the fluid jet die. Basic data 714c may include data identifying a primitive or group of nozzle circuits on the fluid jet die. Address codes and basic data can identify the nozzle circuits used for printing. In the example, the address code identifies the address within a primitive, where each primitive on the fluid jet die includes the same address, and the basic data specifies which primitives the nozzle circuit corresponding to the address code is activated for. In the example, the address code specifies address "1", and the basic data specifies which primitives the nozzle circuit corresponding to address "1" is activated for printing. Therefore, different address codes correspond to different locations on the fluid jet die. The first address code can select the first nozzle circuit at the first position in the nozzle circuit array on the fluid jetting core, and the second address code can select the second nozzle circuit at the second position in the nozzle circuit array on the fluid jetting core.

[0083] Figure 8 It's a diagram. Figure 7 A block diagram of an example repeating address sequence 800 for data packet 710. Repeating address sequence 800 can be a repeating sequence of address codes. Successive address codes of consecutive data packets in data packet 710 follow repeating address sequence 800. In some embodiments, repeating address sequence 800 can be associated with a first type of fluid jet die. The first type of fluid jet die can have circuitry configured to process address bits received according to repeating address sequence 800. A second type of fluid jet die can have circuitry configured to process address bits received according to a second repeating address sequence. Therefore, if a second type of fluid jet die receives address bits according to repeating address sequence 800 instead of the second repeating address sequence, the second type of fluid jet die may print incorrectly. In some embodiments, if a second type of fluid jet die receives address bits according to repeating address sequence 800 instead of the second repeating address sequence, the second type of fluid jet die may not function. In some embodiments, different address bits correspond to different nozzle circuitry positions on different types of fluid jet dies. In some implementations, in order to modify the data packet with the repeating address sequence 800 for use with a second type of fluid jet wick, the repeating address sequence 800 must be modified to a second address sequence, which requires modifying the address bits in the data packet 710.

[0084] In this example, a repeating address sequence 800 is transmitted from the host controller to the integrated circuit 100, and this repeating address sequence 800 is incompatible with the fluid jetting device. In this example, the integrated circuit 100 modifies the data packet 710 to switch from the repeating address sequence 800 to a second repeating address sequence to ensure that the fluid jetting device correctly jets fluid. By modifying the data packet 710, the integrated circuit 100 ensures that the fluid jetting action performed by the fluid jetting device correctly corresponds to the fluid jetting action determined by the host device.

[0085] Figure 9 The diagram illustrates the modifications and Figure 8 An example of a data packet 710 associated with a repeating address sequence 800 to generate a second data packet 910 associated with a second repeating address sequence. Integrated circuit 100 can modify data packet 710 to obtain the second data packet 910. In some embodiments, integrated circuit 100 can receive data packet 710 and generate the second data packet 910. In some embodiments, integrated circuit 100 can modify data packet 710 to obtain the second data packet 910. As discussed herein, integrated circuit 100 can modify the address bits of data packet 710 while keeping other parts of data packet 710 unchanged to obtain the second data packet 910.

[0086] Integrated circuit 100 can perform operation 920 to obtain a second data packet 910. Control logic 105 of integrated circuit 100 can map a first address code to a second address code. The control logic may include operation 920. Operation 920 may include at least one of mathematical operations and lookup tables. In an example, operation 920 is an addition / modulo operation. In an example, operation 920 is a lookup using a lookup table. In some implementations, the lookup table may be based on mathematical operations. Using a lookup table allows the packet 710 associated with the repeating address sequence 800 to be mapped to any other repeating address sequence.

[0087] Data packet 710 and second data packet 910 may include the same address bits, but in a different order. In the example, data packet 710 and second data packet 910 include address bits corresponding to sixteen different address codes. Repeating address sequence 800 and second repeating address sequence may each include sixteen different address codes arranged in a different repeating order. In some embodiments, repeating address sequence 800 and second repeating address sequence each correspond to the same position sequence corresponding to the nozzle circuit position on the fluid jet spool. In the example, repeating address sequence 800 corresponds to a nozzle circuit emitted from left to right along a column on a first type of fluid jet spool configured to receive data packets according to repeating address sequence 800, and second repeating address sequence corresponds to a nozzle circuit emitted from left to right along a column on a second type of second fluid jet spool configured to receive data packets according to second repeating address sequence.

[0088] In this example, the host controller determines print data including the nozzle circuit location. The host controller determines a first address bit of a first fluid jet die of a first type associated with a repeating address sequence 800, where the first address bit corresponds to the nozzle circuit on the first fluid jet die of the first type at the determined nozzle circuit location. However, in this example, a second fluid jet die of a second type is installed in the printer including the host controller. If the first address bit is transmitted to the second fluid jet die, the second fluid device will print incorrectly or malfunction. Therefore, in this example, the integrated circuit 100 converts a first data packet having the first address bit associated with the repeating address sequence 800 into a second data packet 910 having a second address bit associated with a second repeating address sequence. In this example, the second address bit corresponds to the nozzle circuit on the second fluid jet die at the determined nozzle circuit location of the print data. The integrated circuit 100 transmits the second data packet to the second fluid jet die, causing the fluid jet die to print according to the print data.

[0089] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, when integrated circuit 100 is connected to the fluid jetting device and the fluid jetting device is installed in the host device, the first contact 101 can receive a first data packet from the host controller. The first data packet may include address bits and random data. The second contact 102 can transmit a second data packet to the fluid jetting device, including a second address bit based on the first address bit. Control logic 105 can generate a second data packet including a second address bit based on the first address bit.

[0090] In some implementations, integrated circuit 100 generates a second data packet by identifying a first address bit and / or random data. Control logic 105 may identify the first address bit and / or random data based on the end of the first data packet. The first data packet may have a standard length or number of bits from the end of the first data packet to the beginning of the first address bit and / or the non-random data of the first data packet. Control logic 105 may identify the first address bit and / or random data based on the number of bits from the end of the first data packet. In an example, control logic 105 counts the number of bits starting from the end of the first data packet to identify the first address bit and / or random data. In some implementations, generating a second data packet based on the end of the first data packet includes removing and / or changing at least a portion of the random data from the first data packet. In some implementations, generating a second data packet includes converting a first address bit to a second address bit according to an address bit sequence associated with a fluid injection device. In some implementations, generating a second data packet includes applying an address offset associated with a fluid injection device to one or more address bits. In some implementations, generating a second data packet includes modifying one or more control bits of the first data packet. In some implementations, the first data packet and the second data packet include the same primitive data.

[0091] In some embodiments, integrated circuit 100 includes a third contact for receiving a transmit signal from a host controller, wherein identifying the end of the first data packet includes identifying a rising edge of the transmit signal. The rising edge of the transmit signal may be a predetermined identifier for the end of the data packet and / or a predetermined control for ending data packet loading. The transmit signal may be part of a signaling protocol for loading the data packet. The rising edge of the transmit signal may indicate the end of the signaling protocol and / or the end of data packet loading.

[0092] In some implementations, integrated circuit 100 includes a third contact for receiving a clock signal from a host controller, wherein identifying the end of the first data packet includes determining a clock idle time for the clock signal. The clock idle time can be a portion of the clock signal period, identifying when the clock signal is silent or idle. The clock signal can be idle at the end of a data packet. The clock signal can be used to drive the data packet to the fluid jet die, thereby allowing the identification of the end of the data packet based on the clock idle time.

[0093] In some embodiments, the first data packet includes random data, a first header, a first intermediate portion, and a first tail, wherein the first header includes a first address bit, the first intermediate portion includes basic data, and the first tail includes a first address bit and a first control bit. The second data packet includes a second header, a second intermediate portion, and a second tail, wherein the second header includes a second address bit, the second intermediate portion includes basic data, and the second tail includes a second address bit and a second control bit. In some embodiments, the random data is and / or includes pseudo-random data.

[0094] In some embodiments, the first address bit corresponds to the first nozzle circuit in the nozzle circuit array of the fluid jetting device, and the second address bit corresponds to the second nozzle circuit in the nozzle circuit array of the fluid jetting device.

[0095] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, when integrated circuit 100 is connected to the fluid jetting device and the fluid jetting device is installed in the host device, the first contact 101 can receive a first data packet from the host controller, the first data packet including a first payload and additional bits, and the second contact 102 can transmit a second data packet to the fluid jetting device. Control logic 105 can generate a second data packet including a second payload based on the first payload.

[0096] In some implementations, the additional bits include random or pseudo-random data. In some implementations, the first payload includes a first header, a first intermediate portion, and a first tail, wherein the first header includes a first address bit, the first intermediate portion includes basic data, and the first tail includes a first address bit and a first control bit. The second payload includes a second header, a second intermediate portion, and a second tail, wherein the second header includes a second address bit, the second intermediate portion includes basic data, and the second tail includes a second address bit and a second control bit. In some implementations, the second control bit is the same as the first control bit.

[0097] In some embodiments, integrated circuit 100 generates a second data packet by identifying the first payload based on a predetermined amount of time between the first payload and the preceding packet. In some embodiments, control logic 105 determines the predetermined amount of time based on identifying the end of an adjacent data packet. In some embodiments, control logic 105 reads a clock signal received from a host controller. Control logic 105 can use the clock signal to measure the predetermined amount of time.

[0098] In some implementations, generating a second data packet based on the payload of a first data packet includes removing and / or changing additional bits. In some implementations, generating a second data packet includes modifying a first address bit of the first data packet to generate a second address bit. In some implementations, modifying the first address bit includes converting the first address bit to a second address bit according to an address bit sequence associated with the fluid injection device. In some implementations, modifying the first address bit includes applying an address offset associated with the fluid injection device to one or more address bits.

[0099] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, when integrated circuit 100 is connected to the fluid jetting device and the fluid jetting device is installed in the host device, the first contact 101 can receive a first data packet from the host controller, the first data packet including random data. The random data may be pseudo-random data. The second contact 102 can transmit a second data packet to the fluid jetting device. Control logic 105 can generate the second data packet based on the first packet when the first packet is received.

[0100] In some implementations, integrated circuit 100 generates a second data packet by comparing one or more bits of a first packet with predefined bits and generating a second data packet based on the comparison. Comparing one or more bits of the first packet with predefined bits may include using one or more masks or mask state machines to compare the one or more bits with the predefined bits. The predefined bits may follow a bit pattern. Control logic may determine the predefined bits based on one or more bit patterns in consecutive data packets. The predefined bits may be predefined address bits. The bit pattern may correspond to a repeating address sequence, such as... Figure 8The repeated address sequence 800. In some embodiments, control logic 105 may determine predefined address bits based on the address bit sequence received at the first contact. In an example, the first contact 101 may receive a set of data packets from the host controller, and control logic 105 may determine the repeated address sequence based on that set of data packets. In some embodiments, integrated circuit 100 may be configured to be used with a specific repeated address sequence. In some embodiments, the repeated address sequence is associated with a first type of fluid jet device, and integrated circuit 100 is connected to a second type of fluid jet device to translate commands from the host controller for the first type of fluid jet device into commands for the second type of fluid jet device. Integrated circuit 100 may transmit one or more signals to the host controller instructing the host controller to provide commands for the first type of fluid jet device. In this way, fluid jet device 100 may enable a printer including the host controller to recognize the fluid jet device of the installed print cartridge as a first type of fluid jet device. In an example, the printer tracks the ink fill level of the print cartridge to determine when the print cartridge is empty. In this example, integrated circuit 100 causes the printer to treat the print cartridge to which integrated circuit 100 is attached as a print cartridge with a first fill level, while if integrated circuit 100 is not attached to a print cartridge, the print cartridge will be treated as a print cartridge with a second fill level. In this way, integrated circuit 100 can alter the actions taken by the printer, such as issuing a low ink warning.

[0101] In some implementations, the first data packet includes random data, a first header, a first intermediate portion, and a first tail, wherein the first header includes a first address bit, the first intermediate portion includes basic data, and the first tail includes a first address bit and a first control bit. The second data packet may include a second header, a second intermediate portion, and a second tail, wherein the second header includes a second address bit, the second intermediate portion includes basic data, and the second tail includes a second address bit and a second control bit.

[0102] In some embodiments, integrated circuit 100 generates a second data packet by modifying a first address bit of a first data packet to generate a second data packet. In some embodiments, modifying one or more address bits includes converting a first address bit to a second address bit according to an address bit sequence associated with the fluid injection device. In some embodiments, modifying the first address bit includes applying an address offset associated with the fluid injection device to the first address bit.

[0103] In some implementations, control logic 105 begins transmitting a second data packet to the fluid injection device while the first packet is being received. In this way, integrated circuit 100 can achieve low latency between receiving the first packet and transmitting the second packet, starting transmission of the second data packet before the first data packet is fully received. Control logic 105 can begin transmitting the second data packet to the fluid injection device while the first packet is being received, based on determining that the second data packet will be transmitted with low latency. Determining to transmit the second data packet with low latency can be based on one or more signals received from the host controller. Control logic 105 can begin transmitting the second data packet based on the probability that a set of bits in the first data packet matches a predefined set of bits and that the set of bits in the first data packet indicates the start of the payload of the first data packet. In some implementations, control logic 105 can use one or more mask state machines to compare the set of bits in the first data packet with the predefined set of bits.

[0104] In some embodiments, control logic 105 may generate a third data packet based on a mismatch between the second set of bits in the first data packet and the second set of bits in a predefined bit set, and transmit the third data packet to the fluid injection device using a second contact. Control logic 105 may compare the second set of bits in the first data packet with the second set of bits in the predefined bit set to verify that starting transmission of the second data packet is correct. Control logic 105 may determine that the second data packet contains incorrect information or has been transmitted incorrectly based on a mismatch between the second set of bits in the first data packet and the second set of bits in the predefined bit set, and generate a third data packet to correct the information transmitted in the second data packet. In some embodiments, the third data packet may replace the second data packet.

[0105] In some implementations, the control logic may determine the transmission point in the first data packet where the integrated circuit begins transmitting the second data packet based on the target delay, and begin transmitting the second data packet to the fluid injection device based on the fact that this bit in the first data packet is the transmission point. The transmission point may be the last position in the first data packet where the second data packet can be transmitted to meet the target delay, or the corresponding time when the last position is received at the integrated circuit 100.

[0106] Figure 10 The diagram illustrates the modifications. Figure 7The example of data packet 710 removing random data 711 is given. Integrated circuit 100 can receive data packet 710 at host-side contact array 110 and transmit a second data packet 910 at device-side contact array. Integrated circuit 100 can receive signals 701, 702, and 703 at host-side contact array 110 and transmit signals 901, 902, and 903 at device-side contact array. Data packet 710 may each include random data 711 and non-random data 716. Non-random data 716 may include zero-padding data 712, header 713, primitive data 714, and tail 715. The non-random data 716 of each data packet 710 may be referred to as the "payload" of each data packet. Non-random data 716 may include information about the actual use of the fluid jet die. As discussed herein, random data 711 can be discarded from the shift register of the fluid jet device, so that random data 711 is not used by the fluid jet device for printing. The second data packet 910 may include only non-random data 916, so that the integrated circuit 100 transmits only the non-random data 916 actually used by the fluid jetting device in printing to the fluid jetting device.

[0107] In some implementations, the second data packet 910 includes random data 711 or other random data. As discussed herein, extra bits (such as random data 711) are discarded when the data packet is transmitted to the fluid jetting device, meaning that whether or not they contain random data is irrelevant once the data packet 710 has been modified or the second data packet 910 has been generated. As discussed herein, random data 711 is intended to obfuscate the identification of different bits (e.g., random data 711c, zero-padding data 712c, header 713c, etc.) to prevent modification of the data packet 710. Once the random data has been identified and / or the identification of the bits in the data packet 710 has been identified, the data packet 710 can be modified, thereby negating the utility of random data 711. In the example, once the second data packet 910 has been generated based on the data packet 710, new random data and / or random data 711 can be included in the second data packet 910 without affecting printing, as the new random data and / or random data 711 will be discarded by the fluid jetting device.

[0108] DATA_x in Signal 704 may be and / or include data packet 710. Integrated circuit 100 may receive DATA_x using the fifth contact 112e (host-side data contact) of host-side contact array 110. in Signal 701. DCLK in Signal 702 can be an input clock signal. Integrated circuit 100 can receive DCLK using the fourth contact 112d (host-side clock contact) of host-side contact array 110. in Signal 702. FIRE inSignal 703 can be a transmitted signal. Integrated circuit 100 can receive FIRE signals using the tenth contact 112j (host-side transmitting contact) of host-side contact array 110. in Signal 703. FIRE in Signal 703 can be used with DCLK in Signal 702 is in phase. FIRE in Signal 703 can be synchronized with the non-random data 716 of data packet 710. In the example, FIRE in Signal 703 is synchronized with the address bits in the header 712 and trailer 715 of data packet 710, as well as the primitive data 714. FIRE in Signal 703 can be based on DCLK in Signal 702 is in phase with the address bits of data packet 710. In this way, FIRE... in Signal 703 is aligned with non-random data 716 to provide data for proper synchronization of the fluid injection device.

[0109] DATA_x out Signal 901 may be and / or include a second data packet 910. Integrated circuit 100 may output DATA_x using the fifth contact 122e (device-side data contact) of device-side contact array 120. out Signal 901. DCLK out Signal 902 can be an output clock signal. Integrated circuit 100 can output DCLK using the fourth contact 122d (device-side clock contact) of device-side contact array 120. out Signal 902. In some implementations, DCLK out Signal 902 can be compared to DCLK in The 702 signal is faster. FIRE out Signal 903 can be a transmission signal used to control the emission of the nozzle circuit of the fluid injection device. Integrated circuit 100 can output FIRE using the tenth contact 122j (device-side emission contact) of the device-side contact array 120. out Signal 903. FIRE out Signal 903 can be used with DCLK out Signal 902 is in phase. FIRE out Signal 903 can be synchronized with the non-random data 916 of the second data packet 910. In the example, FIRE out Signal 903 synchronizes with the address bits and metadata in the header and trailer of data packet 910. FIRE out Signal 903 can be based on DCLK out Signal 902 is in phase with the address bits of data packet 710. In this way, FIRE... outSignal 903 is aligned with non-random data 916 to provide data for proper synchronization in controlling the fluid jet device.

[0110] Integrated circuit 100 can identify the random data 711 and non-random data 716 of data packet 710 based on the end of data packet 710. The end of the data packet can be the end of non-random data 716 or the end of the tail 715 of data packet 710. Integrated circuit 100 can identify the random data 711 and non-random data 716 of data packet 710 in order to identify address bits and thereby modify the address bits, as discussed herein. In some embodiments, integrated circuit 100 can identify the random data 711 and non-random data 716 of data packet 710 in order to identify address bits and thereby modify the address bits and / or remove random data 711.

[0111] Integrated circuit 100 can identify the end of data packet 710 based on the rising edge of transmit 1002. The rising edge of transmit 1002 can be a fire... in FIRE in Signal 703 in Signal 703 transitions from logic low to logic high. The rising edge of transmit 1002 can be a predetermined identifier for the end of a data packet and / or a predetermined control used to terminate data packet loading. FIRE in Signal 703 may be part of a signaling protocol used to load data packets. The rising edge of transmit 1002 may indicate the end of the signaling protocol and / or the end of data packet loading.

[0112] The first rising edge 1002a can indicate the end of the second data packet 710b. Integrated circuit 100 can determine, based on the first rising edge 1002a, that the data immediately preceding the first rising edge 1002a is the second data packet 710b. Integrated circuit 100 can determine, based on the first rising edge 1002a, that a predefined number of bits immediately preceding the first rising edge 1002a are non-random data 716b of the second data packet 710b. In this way, integrated circuit 100 can utilize a known data transmission protocol between the host controller and the fluid jetting device. Integrated circuit 100 can be configured, based on a known data transmission protocol, to identify different signal sequences and / or protocols used by the host controller to communicate with the fluid jetting device. In the example, integrated circuit 100 can determine that the fourteen bits received immediately preceding the first rising edge 1002a are non-random data 716b of the second data packet 710b. Integrated circuit 100 can determine, based on the first rising edge 1002a, that the first set of bits and the second set of bits (a first predefined number of bits and a second predefined number of bits, respectively) received immediately before the first rising edge 1002a are address bits of the second data packet 710b. In the example, integrated circuit 100 can determine that the first pair of bits and the second pair of bits received at positions 25 and 3 before the first rising edge 1002a are address bits of the second data packet 710b.

[0113] The second rising edge 1002b can indicate the end of the third data packet 710c. Integrated circuit 100 can determine, based on the second rising edge 1002b, that the data immediately preceding the second rising edge 1002b is the third data packet 710c. Integrated circuit 100 can determine, based on the second rising edge 1002b, that a predefined number of bits immediately preceding the second rising edge 1002b are non-random data 716c of the third data packet 710c. In the example, integrated circuit 100 can determine that the 14 bits received immediately preceding the second rising edge 1002b are non-random data 716c of the third data packet 710c. Integrated circuit 100 can determine, based on the second rising edge 1002b, that the first and second groups of bits received immediately preceding the second rising edge 1002b (a first predefined number of bits and a second predefined number of bits, respectively) are address bits of the third data packet 710c. In the example, integrated circuit 100 can determine that the first and second pairs of bits received at the twenty-fifth and third bits before the second transmit rising edge 1002b are the address bits of the third data packet 710c.

[0114] Figure 11 The illustration shows how to identify clock idle times 1102a, 1102b or predetermined time amounts 1104a, 1104b between non-random data 716 of consecutive data packets. Figure 7 Example of the end of data packet 710.

[0115] Integrated circuit 100 can identify the end of the second data packet 710b based on the first clock idle time 1102a. The first clock idle time 1102a can be DCLK. in Signal 702 is idle or does not oscillate between logic high and logic low for a period of time, which is longer than DCLK. in The period of signal 702. Integrated circuit 100 can determine that the second data packet 710b has been received based on the first clock idle time 1102a. Integrated circuit 100 can determine that the bit received immediately before the first clock idle time 1102a is the second data packet 710b. Integrated circuit 100 can identify the end of the third data packet 710c based on the second clock idle time 1102b in a similar manner. The first clock idle time 1102a and the second clock idle time 1102b can have different lengths, both longer than DCLK. in The period of signal 702. The first clock idle time 1102a and the second clock idle time 1102b can have different lengths based on the random data 711c of the third data packet and the random data 711d of the fourth data packet having different lengths. In the example, the random data 711c of the third data packet is shorter than the random data 711d of the fourth data packet, and the first clock idle time 1102a is longer than the second clock idle time 1102b.

[0116] Integrated circuit 100 can identify the end of the second data packet 710b based on a first predetermined time interval 1104a between the non-random data 716b of the second data packet 710b and the non-random data 716c of the third data packet 710b. Integrated circuit 100 can identify the end of the third data packet 710c based on a second predetermined time interval 1104b between the non-random data 716c of the third data packet 710c and the non-random data 716d of the fourth data packet 710d. The first predetermined time interval 1104a and the second predetermined time interval 1104b can be the same time interval. Integrated circuit 100 can determine the end of data packet 710 based on the predetermined time interval 1104 when there is a common predetermined time interval between the non-random data of consecutive data packets.

[0117] Figure 12 The diagram illustrates the use of predefined bits for identification. Figure 7The data packet contains non-random data 716. Predefined bits can be bits known and / or predicted by integrated circuit 100. Predefined bits can be bits determined by integrated circuit 100 based on the analysis of previous data packets of data packet 710. In the example, integrated circuit 100 can determine the value of one or more control bits of data packet 710 based on the values ​​of control bits in previous data packets of data packet 710. Predefined bits can be bits initially programmed into control logic 105 of integrated circuit 100. In the example, predefined bits can be repeating address sequences initially programmed into control logic 105, such as... Figure 8 The repeating address sequence 800.

[0118] Table 1200 and / or one or more masks can be used to compare the bits of packet 710 with predefined bits. Table 1200 is provided for illustrative purposes to describe the logic for comparing the bits of packet 710 with predefined bits. Table 1200 may simply be a representation of the masks used for comparing the bits of packet 710 with predefined bits. The masks may be included in a mask state machine or a representation of a mask state machine. Other data structures are also considered and may be used for this comparison in similar or different ways.

[0119] Table 1200 may include bit number 1210, indicating the number of bits starting from the beginning of the bit sequence. In the illustrated example, bit number 1210 may include thirty-four bits, representing a data packet with twenty-six bits of non-random data and zero to eight bits of random data. Table 1200 may include mask number 1220, identifying different masks used to compare the bits of data packet 710 with predefined bits. In the illustrated example, five different masks are used, corresponding to five different numbers of bits in the random data. Table 1200 may include a random bit count indicator 1230 associated with mask number 1220, indicating how many random bits are associated with each mask. In the illustrated example, the five masks have zero, two, four, six, and eight random bits, respectively. Table 1200 may include a random bit count indicator 1240. Random bit count indicator 1240 may represent the random bits of random data 711 in data packet 710. The number of bits in the packet may correspond to the random bit count indicator 1230. In the example shown, the first mask includes zero bits in the random bit indicator 1240, the second mask includes two bits, the third mask includes four bits, the fourth mask includes six bits, and the fifth mask includes eight bits. Table 1200 may include a primitive bit indicator 1260 corresponding to the primitive data 714 of the data packet 710.

[0120] Table 1200 may include a first predefined bit 1250 and a second predefined bit 1270. The first predefined bit 1250 may correspond to the header 713 of data packet 710. The first predefined bit 1250 may correspond to the address bits in the header 713 of data packet 710. The second predefined bit 1270 may correspond to the tail 715 of data packet 710. The second predefined bit 1270 may correspond to the address bits and control bits in the tail 715 of data packet 710. The first predefined bit 1250 and the second predefined bit 1270 may represent bits that the integrated circuit 100 knows, can determine, or predict.

[0121] The first predefined bit 1250 and the second predefined bit 1270 may correspond to a mask. In some embodiments, the mask includes only the first predefined bit 1250. In an example, the mask may include only the first predefined bit 1250 corresponding to the first set of address bits in the header 713 of the data packet 710. In some embodiments, the mask includes only the second predefined bit 1270. The mask may be static or dynamic. In an example, the mask is static and corresponds to address bits of a known repeating address sequence. In an example, the mask is dynamic and corresponds to address bits of a known repeating address sequence and control bits that may change periodically.

[0122] The mask can be programmed with predefined bits to compare the bits of data packet 710 with the predefined bits. In the example, when integrated circuit 100 receives the bits of the first data packet, it compares these bits with a mask programmed with a repeating address sequence of address bits to determine which mask matches these bits. Once a mask matching these bits has been identified, the integrated circuit generates and transmits a second data packet based on the first data packet.

[0123] Figure 13 The illustration shows the use of a mask for identification. Figure 7 Example method 1300 for non-random data 716 in a data packet. Integrated circuit 100 can execute method 1300. Figure 12 Table 1200 can be used by integrated circuit 100, or another similar data structure can be used to perform method 1300. Method 1300 may include more, fewer, or different operations than shown. Operations may be performed in the order shown, in a different order, or concurrently.

[0124] At position 1301, the decision index and mask index can be set. The mask index can correspond to a specific mask within the mask. In the example, the mask index corresponds to... Figure 12 The decision index can be a point in the packet and / or the time at which a decision is made to identify the packet's non-random data after the packet's start. The decision index can correspond to... Figure 12The bit number in bit number 1210. The decision index can be or define a transmission point at which the second data packet in the second data packet 910 must be sent or transmission must begin. In the example, the decision index can be a six-bit transmission point, indicating that once six bits of the first data packet have been received, integrated circuit 100 will begin transmitting the second data packet based on the first data packet. When integrated circuit 100 receives the first data packet, integrated circuit 100 can generate the second data packet. When data packet 710 is received, identifying the non-random data of data packet 710 is probabilistic because there is a possibility of misidentifying random data of the data packet as non-random data of the data packet. In the example, the first address bit in the header 713c of the third data packet 710c can be "0, 5", and the first mask can be programmed with predefined bits "0, 5" based on a known repeating address sequence to compare the bits of the third data packet 710c with the predefined bits. In this example, if the random data 711c of the third data packet 710c includes a pair of bits "0, 5", the mask may match the random data 711c, causing the random data 711c to be incorrectly identified as the beginning of the non-random data 716c of the third data packet 710c. The later the decision index, and thus the more bits compared with the mask, the greater the probability of identifying the non-random data 716. If the decision index is at the end of the packet, the decision is the same as identifying the end of the packet, and is deterministic.

[0125] The decision index can be based on a target delay. The target delay can be the amount of delay allowed between the start of receiving the first data packet from the host controller and the start of transmitting the second data packet to the fluid injection device. The target delay can be based on a printed acceptable delay and / or the minimum response delay required by the host controller.

[0126] At 1302, it is determined whether low latency is required. Determining the need for low latency can be based on acceptable print latency and / or the minimum response latency required by the host controller. Determining the need for low latency can also be based on determining the timing of the host controller monitoring latency and / or the timing of the host controller monitoring the response from the fluid jet device. In this example, determining the need for low latency can be based on one or more control bits indicating that the host controller is monitoring latency. If low latency is not required, the end of the packet is observed at 1303. As discussed herein, observing the end of the packet is a deterministic method for identifying the non-random data 716 of packet 710. Other deterministic methods can be used to identify the non-random data 716 of packet 710, such as using... Figure 11 The clock idle time is 1102 or the scheduled time is 1104.

[0127] If low latency is required, a decision point is determined at 1304 when bits of a data packet are received. The decision point, or transmission point, corresponds to a decision index. The decision index may correspond to a mask index. In some implementations, each mask index has a different corresponding decision point. Once a decision point is reached, a determination is made at 1305 to see if the received bits match the mask corresponding to the mask index. In the example, if the decision point is at bit number 2, then once two bits have been received, these two bits are compared with the mask corresponding to the mask index. If the bits do not match the mask, the decision index and mask index are iterated at 1306. In the example, if the decision point corresponding to the initial decision index is at bit number 2, resulting in a comparison between the initial mask, including predefined bits, and the first two bits, then the subsequent decision index may be at bit number 4, resulting in a comparison between the subsequent mask, including predefined bits, and the third and fourth bits. Once the subsequent decision point corresponding to the subsequent decision index is reached at 1304, the bits are compared with the subsequent mask at 1305. Repeat steps 1304-1306 until the bit matches the mask.

[0128] Once a match is determined at 1305 between the bit and the mask, transmission of the second packet begins based on the first packet. In this example, integrated circuit 100 modifies the address bits of the first packet to generate the second packet. In this example, once the received bits of the first packet are determined at 1305 to match a mask of predefined address bits including a repeating address sequence, the integrated circuit can identify the address bits. In this example, once the address bits of the first packet are identified, the integrated circuit can modify the address bits and begin transmitting the second packet at 1307. In some embodiments, transmitting the second packet includes modifying the address bits of the first packet, allowing the primitive data of the first packet to be passed to the fluid jetting device unchanged. In some embodiments, modifying the address bits of the first packet includes performing conversions between repeating address sequences and / or applying address offsets to the address bits as discussed herein. The address offset can be one or more address offsets. In this example, a first address offset associated with a first type of fluid jetting device and a second address offset associated with a second type of fluid jetting device corresponding to the fluid jetting device connected to integrated circuit 100 are applied to the address bits. In some embodiments, transmitting the second packet includes generating the second packet based on the first packet.

[0129] At point 1308, it is determined whether the mask decision is correct. This determination can be based on comparing later bits in the first data packet with other predefined bits. In the example, if the decision point only allows... Figure 12By comparing the first predefined bit 1250 with the bits of the first data packet, the decision to identify the address bit and begin transmitting the second data packet can be verified by comparing the second predefined bit 1270 with the bits of the first data packet. In the example, the decision to identify the address bit and begin transmitting the second data packet can be verified by identifying the end of the first data packet to identify the address bit. Since the identification of the address bit using a mask is probabilistic, there is a possibility that this decision is incorrect.

[0130] If the mask decision made at 1305 is correct, as verified at 1308, then the decision index and mask index are set at 1301. The decision index and mask index can be set to initial values. The mask can be updated with new predefined bits (such as subsequent address bits in a repeating address sequence and / or updated control bits).

[0131] If the masking decision made at 1305 is incorrect, as determined at 1308, then a determination is made at 1309 regarding whether low latency is required. Since the second packet has already begun or is being transmitted, the determination at 1309 regarding whether low latency is required depends on whether low latency is more important than print quality, because based on the decision at 1305, the second packet includes incorrect print data. In the example, the second packet includes incorrect print data because random data is incorrectly identified as address bits, causing the address bits and potentially additional random bits of random data to be sent as metadata. In this example, the content of the second packet is shifted based on the incorrect identification of random data as address bits, causing the incorrectly identified random bits to be modified as address bits, any subsequent random bits and actual address bits to be sent as metadata, and the actual metadata is shifted based on the position of the incorrectly identified random bits. Therefore, the second packet includes print data that does not match the print data sent by the host controller.

[0132] In some implementations, determining at 1309 whether low latency is required depends on whether the host controller is checking for low latency. The integrated circuit may determine the need for low latency based on the printer monitoring the latency of packets sent to the fluid jet unit and / or the printer requesting the fluid jet unit to respond within a predetermined time period.

[0133] In the example, if Figure 12If the random bits at positions "3" and "4" in Table 1200 are incorrectly identified as address bits when the actual address bits are at positions "7" and "8", then the random bits at positions "3" and "4" will be modified as address bits. The random bits at positions "5" and "6" and the actual address bits at positions "7" and "8" will be transmitted as primitive bits. The primitive bits at positions "9-18" (the first ten primitive bits) will be transmitted as the fifth to fourteenth primitive bits of the second data packet, and the primitive bits at positions "19-22" will be transmitted as control bits of the second data packet. In this example, because the primitive bits in the second data packet are incorrect, the fluid jetting device will not print according to the print data sent by the host controller, but will print according to the incorrect primitive data.

[0134] If it is determined at 1309 that low latency is not required, the second data packet is retransmitted at 1311 to align with the correct address bits, or a third data packet based on the correct identification of the address bits is transmitted at 1311 to replace the transmitted second data packet. In some embodiments, the second data packet is retransmitted at 1311 or the third data packet is transmitted based on a comparison of additional predefined bits with the first data packet. In some embodiments, the second data packet is retransmitted at 1311 or the third data packet is transmitted at 1311 based on identifying the end of the first data packet to identify the address bits of the first data packet. The retransmitted second or third data packet can be sent to the fluid jetting device, causing the fluid jetting device to print according to the print data from the host controller, but with increased latency. As discussed herein, the clock signal from integrated circuit 100 can be faster than the clock signal from the host controller, meaning that the latency resulting from retransmitting the second or third data packet is less than the amount of time required to determine at 1308 that the mask decision is incorrect and to regenerate the second or third data packet.

[0135] If it is determined at 1309 that low latency is required, the second data packet is not retransmitted, and the fluid jetting device is allowed to print with incorrect print data as in the second data packet transmitted at 1310.

[0136] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6BIn either of these scenarios, when integrated circuit 100 is coupled to the fluid jetting device and the fluid jetting device is installed in the host device, integrated circuit 100 can receive a first data packet at the host-side contact array 110 corresponding to a request to read a first memory bit on the fluid jetting device. Integrated circuit 100 can transmit a second data packet from the device-side contact array 120 corresponding to a request to read a second memory bit on the fluid jetting device. Integrated circuit 100 can receive a read response at the device-side contact array 120 corresponding to the state of the second memory bit. Integrated circuit 100 can transmit this read response from the host-side contact array. In this way, integrated circuit 100 can intercept requests from the host controller to read bits on the fluid jetting device, such that the read response sent to the host controller is different from the response that would be sent from the fluid jetting device to the host controller in response to a read request from the host controller. Integrated circuit 100 can redirect the read response from the host controller to a different bit on the fluid jetting device, or generate a new read response pointing to that different bit. By redirecting read requests and receiving responses from the fluid jet dies, integrated circuit 100 can ensure that the responses from the fluid jet dies have all the characteristics associated with a real and / or expected fluid jet device.

[0137] Integrated circuit 100 can determine which memory bits the host controller is attempting to read and / or write. Integrated circuit 100 can transmit one or more signals to the host controller in response to a request received from the host controller. In some embodiments, integrated circuit 100 can generate a response and / or transmit the request or the request generated by the integrated circuit to the fluid injection device to obtain a response.

[0138] The host-side contact array 110 may include a first column and a second column. The first column includes a host-side transmit contact 112j, and the second column includes a host-side data contact 112e, a host-side mode contact 112c, and a host-side clock contact 112d.

[0139] In some implementations, control logic 105 is configured to receive a first data packet by receiving one or more signals corresponding to a memory access protocol, the memory access protocol including: a first transition to logic high at host-side mode contact 112c, a logic high signal at host-side data contact 112e, and a second transition to logic high at host-side transmit contact 112j. Host-side contact array 110 may include host-side sensing contact 112b. Control logic 105 may transmit a read response by transmitting a read response at host-side sensing contact 112b.

[0140] In some implementations, the second memory bit is an unused bit. As used herein, an "unused bit" can refer to a bit on the fluid jet device that is not normally accessed by the host controller, or a bit that does not correspond to information requested by the host controller during normal operation. In an example, the fluid jet device may include one hundred bits, of which fifteen bits are used to store information accessed by the host controller. In this example, all functions of the host controller can be performed using these fifteen bits on the fluid jet device used to store information accessed by the host controller. Only these fifteen bits are accessed by the host controller throughout the entire lifetime of the fluid jet device. In this example, the other eighty-five bits that are not accessed by the host controller are unused bits.

[0141] In some implementations, control logic 105 may receive a third data packet corresponding to a request to write to a first memory bit at host-side contact array 110. Control logic 105 may transmit a fourth data packet corresponding to a request to write to a second memory bit at device-side contact array 120. In this way, integrated circuit 100 may store or record a request to write to the first memory bit from the host controller in the second memory bit. In some implementations, a read response corresponds to a write to the second memory bit. In an example, if the host controller attempts to read a bit previously written by the host controller, integrated circuit 100 may redirect the read request to the bit where integrated circuit 100 records the original write request, or redirect it to the bit to which integrated circuit 100 redirected the original write request. In this way, integrated circuit 100 may provide a response to the host controller consistent with the host controller's previous action. Control logic 105 may include a mapping from the first memory bit to the second memory bit. Control logic 105 may use this mapping to direct read and write requests from the host controller that point to the first bit to the second bit.

[0142] The second data packet may be based on the first data packet. In some embodiments, the second data packet includes different address bits and / or different primitive bits than the first data packet. Integrated circuit 100 may modify the first data packet to modify the address bits of the first data packet, thereby generating a second data packet such that the second data packet is identical to the first data packet, except that the second data packet is pointed to a second bit.

[0143] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6BIn any one of these scenarios, when the integrated circuit 100 is connected to the fluid jetting device and the fluid jetting device is installed in the host device, the integrated circuit 100 may include one or more host-side contacts, one or more device-side contacts, and control logic to: receive a first read request for a first memory bit on the fluid jetting device at the one or more host-side contacts; transmit a second read request for a second memory bit on the fluid jetting device at the one or more device-side contacts in response to the first read request; receive a read response corresponding to the state of the second memory bit at the one or more device-side contacts; and transmit the read response at the one or more host-side contacts.

[0144] The one or more contacts may include a first column and a second column, the first column including a host-side transmit contact 112j, and the second column including a host-side data contact 112e, a host-side mode contact 112c, and a host-side clock contact 112d.

[0145] In some implementations, control logic 105 is configured to receive a first read request by receiving one or more signals corresponding to a memory access protocol, which includes: a first transition to logic high at host-side mode contact 112c, a logic high signal at host-side data contact 112e, and a second transition to logic high at host-side transmit contact 112j. The one or more contacts may include host-side sensing contact 112b. Control logic 105 may transmit a read response by transmitting a read response at host-side sensing contact 112b.

[0146] In some implementations, the second memory bit is an unused bit. In some implementations, control logic 105 may receive a first write request for the first memory bit at one or more contacts. Control logic 105 may transmit a second write request for the second memory bit at the device-side contact array 120. In this way, integrated circuit 100 may store or record the first write request for the first memory bit from the host controller in the second memory bit. In some implementations, a read response corresponds to a second write request for the second memory bit. In an example, if the host controller attempts to read a bit previously written by the host controller, integrated circuit 100 may redirect the read request to the bit where integrated circuit 100 records the original write request, or redirect it to the bit to which integrated circuit 100 redirected the original write request. In this way, integrated circuit 100 may provide the host controller with a response consistent with the host controller's previous action. Control logic 105 may include a mapping from the first memory bit to the second memory bit. Control logic 105 may, based on this mapping, direct read and write requests from the host controller pointing to the first bit to the second bit.

[0147] The second data packet may be based on the first data packet. In some implementations, the second data packet includes address bits different from those of the first data packet. Integrated circuit 100 may modify the first read request to modify the address bits of the first read request, thereby generating a second read request such that the second read request is identical to the first read request, except that the second read request is pointed to a second bit.

[0148] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, integrated circuit 100 can be configured to be attached to or has been attached to a print cartridge including a fluid jet device, and host-side contact array 110 includes at least one column of contacts to contact corresponding printer contacts. Host-side contact array 110 may include transmitting contacts and contact columns including analog contacts, mode contacts, clock contacts, and at least one data contact. Control logic 105 may receive a first data access signal sequence over multiple (e.g., 13) clock cycle periods, the first data access signal sequence including: a high signal on the mode contact, a low signal on the transmitting contact, and a signal on the data contact. Control logic 105 may receive a second data access signal sequence, the second data access signal sequence including: a high signal on the mode contact, a low signal on the transmitting contact, and a data access signal on the data contact. The data signal may indicate a read or write event. The second data access signal may be received over multiple (e.g., 3, 13) clock cycle periods.

[0149] In response to the first and second data access signal sequences, if the data access signal indicates a read event, the control logic 105 can respond with the data value corresponding to the data access signal for the read event; if the data access signal indicates a write event, the control logic processes the bits of the write event to respond with the processed bits in a subsequent read event. The control logic 105 can also respond to other signal sequences that do not include the first and second data access signal sequences without responding with a data value.

[0150] In some embodiments, the device-side contact array 120 includes device-side contacts for contacting the fluid jetting device. Control logic 105 may be configured to modify and / or transmit additional signals to the fluid jetting device. In some embodiments, the host-side contact array 110 and / or the device-side contact array are arranged in two columns extending along two parallel lines, and the host-side contact array 110 and / or the device-side contact array include additional contacts, including at least one of logic power, high power, ground, reset, and pen detection contacts.

[0151] In some embodiments, the contact array is a host-side contact array, and the integrated circuit further includes a device-side contact array to contact the fluid jetting device with some or all of the same contacts in at least a partially identical but mirror-image arrangement, wherein the integrated circuit includes a thin substrate that includes an isolation layer between at least some of the host-side circuitry and the device-side circuitry.

[0152] By redirecting read and / or write requests from the host controller and receiving responses from the fluid jet die, integrated circuit 100 can ensure that the response from the fluid jet die possesses all the characteristics associated with a genuine and / or expected response from the fluid jet device. Therefore, the host controller will recognize the response as a genuine and / or expected response from the fluid jet device. Furthermore, integrated circuit 100 can manipulate various memory access protocols to deliver specific responses to the host controller. In an example, if the host controller attempts to access a memory bit associated with the use of the fluid jet device to determine whether to send a fluid jet command to the fluid jet device, integrated circuit 100 can redirect the memory access attempted by the host controller to a different bit, causing the host controller to determine that the fluid jet device is not used or substantially unused (e.g., 90% ink level remaining). In this example, if a specific usage gauge on the fluid jet device includes bits that are written during printing on the fluid jet device, the integrated circuit can redirect a read from the host controller of that usage gauge to another unwritten bit on the fluid jet device. In this way, integrated circuit 100 can modify the operation of the host controller so that the host controller treats the fluid jet device as an unused and / or less-used fluid jet device in good condition and / or operating as expected. In the example, integrated circuit 100 can cause the host controller to treat the fluid jet device as being used at 5% of its expected lifespan instead of 100% of its expected lifespan. By redirecting bit access requests from the host controller, fluid jet device 100 can modify various operations of the host controller and / or fluid jet device performed in response to known access protocols between the host controller and the fluid jet device.

[0153] Figure 14This is a flowchart of an example memory access protocol 1400. The method access protocol 1400 may include more, fewer, or different operations than shown. Operations may be performed in the order shown, in a different order, or concurrently. The memory access protocol can be used to access memory bits on a fluid injection device, such as memory bits used to control nozzle circuit actuation. The memory access protocol 1400 can be observed, modified, and / or executed by integrated circuit 100. In this example, integrated circuit 100 may receive one or more signals corresponding to the memory access protocol 1400 from a host controller. Although specific bits, signals, and circuit components (such as registers) are named, these specific elements are merely examples of more general components and elements that may also have the same result.

[0154] At 1402, a non-volatile memory (NVM) enable bit is written into the configuration register. As used herein, an NVM enable bit can refer to a bit used to enable a floating-gate avalanche metal-oxide-semiconductor (FAMOS) element that can act as a memory element. As shown above, other memory elements capable of storing at least two states of information bits and switching between those states can also be used. Writing an NVM enable bit into the configuration register can also refer to other examples of memory elements other than registers. The configuration register can be replaced by other circuitry or data organization methods capable of receiving and storing information, such as an NVM enable bit for configuring circuitry within a fluid jet device.

[0155] At 1404, nozzle data is loaded into the integrated circuit and / or the fluid injection device. The nozzle data may include information for setting NVM enable bits in the data stream and information for selecting which non-volatile memory (NVM) bits to use for specific address access for the nozzle. The nozzle data can be loaded using data contacts 112e of the host-side contact array 110 and / or data contacts 122e of the device-side contact array. Data contacts 112e of the host-side contact array 110 can be used when the host controller is loading nozzle data into the integrated circuit 100. Data contacts 122e of the device-side contact array 120 can be used when the integrated circuit 100 is loading nozzle data or modified nozzle data into the fluid injection device.

[0156] Nozzle data can indicate the selection of which nozzle circuits to fire in response to an upcoming FIRE signal. The selection of which nozzle circuits to fire can be stored in nozzle memory bits (e.g., triggers or latches) corresponding to the nozzle circuits. In the example, the selection data provided by the data contacts 122e of the device-side contact array 120 also includes a corresponding NVM enable bit in the nozzle selection data. In the example, the NVM enable bit can be transmitted in the header or trailer of the nozzle selection data. In some embodiments, the selection data provided by the data contacts 122e of the device-side contact array 120 also includes a memory selection bit indicating which memory bank the selected bit resides in within the fluid ejection device.

[0157] As described above, steps 1402 and 1404 can be performed in either order. The result of these two steps is that the NVM enable bit is written to the configuration register and the NVM enable bit is set.

[0158] At 1406, the FIRE signal is driven high and then low. The FIRE signal can be a signal sent to each nozzle circuit of the fluid jetting device. The FIRE signal can be transmitted from integrated circuit 100 using the emitter contact 122j of the device-side contact array 120. Bits of the register can be electrically connected to the nozzle circuit and the emitter contact 122j of the device-side contact array 120, causing an action to be taken at the configuration register when a signal is sent using the emitter contact 122j of the device-side contact array 120. The signal being driven high and then low can indicate the signal amplitude (roughly corresponding to the signal strength, regardless of whether the signal is current or voltage). In the example, driving the FIRE signal high can be interpreted as the value 1, while driving the FIRE signal low or not driving it at all can be interpreted as the value 0. These high and low values ​​can be referred to as "logic high" and "logic low," respectively. In the example, the FIRE signal is driven from 0 to 1 and then back to 0. The change in signal transmission can indicate when an action should be taken (such as launching the nozzle). Driving the FIRE pad from high to low clears the NVM enable bit in the configuration register. Driving the FIRE pad from high to low also sets a latch within the fluid jet device. This internal latch, in conjunction with future signal passes, enables memory bit access.

[0159] At 1408, the NVM enable bit is written to the configuration register. This is the same action as at 1402, but at 1408, the internal latch has been set, and the NVM enable bit in the configuration register has been cleared. When the NVM enable bit is transmitted using data contact 122e, the NVM enable bit is written to the configuration register again, enabling access to the memory access bits in the memory configuration register.

[0160] At 1410, the memory access bits are written to the memory configuration register. The memory configuration register can be a separate memory element from the configuration register. In some examples, the memory configuration register has fewer bits than the configuration register. Once the memory access bits are written to the memory configuration register, the memory of the fluid jet device can be accessed. The enable bit of the memory configuration register can be used as a control signal to enable access to the NVM or FAMOS memory elements.

[0161] At decision 1412, a determination is made based on the control signal indicated by the bit in the memory configuration register as written at 1410. If the bit in the memory configuration register indicates a memory write, method 1400 proceeds to 1414. If the bit in the memory configuration register does not indicate a memory write, method 1400 proceeds to 1416.

[0162] At 1414, the FIRE contact 122j is driven high for the desired write time, and then driven low. In the example, driving the FIRE contact 122j may include providing a 0 signal, then a 1 signal, and then a 0 signal on the transmit line. The values ​​of the signals may correspond to a current or voltage on the FIRE contact 122j. During the duration of the write time, access to a memory element (such as a FAMOS) may be performed. Access to the FAMOS or other memory element may include writing information into the FAMOS or memory element.

[0163] At 1416, the FIRE contact 122j can be driven high to force a voltage or current onto the sensing contact 122b for measurement, and then the FIRE contact 122j can be returned to a low signal. During the readout period, memory elements (e.g., FAMOS) can be accessed. The current or voltage response on the sensing contact 122b can indicate the value of the memory element (e.g., programming level). The sensing contact 122b can be used to detect conditions in a fluid ejection device, such as cracks in the printing die or temperature. Regardless of whether it is done via 1414 or 1416, the falling edge of the FIRE signal clears the memory configuration register and clears the NVM enable bit of the configuration register.

[0164] Memory access protocol 1400 includes various signals that cause a specific response at the fluid jet wick of the fluid jetting device. When integrated circuit 100 executes memory access protocol 1400 by transmitting various signals of memory access protocol 1400 to the fluid jetting device via device-side contact array 120, the fluid jetting device responds as described in steps 1402-1414. However, when the host controller executes memory access protocol 140 by transmitting various signals of memory access protocol 1400 to integrated circuit 100, integrated circuit 100 does not necessarily respond in the same manner as the fluid jetting device. Integrated circuit 100 may include memory elements for mirroring the memory elements of the fluid jetting device, or the integrated circuit may have different memory elements. In this way, integrated circuit 100 can provide a response different from the response that the fluid jetting device will provide. Integrated circuit 100 can provide a response to the host controller that is configured to elicit a specific response from the host controller. In the example, if the host controller attempts to read memory bits to determine whether the fluid jet device is in use or a compatible type of fluid jet device, the integrated circuit 100 provides a response that causes the host controller to regard the fluid jet device as an unused, less used, and / or compatible type of fluid jet device.

[0165] Integrated circuit 100 can receive various signals from memory access protocol 1400, identify that memory access protocol 1400 is being executed, and respond accordingly. Integrated circuit 100 can respond by redirecting signals from memory access protocol 1400 to another protocol not specified in memory access protocol 1400. Integrated circuit 100 can respond by generating its own signals for memory access protocol 1400 to access memory bits of the fluid jet device. Integrated circuit 100 can allow some signals of memory access protocol 1400 to be transmitted from the host controller to the fluid jet device while modifying other signals of memory access protocol 1400. As discussed herein, the integrated circuit can allow signals from the host controller intended for use with the fluid jet device to pass through, intercept, and / or overwrite these signals. In the example, integrated circuit 100 can allow signals of memory access protocol 1400 to be transmitted from the host controller to the fluid jet device, changing only which bits are addressed in memory access protocol 1400.

[0166] Figure 15 The illustration depicts an example configuration register write protocol 1500. Configuration register write protocol 1500 may include a series of signals for accessing the configuration registers of a fluid injection device. Configuration register write protocol 1500 can... Figure 14At position 1410, memory access bits are written to the memory configuration register. Integrated circuit 100 can access the memory configuration register of the fluid jet device using configuration register write protocol 1500, as at position 1410. Integrated circuit 100 can receive configuration register write protocol 1500 from the host controller at host-side contact array 110 and transmit configuration register write protocol 1500 at device-side contact array 120.

[0167] As described above, other data organization and storage structures besides registers have been considered. In the example, other storage elements can be used instead of registers. The signal set is provided to illustrate a way of accessing the configuration register using the same contacts used to provide data to fluid actuators, such as nozzle circuits.

[0168] The configuration register write protocol 1500 may include a MODE signal 1502, a FIRE signal 1504, a DCLK signal 1506, and a DATA signal 1508. As discussed herein, the host controller and / or integrated circuit 100 may generate and / or transmit the configuration register write protocol 1500 to the fluid jet device. The MODE signal 1502 may be transmitted using the mode contact 122c of the device-side contact array 120. The transmit signal 1504 may be transmitted using the transmit contact 122j of the device-side contact array 120. The transmit signal 1504 may be transmitted to the configuration register of the fluid jet device and the nozzle circuit, and may indicate the actuation of the nozzle circuit. Actuation of the nozzle circuit may include dispersing ink droplets corresponding to the selected nozzle circuit toward the printing medium. The FIRE signal 1504 may also cause the writing or clearing of bits in a register or memory, as in Figure 14 The memory access protocol 1400 is discussed. The DCLK signal 1506 can be transmitted using the clock contact 122d of the device-side contact array 120. The DCLK signal 1506 is enabled on the rising action of each clock tick. The DATA signal 1508 can be transmitted using the data contact 122e of the device-side contact array 120. The DATA signal 1508 can be included in... Figure 14 Configuration data transmitted during the memory access protocol.

[0169] When the MODE signal 1502 transitions to logic high at 1510 and the DATA signal 1508 is also logic high at 1512, the configuration register can be enabled for a write operation. After the configuration register is enabled in both the MODE and DATA signals, additional data can be loaded into the configuration register with the rising edge of the DCLK signal 1506. The DCLK signal 1506 may include a first rising edge 1514, a second rising edge 1516, a third rising edge 1518, and a fourth rising edge 1520. Data from the DATA signal 1508 can be transferred to the configuration register with each of these rising edges.

[0170] In the example, when the DATA signal 1508 is high during the first rising action 1514 on the DCLK signal 1506, data at bit 1522, which is used to set the third position of the configuration register, can be shifted into the configuration register. When the DATA signal 1508 is low during the second rising action 1516 on the DCLK signal 1506, data at bit 1524, which is used to set the second position of the configuration register, can be shifted into the configuration register. When the DATA signal 1508 is high during the third rising action 1518 on the DCLK signal 1506, data at bit 1526, which is used to set the first position of the configuration register, can be shifted into the configuration register. When the DATA signal 1508 is high during the fourth rising action 1520 on the DCLK signal 1506, data at bit 1528, which is used to set the zeroth position of the configuration register, can be shifted into the configuration register. This example illustrates a 4-bit configuration register write, thus allowing data to be transferred at the four data positions indicated on the DATA signal 1508 with the corresponding rising action on the DCLK signal 1506. As mentioned above, the length of other data written to the configuration register can be larger or smaller, depending on the size of the configuration register. Similarly, similar signaling can be used to write other memory configurations, and the length and amount of data transferred can also be varied depending on the size and structure of the memory. In the example, the rising edge of the DCLK signal 1506 shifts data into the configuration register, and the old / extra bits are shifted out of the end.

[0171] Figure 16An example status register access protocol 1600 is illustrated. Status register access protocol 1600 can be used to access the status register of a fluid jetting device and / or a status register or similar function on an integrated circuit. Example status register access protocol 1600 can be received and / or processed by the fluid jetting device or integrated circuit 100. The fluid jetting device may include a status register accessed using status register access protocol 1600. Integrated circuit 100 may include hardware, software, or a combination of hardware and software that performs a function similar to that of the status register, or provides a signal similar to that provided by the fluid jetting device in response to status register access protocol 1600.

[0172] As discussed herein, integrated circuit 100 can enable, intercept, and / or overwrite of status register access protocol 1600 provided by the host controller. Integrated circuit 100 can generate signals of status register access protocol 1600 to access the status register of the fluid jet device. Integrated circuit 100 can recognize signals of status register access protocol 1600 and respond accordingly. Integrated circuit 100 can respond by redirecting signals of status register access protocol 1600 to another unspecified entity in status register access protocol 1600. Integrated circuit 100 can respond by generating its own signals for status register access protocol 1600 to access memory bits of the fluid jet device. Integrated circuit 100 can allow some signals of status register access protocol 1600 to be transmitted from the host controller to the fluid jet device while modifying other signals of status register access protocol 1600.

[0173] The status register access protocol 1600 may include a MODE signal 1601, a FIRE signal 1603, a DCLK signal 1605, and a DATA signal 1607. As discussed herein, the host controller and / or integrated circuit 100 may generate the status register access protocol 1600 and / or transmit the status register access protocol to the fluid injection device. The MODE signal 1601 may be transmitted using the mode contact 122c of the device-side contact array 120. The FIRE signal 1603 may be transmitted using the transmit contact 122j of the device-side contact array 120. The DCLK signal 1605 may be transmitted using the clock contact 122d of the device-side contact array 120. The DCLK signal 1605 is enabled on the rising action of each clock tick. The DATA signal 1607 may be transmitted using the data contact 122e of the device-side contact array 120.

[0174] With DATA signal 1607 at logic high at 1602, MODE signal 1601 transitions from logic low to logic high at 1604. Then, DATA signal 1607 transitions to a high-impedance state (floating) at 1606. With DATA signal 1607 in a high-impedance state, FIRE signal 1603 transitions from logic low to logic high at 1608 to enable reading of the status register.

[0175] Status Register Access Protocol 1600 can be similar to Figure 15 The difference between the configuration register write protocol 1500 and the status register access protocol 1600 is that the FIRE signal 1603 is logic high at 1608, while the FIRE signal 1504 is logic low in the configuration register write protocol 1500.

[0176] By setting the NVM enable bit and NVM lock bit before executing the status register access protocol 1600, the status register access protocol 1600 can be used to access the special status register of the fluid injection device. In one example, the NVM enable bit and NVM lock bit can be set in the specified position. Figure 14 The memory access protocol 1400 is set at 1408.

[0177] When the status register (or special status register) is enabled for reading, the status register can output a data stream via the DATA signal 1607. In this example, the data stream (i.e., bits MSB, MSB-1, MSB-2, MSB-3, etc.) is read from the status register. Any suitable number of bits can be read from the status register. Each bit of the data stream can be read from the status register in response to the DCLK signal 1605. For example, the MSB bit can be read from the status register in response to enabling the status register to be read. The rising edge of the DCLK signal 1605 indicated at 1610 can output the MSB-1 bit via the data signal. Similarly, the rising edges of the DCLK signal 1605 indicated at 1612, 1614, etc., can output bits MSB-2, MSB-3, etc., respectively via the DATA signal 1607. In other examples, each bit of the data stream can be output from the status register in response to each corresponding falling edge of the clock signal or in response to both the rising and falling edges of the clock signal. Reading from the status register can be disabled by switching the FIRE signal 1603 back to logic low as indicated at 1616 and / or by switching the MODE signal 1601 back to logic low as indicated at 1618.

[0178] A special status register can store address offsets or bits associated with address offsets. In the example, the address offset consists of four bits stored in non-volatile memory. The address offset can be specific to the type of fluid jet device. In the example, the address offset corresponds to a specific product (such as a print cartridge) that includes a fluid jet device. The address offset can be used by the fluid jet device to modify print data received at the fluid jet device. The address offset can be used by the fluid jet device to modify the address bits or address code of data packets received at the fluid jet device. The host controller can prepare data packets based on the address offset. In this way, the data packets provided by the host controller correspond to the type of fluid jet device because the data packets are prepared based on the address offset of the fluid jet device. Integrated circuits can modify data packets (such as...) Figure 7 The data packet 710 allows the data packet provided based on the first address offset to be used with a fluid jetting device having a second address offset.

[0179] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, when integrated circuit 100 is connected to the fluid jetting device and the fluid jetting device is installed in the host device, the first contact 101 can be a host-side data contact for receiving a first address data packet from the host controller, and the second contact 102 can be a device-side data contact for transmitting a second address packet to the fluid jetting device. Control logic 105 can modify the first address data packet based on the address offset to generate the second packet.

[0180] The address offset may be in the fluid jetting device and / or pre-configured in an integrated circuit. The address offset may be stored on the fluid jetting device. The fluid jetting device may include non-volatile memory bits that include the address offset of the fluid jetting device. The address offset may be stored on integrated circuit 100. The address offset may be specific to the type of fluid jetting device or include a print cartridge containing the fluid jetting device. Modifying the first packet to generate the second packet may include subtracting the address offset from the first address bits of the first packet to obtain the second address bits of the second packet. The fluid jetting device may use the address offset to modify the second address bits of the second packet to obtain the modified address bits. In some embodiments, modifying the address bits of the second packet includes adding the second address bits of the second packet to the address offset to obtain the modified address bits. The fluid jetting device may include an array of nozzle circuits to jet droplets from each nozzle circuit in the array, with the modified address bits used to select a nozzle circuit for jetting droplets.

[0181] In the example, the fluid jet device adds an address offset to the address bits received at the fluid jet device. This means that to obtain the correct print data, control logic 105 subtracts the address offset from the address bits of the first packet. In this example, once the fluid jet device adds the address offset to the second address bit, the fluid jet device will have the correct print data including the correct address bits. Based on the correct print data, the fluid jet device actuates the nozzle circuitry of the nozzle circuitry array to perform printing. It should be understood that addition and subtraction can include wraparound at the maximum and minimum values. In the example, for a 4-bit adder, once the counter reaches fifteen, adding 1 will result in zero due to data wraparound. In this example, subtracting one from zero yields fifteen because of data wraparound. Therefore, both addition and subtraction can be used to obtain the correctly modified address bits based on the address offset.

[0182] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either of these scenarios, when integrated circuit 100 is coupled to the fluid jetting device and the fluid jetting device is installed in the host device, the first contact 101 may be a host-side data contact for receiving a first address offset read request from the host controller, and the second contact 102 may be a device-side data contact for transmitting a second address offset read request to the fluid jetting device. Control logic 105 may determine the address offset of the fluid jetting device in response to an address offset read response transmitted by the fluid jetting device. As described above, integrated circuit 100 may be pre-configured using the address offset of the fluid jetting device. However, in some embodiments, integrated circuit 100 may learn the address offset based on the address offset read response.

[0183] Control logic 105 can receive a first data packet at the host-side contact and transmit a second data packet based on the first data packet at the device-side data contact based on the determined address offset of the fluid jet device.

[0184] Integrated circuit 100 may include host-side mode contacts and host-side transmit contacts. Control logic 105 determines that a first data packet is associated with an address offset read by identifying the access protocol and one or more bits in the packet associated with the address offset read. The access protocol may be... Figure 16 The status register read protocol 1600 discussed in the document. The one or more bits associated with the access protocol in the packet can be NVM enable bits and NVM lock bits associated with a special status register read protocol. Therefore, address offset reads can be special status register reads, requiring... Figure 16 Before reading the status register, the NVM enable bit and NVM lock bit are set according to the 1600 protocol.

[0185] The access protocol may include: a first transition to logic high at a host-side mode contact, a logic high signal at a host-side data contact, and a second transition to logic high at a host-side transmit contact. In some implementations, determining the address offset of the fluid jet device includes: transmitting the access protocol and a first address bit of a first packet to the fluid jet device, and comparing the first address bit of the first packet with a response from the fluid jet device. In an example, the fluid jet device responds to a special status register read with a response including the sum of the provided address bits and the address offset bits. In this example, the address offset can be determined by recording the first address bits provided in the first data packet and comparing them with the response from the fluid jet device. In some implementations, determining the address offset of the fluid jet device includes comparing the response from the fluid jet device with default packet address bits. Integrated circuit 100 may provide default packet address bits to the fluid jet device to determine the address offset based on the response from the fluid jet device. In an example, integrated circuit 100 provides four address bits "0" to the fluid jet device, such that the response indicates an address offset.

[0186] In some implementations, determining the address offset of the fluid jetting device involves comparing multiple address bits of multiple packets with multiple responses from the fluid jetting device. In some implementations, determining the address offset of the fluid jetting device involves comparing a default set of packet address bits with multiple responses from the fluid jetting device. In an example, integrated circuit 100 may provide the fluid jetting device with sixteen different sets of four address bits to receive sixteen different responses to determine the address offset. In this way, any errors in the individual responses can be taken into account.

[0187] In some embodiments, modifying the second packet to generate the third packet includes subtracting an address offset from the second address bits of the second packet to obtain the third address bits of the third packet. The fluid jetting device may include non-volatile memory bits that include address offsets for the fluid jetting device. The fluid jetting device may use the address offset to modify the third address bits of the third packet to obtain the modified address bits. In some embodiments, modifying the address bits of the third packet includes adding the third address bits of the third packet to the address offset to obtain the modified address bits. In some embodiments, the fluid jetting device includes a nozzle circuit array to jet droplets from each nozzle circuit in the array, and the modified address bits are used to select a nozzle circuit for jetting droplets.

[0188] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6BIn either case, when integrated circuit 100 is coupled to a fluid jetting device and the fluid jetting device is installed in a host device, host-side contact array 110 may include host-side mode contacts, host-side transmit contacts, and host-side data contacts, and device-side contact array 120 may include device-side data contacts. Control logic 105 may recognize an address offset read, which includes a read enable data packet for setting two read enable bits on the fluid jetting die, wherein the two read enable bits are set on the fluid jetting die, the host-side mode contact is logic high, the host-side transmit contact is logic high, and the host-side data contact is logic high. Control logic 105 may, in response to the address offset read, transmit a first address offset at the host-side data contact, receive a first data packet at the host-side data contact including first address bits for use with the first address offset, and transmit a second data packet based on the first data packet at the device-side data contact, the second data packet including second address bits for use with a second address offset associated with the fluid jetting device.

[0189] Control logic 105 can modify a first address bit of a first packet using a first address offset and a second address offset to obtain a second address bit of a second packet. According to the integrated circuit of claim 20, modifying the first address bit of the first packet includes adding a first address offset and subtracting a second address offset to obtain the second address bit. In the example, the host controller generates print data including the actual address bit and subtracts the first address offset to obtain the first address bit. In this example, integrated circuit 100 adds the first address offset to obtain the actual address bit and subtracts the second address offset to obtain the second address bit, and the fluid jetting device is expected to add the second address offset to the second address bit.

[0190] In some implementations, modifying the first address bit of the first packet includes applying an address offset adjustment based on a first address offset and a second address offset. In an example, the address offset adjustment is based on a net mathematical operation of the first and second address offsets. In the example, the first address offset is seven, the second address offset is fifteen, and the address offset adjustment is negative eight, based on the net result of adding seven and subtracting fifteen.

[0191] The fluid jetting device may include non-volatile memory bits that include a second address offset for the fluid jetting device. The fluid jetting device may modify the second address bits to obtain modified address bits. The fluid jetting device may include an array of nozzle circuits to jet droplets from each nozzle circuit in the array, and the modified address bits are used to select a nozzle circuit for jetting droplets.

[0192] In some implementations, transmitting the first address offset at the host-side data contact includes transmitting a modified address offset read at the device-side data contact and receiving the first address offset at the device-side data contact. Integrated circuit 100 can receive the address offset read from the host controller, modify the address offset read to ensure the fluid jet device responds with the first address offset, and provide the first address offset to the host controller. In the example, the first address offset is seven, the second address offset is fifteen, and the host controller provides an address offset read with address bits having a value of zero. If the fluid jet device is to respond, the response will be fifteen. However, in this example, integrated circuit 100 modifies the address offset read to have address bits with a value of negative eight, such that the response from the fluid jet device is seven, i.e., the first address offset.

[0193] By providing a first address offset to the host controller, integrated circuit 100 can cause the host controller to recognize the fluid jetting device as a fluid jetting device of the type associated with the first address offset. By modifying the address bits provided in the packet from the host controller, integrated circuit 100 can compensate for the fact that the host controller provides print data in packets configured to be used with the first address offset. In the example, when a low-fill print cartridge is installed, integrated circuit 100 provides an address offset for the fluid jetting device installed in a high-fill print cartridge, allowing the host controller to estimate the fill level of the low-fill print cartridge based on the characteristics of the high-fill print cartridge. Although in this example, the host controller provides data packets for use by the fluid jetting device installed in the high-fill print cartridge, integrated circuit 100 can modify them for use by the fluid jetting device installed in the low-fill print cartridge.

[0194] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, integrated circuit 100 includes a host-side contact array 110, which includes mode contacts, transmit contacts, and data contacts. Control logic 105 can recognize an address offset read, which includes a read enable data packet for setting two read enable bits, and when both read enable bits are set, the mode contact is logic high, the transmit contact is logic high, and the data contact is logic high. Control logic 105 can provide an address offset at the data contact in response to the address offset read. In this way, the integrated circuit or fluid jetting device can provide an address offset to the host controller. The address offset can be associated with a fluid jetting device or a different fluid jetting device.

[0195] Integrated circuit 100 may include non-volatile memory bits, including address offsets. Control logic 105 may receive a data packet including address bits at a data contact and modify the address bits using the address offsets to obtain modified address bits. Integrated circuit 100 may include a nozzle circuit array to eject droplets from each nozzle circuit in the array, the modified address bits being used to select a nozzle circuit for ejecting droplets.

[0196] Figure 17 An example integrated circuit 1720 is illustrated, which enables a host 1710 to treat a fluid jet device 1730 having a second address offset as if it were a fluid jet device having a first address offset. The host 1710 may include a host controller as discussed herein. In this example, the host 1710 is a printer. Integrated circuit 1720 may be integrated circuit 100 discussed herein. The fluid jet device 1730 may be a second type of fluid jet device on which the second address offset is stored.

[0197] At 1701, integrated circuit 1720 receives a query for an address offset from host 1710. This query may be an address offset read. At 1702, in response to the query, integrated circuit provides a first address offset. The first address offset may be associated with a first type of fluid jetting device. In this example, the first type of fluid jetting device may be installed in a high-fill print cartridge, such that host 1710 estimates the fill level of the print cartridge including fluid jetting device 1730 based on the characteristics of the high-fill print cartridge. In this example, this allows a low-fill print cartridge to be filled to the level of a high-fill print cartridge while host 1710 reads and / or indicates the ink level corresponding to the high fill.

[0198] At 1703, host 1710 provides data based on a first address offset. This data may be a data packet including address bits prepared by host 1710 based on the first address offset. At 1704, integrated circuit 1720 modifies the data based on a second address offset. In some embodiments, as discussed herein, integrated circuit 1720 modifies the data based on both the first and second address offsets. At 1705, integrated circuit 1720 provides the modified data to fluid injection device 1730.

[0199] Figure 18An example integrated circuit 1820 is illustrated, mapping bits of the fluid jet device 1830 to other bits of the fluid jet device 1830. The host 1810 may include a host controller as discussed herein. In this example, the host 1810 is a printer. The integrated circuit 1820 may be the integrated circuit 100 discussed herein. The fluid jet device 1830 may be a fluid jet device with a first bit written to it. In this example, the first bit is part of the usage gauge of the fluid jet device 1830. In this example, the host 1810 may not allow the fluid jet device 1830 to print because the gauge bit is written to it. The host 1810 may write to the fluid jet device's gauge while the fluid jet device is printing to measure the fluid jet device's usage and potential degradation. To prevent print quality degradation, the host 1810 may generate warnings and / or other indications when print data is provided to a used and potentially degraded fluid jet device for printing.

[0200] In some embodiments, integrated circuit 1820 may include a memory array of fluid jet devices in good condition and / or as intended operating within memory 2322 to identify the programming state of memory bits of the fluid jet devices in good condition and / or as intended operating. In this way, integrated circuit 1820 does not need to know what type of bit is being requested because integrated circuit 1820 includes the entire memory array of the fluid jet devices. In some embodiments, integrated circuit 1820 may include a mapping in memory 2322 of different types of bits to specific positions on the fluid jet devices in good condition and / or as intended operating. In an example, memory 2322 may include a mapping from usage gauge bits to specific positions on the fluid jet devices in good condition and / or as intended operating, such that integrated circuit 1820 can know which bits are requested and identify their programming state on the fluid jet devices in good condition and / or as intended operating.

[0201] At 1801, host 1810 provides integrated circuit 1820 with a read request for first bit 1832. The read request may include one or more identifiers of first bit 1832 corresponding to the position of first bit 1832 on fluid injection device 1830.

[0202] At 1802, the integrated circuit provides a read request for the second bit 1834 to the fluid jetting device 1830. The integrated circuit 1820 can provide a read request for the second bit 1834 in response to a read request for the first bit 1832. The integrated circuit 1820 can determine that a read request for the first bit 1832 should not be transmitted to the fluid jetting device 1830. In this example, the first bit 1832 is a usage gauge bit corresponding to the usage status of the fluid jetting device 1830. The integrated circuit 1820 may include a bit map 1822. The bit map 1822 can map bits on the fluid jetting device to other bits. In this example, the bit map 1822 can map bits corresponding to the state or type of the fluid jetting device 1830 to other bits to present a different state or type to the host 1810.

[0203] Bit mapping 1822 can map a first bit 1832 to a second bit 1834. In some embodiments, the second bit 1834 is an unused bit on the fluid jetting device. Unused bits may be bits that are not normally accessed by the host controller 1810, or bits that do not correspond to information requested by the host controller 1810 during normal operation. In some embodiments, bit mapping 1822 maps all used bits of the fluid jetting device 1830 to unused bits on the fluid jetting device 1830. In some embodiments, bit mapping 1822 maps a subset of used bits of the fluid jetting device 1830 to unused bits on the fluid jetting device 1830, the subset of used bits corresponding to bits whose values ​​are modified by integrated circuit 1820 for presentation to the host 1810. In subsequent requests, bit mapping 1822 can be used to provide the host 1810 with a response consistent with the actions of the host 1810. In the example, bit mapping 1822 allows a write to the first bit to be applied to the second bit, causing subsequent reads of the first bit to be redirected to the second bit, which has already been written based on an earlier write to the first bit from host 1810.

[0204] At 1803, the fluid jetting device 1803 provides a read response for the second bit 1834 to the integrated circuit 1820 in response to a read request for the second bit 1834. At 1804, the integrated circuit 1820 provides a read response for the second bit to the host 1810. In some embodiments, at 1804, the integrated circuit 1820 allows the read response for the second bit from the fluid jetting device 1830 to be transmitted unchanged or directly to the host 1810. The host 1810 can interpret the read response for the second bit as a read response for the first bit. In this way, the integrated circuit 1820 can redirect a read request for the first bit to the second bit.

[0205] Integrated circuit 1820 can redirect read and / or write requests to the first bit to other bits for various reasons. As discussed herein, integrated circuit 1820 can alter the usage indication of fluid jet device 1830. In some embodiments, integrated circuit 1820 can write a dummy address offset to an unused bit on fluid jet device 1830 and direct address offset reads from host 1810 to that dummy address offset. In some embodiments, integrated circuit 1820 can redirect read and / or write requests to change the value of the first bit as seen by host 1810. Integrated circuit 1820 can redirect read and / or write requests to provide host 1810 with a correct or expected response from the fluid jet device. In an example, integrated circuit 1820 can redirect read and / or write requests to provide an expected response to a partially programmed write request from fluid jet device 1830. In an example, integrated circuit 1820 can redirect read and / or write requests to provide a true and / or expected response to a parallel read request from fluid jet device 1830.

[0206] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, when integrated circuit 100 is connected to a fluid jetting device and the fluid jetting device is installed in a host device, first contact 101 can receive a first write signal corresponding to a write to a non-volatile memory bit on the fluid jetting device. Control logic 105 can, in response to the first write signal, store a programming level of the non-volatile memory bit in the memory of the integrated circuit based on the first write signal. First contact 101 can receive a first read signal corresponding to a read of the non-volatile memory bit. Control logic 105 can, in response to the first read signal, transmit a first response signal at first contact 101 based on the stored programming level. First contact 101 can receive a second write signal corresponding to a write to the non-volatile memory bit on the fluid jetting device. In response to the second write signal, control logic 105 can update the stored programming level of the non-volatile memory bit based on the second write signal, wherein a first change in the programming level based on the first write signal is greater than a second change in the programming level based on the second write signal. First contact 101 can receive a second read signal corresponding to a read of the non-volatile memory bit. Control logic 105 may, in response to a second read signal, transmit a second response signal at a host-side contact based on the stored programming level. In the example discussed in this disclosure, integrated circuit 100 typically receives signals at its contacts, which are thus received by integrated circuit 100, and more specifically by control logic 105 of integrated circuit 100.

[0207] Multiple signals corresponding to reading from and writing to the non-volatile memory bit may include a “tap test” of the non-volatile memory bit. A tap test can be used to verify that the non-volatile memory bit is in good condition and / or operating as expected, and can be incrementally programmed through multiple incremental writes (“tap”). The host controller may perform a tap test to verify that the fluid jet device is in good condition and / or operating as expected. The examples discussed herein relate to actions that integrated circuit 100 may take to provide the expected response to the host controller and to continue modifying the signals between the host controller and the fluid jet device, as discussed herein. Integrated circuit 100 may include stored programming levels to track multiple incremental writes of the tap test, thereby ensuring that integrated circuit 100 provides the correct response to the host controller, or provides a response corresponding to how the original OEM fluid jet device would respond.

[0208] In some implementations, integrated circuit 100 may allow the host controller to perform a touch test on the fluid jetting device, enabling the host controller to receive a correct response to the touch test. However, the touch test that the host controller is performing on it may have been written, causing the fluid jetting device to give an incorrect or unexpected response, thus failing the touch test. In some implementations, integrated circuit 100 may respond to a touch test performed by the host controller by redirecting the touch test signal to an unused bit, such as in combination with... Figure 18 The discussion focuses on how integrated circuits provide the correct response to touch tests, since unused bits are non-volatile memory bits on the fluid jet device that are in good condition and / or functioning as expected.

[0209] In some implementations, the stored programming level corresponds to the duration of the first write signal. In some implementations, updating the stored programming level includes updating the stored programming level to correspond to the duration of the first write signal and the duration of the second write signal. In an example, a bit on a fluid injection device can be programmed by applying a voltage for a predetermined amount of time. In this example, the longer the voltage is applied, the higher the voltage level of the bit, and the higher the programming level.

[0210] In some implementations, the duration of the first write signal is equal to the duration of the second write signal. In an example, the incremental write of the touch test has the same amplitude each time. In some implementations, the first and second write signals each increase the stored programming level. In some implementations, the increase in the stored programming level is cumulative. The cumulative increase in the stored programming level corresponds to the cumulative programming of a non-volatile memory bit as the voltage of that non-volatile memory bit increases.

[0211] In some implementations, the first response signal is based on whether the first read signal is voltage-driven or current-driven. The host controller can apply a predetermined voltage to the non-volatile memory bit and read a current response, or apply a predetermined current to the non-volatile memory bit and read a voltage response. Therefore, in order to provide a correct response, the integrated circuit must determine whether the first read signal is voltage-driven or current-driven and provide a current response or a voltage response, respectively.

[0212] In some implementations, the integrated circuit includes device-side contacts electrically connected to the fluid jetting device, and control logic 105 transmits a first write signal at the device-side contacts. Transmitting a first response signal at the host-side contacts may include transmitting a first read signal at the device-side contacts and receiving the first response signal at the device-side contacts. In this way, the fluid jetting device can transmit the first read signal to the fluid jetting device (to a target bit or another) and respond to the host controller using a response from the fluid jetting device (which is essentially correct).

[0213] The control logic can determine that the non-volatile bit has been programmed in response to the first write signal. As mentioned above, if the non-volatile bit has been programmed, it will not give a correct response to the touch test. Therefore, if the non-volatile bit has been programmed, the integrated circuit can generate a response to the touch test or redirect the touch test to another one.

[0214] In some embodiments, control logic 105, in response to a first write signal, transmits a modified write signal at a device-side contact corresponding to a write to a second non-volatile memory bit on the fluid jetting device, based on the first write signal. Transmitting a first response signal may include transmitting the modified write signal at the device-side contact and receiving the first response signal at the device-side contact. The modified write signal may be a first write signal modified to redirect the first write signal to another bit (such as an unused bit). In some embodiments, control logic 105, in response to a second write signal, transmits a second modified write signal at a device-side contact corresponding to a write to a second non-volatile memory bit on the fluid jetting device, based on the second write signal, wherein transmitting a second response signal includes transmitting the second modified write signal at the device-side contact and receiving the second response signal at the device-side contact. The second modified write signal may be a second write signal modified to redirect the second write signal to the bit to which the first write signal was redirected. In this way, the integrated circuit can redirect a touch test to another bit to provide the correct response to the touch test, as discussed herein. In some implementations, the stored programming level includes the programming level of a second non-volatile memory bit.

[0215] In some implementations, the first write signal includes: a first transition to logic high at the host-side mode contact, a logic high signal at the host-side data contact, and a second transition to logic high at the host-side transmit contact. In this way, the first write signal may include... Figure 14 One or more operations of the memory access protocol 1400. In some embodiments, the first read signal includes: a first transition to logic high at the host-side mode contact, a logic high signal at the host-side data contact, and a second transition to logic high at the host-side transmit contact, wherein the signal on the host-side data contact is in a high-impedance state. In some embodiments, after these register accesses are completed, the host-side mode and host-side data contacts return to logic low. Therefore, when an actual write or read event occurs, the host-side mode contact is low, the host-side data contact is low, and only the host-side transmit contact is high. In this way, the first read signal may include Figure 14 One or more operations of the memory access protocol 1400.

[0216] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In any of the following scenarios, when integrated circuit 100 is coupled to a fluid jetting device and the fluid jetting device is installed in a host device, host-side contact array 110 (e.g., printer-side contact array) can receive a first write signal sequence, which includes a first write signal for a data address, the first write signal having a first amplitude. After receiving the first write signal sequence, host-side contact array 110 can receive a first read signal sequence for reading the data address. In response to the first read signal sequence, integrated circuit 100 can provide a first response signal at a first level at host-side contact array 110. Integrated circuit 100 can receive a second write signal sequence at host-side contact array 110, which includes a second write signal for the same data address, the second write signal having a second amplitude. After receiving the second write signal, integrated circuit 100 can receive a second read signal sequence for reading the data address, and in response to the second read signal sequence, provide a second response signal at a second level at host-side contact array 110, wherein the ratio of the first amplitude to the first level is greater than the ratio of the second amplitude to the second level.

[0217] In some implementations, the first amplitude differs from the second amplitude. A first level may correspond to the first amplitude, and a second level may correspond to the second amplitude. The first amplitude may correspond to at least one of the duration of the first write signal, a voltage level, or a current level. The second amplitude may correspond to at least one of the duration of the second write signal, a voltage level, or a current level. The duration of the first write signal may be equal to the duration of the second write signal.

[0218] In some implementations, the first write signal and the second write signal each increment a response associated with a data address. The increment of the response can be cumulative. The first response signal can be based on whether the first read signal is voltage-driven or current-driven. In one example, the first response signal includes a current response based on the first read signal being voltage-driven. In another example, the first response signal includes a voltage response based on the first read signal being current-driven.

[0219] In some implementations, control logic 105 may transmit a first write signal at the device-side contact array 120, wherein transmitting a first response signal at the host-side contact array 110 includes transmitting a first read signal at the device-side contact array and receiving the first response signal at the device-side contact array. Control logic 105 may determine, in response to the first write signal, that a memory bit corresponding to the memory address has been programmed.

[0220] In some implementations, control logic 105 may, in response to a first write signal, transmit a modified write signal corresponding to a write to a second memory address at a device-side contact array, wherein transmitting a first response signal includes transmitting the modified write signal at the device-side contact array and receiving the first response signal at the device-side contact array. Control logic 105 may, in response to a second write signal, transmit a second modified write signal corresponding to a write to the second memory address at a device-side contact array, wherein transmitting a second response signal includes transmitting the second modified write signal at the device-side contact array and receiving the second response signal at the device-side contact array.

[0221] In some embodiments, the first write signal includes: a first transition to logic high at the host-side mode contact, a logic high signal at the host-side data contact, and a second transition to logic high at the host-side transmit contact. In some embodiments, the first read signal includes: a first transition to logic high at the host-side mode contact, a logic high signal at the host-side data contact, and a second transition to logic high at the host-side transmit contact, wherein the signal on the host-side data contact is in a high-impedance state.

[0222] Figure 19The illustration shows an example response curve 1900 for incremental programming of a non-volatile memory (NVM) bit. Response curve 1900 illustrates the relationship between the programming level of the NVM bit and the current response. A predetermined voltage can be applied to the NVM bit, and the resulting current can be measured as the current response. In the example, two volts are applied to the NVM bit, and the current response ranges from zero to five hundred microamps. In some implementations, a predetermined current can be applied to the NVM bit, and the resulting voltage can be measured as the voltage response.

[0223] The response curve 1900 may include a first measurement point 1901, a second measurement point 1902, a third measurement point 1903, a fourth measurement point 1904, a fifth measurement point 1905, and a sixth measurement point 1906. Measurement points 1901-1906 may correspond to incremental programming steps in a touch test. In some implementations, the touch test includes a subset of measurement points 1901-1906. In one example, the touch test includes only the first measurement point 1901, the third measurement point 1903, and the fifth measurement point 1905. In another example, the touch test includes only the first measurement point 1901, the second measurement point 1902, and the third measurement point 1903.

[0224] Each of the measurement points 1901-1906 can correspond to a read and a write operation in a touch test. In this example, the host controller can transmit a first write signal to give the NVM bit a programmed level associated with the first measurement point 1901. The host controller can then transmit a first read signal to read the programmed level of the NVM bit, thereby verifying that the NVM bit has a current response associated with the first measurement point 1901. The host controller can then transmit a second write signal to give the NVM bit a programmed level associated with the second measurement point 1902. The host controller can then transmit a second read signal to read the programmed level of the NVM bit, thereby verifying that the NVM bit has a current response associated with the second measurement point 1902. In this example, the host controller can transmit consecutive write and read signals to verify that the NVM bit responds according to the response curve 1900. In this way, the host controller can verify that the NVM bit is in good condition and / or operating as expected.

[0225] However, integrated circuit 100 can provide a current and / or voltage response to the host controller according to response curve 1900 in response to a touch test performed by the host controller. In this way, integrated circuit 100 can modify the signal between the host controller and the fluid injection device without causing the host controller to only detect normal operation. Integrated circuit 100 can determine the amplitude of various write signals for the touch test and determine the correct response to a read signal for the touch test based on response curve 1900. Integrated circuit 100 can store the programming level of NVM bits to determine the correct response to a read signal for the touch test. Integrated circuit 100 can determine whether the read signal is current-driven or voltage-driven and provide the correct voltage or current response respectively.

[0226] If integrated circuit 100 only determines whether the NVM bit has been written or not (e.g., programmed or unprogrammed), without considering the magnitude of the write, then integrated circuit 100 will respond to the incremental write with the current response characteristics of a fully written or programmed bit. This would allow the host controller to determine that the NVM bit is not in good condition and / or is not operating as expected, or that the signal between the host controller and the fluid jet device is corrupted (e.g., not transmitted correctly due to an electrical interface problem between the host controller and the fluid jet device). Therefore, to avoid causing the host controller to determine that there is a problem with the electrical interface between the host controller and the fluid jet device, integrated circuit 100 recognizes the incremental write and responds according to the response curve 1900, or redirects the incremental write to another die on the fluid jet device.

[0227] In some implementations, as discussed herein, integrated circuit 100 can redirect the read and write signals of a touch test to different NVM bits on the fluid jetting device. In this way, the different NVM bit provides the correct response because it is the NVM bit on the fluid jetting device that is in good condition and / or operating as expected.

[0228] In some implementations, measurement points 1901-1906 are evenly spaced according to the programming level. Since the write signals for the touch test have the same amplitude, measurement points 1901-1906 can be evenly spaced according to the programming level. Successive write signals with the same amplitude can increment the programming level of the NVM bit by the same amount. Successive write signals with the same amplitude can increase the current response by successively decreasing the current response. In the example, a first difference between the current response of the NVM bit at the programming level of zero and the current response of the NVM bit at the first measurement point 1901 can be greater than a second difference between the current response of the NVM bit at the first measurement point 1901 and the current response of the NVM bit at the second measurement point 1902.

[0229] Figure 20An example integrated circuit 2020 is illustrated that provides a response to incremental write and read signals from host 2010. Incremental write and read signals can be touch tests as discussed herein. Host 2010 may include a host controller. Host 2010 can perform touch tests to verify that the fluid jetting device is operating as expected. In the example, host 2010 can determine that there is a problem with the electrical interface or connection between host 2010 and the fluid jetting device and indicate that the print cartridge must be reinstalled. Integrated circuit 2020 can determine the correct response to the touch test to prevent host 2010 from determining that there is a problem with the fluid jetting device or the electrical interface between host 2010 and the fluid jetting device.

[0230] At position 2001, host 2010 transmits a first write signal to integrated circuit 2020 for the NVM bit. In this example, the first write signal corresponds to Figure 19 The first measurement point is 1901. The host 2010 transmits a first write signal on one or more contacts to be electrically connected to the fluid jet device. Therefore, the host 2010 is unaware of the integrated circuit 2020 and must use the response to the touch test to determine whether the host 2010 is communicating with the fluid jet device in good condition and / or operating as intended. The first write signal may include a sequence of write signals from different contacts on the host controller. Each different write signal of the touch test may include this sequence of write signals, and each different read signal of the touch test may include a sequence of read signals.

[0231] In some implementations, in response to a first write signal, integrated circuit 2020 determines a programming level for the NVM bit corresponding to the amplitude of the first write signal. Integrated circuit 2020 does not transmit the first write signal to the fluid jet die, and the NVM bit is not actually written. Therefore, the stored programming level of the NVM bit does not correspond to the actual programming level of the NVM bit. Integrated circuit 2020 stores the determined programming level of the NVM bit as a stored programming level in its memory 2022.

[0232] In some implementations, in response to a first write signal, integrated circuit 2020 redirects the first write signal to a second NVM bit on the fluid jet die. Integrated circuit 2020 may redirect the first write signal to the second NVM bit based on a mapping stored in memory 2022. Integrated circuit 2020 may redirect the first write signal to the second NVM bit and store the mapping from the NVM bit to the second NVM bit in memory 2022.

[0233] At position 2002, host 2010 transmits a first read signal for the NVM bit to integrated circuit 2020. In this example, the first read signal corresponds to Figure 19 The first measurement point is 1901. The first read signal may include a read signal sequence, which includes a sequence of signals from different contacts on the host controller.

[0234] In some implementations, in response to a first read signal, integrated circuit 2020 determines a first response based on the stored programming level of the NVM bit in memory 2022. Integrated circuit 2020 determines whether the first read signal is a current-driven or voltage-driven read of the NVM bit. Integrated circuit 2020 can calculate the first response based on how the NVM bit will respond. In the example, integrated circuit 2020 calculates the first response based on the response curve 1900 of Figure 1.

[0235] In some implementations, in response to a first read signal, integrated circuit 2020 redirects the first read signal to a second NVM bit on the fluid jet die. Integrated circuit 2020 may redirect the first read signal to the second NVM bit based on a mapping stored in memory 2022. Integrated circuit 2020 may receive a first response from the second NVM bit.

[0236] At point 2003, integrated circuit 2020 transmits a first response to host 2010. Host 2010 can compare the first response with a predetermined response to determine whether the first response is correct, or whether it corresponds to a response from an NVM bit that is in good condition and / or operating as expected. Alternatively, host 2010 can determine that the first response is incorrect. If host 2010 determines that the first response is correct, host 2010 can complete the touch test and begin sending print data or continue the touch test.

[0237] At point 2004, host 2010 transmits a second write signal to integrated circuit 2020 for the NVM bit. As described above, host 2010 is unaware of integrated circuit 2020, and the second write signal is intended for the NVM bit on the fluid injection device. In this example, the second read signal corresponds to... Figure 19 The second measurement point is 1902.

[0238] In some implementations, in response to a second write signal, integrated circuit 2020 determines the programming level of the NVM bit corresponding to the amplitudes of the second write signal and the first write signal. Integrated circuit 2020 may increment the stored programming level of the NVM bit in memory 2022 based on the amplitude of the second write signal. Integrated circuit 2020 does not transmit the second write signal to the fluid jet die, and the NVM bit is not actually written. Therefore, the stored programming level of the NVM bit does not correspond to the actual programming level of the NVM bit. Integrated circuit 2020 updates the stored programming level of the NVM bit in its memory 2022.

[0239] In some implementations, in response to a second write signal, integrated circuit 2020 redirects the second write signal to a second NVM bit on the fluid jet die. Integrated circuit 2020 may redirect the second write signal to the second NVM bit based on a mapping stored in memory 2022.

[0240] At position 2005, host 2010 transmits a second read signal for the NVM bit to integrated circuit 2020. In this example, the second read signal corresponds to Figure 19 The second measurement point is 1902. The second read signal may include a read signal sequence, which includes a sequence of signals from different contacts on the host controller.

[0241] In some implementations, in response to the second read signal, integrated circuit 2020 determines a second response based on the updated stored programming level of the NVM bit in memory 2022. Integrated circuit 2020 determines whether the second read signal is a current-driven or voltage-driven read of the NVM bit. Integrated circuit 2020 can calculate the second response based on how the NVM bit will respond. In the example, integrated circuit 2020 calculates the second response based on the response curve 1900 of Figure 1.

[0242] In some implementations, in response to a second read signal, integrated circuit 2020 redirects the second read signal to a second NVM bit on the fluid jet die. Integrated circuit 2020 may redirect the second read signal to the second NVM bit based on a mapping stored in memory 2022. Integrated circuit 2020 may receive a second response from the second NVM bit.

[0243] At position 2006, integrated circuit 2020 transmits a second response to host 2010. Host 2010 can compare the second response with a predetermined response to determine whether the second response is correct, or whether it corresponds to a response from an NVM bit on the fluid jet die that is in good condition and / or operating as expected. Alternatively, host 2010 can determine that the second response is incorrect. If host 2010 determines that the second response is correct, host 2010 can complete the touch test and begin sending print data or continue the touch test.

[0244] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6BIn any of these embodiments, when integrated circuit 100 is coupled to the fluid jetting device and the fluid jetting device is mounted in the host device, control logic 105 may, in response to a first memory access sequence accessing a first memory bit, provide a first signal at host-side contact array 110 having a first value corresponding to the first memory bit. The first value may correspond to the programming level of the first memory bit. In an example, if the first memory bit is not programmed, the first value corresponds to the current or voltage response characteristic of the unprogrammed bit. In an example, if the first memory bit is programmed, the first value corresponds to the current or voltage response characteristic of the programmed bit. In response to a second memory access sequence accessing a second memory bit, control logic 105 may provide a second signal at host-side contact array 110 having a second value corresponding to the second memory bit. The second value may correspond to the programming level of the second memory bit. In some embodiments, the programming level of the second memory bit may be programmed or unprogrammed.

[0245] In response to a third memory access sequence that accesses a combination of first and second memory bits, control logic 105 may provide a third signal at host-side contact array 110 having a third value corresponding to the combination of first and second memory bits. The third value may correspond to the programming level of the first and second memory bits. The third value corresponds to the current or voltage response characteristics of the combination of the programming levels of the first and second memory bits. In an example, if both first and second memory bits are programmed, the third value corresponds to the current or voltage response characteristics of two programmed bits in parallel. In an example, if neither first nor second memory bits are programmed, the third value corresponds to the current or voltage response characteristics of two unprogrammed bits in parallel. In an example, if one of the first and second memory bits is programmed and the other is not programmed, the third value corresponds to the current or voltage response characteristics of the programmed and unprogrammed bits in parallel.

[0246] In some implementations, the memory of integrated circuit 100 stores a first value, a second value, and a third value separately. Integrated circuit 100 can determine, based on the received memory access sequence, which of the first, second, and third values ​​should be provided at the host-side contact array 110. The host controller can execute the first, second, and third memory access sequences to verify that the first and second memory bits are in good condition and / or operating as expected, and / or that the fluid injection device is in good condition and / or operating as expected.

[0247] In some implementations, the third value corresponds to the number of programmed bits in the first and second memory bits. As described above, the third value may depend on zero, one, or two of the first and second memory bits being programmed. Control logic 105 may determine the number of programmed bits in the first and second memory bits. Control logic 105 may determine the number of programmed bits in order to determine the correct response to the host controller. Control logic 105 may determine the number of programmed bits based on the mapping of the fluid jet die bits to the memory of integrated circuit 100. In an example, control logic 105 may identify the first and second memory bits, use a bit mapping to map the first and second memory bits to locations in the memory of integrated circuit 100, and read those locations in the memory to determine whether the first and second memory bits are programmed.

[0248] In some implementations, transmitting the third signal includes determining whether a read of the combination of the first and second memory bits is voltage-driven or current-driven. As discussed herein, voltage-driven reads produce a current response, and current-driven reads produce a voltage response. Control logic 105 can determine whether a read of the combination of the first and second memory bits is voltage-driven or current-driven to provide a current response or a voltage response, respectively.

[0249] In some implementations, the memory access sequence includes: a first transition to logic high at a host-side mode contact of the contact array, a logic high signal at a host-side data contact of the contact array, and a second transition to logic high at a host-side transmit contact of the contact array.

[0250] In some implementations, control logic 105 may disable the third signal in response to detecting the end of a memory access protocol. In this way, control logic 105 may provide the third signal only when the host controller is requesting it or only when the host controller anticipates it. Control logic 105 may disable the third signal after a predetermined amount of time. Control logic 105 may provide the third signal during the duration of the memory access protocol. In an example, control logic 105 may provide the third signal at the host-side data contact as long as a logic high signal remains on the host-side transmit contact.

[0251] Control logic 105 can provide a fourth signal having a fourth value corresponding to the combination of the second and third memory bits in response to a fourth memory access sequence that accesses a combination of the second and third memory bits. In this way, integrated circuit 100 can store values ​​and provide responses to various parallel reads corresponding to different memory bits. Control logic 105 can also provide a fifth signal having a fifth value corresponding to the combination of the first, second, and third memory bits in response to a fifth memory access sequence that accesses a combination of the first, second, and third memory bits. In this way, integrated circuit 100 can store values ​​and provide responses to various different memory bits and various different numbers of memory bits. In some embodiments, the memory of the integrated circuit stores the first, second, third, and fifth values ​​separately.

[0252] refer to Figure 1A , Figure 1B , Figures 2 to 4 and Figure 6B In either case, the host-side contact array 110 may include a first host-side column, which includes host-side transmit contacts. The host-side contact array may also include a second host-side column, which includes host-side mode contacts and host-side data contacts. Control logic 105 may receive at the host-side contact array 110 one or more first signals corresponding to a memory access protocol for accessing the memory of the fluid jet dies, receive at the host-side contact array a data packet indicating the first and second bits, and, in response to the data packet, transmit at the host-side contact array a second signal corresponding to a read of the first and second bits. The second signal may correspond to a signal obtained by connecting both the first and second bits in parallel to a single contact. In an example, the second signal corresponds to a current obtainable by driving a predetermined voltage across the first and second bits in parallel. In this way, integrated circuit 100 can provide a correct response to parallel reads of multiple bits on the fluid jet device. The host controller may request parallel reads of multiple bits on the fluid jet device to verify that the fluid jet device is operating as expected. If integrated circuit 100 provides an incorrect response to the parallel bit read, the host controller can determine that the fluid jet device is damaged, and / or there is a problem with the electrical interface between the host controller and the fluid jet device. Integrated circuit 100 can recognize the parallel bit read and provide the expected response to the host controller.

[0253] In some implementations, one or more first signals corresponding to the memory access protocol include: a first transition to logic high at the host-side mode contact, a logic high signal at the host-side data contact, and a second transition to logic high at the host-side transmit contact. In some implementations, as discussed herein, only the host-side transmit contact remains logic high during an actual read event. The data contact can be in a high-impedance state to transmit a response to a read request.

[0254] In some implementations, control logic 105 receives data packets by receiving data packets at host-side data contacts. The data packets may include address bits indicating addresses corresponding to first and second memory bits.

[0255] In some implementations, the second signal is based on the number of programmed bits in the first and second bits. In some implementations, the second signal has a first value if neither the first nor the second bit is programmed; a second value if one of the first and second bits is programmed; and a third value if both the first and second bits are programmed. In some implementations, control logic 105 determines the number of programmed bits in the first and second bits. In some implementations, control logic 105 determines the number of programmed bits based on the bit-to-memory mapping of the fluid jet die. In some implementations, transmitting the second signal includes determining whether the read of the first and second bits is voltage-driven or current-driven.

[0256] In some embodiments, the control logic receives a second data packet indicating the second and third bits at the host-side contact array, and in response to the second data packet, transmits a third signal corresponding to the reading of the second and third bits at the host-side contact array. In this way, the integrated circuit 100 can provide a correct response to parallel bit reads of various different bits. In some embodiments, the control logic 105 receives a third data packet indicating the first, second, and third bits at the host-side contact array, and in response to the second data packet, transmits a third signal corresponding to the reading of the first, second, and third bits at the host-side contact array. In this way, the integrated circuit 100 can provide a correct response to parallel reads of different bits and different numbers of bits.

[0257] In some embodiments, the device-side contact array 120 includes a first device-side column and a second device-side column. The first device-side column includes device-side transmit contacts, and the second device-side column includes device-side mode contacts and device-side data contacts. The device-side contact array 120 may include additional contacts, such as... Figure 4 As shown.

[0258] As discussed herein, integrated circuit 100 can redirect reads of bits on the fluid jet device to other bits to provide a correct response to the host controller. In the example, integrated circuit 100 receives a parallel read request for two bits in the usage gauge of the fluid jet device, which contains bits used to track the usage of the fluid jet device. In this example, the fluid jet device has a fully filled usage gauge (i.e., all bits are programmed), indicating heavy usage and potentially degraded print quality. In this example, integrated circuit 100 redirects the parallel read request for these two bits to two other unprogrammed bits on the fluid jet die. In this example, the host controller can determine that these memory bits have values ​​that match the expected values ​​and / or states.

[0259] Figure 21 An example voltage response curve 2100 for parallel bit reads is illustrated. Response curve 2100 shows an example voltage response for parallel bit reads at different programming levels. The voltage response curve can be obtained by driving a predetermined current in parallel to two bits to measure the voltage response. The voltage response curve can include a one-bit response curve 2110 and a two-bit response curve 2120. The one-bit response curve 2110 corresponds to a parallel bit read of two bits, where one of the two bits is programmed. The two-bit response curve 2120 corresponds to a parallel bit read of two bits, where both bits are programmed. The two bits can have the same programming level. If neither bit is programmed, the voltage response is zero.

[0260] The one-bit response curve 2110 and the two-bit response curve 2120 do not intersect; therefore, the number of programmable bits is distinguishable despite the different programming levels. The first programming level 2101 represents the first difference between the one-bit response curve 2110 and the two-bit response curve 2120. The second programming level 2102 represents the second difference between the one-bit response curve 2110 and the two-bit response curve 2120. The second programming level 2102 is higher than the first programming level 2101, and the second difference is greater than the first difference. The third programming level 2103 represents the third difference between the one-bit response curve 2110 and the two-bit response curve 2120. The third programming level 2103 is higher than the second programming level 2102, and the third difference is greater than the second difference.

[0261] Figure 22An example current response curve 2200 for parallel bit reads is illustrated. Response curve 2200 shows example current responses for parallel bit reads at different programming levels. Current response curves can be obtained by driving a predetermined voltage in parallel to two bits to measure the current response. Current response curves can include a one-bit response curve 2210 and a two-bit response curve 2220. One-bit response curve 2210 corresponds to a parallel bit read of two bits, where one of the two bits is programmed. Two-bit response curve 2220 corresponds to a parallel bit read of two bits, where both bits are programmed. These two bits can have the same programming level. If neither bit is programmed, the voltage response is zero.

[0262] The one-bit response curve 2210 and the two-bit response curve 2220 do not intersect; therefore, the number of programmable bits is distinguishable despite the different programming levels. The first programming level 2201 represents the first difference between the one-bit response curve 2210 and the two-bit response curve 2220. The second programming level 2202 represents the second difference between the one-bit response curve 2210 and the two-bit response curve 2220. The second programming level 2202 is higher than the first programming level 2201, and the second difference is greater than the first difference. The third programming level 2203 represents the third difference between the one-bit response curve 2210 and the two-bit response curve 2220. The third programming level 2203 is higher than the second programming level 2202, and the third difference is greater than the second difference.

[0263] Figure 23 The illustration shows an example integrated circuit 2320 that responds to a parallel bit read from a host 2310. At 2301, the host 2310 transmits a first request to read a first memory bit on a fluid jet device. The first request may include a first memory access sequence for accessing the first memory bit. The first memory access sequence may include... Figure 14 One or more operations of the memory access protocol 1400 and data packets including address bits for the first memory bit.

[0264] In some implementations, in response to a first request to read a first memory bit, integrated circuit 2320 determines the programming state of the first bit and selects a first value 2324 from memory 2322 of integrated circuit 2320 based on the programming state of the first bit. Host 2310 has an expected value corresponding to what the host 2310 expects the first value to be. Host 2310 compares the expected value with the response from integrated circuit 2320 to ensure that the fluid jet device gives the correct response. The expected value at host 2310 may be based on the state of memory bits of the fluid jet die in good condition and / or operating as expected. In some implementations, integrated circuit 2320 may include a copy of the memory array of the fluid jet device in good condition and / or operating as expected in memory 2322 to identify the programming state of memory bits in the copy of the memory array. In this way, integrated circuit 2320 does not need to know what type of bit is being requested because integrated circuit 2320 includes a copy of the entire memory array of the fluid jet device. In some implementations, integrated circuit 2320 may include in memory 2322 a mapping of different types of bits to specific positions on the associated fluid injection device, provided that these bits are in good condition and / or operate as intended. In an example, memory 2322 may include a mapping from usage gauge bits to specific positions on the associated fluid injection device, provided that these bits are in good condition and / or operate as intended, such that integrated circuit 2320 can know which bits are requested and identify their programming status and / or operation as intended.

[0265] In some implementations, in response to a first request to read a first memory bit, integrated circuit 2320 identifies a first other bit on the fluid jetting device that has a desired programming state and redirects the first request to read the first memory bit to the first other memory bit. Integrated circuit 2320 may identify the first other bit based on a mapping from the first bit to the first other bit in memory 2322. Based on the redirected third request, integrated circuit 2320 can receive a signal with a first value 2324 from the fluid jetting device.

[0266] At 2302, in response to the first request, integrated circuit 2320 provides a first signal having a first value corresponding to the first memory bit. At 2303, host 2310 transmits a second request to read a second memory bit on the fluid jetting device. The first request may include a second memory access sequence for accessing the first memory bit. The second memory access sequence may include... Figure 14The memory access protocol 1400 includes one or more operations and data packets including address bits for a second memory bit. The second memory access sequence may be the same as the first memory access sequence, except that the first memory access sequence includes address bits for a first memory bit, while the second memory access sequence includes address bits for a second memory bit.

[0267] In some implementations, in response to a second request to read the second memory bit, integrated circuit 2320 determines the programming state of the second bit and selects a second value 2326 from the memory 2322 of integrated circuit 2320 based on the programming state of the second bit.

[0268] In some implementations, in response to a second request to read a second memory bit, integrated circuit 2320 identifies a second additional bit on the fluid jetting device that has a desired programming state and redirects the second request to read the second memory bit to the second additional memory bit. Integrated circuit 2320 may identify the second additional bit based on a mapping from the second bit to the second additional bit in memory 2322. Based on the redirected third request, integrated circuit 2320 can receive a signal with a second value 2326 from the fluid jetting device.

[0269] At 2304, in response to the second request, integrated circuit 2320 provides a second signal having a second value corresponding to the second memory bit. At 2305, host 2310 transmits a third request to read the first and second memory bits in parallel. The third request may include a third memory access sequence for accessing the first and second memory bits. This third memory access sequence may include... Figure 14 The memory access protocol 1400 includes one or more operations and data packets including address bits for the first and second memory bits. A third memory access sequence may be the same as the first and second memory access sequences, except that the third memory access sequence includes address bits for the first memory bit and address bits for the second memory bit.

[0270] By transmitting the first, second, and third requests, host 2310 is able to receive the values ​​of the first and second bits and then compare these values ​​with parallel bit reads. This allows host 2310 to ensure that the parallel bit reads are consistent with the values ​​of the first and second bits that were previously returned individually. Integrated circuit 2320 can store the first value 2324 and the second value 2326 in memory 2322 to provide a consistent response to multiple reads and parallel reads of the first and second memory bits.

[0271] In some embodiments, in response to a third request to read the first and second memory bits, integrated circuit 2320 determines the programming state of the first and second memory bits and selects a third value 2328 from the memory 2322 of integrated circuit 2320 based on the programming state of the first and second memory bits and / or a first value 2324 and a second value 2326. In some embodiments, integrated circuit 2320 is based on... Figure 21 The response curve 2100 or Figure 22 The response curve 2200 selects the third value 2328.

[0272] In some implementations, in response to a third request to read the first and second memory bits, integrated circuit 2320 redirects the third request to read other first and second memory bits. Integrated circuit 2320 can identify the first and second other memory bits based on the mapping of the first and second memory bits to the first and second other memory bits in memory 2322. Based on the redirected third request, integrated circuit 2320 can receive a signal with a third value 2328 from the fluid injection device.

[0273] At 2306, integrated circuit 2320 provides host 2310 with a third signal having a third value 2328 corresponding to the parallel reads of the first and second memory bits. In this way, integrated circuit 2320 provides consistent and expected response signals to multiple reads and parallel reads of the first and second memory bits. In response to the third signal, host 2310 can determine that the fluid injection device is in good condition and / or operating as expected.

[0274] This disclosure relates to examples of integrated circuits used in association with printhead cartridges. These cartridges are equipped with printheads, also known as fluid jetting devices (which can be implemented in applications other than printing). The integrated circuit can be an intermediate circuit between an OEM (Original Equipment Manufacturer) cartridge and the printer, or it can be part of the printhead, such as a non-OEM printhead. Different aspects of the integrated circuit may include any one or any combination of the following features.

[0275] The integrated circuit may include a first contact to receive a first address bit from a host controller. The integrated circuit may include a second contact to transmit a second address bit to the fluid jetting device, the second address bit being based on the first address bit. The first contact may be a contact of a host-side contact array, which includes host-side data contacts for receiving a first data packet from the host controller. The second contact may be a contact of a device-side contact array, which includes device-side data contacts for outputting second data packets to the fluid jetting device, each second data packet corresponding to a received first data packet. The integrated circuit may be configured to transmit a second data packet modified relative to a corresponding first data packet, such that the fluid jetting device jets fluid based on the second data packet. The first contact may be used to receive the first data packet from the host controller, the first data packet including address bits and random data. The second contact may be used to transmit the second data packet to the fluid jetting device.

[0276] The integrated circuit may include control logic to generate a second data packet including a second address bit based on a first address bit. The control logic may be configured to generate the second data packet based on the first packet when the first packet is received. The first data packet may include a first payload and additional bits. The control logic may be configured to generate a second data packet including a second payload based on the first payload. The control logic may be configured to modify the first address data packet based on an address offset to generate the second packet. The first data packet may include random data. The control logic is configured to respond to the host controller with a data signal in response to a memory read request from the host controller (e.g., without transmitting a signal to the fluid jetting device), thereby further configuring the control logic to transmit other signals to the fluid jetting device in a modified or unmodified format.

[0277] The integrated circuit may include a contact array of parallel contact columns to align with corresponding host contacts and / or cartridge contacts. The contact array may include one or more of transmitter contacts, analog contacts, mode contacts, clock contacts, and at least one data contact. The control logic can be configured to: (a) receive: (i) a first data access signal sequence, comprising a high signal on a mode contact, a low signal on a transmit contact, and a signal on a data contact, over a period of multiple clock cycles; (ii) a second data access signal sequence, comprising a high signal on a mode contact, a low signal on a transmit contact, and a data access signal on a data contact, the data signal indicating a read or write event; and, in response to the first and second data access signal sequences: (c) if the data access signal indicates a read event, respond with a data value corresponding to the data access signal of the read event; and (b) if the data access signal indicates a write event, process the bits of the write event to respond with the processed bits in a subsequent read event; and, in response to other signal sequences not including the first and second data access signal sequences, not respond with a data value, thereby the control logic can be configured to transmit other signal sequences in a modified or unmodified format.

[0278] The topics described herein sometimes illustrate different components contained within or connected to different other components. It should be understood that such depicted architectures are merely exemplary, and many other architectures that achieve the same functionality can actually be implemented. Conceptually, any arrangement of components that achieve the same functionality is effectively “associated” to achieve the desired functionality. Therefore, any two components combined herein to achieve a particular function can be considered “associated” with each other to achieve the desired functionality regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” to each other to achieve the desired functionality, and any two components that can be suchly associated can also be considered “operably coupled” to each other to achieve the desired functionality. Specific examples of components that can be operatedly coupled include, but are not limited to, components that can physically cooperate and / or physically interact, and / or components that can wirelessly interact and / or wirelessly interact, and / or components that can logically interact and / or logically interact.

[0279] Regarding the use of virtually any plural and / or singular terms in this document, those skilled in the art can appropriately convert from plural to singular and / or from singular to plural depending on the context and / or application. For clarity, various singular / plural permutations may be explicitly stated herein. For example, a statement about a plural element may be understood to include the element under discussion.

[0280] Those skilled in the art will understand that, in general, the terminology used herein, and especially in the appended claims (e.g., the body of the appended claims), is intended to be “open-ended” terminology (e.g., the term “comprising” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “at least having,” the term “including” should be interpreted as “comprising but not limited to,” etc.). Those skilled in the art will further understand that if there is an intent to specify a particular number for the introduced claim statement, such intent will be explicitly stated in the claim, and if such a statement is absent, such intent does not exist. For example, to aid understanding, the following appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce the claim statement. However, the use of such phrases should not be construed as implying that introducing a claim statement with the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to the invention containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and, for example, the indefinite articles “a” or “an” (e.g., “a” and / or “an” should typically be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim statements. Furthermore, even when a specific number of introduced claim statements is explicitly stated, those skilled in the art will recognize that such a statement should typically be interpreted as meaning at least the number stated (e.g., a simple statement of “two statements” without other modifiers typically means at least two statements, or two or more statements). Furthermore, in cases where conventional expressions such as "at least one of A, B, and C" are used, such grammatical structures are generally intended to convey the meaning of the conventional expression as would be understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" includes, but is not limited to, systems having only A, only B, only C, having A and B together, having A and C together, having B and C together, and / or having A, B, and C together, etc.). In cases where conventional expressions such as "at least one of A, B, or C" are used, such grammatical structures are generally intended to convey the meaning of the conventional expression as would be understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" includes, but is not limited to, systems having only A, only B, only C, having A and B together, having A and C together, having B and C together, and / or having A, B, and C together, etc.). Those skilled in the art will further understand that, whether in the specification, claims, or drawings, virtually any parallel words and / or phrases presenting two or more alternative terms should be understood to presuppose the possibility of including one term, any one term, or both terms. For example, the phrase “A or B” would be understood to include the possibility of “A” or “B” or “A and B”.Furthermore, unless otherwise stated, the terms “approximately,” “about,” “around,” “basically,” etc., are used to mean positive or negative 10 percent.

[0281] For purposes of illustration and description, the foregoing description of illustrative examples has been presented. The foregoing description is not intended to be exhaustive or to limit the precise forms disclosed, and modifications and variations are possible or may be derived from practice of the disclosed examples in light of the above teachings. The scope of the invention is intended to be defined by the appended claims and their equivalents.

Claims

1. An integrated circuit, comprising: The first contact is used to receive the first address bit from the host controller; as well as The second contact is used to transmit a second address bit to the fluid injection device, the second address bit being based on the first address bit.

2. The integrated circuit as claimed in claim 1, wherein, The first address bit includes a first address code, and the second address bit includes a second address code. The first address code is used to select the first nozzle circuit of the fluid jetting device, and the second address code is used to select the second nozzle circuit of the fluid jetting device.

3. The integrated circuit as described in claim 2, wherein, The first nozzle circuit is located at a first position on the fluid jetting device, and the second nozzle circuit is located at a second position on the fluid jetting device.

4. The integrated circuit as described in claim 3, wherein, The integrated circuit is configured to receive a first data packet from the host controller and transmit a second data packet to the fluid jetting device, wherein the first data packet and the second data packet respectively include the first address code and the second address code.

5. The integrated circuit according to any one of claims 2 to 4, wherein, The integrated circuit includes control logic that maps the first address code to the second address code.

6. The integrated circuit of claim 5, wherein the control logic is configured to determine the second address bit by converting between the first address bit sequence and the second address bit sequence based on the first address bit sequence received from the host controller.

7. The integrated circuit of any one of claims 5 to 6, wherein the control logic includes at least one of mathematical operations and a lookup table.

8. The integrated circuit according to any one of claims 4 to 7, wherein, The second data packet includes: Header, the header including a first subset of the address bits; The middle part; and The tail portion includes a second subset of the address bits, and the first subset and the second subset of the address bits include the second address code.

9. The integrated circuit as claimed in claim 8, wherein, The intermediate part includes basic data.

10. The integrated circuit of claim 8, wherein the tail portion includes a control bit.

11. The integrated circuit according to any one of claims 4 to 8, wherein, The first data packet and the second data packet include the same primitive bits.

12. The integrated circuit according to any one of claims 1 to 9, wherein, The fluid jetting device includes a nozzle circuit array for jetting droplets from each nozzle circuit in the array, and a second address bit for selecting the second nozzle circuit for jetting droplets.

13. The integrated circuit according to any one of claims 1 to 10, further comprising: A host-side contact array, the host-side contact array including the first contact, the host-side contact array including at least one contact column to contact a corresponding contact column of the host controller, for transmitting signals between the integrated circuit and the host printer; as well as A device-side contact array, wherein the device-side contact array includes the second contact.

14. The integrated circuit according to any one of claims 1 to 11, wherein, The first address bit is received in the packet, and the integrated circuit is used to modify the packet such that a first part of the packet is modified, the first part including the address bit, and a second part of the packet is not modified.

15. The integrated circuit of any one of claims 1 to 12, wherein the integrated circuit further comprises: A first clock contact is used to receive a first clock signal from the host controller; as well as The second clock contact is used to output a second clock signal to the fluid injection device.

16. The integrated circuit of claim 13, further comprising: A first transmitting contact is used to receive a first transmitting signal from the host controller; as well as The second transmitting contact is used to output a second transmitting signal to the fluid injection device, wherein the first transmitting signal is in phase with the first address bit based on the first clock signal, and the second transmitting signal is in phase with the second address bit based on the second clock signal.

17. The integrated circuit of any one of claims 1 to 6, wherein the integrated circuit is attached to or can be attached to a print cartridge including the fluid jetting device, the print cartridge being inserted into a printer including the host controller.

18. An integrated circuit, comprising: Host-side contact array, the host-side contact array comprising: The host-side data contact is used to receive the first data packet from the host controller; as well as Device-side contact array, the device-side contact array comprising: The device-side data contacts are used to output second data packets to the fluid injection device, each second data packet corresponding to a received first data packet. The integrated circuit is configured to transmit a second data packet modified relative to the corresponding first data packet, such that the fluid jetting device jets fluid based on the second data packet.

19. The integrated circuit of claim 18, wherein the host-side contact array comprises: A host-side clock contact is used to receive a first clock signal from the host controller; as well as A host-side transmitter contact is used to receive a first transmitter signal from the host controller; The device side contact array includes: A device-side clock contact is used to output a second clock signal to the fluid jetting device; as well as The device-side transmitting contact is used to output a second transmitting signal to the fluid jetting device.

20. The integrated circuit as claimed in any one of claims 18 to 19, wherein, The first address bit of a first data packet in the first data packet includes a first address code, and the second address bit of a second data packet in the second data packet includes a second address code, wherein the first address code selects the first nozzle circuit of the fluid jetting device, and the second address code selects the second nozzle circuit of the fluid jetting device.

21. The integrated circuit of claim 20, wherein, The first nozzle circuit is located at a first position on the fluid jetting device, and the second nozzle circuit is located at a second position on the fluid jetting device.

22. The integrated circuit according to any one of claims 20 to 21, wherein, The integrated circuit includes control logic that maps the first address code to the second address code.

23. The integrated circuit of claim 22, wherein the control logic is configured to determine the second address code by converting between the first address bit sequence and a second address bit sequence based on a first address bit sequence received from the host controller.

24. The integrated circuit of any one of claims 19 to 20, wherein the control logic includes at least one of mathematical operations and a lookup table.

25. The integrated circuit as claimed in any one of claims 18 to 24, wherein, The second data packet includes: Header, the header including a first subset of the address bits; The middle part; and The tail portion includes a second subset of the address bits, and the first subset and the second subset of the address bits include the second address code.

26. The integrated circuit of claim 25, wherein, The intermediate part includes basic data.

27. The integrated circuit of claim 25, wherein the tail portion includes a control bit.

28. The integrated circuit as claimed in any one of claims 18 to 27, wherein, The first data packet and the second data packet include the same primitive bits.

29. The integrated circuit according to any one of claims 18 to 28, wherein, The fluid jetting device includes a nozzle circuit array for jetting droplets from each nozzle circuit in the array, and a second address bit for selecting the second nozzle circuit for jetting droplets.

30. The integrated circuit according to any one of claims 19 to 29, wherein, The host-side contact array includes: A first contact column, the first contact column including the host-side transmitting contact; and The second contact column includes the host-side clock contact and the host-side data contact; and The device side contact array includes: A first contact array, the first contact array including the device-side transmitting contact; and The second contact column includes the device-side clock contact and the device-side data contact.

31. The integrated circuit of any one of claims 18 to 30, wherein the integrated circuit is configured to modify the first packet such that a first portion of the first packet is modified, the first portion including the address bits, and a second portion of the first packet is not modified.

32. The integrated circuit according to any one of claims 19 to 31, wherein, The first transmission signal is in phase with the first address bit based on the first clock signal, and the second transmission signal is in phase with the second address bit based on the second clock signal.

33. The integrated circuit according to any one of claims 19 to 32, wherein the integrated circuit is used to modify the first clock signal to obtain the second clock signal, wherein, The second clock signal has a higher frequency than the first clock signal.

34. The integrated circuit of any one of claims 18 to 33, wherein the integrated circuit is attached to a fluid jetting cartridge including the fluid jetting device, the fluid jetting cartridge being inserted into a fluid jetting device including the host controller.

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