An ADC chip-based data acquisition system applied to power detection equipment

Abstract

This invention relates to a data acquisition system based on an ADC chip for use in power detection equipment. The system includes a data acquisition circuit that acquires voltage and current traveling wave signals, performs signal conditioning, impedance matching, and differential drive processing; an ADC chip that performs analog-to-digital conversion on the signals output from the data acquisition circuit; an FPGA chip that receives digital signals, performs buffering, processing, and digital filtering operations, extracts the characteristics of power frequency signals and traveling wave signals in the power system, and performs data synchronization processing; and a CNV processing circuit that performs synchronization processing and edge shaping on the system master clock signal, outputting a synchronization signal to the FPGA to keep the sampling timing of the ADC chip synchronized with the system master clock. This invention converts the system master clock and drives the ADC sampling trigger path, achieving system-wide clock unification. After buffering and trigger shaping, the CNV signal has sharp edges and low jitter, suitable for high-speed ADC sampling. During long-term operation, the sampling points will not drift relative to the system clock, facilitating multi-module data alignment and synchronization processing.

Description

Technical Field

[0001] This invention relates to the field of data acquisition technology, and in particular to a data acquisition system based on an ADC chip for use in power detection equipment. Background Technology

[0002] Currently, many power monitoring equipment products use a pure analog operational amplifier circuit + digital high and low gain amplifier solution, which is complex and has relatively low reliability. Alternatively, they use a sampling rate of about 1MHz, which is difficult to cover the full dynamic acquisition of traveling wave currents from 0.01A to 1A (linear region) and from 1A to 1500A (nonlinear region).

[0003] Furthermore, most current high-speed ADC acquisition systems use FPGAs to directly generate CNV (conversion start) signals to drive the ADC for analog-to-digital conversion at a fixed sampling rate. However, in multi-module collaborative or system-level acquisition scenarios, the ADC sampling clock often cannot maintain strict synchronization with the system master clock (e.g., an 8kHz system synchronization clock). This leads to the following problems: Sampling time drift: There is a phase difference or frequency offset between the ADC sampling frequency and the system clock, causing the sampling points to gradually drift over long-term operation.

[0004] Data alignment difficulties: In multi-channel or multi-module systems, if the sampling of each ADC is not synchronized with the system master clock, it will cause inconsistencies in the time base of data from different modules, increasing the complexity of back-end data fusion and timing calibration.

[0005] Insufficient triggering accuracy: In traditional systems, the CNV signal generated by the FPGA is easily affected by internal delay and jitter, making it difficult to achieve synchronized sampling that is precisely locked with the system clock. Summary of the Invention

[0006] The purpose of this invention is to provide a data acquisition system based on an ADC chip for use in power detection equipment, thereby solving the aforementioned problems in the prior art.

[0007] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A data acquisition system based on an ADC chip for use in power detection equipment includes an FPGA chip, an ADC chip, a CNV processing circuit, and a data acquisition circuit. The data acquisition circuit is used to acquire voltage traveling wave signals and current traveling wave signals, perform signal conditioning, impedance matching and differential drive processing, and output the processed differential analog voltage traveling wave signals and differential analog current traveling wave signals to the ADC chip. The ADC chip is used to perform analog-to-digital conversion on the differential analog voltage traveling wave signal and differential analog current traveling wave signal output by the data acquisition circuit, and output the converted digital voltage traveling wave signal and digital current traveling wave signal to the FPGA chip. The FPGA chip is used to receive the digital voltage traveling wave signal and digital current traveling wave signal output by the ADC chip, buffer, process and digitally filter the digital voltage traveling wave signal and digital current traveling wave signal to extract the characteristics of the power frequency signal and traveling wave signal in the power system, and perform data synchronization processing and output. The CNV processing circuit is used to synchronize and shape the system master clock signal, synchronize the system 8kHz clock, and output a 100MHz synchronization signal to the dedicated clock pin of the FPGA chip, so that the sampling timing of the ADC chip is synchronized with the system master clock.

[0008] The beneficial effects of this invention are as follows: This invention adopts a digital filtering and shaping method, eliminating the need for graded gain amplification, and acquires traveling wave signals across the entire frequency range, avoiding signal attenuation and improving system stability and integration; by accurately converting the system's 8kHz master clock and driving the ADC sampling trigger path, clock unification of the entire system is achieved; after buffering and trigger shaping, the CNV signal has sharp edges and low jitter, making it suitable for high-speed ADC sampling; during long-term operation, the sampling points will not drift relative to the system clock, facilitating data alignment and synchronization processing across multiple modules; and hardware-level timing locking is achieved using an external clock and mature logic devices, without relying on complex FPGA clock management logic.

[0009] Based on the above technical solution, the present invention can be further improved as follows.

[0010] Furthermore, the CNV processing circuit includes a clock synchronization chip, inverters U32, U33, and U34, a D flip-flop U35, capacitors C186, C187, C188, C189, and C191, and resistors R201, R202, R204, R205, R208, R211, and R212. The clock synchronization chip is electrically connected to one end of R204 and one end of C188. The other end of C188 is electrically connected to one end of R205, one end of R201, and pin 2 of U32 in sequence. The other ends of R204 and R205 are grounded, and the other end of R201 is connected to a 1.8V power supply. Pin 4 of U32 is electrically connected to pin 2 of U33 and pin 1 of U35. Pin 4 of U33 is connected in series with R202 and outputs a 100MHz clock signal to the FPGA. The FPGA is connected in series with R208 and electrically connected to pin 2 of U34. Pin 4 of U34 is connected in series with pin 2 of U35. Pin 3 of U35 is connected in series with R211 and electrically connected to the ADC chip. R211, R212 and R208 are connected in series. Pin 3 of U32, pin 3 of U33, and pin 3 of U34 are all grounded. Pin 4 of U35 is grounded. Pin 6 of U35 is electrically connected to pins 7 and 8 of U35. Pin 8 of U35 is connected to one end of capacitor C191 after being powered by 1.8 V, and the other end of C191 is grounded. Pin 5 of U32 is connected to one end of capacitor C186 after being powered by 1.8 V, and the other end of C186 is grounded. Pin 5 of U33 is connected to one end of capacitor C187 after being powered by 1.8 V, and the other end of C187 is grounded. Pin 5 of U34 is connected to one end of capacitor C189 after being powered by 1.8 V, and the other end of C189 is grounded.

[0011] Furthermore, the data acquisition circuit includes a voltage data acquisition circuit and a current data acquisition circuit. The voltage data acquisition circuit includes a differential amplifier chip U10, resistors R99, R100, R102, R103, R105, R107, R108, R110, R112, R113, R293, R294, capacitors C76, C77, C79, C83, and C84. Pin 2 of U10 is electrically connected to one end of R102, one end of C77 and one end of R103. The other end of R103 is electrically connected to one end of R105. The other end of R105 is electrically connected to the voltage sensor. Pin 3 of U10 is electrically connected to one end of R110, one end of C79 and one end of R108. The other end of R108 is electrically connected to one end of R107. The other end of R107 is grounded. Pins 5, 6, 7, 8 and 12 of U10 are electrically connected to each other and to one end of C84. The other end of C84 is grounded. Pin 12 of U10 is connected to a 5.4V power supply. Pin 9 of U10 is electrically connected to one end of R113, one end of R112, and one end of C83. The other ends of R113 and C83 are grounded, and the other end of R112 is connected to a 5V power supply. Pin 10 of U10 is electrically connected to one end of R294, the other end of R110, and the other end of C79. The other end of R294 is electrically connected to the positive input terminal of the ADC chip. Pin 11 of U10 is electrically connected to one end of R293, the other end of R102, and the other end of C77. The other end of R293 is electrically connected to the negative input terminal of the ADC chip. Pin 16 of U10 is electrically connected to one end of R99 and one end of R100. The other end of R100 is grounded. Pin 17 of U10, the other end of R99, pin 15 of U10, pin 14 of U10, pin 13 of U10, and one end of C76 are electrically connected to each other and connected to a 3.3V power supply. The other end of C76 is grounded.

[0012] Furthermore, the data acquisition circuit also includes an RF positive pin socket CN2. The other end of R105 is electrically connected to pin 1 of CN2. Pins 2, 3, 4 and 5 of CN2 are interconnected and grounded. A voltage sensor is plugged into CN2.

[0013] Furthermore, the FPGA chip model is 10CL040YF484I7G.

[0014] Furthermore, the ADC chip model is AC9610D-24. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 This is a circuit diagram of the voltage data acquisition circuit in the data acquisition circuit of the present invention; Figure 3 This is a schematic diagram of the output voltage amplitude of the ADA4945 of the present invention; Figure 4 This is the Bode plot of the present invention; Figure 5 This is a rendering of the invention; Figure 6 This is a circuit diagram of the CNV processing circuit of the present invention; Figure 7 This is a flowchart of the CNV processing of the present invention. Detailed Implementation

[0016] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0017] Example 1 like Figure 1 A data acquisition system based on an ADC chip for use in power detection equipment includes an FPGA chip, an ADC chip, a CNV processing circuit, and a data acquisition circuit. The data acquisition circuit is used to acquire voltage traveling wave signals and current traveling wave signals, perform signal conditioning, impedance matching and differential drive processing, and output the processed differential analog voltage traveling wave signals and differential analog current traveling wave signals to the ADC chip. The ADC chip is used to perform analog-to-digital conversion on the differential analog voltage traveling wave signal and differential analog current traveling wave signal output by the data acquisition circuit, and output the converted digital voltage traveling wave signal and digital current traveling wave signal to the FPGA chip. The FPGA chip is used to receive the digital voltage traveling wave signal and digital current traveling wave signal output by the ADC chip, buffer, process and digitally filter the digital voltage traveling wave signal and digital current traveling wave signal to extract the characteristics of the power frequency signal and traveling wave signal in the power system, and perform data synchronization processing and output. The CNV processing circuit is used to synchronize and shape the system master clock signal, synchronize the system 8kHz clock, and output a 100MHz synchronization signal to the dedicated clock pin of the FPGA chip, so that the sampling timing of the ADC chip is synchronized with the system master clock.

[0018] This invention employs a digital filtering and shaping method, eliminating the need for graded gain amplification. It acquires traveling wave signals across the entire frequency range, avoiding signal attenuation and improving system stability and integration. By precisely converting the system's 8kHz master clock and driving the ADC sampling trigger path, it achieves clock unification across the entire system. After buffering and trigger shaping, the CNV signal has sharp edges and low jitter, making it suitable for high-speed ADC sampling. During long-term operation, the sampling points will not drift relative to the system clock, facilitating data alignment and synchronization across multiple modules. It uses an external clock and mature logic devices to achieve hardware-level timing locking, without relying on complex FPGA clock management logic.

[0019] Example 2 like Figure 6 As shown, this embodiment is a further improvement on embodiment 1, as detailed below: The CNV processing circuit includes a clock synchronization chip, inverters U32, U33, and U34, a D flip-flop U35, capacitors C186, C187, C188, C189, and C191, and resistors R201, R202, R204, R205, R208, R211, and R212. The clock synchronization chip is electrically connected to one end of R204 and one end of C188. The other end of C188 is electrically connected to one end of R205, one end of R201, and pin 2 of U32 in sequence. The other ends of R204 and R205 are grounded, and the other end of R201 is connected to a 1.8V power supply. Pin 4 of U32 is electrically connected to pin 2 of U33 and pin 1 of U35. Pin 4 of U33 is connected in series with R202 and outputs a 100MHz clock signal to the FPGA. The FPGA is connected in series with R208 and electrically connected to pin 2 of U34. Pin 4 of U34 is connected in series with pin 2 of U35. Pin 3 of U35 is connected in series with R211 and electrically connected to the ADC chip. R211, R212 and R208 are connected in series. Pin 3 of U32, pin 3 of U33, and pin 3 of U34 are all grounded. Pin 4 of U35 is grounded. Pin 6 of U35 is electrically connected to pins 7 and 8 of U35. Pin 8 of U35 is connected to one end of capacitor C191 after being powered by 1.8 V, and the other end of C191 is grounded. Pin 5 of U32 is connected to one end of capacitor C186 after being powered by 1.8 V, and the other end of C186 is grounded. Pin 5 of U33 is connected to one end of capacitor C187 after being powered by 1.8 V, and the other end of C187 is grounded. Pin 5 of U34 is connected to one end of capacitor C189 after being powered by 1.8 V, and the other end of C189 is grounded.

[0020] Example 3 like Figure 2 As shown, this embodiment is a further improvement on embodiment 1, as detailed below: The data acquisition circuit includes a voltage data acquisition circuit and a current data acquisition circuit. The voltage data acquisition circuit includes a differential amplifier chip U10, resistors R99, R100, R102, R103, R105, R107, R108, R110, R112, R113, R293, R294, capacitors C76, C77, C79, C83, and C84. Pin 2 of U10 is electrically connected to one end of R102, one end of C77, and one end of R103. The other end of R103 is electrically connected to one end of R105, and the other end of R105 is electrically connected to the voltage sensor. In specific implementations, the current data acquisition circuit and the voltage data acquisition circuit adopt the same topology. Pin 3 of U10 is electrically connected to one end of R110, one end of C79 and one end of R108. The other end of R108 is electrically connected to one end of R107. The other end of R107 is grounded. Pins 5, 6, 7, 8 and 12 of U10 are electrically connected to each other and to one end of C84. The other end of C84 is grounded. Pin 12 of U10 is connected to a 5.4V power supply. Pin 9 of U10 is electrically connected to one end of R113, one end of R112, and one end of C83. The other ends of R113 and C83 are grounded, and the other end of R112 is connected to a 5V power supply. Pin 10 of U10 is electrically connected to one end of R294, the other end of R110, and the other end of C79. The other end of R294 is electrically connected to the positive input terminal of the ADC chip. Pin 11 of U10 is electrically connected to one end of R293, the other end of R102, and the other end of C77. The other end of R293 is electrically connected to the negative input terminal of the ADC chip. Pin 16 of U10 is electrically connected to one end of R99 and one end of R100. The other end of R100 is grounded. Pin 17 of U10, the other end of R99, pin 15 of U10, pin 14 of U10, pin 13 of U10, and one end of C76 are electrically connected to each other and connected to a 3.3V power supply. The other end of C76 is grounded.

[0021] The data acquisition circuit also includes an RF positive pin socket CN2. The other end of R105 is electrically connected to pin 1 of CN2. Pins 2, 3, 4 and 5 of CN2 are interconnected and grounded. A voltage sensor is plugged into CN2.

[0022] Example 4 like Figures 1 to 7 As shown, this embodiment is a further improvement on embodiment 1, as detailed below: The FPGA chip model is 10CL040YF484I7G.

[0023] The FPGA and ADC are interconnected via QSPI to enable read / write control of the ADC. The FPGA includes modules for clock generation, command transmission, and data reception. By acquiring voltage and current sensor signals, real-time monitoring and data processing of the power system can be achieved. The design must consider CNV signal synchronization and anti-interference capabilities to improve acquisition accuracy and system stability.

[0024] Example 5 like Figures 1 to 7 As shown, this embodiment is a further improvement on embodiment 1, as detailed below: The ADC chip model is AC9610D-24.

[0025] High precision advantage: 2M, 24-bit can meet the full dynamic range data acquisition of 0.01A to 1500A.

[0026] Dual-channel advantages: The AC9610D-24 features a dual-channel ADC with two isolated channels that can cross-average suppress random noise, making it more suitable for anti-crosstalk scenarios. Specific implementation examples: like Figures 1 to 7 As shown, this invention proposes an FPGA+ADC technical solution. The FPGA has a built-in algorithm processing IP core with a 2MHz sampling rate, enabling non-destructive waveform detection. Furthermore, to achieve full-range dynamic range acquisition (0.01A–1A (linear region) and 1A–1500A (non-linear region), the ADC bit depth is 1500A / 0.01A = 150000. Must meet, calculate We choose 18, taking into account the sign bit, positive / negative distinction, and margin. At least 21 bits should be used. This invention proposes to use a 24-bit ADC to improve the accuracy of traveling wave detection.

[0028] Meanwhile, considering that the accuracy and synchronization of the 2MHz CNV clock are crucial to the system accuracy, this invention uses an ADC sampling triggering method based on system clock synchronization. By introducing a clock synchronization chip (AU5327) and a D flip-flop (NL17SZ74) shaping circuit, the CNV start signal of the ADC is precisely aligned with the system's 8kHz synchronous clock.

[0029] In the technical solution, the signal flow direction is as follows: (1) After the sensor signal received by CN2 enters the PCB, it passes through a low-pass filter, and its cutoff frequency is: ; Substitution : ; (2) After passing through the LP low-pass filter, the signal is output to the ADC chip (AD4630-24 chip) after passing through the differential amplifier chip U10 (ADA4945).

[0030] It is particularly important to emphasize that, in order to increase the voltage amplitude corresponding to ADC1LSB, this invention sets the voltage reference to 5V instead of 3.3V, which can significantly improve the system's noise immunity. See the schematic diagram of the ADA4945 output voltage amplitude. Figure 5 ; It should be noted that R102 and R110 can be adjusted to 1k-10k as needed. Specifically, when R102=R110=1k, it is a follower amplification. When the signal frequency is a typical frequency of 10kHz, the signal is amplified 1:1, and the -3dB cutoff frequency of the entire signal link is approximately 150kHz, which meets the main frequency range for traveling wave detection. See the Bode plot for details. Figure 6 See enlarged image for effect. Figure 7 ; The above design offers several significant advantages: the use of a high-cutoff-frequency low-pass filter effectively filters out high-frequency interference, enhancing the system's EMC characteristics, and protecting traveling wave voltage and power frequency voltage from interference. Simultaneously, the differential amplifier chip U10 (ADA4945), as a differential amplifier, serves as impedance buffer and improves the dynamic acquisition range of the ADC.

[0031] (3) After conversion by the ADC chip (24-bit, 2MSARADC), the data is transmitted to the FPGA chip in QSPI format. The FPGA chip extracts key data features and uses digital filtering algorithms to restore the power frequency signal and traveling wave voltage signal.

[0032] This solution eliminates the need for a dedicated 50Hz notch filter circuit. Both power frequency and traveling wave signals can be extracted and analyzed by the FPGA algorithm without distinction and transmitted to the host computer. This avoids the need for a pure analog operational amplifier circuit + digital high and low gain amplifier solution, thus simplifying the design, reducing complexity, and improving the reliability of the system design. Meanwhile, the 24-bit ADC, after removing its own local noise, achieves a dynamic range of 150,000, satisfying the full-range dynamic range acquisition requirements of 0.01A to 1A (linear region) and 1A to 1500A (non-linear region).

[0033] The obvious benefits of adopting the above design are: constructing a normalized hardware path without increasing hardware costs; combining traveling wave and power frequency analog signals into one, which is then sampled and reconstructed indiscriminately by the ADC; providing a low-cost, highly reliable hardware path for digital filtering algorithms; and using a high-precision ADC, dynamic acquisition of traveling wave voltage over a range of 150,000 times can be achieved.

[0034] (4) To achieve high-precision sample-and-hold functionality, the CNV circuit signal flow is indispensable: after the clock synchronization chip (AU5327) obtains the system clock, it outputs a 100MHz synchronization signal, which is then connected to pin 1 of the U35 clock pin via a driver. Simultaneously, pin 2 of U35 is connected to the CNV signal output by the FPGA. After triggering, the signal is output to the CNV pin of the AD4630-24 via pin 3 of U35. Specifically, to ensure compatibility with the 1.8V QSPI level and simplify the design, this scheme selects the NL17SZ74 and SN74LCV1G04 chips, which support low-voltage power rails. Furthermore, the typical jitter value of the NL17SZ74 is 10–30ps, far lower than the hundreds of ps directly output by the FPGA, thus achieving low temperature drift and high-precision sampling, which is superior to directly outputting the CNV signal from the FPGA and connecting it to the ADC CNV conversion pin. For detailed design, see [link to design details]. Figure 6 and Figure 7 .

[0035] Benefits: Strong system-level synchronization: The AU5327 accurately converts the system's 8kHz master clock and drives the ADC sampling trigger path, achieving clock uniformity across the entire system.

[0036] Signal quality improvement: After being buffered and driven by SN74LVC1G04 and triggered and shaped by NL17SZ74, the CNV signal has sharp edges and low jitter, making it suitable for high-speed ADC sampling.

[0037] (5) In order to achieve device clock synchronization, the 100M clock is connected to the dedicated clock pin of the FPGA after passing through the two-stage inverters U32 and U33, in order to generate a cnv signal synchronized with the system clock. Benefits: Excellent sampling stability: During long-term operation, the sampling points will not drift relative to the system clock, which facilitates data alignment and synchronization processing of multiple modules and achieves system-level synchronization.

[0038] Simple design and high reliability: It adopts an external clock and mature logic devices to achieve hardware-level timing locking, without relying on complex FPGA clock management logic.

[0039] (6) The FPGA is interconnected with the EMMC and MCU through the SPI and DCMI digital bus to report traveling wave fault information and power frequency recording, so as to ensure the overall reliable and accurate operation of the power monitoring equipment.

[0040] The MCU and FPGA communicate via a DCMI interface for large data transfer, while the EMMC module is used for power frequency waveform recording. The modular design minimizes design costs while ensuring functionality, facilitates fault diagnosis, power frequency waveform playback, and improves the success rate of power system diagnostics.

[0041] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A data acquisition system based on an ADC chip for use in power detection equipment, characterized in that, This includes FPGA chips, ADC chips, CNV processing circuits, and data acquisition circuits; The data acquisition circuit is used to acquire voltage traveling wave signals and current traveling wave signals, perform signal conditioning, impedance matching and differential drive processing, and output the processed differential analog voltage traveling wave signals and differential analog current traveling wave signals to the ADC chip. The ADC chip is used to perform analog-to-digital conversion on the differential analog voltage traveling wave signal and the differential analog current traveling wave signal output by the data acquisition circuit, and output the converted digital voltage traveling wave signal and digital current traveling wave signal to the FPGA chip. The FPGA chip is used to receive the digital voltage traveling wave signal and the digital current traveling wave signal output by the ADC chip, perform buffering, processing and digital filtering operations on the digital voltage traveling wave signal and the digital current traveling wave signal to extract the power frequency signal and traveling wave signal characteristics in the power system, and perform data synchronization processing and output. The CNV processing circuit is used to synchronize and shape the system master clock signal, synchronize the system 8kHz clock, and output a 100MHz synchronization signal to the dedicated clock pin of the FPGA chip, so that the sampling timing of the ADC chip is synchronized with the system master clock.

2. The data acquisition system based on an ADC chip applied in power detection equipment according to claim 1, characterized in that, The CNV processing circuit includes a clock synchronization chip, inverters U32, U33, and U34, a D flip-flop U35, capacitors C186, C187, C188, C189, and C191, and resistors R201, R202, R204, R205, R208, R211, and R212. The clock synchronization chip is electrically connected to one end of R204 and one end of C188. The other end of C188 is electrically connected to one end of R205, one end of R201, and pin 2 of U32 in sequence. The other ends of R204 and R205 are grounded, and the other end of R201 is connected to a 1.8V power supply. Pin 4 of U32 is electrically connected to pin 2 of U33 and pin 1 of U35. Pin 4 of U33 is connected in series with R202 and outputs a 100MHz clock signal to the FPGA. The FPGA is connected in series with R208 and electrically connected to pin 2 of U34. Pin 4 of U34 is connected in series with pin 2 of U35. Pin 3 of U35 is connected in series with R211 and electrically connected to the ADC chip. R211, R212, and R208 are connected in series. Pin 3 of U32, pin 3 of U33, and pin 3 of U34 are all grounded. Pin 4 of U35 is grounded. Pin 6 of U35 is electrically connected to pins 7 and 8 of U35. Pin 8 of U35 is connected to one end of capacitor C191 after being powered by 1.8V, and the other end of C191 is grounded. Pin 5 of U32 is connected to one end of capacitor C186 after being powered by 1.8V, and the other end of C186 is grounded. Pin 5 of U33 is connected to one end of capacitor C187 after being powered by 1.8V, and the other end of C187 is grounded. Pin 5 of U34 is connected to one end of capacitor C189 after being powered by 1.8V, and the other end of C189 is grounded.

3. The data acquisition system based on an ADC chip applied in power detection equipment according to claim 1, characterized in that, The data acquisition circuit includes a voltage data acquisition circuit and a current data acquisition circuit. The voltage data acquisition circuit includes a differential amplifier chip U10, resistors R99, R100, R102, R103, R105, R107, R108, R110, R112, R113, R293, R294, capacitors C76, C77, C79, C83, and C84. Pin 2 of U10 is electrically connected to one end of R102, one end of C77 and one end of R103. The other end of R103 is electrically connected to one end of R105 and the other end of R105 is electrically connected to the voltage sensor. Pin 3 of U10 is electrically connected to one end of R110, one end of C79 and one end of R108. The other end of R108 is electrically connected to one end of R107, and the other end of R107 is grounded. Pins 5, 6, 7, 8 and 12 of U10 are electrically connected to each other and to one end of C84. The other end of C84 is grounded. Pin 12 of U10 is connected to a 5.4V power supply. Pin 9 of U10 is electrically connected to one end of R113, one end of R112 and one end of C83. The other ends of R113 and C83 are grounded, and the other end of R112 is connected to a 5V power supply. Pin 10 of U10 is electrically connected to one end of R294, the other end of R110, and the other end of C79. The other end of R294 is electrically connected to the positive input terminal of the ADC chip. Pin 11 of U10 is electrically connected to one end of R293, the other end of R102, and the other end of C77. The other end of R293 is electrically connected to the negative input terminal of the ADC chip. Pin 16 of U10 is electrically connected to one end of R99 and one end of R100. The other end of R100 is grounded. Pin 17 of U10, the other end of R99, pin 15 of U10, pin 14 of U10, pin 13 of U10, and one end of C76 are electrically connected to each other and connected to a 3.3V power supply. The other end of C76 is grounded.

4. A data acquisition system based on an ADC chip for use in power detection equipment according to claim 3, characterized in that, The data acquisition circuit also includes an RF positive pin socket CN2. The other end of R105 is electrically connected to pin 1 of CN2. Pins 2, 3, 4 and 5 of CN2 are interconnected and grounded. A voltage sensor is plugged into CN2.

5. A data acquisition system based on an ADC chip for use in power detection equipment according to claim 1, characterized in that, The FPGA chip is model number 10CL040YF484I7G.

6. A data acquisition system based on an ADC chip for use in power detection equipment according to claim 1, characterized in that, The ADC chip is model AC9610D-24.

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