An oscillator detection circuit

Abstract

This invention discloses an oscillator detection circuit, relating to the field of integrated circuit technology, to solve the problem of poor accuracy in oscillator detection and judgment by the main control chip due to existing detection circuits. The detection circuit includes a frequency shaping circuit, a high-voltage generation circuit, a negative-voltage generation circuit, and a voltage conversion circuit connected in stages. The frequency shaping circuit shapes the oscillator's output signal; the high-voltage generation circuit processes the output signal of the frequency shaping circuit to generate a high-voltage signal; the negative-voltage generation circuit provides a negative bias to the detection circuit; and finally, the voltage conversion circuit converts the received signal into a voltage output related to the oscillator frequency. This improves the accuracy of oscillator detection and judgment by the main control chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an oscillator detection circuit. Background Technology

[0002] As a core module in integrated circuits, the oscillator provides the clock for digital chips. However, oscillators are often affected by factors such as structure, voltage, or temperature, and may fail to start. If the oscillator fails to start, other circuits will malfunction, making oscillator start-up detection particularly important.

[0003] The most common method for oscillation detection circuits is to use the oscillator's output as the clock for a trigger after the oscillator starts. The trigger samples the data and updates its output accordingly. For example, the default output of the trigger is "0". When the oscillator is not running, the trigger output is "0". When the oscillator starts, the trigger samples a high level and outputs a high level, thus achieving the effect of "0" when oscillation is not running and "1" when oscillation is running. However, this type of oscillation circuit can only detect the presence or absence of a frequency, not its magnitude. This leads to a decrease in the accuracy of the main control chip's detection and judgment of the oscillator, making it impossible to accurately determine the oscillator's performance.

[0004] Therefore, there is an urgent need for a more advanced oscillator detection circuit to solve the problem that the detection circuit in the existing technology results in poor accuracy of the main control chip in detecting and judging the oscillator. Summary of the Invention

[0005] The purpose of this invention is to provide an oscillator detection circuit to solve the problem that the detection circuit in the prior art results in poor accuracy of the main control chip in detecting and judging the oscillator.

[0006] To achieve the above objectives, the present invention provides the following technical solution: This invention provides an oscillator detection circuit, which may include: Frequency shaping circuit, high voltage generating circuit, negative voltage generating circuit, and voltage conversion circuit; The frequency shaping circuit is connected to the high voltage generating circuit, and the frequency shaping circuit is connected to the frequency output terminal of the oscillator; the high voltage generating circuit is connected to the negative voltage generating circuit, and the negative voltage generating circuit is connected to the voltage conversion circuit. The frequency shaping circuit is used to shape the output signal of the oscillator; the high voltage generating circuit is used to process the output signal of the frequency shaping circuit to generate a high voltage signal; the negative voltage generating circuit provides a negative bias for the detection circuit; and the voltage conversion circuit is used to convert the received signal into a voltage output related to the oscillator frequency.

[0007] As an optional embodiment, the frequency shaping circuit may include a target flip-flop; The clock signal input terminal of the target flip-flop is connected to the clock signal output terminal of the target oscillator, the data input terminal of the target flip-flop is connected to the inverting output terminal of the target flip-flop, the positive output terminal of the target flip-flop is connected to the high voltage generating circuit, and the voltage terminal of the target flip-flop is connected to the system power supply.

[0008] As an optional embodiment, the high-voltage generating circuit may include a first inverter, a second inverter, a first capacitor, a first diode, and a second diode; The input terminal of the first inverter is connected to the frequency shaping circuit, the output terminal of the first inverter is connected to one end of the first capacitor, the other end of the first capacitor is connected to the negative terminal of the first diode, the power supply terminal of the first inverter is connected to the system power supply, and the positive terminal of the first diode is connected to the system power supply. The positive terminal of the second diode is connected to the negative terminal of the first diode, and the negative terminal of the second diode is connected to the power supply terminal of the second inverter; the input terminal of the second inverter is connected to the frequency shaping circuit, and the output terminal of the second inverter is connected to the negative voltage generating circuit.

[0009] As an optional embodiment, the negative voltage generating circuit may include a second capacitor and a third diode; One end of the second capacitor is connected to the high-voltage generating circuit, and the other end is connected to the positive terminal of the third diode; the negative terminal of the third diode is grounded, and the positive terminal of the third diode is connected to the voltage conversion circuit.

[0010] As an optional embodiment, the voltage conversion circuit may include a first resistor, a second resistor, a third capacitor, a fourth diode, and a fifth diode; One end of the first resistor is connected to the system power supply, and the other end of the first resistor is connected to one end of the third capacitor, and the other end of the third capacitor is grounded; one end of the second resistor is connected to the end of the first resistor that is connected to the third capacitor, and the other end of the second resistor is grounded. The negative terminal of the fourth diode is connected to the negative voltage generating circuit, and the positive terminal of the fourth diode is connected to the negative terminal of the fifth diode; the positive terminal of the fifth diode is connected to the end of the third capacitor that is connected to the first resistor, and the positive terminal of the fifth diode is connected to the output terminal of the oscillator detection circuit.

[0011] As an optional embodiment, the first resistor and the second resistor are megohm-level resistors, and the resistance value of the first resistor is greater than the resistance value of the second resistor.

[0012] As an optional embodiment, the following formula is included: Determine the mean value of the target voltage; wherein, Indicates the average value of the target voltage. Indicates the threshold voltage of the third diode, Indicates system power supply voltage, Indicates the threshold voltage of the first diode, Indicates the threshold voltage of the second diode, Indicates the threshold voltage of the fourth diode, Indicates the threshold voltage of the fifth diode, The voltage at the sixth node is... The rise voltage of the target voltage The voltage at the sixth node is V. TH_D2 -(2VDD-V TH_D0 -V TH_D1 The rising voltage of the target voltage at that time.

[0013] As an optional embodiment, when no oscillation waveform is input to the clock signal input terminal of the target trigger, the voltage of the first node is the system power supply voltage or 0V; When the voltage of the first node is the system power supply voltage, the voltage of the second node is 0V, the voltage of the third node is the difference between the system power supply voltage and the threshold voltage of the first diode, the voltage of the fourth node is the difference between the system power supply voltage and the threshold voltages of the first and second diodes, the voltage of the fifth node is 0V, the voltage of the sixth node is the threshold voltage of the third diode, and the voltage at the output of the oscillator detection circuit is the sum of the voltages of the third and fourth diodes and the threshold voltage of the third diode. When the voltage of the first node is 0V, the voltage of the second node is the system power supply voltage, the voltage of the third node is 0V, the voltage of the fourth node is the system power supply voltage minus the difference between the threshold voltages of the first and second diodes, the voltage of the fifth node is the system power supply voltage minus the difference between the threshold voltages of the first and second diodes, the voltage of the sixth node is the threshold voltage of the third diode, and the voltage at the output of the oscillator detection circuit is the sum of the voltages of the third and fourth diodes and the threshold voltage of the third diode. The voltage at the output of the oscillator detection circuit is the sum of the threshold voltages of the third, fourth, and fifth diodes.

[0014] As an optional embodiment, when an oscillation waveform is input to the clock signal input terminal of the target flip-flop, the period of the oscillation waveform formed by the clock signal terminal is a first time period; The oscillation waveform of the first node is a frequency divider of CLK, the period of the oscillation waveform is the second time period, and the voltage variation range is 0V to VDD; the second time period is twice the first time period. The period of the oscillation waveform formed by the second node is the second time period, and the voltage change is from 0V to VDD. The period of the oscillation waveform formed by the third node is the second time period, and the voltage change is from the difference between VDD and the first threshold voltage to the difference between 2VDD and the first threshold voltage; the first threshold voltage represents the threshold voltage of the first diode; The period of the oscillation waveform formed by the fourth node is the second time period. When the voltage of the first node is 0V, the output voltage of the fourth node reaches its maximum value, which is the difference between 2VDD and the first threshold voltage minus the second threshold voltage. When the voltage of the first node is VDD, the output of the second inverter changes from high level to low level. The second threshold voltage represents the threshold voltage of the second diode. The period of the oscillation waveform formed by the fifth node is the second time period, and the voltage variation range is from 0V to the difference between 2VDD minus the first threshold voltage minus the second threshold voltage. When the voltage of the first node is 0V, the voltage of the fifth node is the difference between 2VDD minus the first threshold voltage minus the second threshold voltage. When the voltage of the first node is VDD, the voltage of the fifth node is 0V.

[0015] As an optional embodiment, when an oscillation waveform is input to the clock signal input terminal of the target flip-flop, the method further includes: The voltage variation range of the sixth node is the difference between the third threshold voltage and the voltage of the fifth node; the third threshold voltage represents the threshold voltage of the third diode. When the voltage of the sixth node is the difference between the third threshold voltage and the voltage of the fifth node, the difference is a negative voltage. The voltage at the output of the oscillator detection circuit is the sum of the voltage of the sixth node, the fourth threshold voltage, and the fifth threshold voltage. The fourth threshold voltage represents the threshold voltage of the fourth diode, and the fifth threshold voltage represents the threshold voltage of the fifth diode. When the voltage at the sixth node is the third threshold voltage, the voltage at the output of the oscillator detection circuit rises slowly, and the charging time is the first time period.

[0016] Compared with existing technologies, the oscillator detection circuit provided by this invention includes a frequency shaping circuit, a high-voltage generation circuit, a negative-voltage generation circuit, and a voltage conversion circuit. The frequency shaping circuit is connected to the high-voltage generation circuit, the high-voltage generation circuit is connected to the negative-voltage generation circuit, and the negative-voltage generation circuit is connected to the voltage conversion circuit. This allows the frequency shaping circuit to receive the original clock signal output from the target oscillator and perform frequency shaping to obtain a square wave clock signal at the target frequency. Then, the high-voltage generation circuit generates a high-voltage pulse signal based on the square wave clock signal at the target frequency, activating the oscillator detection circuit. The negative-voltage generation circuit further converts the high-voltage pulse signal into a negative-voltage pulse signal, providing a negative bias for the detection circuit. Finally, the voltage conversion circuit converts the power supply voltage into a target voltage based on the change in the negative-voltage pulse signal and outputs it. The target voltage reflects the state and magnitude of the oscillation frequency of the target oscillator. This not only detects whether the oscillator circuit has started oscillating (high level 1 or low level 0) but also estimates the magnitude of the oscillator's start-up frequency, improving the accuracy of the main control chip's oscillator detection and judgment, and helping to accurately determine the oscillator's operating performance. Attached Figure Description

[0017] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, are illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention.

[0018] In the attached diagram: Figure 1 A schematic diagram of the circuit structure of an oscillator detection circuit provided by the present invention; Figure 2 A schematic diagram of the voltage waveform of the second node in an oscillator detection circuit provided by the present invention; Figure 3 A schematic diagram of the voltage waveform of the fifth node in an oscillator detection circuit provided by the present invention; Figure 4 The waveform diagram of the input and output nodes of an oscillator detection circuit provided by the present invention is shown.

[0019] Figure reference numerals: 10-Frequency shaping circuit, 20-High voltage generating circuit, 30-Negative voltage generating circuit, 40-Voltage conversion circuit, U0-Target trigger, U1-First inverter, U2-Second inverter, C0-First capacitor, C1-Second capacitor, C2-Third capacitor, D0-First diode, D1-Second diode, D2-Third diode, D3-Fourth diode, D4-Fifth diode, R1-First resistor, R2-Second resistor, X0-First node, X1-Second node, X2-Third node, X3-Fourth node, X4-Fifth node, X5-Sixth node. Detailed Implementation

[0020] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0021] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0022] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding related objects have an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0023] Existing oscillator detection circuits can only detect the presence or absence of a detection frequency, but cannot detect the magnitude of the frequency. This leads to a decrease in the automatic detection effect of the main control chip on the oscillator, making it impossible to accurately determine the oscillator's operating performance. Therefore, this invention designs an oscillator detection circuit whose output value is related to the oscillator's output frequency. By utilizing the frequency correspondence, it can not only detect whether the oscillation circuit has started oscillating, but also estimate and determine the magnitude of the frequency, thereby improving the chip's automatic detection effect on the oscillator and enhancing the accuracy of the main control chip's detection and judgment of the oscillator.

[0024] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings: In a first aspect, the present invention provides an oscillator detection circuit, see [link to relevant documentation]. Figure 1 , Figure 1This is a schematic diagram of the circuit structure of an oscillator detection circuit provided by the present invention.

[0025] exist Figure 1 In this circuit, the oscillator detection circuit may include: a frequency shaping circuit 10, a high voltage generating circuit 20, a negative voltage generating circuit 30, and a voltage conversion circuit 40.

[0026] Specifically, the frequency shaping circuit 10 can be connected to the high voltage generating circuit 20, and the frequency shaping circuit 10 can be connected to the frequency output terminal of the oscillator; then the high voltage generating circuit 20 can be connected to the negative voltage generating circuit 30, and finally the negative voltage generating circuit 30 can be connected to the voltage conversion circuit 40; the frequency shaping circuit 10 is used to shape the output signal of the oscillator, and the high voltage generating circuit 20 is used to process the output signal of the frequency shaping circuit 10 to generate a high voltage signal. The negative voltage generating circuit 30 is further used to provide a negative bias for the detection circuit; finally, the voltage conversion circuit 40 is used to convert the received signal into a voltage output related to the oscillator frequency; thus forming the oscillator detection circuit provided by the present invention.

[0027] Based on this, the oscillator detection circuit provided by the present invention can first use the frequency shaping circuit 10 to receive the original clock signal output by the target oscillator and perform frequency shaping on the original clock signal to obtain a square wave clock signal of the target frequency; then, the high voltage generation circuit 20 uses the square wave clock signal of the target frequency to generate a high voltage pulse signal to activate the oscillator detection circuit; further, the negative voltage generation circuit 30 uses the negative voltage generation circuit 30 to convert the high voltage pulse signal into a negative voltage pulse signal to provide a negative bias for the detection circuit; finally, the voltage conversion circuit 40 uses the change of the negative voltage pulse signal to convert the power supply voltage into the target voltage and output it; wherein, the target voltage is used to reflect the state and magnitude of the oscillation frequency of the target oscillator. This realizes the ability to detect whether the oscillator has started. At the same time, as the frequency increases, its output value will become lower and lower, which is equivalent to adding a frequency value detection function. It can also estimate the magnitude of the oscillator's start-up frequency, improving the accuracy of the main control chip's detection and judgment of the oscillator; and the initial value of VOUT (target voltage) is adjustable, which also makes it easy to convert the output value into a digital quantity or connect it to an analog circuit.

[0028] As an optional embodiment, the frequency shaping circuit 10 may include a target flip-flop U0; wherein the clock signal input terminal of the target flip-flop U0 is connected to the clock signal output terminal of the target oscillator, the data input terminal of the target flip-flop U0 is connected to the inverting output terminal of the target flip-flop U0, the positive output terminal of the target flip-flop U0 is connected to the high-voltage generation circuit 20, and the voltage terminal of the target flip-flop U0 is connected to the system power supply. It should be noted that the positive output terminal of the target flip-flop U0 is connected to the high-voltage generation circuit 20 through a first terminal.

[0029] For details, please continue reading. Figure 1 ,exist Figure 1 In this circuit, the CLK port of the target flip-flop U0 is connected to the frequency output period of the oscillator, which is Ts (the first time period). In practical applications, U0 can be selected according to the oscillator model or design requirements, with a duty cycle ranging from 30% to 70%, preferably 50%. The inverting output of this flip-flop is connected to its own input, i.e., a divide-by-two configuration. When CLK is the rising edge, the output of the flip-flop flips, and the period of the signal at the first node X0 is 2Ts (the second time period), with a duty cycle of 50%. This allows for frequency shaping of the original clock signal to obtain a square wave clock signal at the target frequency.

[0030] Furthermore, in Figure 1 In the high voltage generating circuit 20, a first inverter U1, a second inverter U2, a first capacitor C0, a first diode D0, and a second diode D1 may be included.

[0031] Specifically, the input terminal of the first inverter U1 can be connected to the frequency shaping circuit 10, the output terminal of the first inverter U1 can be connected to one end of the first capacitor C0, the other end of the first capacitor C0 can be connected to the negative terminal of the first diode D0, and the power supply terminal of the first inverter U1 can be connected to the system power supply; the positive terminal of the first diode D0 can be connected to the system power supply; further, the positive terminal of the second diode D1 can be connected to the negative terminal of the first diode D0, and the negative terminal of the second diode D1 can be connected to the power supply terminal of the second inverter U2; finally, the input terminal of the second inverter U2 can be connected to the frequency shaping circuit 10, and the output terminal of the second inverter U2 can be connected to the negative voltage generating circuit 30, that is, the output terminal of the second inverter U2 can be connected to the negative voltage generating circuit 30 through the fifth node X4. Thus, the high voltage generating circuit 20 provided by the present invention is obtained.

[0032] Please continue reading. Figure 1 The second node X1 is the frequency-divided output of the first node X0, and the waveform is as follows: Figure 2 As shown, Figure 2 This is a schematic diagram of the voltage waveform of the second node X1 in an oscillator detection circuit provided by the present invention. Figure 2 In the figure, the vertical axis represents voltage in V, and the horizontal axis represents time in milliseconds. After the original frequency CLK is input to U0, the curve shown in the figure is the waveform of the second node X1, that is, the frequency divider waveform of the CLK signal, with a duty cycle of 50% and a maximum voltage amplitude of VDD (system power supply voltage).

[0033] Furthermore, at the third node X2, VDD charges it through the first diode D0, clamping it to its minimum value at VDD-V. TH_D0Since the voltage at the second node X1 of the lower plate of the first capacitor C0 changes from 0V to VDD after the oscillator starts oscillating, and the voltage across the capacitor cannot change abruptly, the voltage change at the third node X2 is VDD - VDD. TH_D0 To 2VDD-V TH_D0 The voltage changes periodically. Furthermore, the third node X2 supplies power to the second inverter U2 through the second diode D1, and the voltage at the fourth node X3 is VDD-V when the oscillator is not oscillating. TH_D0 -V TH_D1 After the oscillator starts oscillating, the maximum voltage at the fourth node X3 reaches 2VDD-V. TH_D0 -V TH_D1 When the fourth node X3 reaches 2VDD-V TH_D0 -V TH_D1 At this time, the first node X0 is at a low level, and the fifth node X4 outputs a high level, that is, the voltage change of the fifth node X4 is from 0V to 2VDD-V. TH_D0 -V TH_D1 , to obtain Figure 3 The waveform shown. Figure 3 This is a schematic diagram of the voltage waveform at the fifth node X4 in an oscillator detection circuit provided by the present invention. Figure 3 In the diagram, the vertical axis represents voltage in volts (V), and the horizontal axis represents time in milliseconds. The waveform at the fifth node X4 is the output of the second inverter U2. When the first node X0 is high, the fifth node X4 is 0V; when the first node X0 is low, the fifth node X4 is 2VDD-V. TH_D0 -V TH_D1 Therefore, when X0~X4 are outputting stably, the states of each node are as follows: when X0 is high, X1 is 0V, and X2 is VDD-V. TH_D0 X4 is 0V. When X0 is low, X1 is VDD and X2 is 2VDD-V. TH_D0 X4 is 2VDD-V TH_D0 -V TH_D1 This enables high-voltage regulation.

[0034] Furthermore, in Figure 1 In this circuit, the negative voltage generating circuit 30 may include a second capacitor C1 and a third diode D2. One end of the second capacitor C1 in the negative voltage generating circuit 30 can be connected to the high voltage generating circuit 20, and the other end can be connected to the positive terminal of the third diode D2. The negative terminal of the third diode D2 is grounded, and the positive terminal of the third diode D2 is connected to the voltage conversion circuit 40. Thus, the negative voltage generating circuit 30 of the present invention is obtained. The negative voltage generating circuit 30 can be used to convert the high voltage pulse signal into a negative voltage pulse signal to provide a negative bias for the detection circuit.

[0035] exist Figure 1In the negative voltage generating circuit 30, the maximum voltage at the sixth node X5 is clamped at V due to the third diode D2 being held at V. TH_D2 Because the voltage change at node 5 X4 is from 0V to 2VDD-V TH_D0 -V TH_D1 Without considering the reverse conduction of the third diode D2 and the charging of the fourth diode D3, after several frequency cycles, the minimum voltage of the sixth node X5 stabilizes at V. TH_D2 -(2VDD-V TH_D0 -V TH_D1 This achieves negative pressure regulation.

[0036] Furthermore, in Figure 1 In the circuit, the voltage conversion circuit 40 may include a first resistor R1, a second resistor R2, a third capacitor C2, a fourth diode D3, and a fifth diode D4. One end of the first resistor R1 can be connected to the system power supply, and the other end of the first resistor R1 can be connected to one end of the third capacitor C2, with the other end of the third capacitor C2 grounded. One end of the second resistor R2 can be connected to the end of the first resistor R1 connected to the third capacitor C2, and the other end of the second resistor R2 can be grounded. Then, the negative terminal of the fourth diode D3 is connected to the negative voltage generating circuit 30, and the positive terminal of the fourth diode D3 is connected to the negative terminal of the fifth diode D4. The positive terminal of the fifth diode D4 is connected to the end of the third capacitor C2 connected to the first resistor R1, and the positive terminal of the fifth diode D4 is connected to the output terminal of the oscillator detection circuit. Thus, the voltage conversion circuit 40 of the present invention is obtained, which can convert the power supply voltage into a target voltage and output it according to the change of the negative voltage pulse signal; wherein, the target voltage is used to reflect the state and magnitude of the oscillation frequency of the target oscillator; the first resistor R1 and the second resistor R2 are megaohm-level resistors, and the resistance value of the first resistor R1 is greater than the resistance value of the second resistor R2. For example, the first resistor R1 can be 150 megaohms and the second resistor R2 can be 50 megaohms.

[0037] Please continue reading. Figure 1 In the initial state, the voltage at the sixth node X5 is V. TH_D2 The voltage VOUT is determined by resistors R1 and R2, and diodes D2, D3, and D4. The voltage VOUT is approximately V. TH_D2 +V TH_D3 +V TH_D4 .

[0038] After the oscillator starts oscillating, the voltage at the sixth node X5 will change from V... TH_D2 To V TH_D2 -(2VDD-V TH_D0 -V TH_D1 (Periodic variation. When the voltage at the sixth node X5 is V)TH_D2 -(2VDD-V TH_D0 -V TH_D1 At that time, due to the fourth diode D3 and the fifth diode D4, the voltage at node VOUT is V. TH_D2 -(2VDD-V TH_D0 -V TH_D1 )+V TH_D3 +V TH_D4 Simultaneously, the sixth node X5 is charged through the fourth diode D3 and the fifth diode D4. The charging current is determined by the first resistor R1 and the second resistor R2. The voltage at the sixth node X5 and VOUT will rise slowly. To ensure a slow voltage rise, the specific input and output waveforms are as follows: Figure 4 As shown, Figure 4 This is a waveform diagram of the input and output nodes of an oscillator detection circuit provided by the present invention. From... Figure 4 It can be concluded without a doubt that when the oscillator is not oscillating, the voltage at node VOUT is approximately V. TH_D2 +V TH_D3 +V TH_D4 When the oscillator starts oscillating, the voltage at node VOUT drops, and eventually reaches the target voltage and stabilizes.

[0039] Preferred, Figure 4 The target value mentioned above can be expressed using the formula: (1); Determine the mean value of the target voltage; where, Indicates the average value of the target voltage. Indicates the threshold voltage of the third diode, Indicates system power supply voltage, Indicates the threshold voltage of the first diode, Indicates the threshold voltage of the second diode, Indicates the threshold voltage of the fourth diode, Indicates the threshold voltage of the fifth diode, The voltage at the sixth node is... The rise voltage of the target voltage The voltage at the sixth node is V. TH_D2 -(2VDD-V TH_D0 -V TH_D1 The rising voltage of the target voltage at that time.

[0040] Furthermore, the working principle of the oscillator detection circuit provided by the present invention is explained as follows.

[0041] (1) When no oscillation waveform is input to the clock signal input terminal of the target flip-flop, the voltage of the first node is the system power supply voltage or 0V; when the voltage of the first node is the system power supply voltage, the voltage of the second node is 0V, the voltage of the third node is the difference between the system power supply voltage and the threshold voltage of the first diode, the voltage of the fourth node is the difference between the system power supply voltage and the threshold voltages of the first and second diodes, the voltage of the fifth node is 0V, the voltage of the sixth node is the threshold voltage of the third diode, and the voltage at the output terminal of the oscillator detection circuit is the sum of the threshold voltages of the third diode, the fourth diode, and the third diode; when the first node is the system power supply voltage and the second node is the system power supply voltage and the second node is the system power supply voltage and the third ... When the voltage of node one is 0V, the voltage of node two is the system power supply voltage, the voltage of node three is 0V, the voltage of node four is the system power supply voltage minus the difference between the threshold voltages of the first and second diodes, the voltage of node five is the system power supply voltage minus the difference between the threshold voltages of the first and second diodes, the voltage of node six is ​​the threshold voltage of the third diode, the voltage at the output of the oscillator detection circuit is the sum of the threshold voltages of the third and fourth diodes, and the voltage at the output of the oscillator detection circuit is the sum of the threshold voltages of the third, fourth, and fifth diodes.

[0042] Specifically, in combination Figure 1 In the circuit structure shown, when the oscillator is not oscillating, CLK does not form an oscillating waveform, and the voltage of node X0 is VDD or 0V at this time.

[0043] When the voltage of X0 is VDD, X1 is 0V, and X2 is VDD-V. TH_D0 X3 is VDD-V TH_D0 -V TH_D1 X4 is 0V, X5 is V TH_D2 VOUT is approximately V TH_D2 +V TH_D3 +V TH_D4 .

[0044] When the voltage of X0 is 0V, X1 is VDD, X2 is 0V, and X3 is VDD-V. TH_D0 -V TH_D1 X4 is VDD-V TH_D0 -V TH_ D1 V, X5 is V TH_D2 VOUT is approximately V TH_D2 +V TH_D3 +V TH_D4 .

[0045] (2) When the clock signal input terminal of the target flip-flop receives an oscillation waveform, the period of the oscillation waveform formed by the clock signal terminal is T (first time period, in seconds); the oscillation waveform of the first node is a 2-division output of CLK, the period of the oscillation waveform is 2T (second time period, in seconds), and the voltage variation range is 0V to VDD; wherein, the second time period is twice the first time period; the period of the oscillation waveform formed by the second node is 2T, and the voltage variation is 0V to VDD; the period of the oscillation waveform formed by the third node is 2T, and the voltage variation is the difference between VDD and the first threshold voltage to the difference between 2VDD and the first threshold voltage; the first threshold voltage represents the threshold voltage of the first diode; Section 4 The period of the oscillation waveform formed by the first node is 2T. When the voltage of the first node is 0V, the output voltage of the fourth node reaches its maximum value, which is 2VDD minus the difference between the first threshold voltage and the second threshold voltage. When the voltage of the first node is VDD, the output of the second inverter changes from high level to low level. The second threshold voltage represents the threshold voltage of the second diode. The period of the oscillation waveform formed by the fifth node is 2T, and the voltage variation range is from 0V to the difference between 2VDD minus the first threshold voltage and the second threshold voltage. When the voltage of the first node is 0V, the voltage of the fifth node is the difference between 2VDD minus the first threshold voltage and the second threshold voltage. When the voltage of the first node is VDD, the voltage of the fifth node is 0V.

[0046] The voltage variation range of the sixth node is from the third threshold voltage to the difference between the third threshold voltage and the voltage of the fifth node; the third threshold voltage represents the threshold voltage of the third diode; when the voltage of the sixth node is the difference between the third threshold voltage and the voltage of the fifth node, the difference is a negative voltage, and the voltage at the output of the oscillator detection circuit is the sum of the voltage value of the sixth node, the fourth threshold voltage, and the fifth threshold voltage; the fourth threshold voltage represents the threshold voltage of the fourth diode, and the fifth threshold voltage represents the threshold voltage of the fifth diode; when the voltage of the sixth node is the third threshold voltage, the voltage at the output of the oscillator detection circuit rises slowly, and the charging time is T.

[0047] For details, please continue reading. Figure 1 During the detection process of the oscillator detection circuit, the following operating states exist: 1. The voltage at node X5 when the oscillator is not oscillating is V. TH_D2 When the voltage at node X4 starts to increase from 0V to 2VDD-V TH_D0 -V TH_D1 Due to the periodic variation, the highest voltage at node X5 is clamped at V due to diode D2. TH_D2 .

[0048] 2. The voltage at node VOUT when the oscillator is not oscillating is V. TH_D2 +VTH_D3 +V TH_D4 .

[0049] 3. When the oscillator starts oscillating, CLK forms an oscillation waveform with a period of T s, and the following operating states exist: a) Node X0 is a 2-division output of CLK with a period of 2T s and a voltage change from 0 to VDD.

[0050] b) Node X1 has the same oscillation period as X0, with a period of 2T s, and the voltage changes from 0 to VDD.

[0051] c) Node X2 has the same oscillation period as X0, which is 2T s. Due to the presence of capacitor C0, its voltage change is VDD-V TH_D0 To 2VDD-V TH_D0 .

[0052] d) Node X3 has the same oscillation period as X0, which is 2T s. When X0 is 0V, its output voltage reaches its maximum value, which is 2VDD-V. TH_D0 -V TH_D1 When X0 is VDD, the output of the inverting U2 changes from high level to low level, and the voltage of node X3 is determined by the redistribution of node parasitic capacitance and C1 charge.

[0053] e) Node X4 has the same oscillation period as X0, which is 2T s, and its voltage changes from 0V to 2VDD-V. TH_D0 -V TH_D1 .

[0054] f) When the oscillator starts oscillating and X0 is 0V, the voltage at node X4 is 2VDD-V. TH_D0 -V TH_D1 The voltage at node X5 is V. TH_D2 When X0 is VDD, the voltage at node X4 becomes 0V. Since the voltage across capacitor C1 cannot change abruptly, the voltage at node X5 drops to VDD. TH_D2 -(2VDD-V TH_D0 -V TH_D1 That is, the voltage at node X5 changes from V. TH_D2 Change to V TH_D2 -(2VDD-V TH_D0 -V TH_D1 ), which changes periodically with a period of 2T s.

[0055] g) When the oscillator starts oscillating, the voltage at node X5 changes from V TH_D2 Change to V TH_D2 -(2VDD-V TH_D0 -V TH_D1 ).

[0056] Specifically, when the voltage V at node X5 TH_D2 -(2VDD-V TH_D0 -V TH_D1 When the voltage at this node is negative, the voltage at node VOUT is V due to diodes D3 and D4. TH_D2 -(2VDD-V TH_D0 -V TH_D1 )+V TH_D3 +V TH_D4 At this time, VDD charges node VOUT through R1, and GND charges node X5 through R2. At the same time, it charges node X5 through diodes D3 and D4. Since R1 and R2 are large resistors in the M-ohm range, the charging current for nodes X5 and VOUT is small. Within a time T s, the voltages of the two nodes rise. The magnitude of the voltage rise can be adjusted by adjusting the resistance values ​​of R1 and R2. The charging time is T s. The larger the period T is, the larger the voltage rise ΔV1 of node VOUT.

[0057] When the voltage at node X5 is V TH_D2 At that time, because node VOUT is at node X5 voltage V TH_D2 -(2VDD-V TH_D0 -V TH_D1 When the charging current is very small, the voltage rise is very small, so node VOUT is still negative and node X5 voltage is positive. Diodes D3 and D4 are reverse cut off. At this time, only VDD charges node VOUT through R1 and GND through R2. Node VOUT continues to rise slowly. The charging time is T s. The larger the period T is, the larger the voltage ΔV2 of node VOUT rises.

[0058] When the voltage V at node X5 TH_D2 -(2VDD-V TH_D0 -V TH_D1 When VOUT is at this point, due to diodes D3 and D4, the voltage at node VOUT is pulled up to V. TH_D2 -(2VDD-V TH_D0 -V TH_D1 )+V TH_D3 +V TH_D4 This results in a periodic change; therefore, the average voltage of node VOUT is: VOUT AVG =V TH_D2 -(2VDD-V TH_D0 -V TH_D1 )+V TH_D3 +V TH_D4+ (ΔV1 + ΔV2) / 2. Since ΔV1 and ΔV2 are directly related to the period T, the voltage value of VOUT is directly related to the frequency. This allows for the estimation of the oscillation frequency while simultaneously detecting whether the oscillator is oscillating, further improving the accuracy of the main control chip's oscillator detection and judgment.

[0059] In practical applications, the oscillator detection circuit provided by this invention can not only detect whether the oscillator circuit in the chip is oscillating, but also selectively detect the oscillator's period. For example, the time constant in the circuit is... The smaller the oscillator period, the lower the voltage at node VOUT. The initial voltage of VOUT can be adjusted by changing the number of diodes D3 and D4 connected in series and the resistance values ​​of R1 and R2, thereby enabling the selection of the oscillator period.

[0060] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0061] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. An oscillator detection circuit, characterized in that, include: Frequency shaping circuit, high voltage generating circuit, negative voltage generating circuit, and voltage conversion circuit; The frequency shaping circuit is connected to the high voltage generating circuit, and the frequency shaping circuit is connected to the frequency output terminal of the oscillator; the high voltage generating circuit is connected to the negative voltage generating circuit, and the negative voltage generating circuit is connected to the voltage conversion circuit. The frequency shaping circuit is used to shape the output signal of the oscillator; the high voltage generating circuit is used to process the output signal of the frequency shaping circuit to generate a high voltage signal; the negative voltage generating circuit provides a negative bias for the detection circuit; and the voltage conversion circuit is used to convert the received signal into a voltage output related to the oscillator frequency.

2. The oscillator detection circuit as described in claim 1, characterized in that, The frequency shaping circuit includes a target trigger; The clock signal input terminal of the target flip-flop is connected to the clock signal output terminal of the target oscillator, the data input terminal of the target flip-flop is connected to the inverting output terminal of the target flip-flop, the positive output terminal of the target flip-flop is connected to the high voltage generating circuit, and the voltage terminal of the target flip-flop is connected to the system power supply.

3. The oscillator detection circuit as described in claim 1, characterized in that, The high-voltage generating circuit includes a first inverter, a second inverter, a first capacitor, a first diode, and a second diode; The input terminal of the first inverter is connected to the frequency shaping circuit, the output terminal of the first inverter is connected to one end of the first capacitor, the other end of the first capacitor is connected to the negative terminal of the first diode, the power supply terminal of the first inverter is connected to the system power supply, and the positive terminal of the first diode is connected to the system power supply. The positive terminal of the second diode is connected to the negative terminal of the first diode, and the negative terminal of the second diode is connected to the power supply terminal of the second inverter; the input terminal of the second inverter is connected to the frequency shaping circuit, and the output terminal of the second inverter is connected to the negative voltage generating circuit.

4. The oscillator detection circuit as described in claim 1, characterized in that, The negative voltage generating circuit includes a second capacitor and a third diode; One end of the second capacitor is connected to the high-voltage generating circuit, and the other end is connected to the positive terminal of the third diode; the negative terminal of the third diode is grounded, and the positive terminal of the third diode is connected to the voltage conversion circuit.

5. The oscillator detection circuit as described in claim 1, characterized in that, The voltage conversion circuit includes a first resistor, a second resistor, a third capacitor, a fourth diode, and a fifth diode; One end of the first resistor is connected to the system power supply, and the other end of the first resistor is connected to one end of the third capacitor, and the other end of the third capacitor is grounded; one end of the second resistor is connected to the end of the first resistor that is connected to the third capacitor, and the other end of the second resistor is grounded. The negative terminal of the fourth diode is connected to the negative voltage generating circuit, and the positive terminal of the fourth diode is connected to the negative terminal of the fifth diode; the positive terminal of the fifth diode is connected to the end of the third capacitor that is connected to the first resistor, and the positive terminal of the fifth diode is connected to the output terminal of the oscillator detection circuit.

6. The oscillator detection circuit as described in claim 5, characterized in that, The first resistor and the second resistor are megohm-level resistors, and the resistance value of the first resistor is greater than the resistance value of the second resistor.

7. The oscillator detection circuit as described in claim 1, characterized in that, Including the use of formulas: Determine the mean value of the target voltage; wherein, Indicates the average value of the target voltage. Indicates system power supply voltage, Indicates the threshold voltage of the first diode, Indicates the threshold voltage of the second diode, Indicates the threshold voltage of the third diode, Indicates the threshold voltage of the fourth diode, Indicates the threshold voltage of the fifth diode, The voltage at the sixth node is... The rise voltage of the target voltage The voltage at the sixth node is V. TH_D2 -(2VDD-V TH_D0 -V TH_D1 The rising voltage of the target voltage at that time.

8. The oscillator detection circuit as described in claim 1, characterized in that, When no oscillation waveform is input to the clock signal input terminal of the target trigger, the voltage of the first node is the system power supply voltage or 0V; When the voltage of the first node is the system power supply voltage, the voltage of the second node is 0V, the voltage of the third node is the difference between the system power supply voltage and the threshold voltage of the first diode, the voltage of the fourth node is the difference between the system power supply voltage and the threshold voltages of the first and second diodes, the voltage of the fifth node is 0V, the voltage of the sixth node is the threshold voltage of the third diode, and the voltage at the output of the oscillator detection circuit is the sum of the voltages of the third and fourth diodes and the threshold voltage of the third diode. When the voltage of the first node is 0V, the voltage of the second node is the system power supply voltage, the voltage of the third node is 0V, the voltage of the fourth node is the system power supply voltage minus the difference between the threshold voltages of the first and second diodes, the voltage of the fifth node is the system power supply voltage minus the difference between the threshold voltages of the first and second diodes, the voltage of the sixth node is the threshold voltage of the third diode, and the voltage at the output of the oscillator detection circuit is the sum of the voltages of the third and fourth diodes and the threshold voltage of the third diode. The voltage at the output of the oscillator detection circuit is the sum of the threshold voltages of the third, fourth, and fifth diodes.

9. The oscillator detection circuit as described in claim 1, characterized in that, When an oscillation waveform is input to the clock signal input terminal of the target trigger, the period of the oscillation waveform formed by the clock signal terminal is the first time period; The oscillation waveform of the first node is a frequency divider of CLK, the period of the oscillation waveform is the second time period, and the voltage variation range is 0V to VDD; the second time period is twice the first time period. The period of the oscillation waveform formed by the second node is the second time period, and the voltage change is from 0V to VDD. The period of the oscillation waveform formed by the third node is the second time period, and the voltage change is from the difference between VDD and the first threshold voltage to the difference between 2VDD and the first threshold voltage; the first threshold voltage represents the threshold voltage of the first diode; The period of the oscillation waveform formed by the fourth node is the second time period. When the voltage of the first node is 0V, the output voltage of the fourth node reaches its maximum value, which is the difference between 2VDD and the first threshold voltage minus the second threshold voltage. When the voltage of the first node is VDD, the output of the second inverter changes from high level to low level. The second threshold voltage represents the threshold voltage of the second diode. The period of the oscillation waveform formed by the fifth node is the second time period, and the voltage variation range is from 0V to the difference between 2VDD minus the first threshold voltage minus the second threshold voltage. When the voltage of the first node is 0V, the voltage of the fifth node is the difference between 2VDD minus the first threshold voltage minus the second threshold voltage. When the voltage of the first node is VDD, the voltage of the fifth node is 0V.

10. The oscillator detection circuit as described in claim 1, characterized in that, When an oscillation waveform is input to the clock signal input terminal of the target flip-flop, the following is also included: The voltage variation range of the sixth node is the difference between the third threshold voltage and the voltage of the fifth node; the third threshold voltage represents the threshold voltage of the third diode. When the voltage of the sixth node is the difference between the third threshold voltage and the voltage of the fifth node, the difference is a negative voltage. The voltage at the output of the oscillator detection circuit is the sum of the voltage of the sixth node, the fourth threshold voltage, and the fifth threshold voltage. The fourth threshold voltage represents the threshold voltage of the fourth diode, and the fifth threshold voltage represents the threshold voltage of the fifth diode. When the voltage at the sixth node is the third threshold voltage, the voltage at the output of the oscillator detection circuit rises slowly, and the charging time is the first time period.

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