Signal analysis methods, devices, chips, equipment, media, and software products

Abstract

This application relates to a signal analysis method, apparatus, chip, device, medium, and program product, applied to a decoding control module. The method includes: first, in response to a signal analysis command for a debug signal, acquiring target control matching data from multiple control matching data sets, and performing command type analysis on the target control matching data to determine its command type; the multiple control matching data sets include control matching data with various command types, and the target control matching data is determined from the multiple control matching data sets based on the attribute information of the debug signal; then, based on the command type of the target control matching data, determining a target arithmetic unit from multiple arithmetic units of the arithmetic module; finally, inputting the target control matching data to the target arithmetic unit, so that the arithmetic module determines the signal analysis result of the debug signal based on the target control matching data and the debug signal. This method improves the flexibility of the signal matching process.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a signal analysis method, apparatus, chip, device, medium, and program product. Background Technology

[0002] After a chip is manufactured, it needs to undergo a series of tests to verify whether its actual performance and functions meet the design specifications. If a chip malfunctions during testing, its internal state can be determined by capturing the chip's pre-defined debug signals, thus identifying the source of the fault.

[0003] In related technologies, when analyzing the source of a chip failure, the chip's on-chip signal logic analyzer is usually used to perform logic analysis on the chip's debugging signals. That is, by matching the debugging signals with pre-set matching data, the chip fault can be located. However, current logic analysis methods usually match one matching data at a time, and cannot match multiple matching data concurrently, resulting in low matching flexibility. Summary of the Invention

[0004] Therefore, it is necessary to provide a signal analysis method, apparatus, chip, device, medium, and program product capable of concurrently matching multiple matching data to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a signal analysis method applied to a decoding control module, the method comprising:

[0006] In response to the signal analysis command of the debug signal, the target control matching data is obtained from multiple control matching data, and the command type analysis of the target control matching data is performed to determine the command type of the target control matching data; the multiple control matching data includes control matching data with various command types, and the target control matching data is determined from the multiple control matching data based on the attribute information of the debug signal;

[0007] Based on the command type of the target control matching data, the target operation unit is determined from multiple operation units of the operation module;

[0008] The target control matching data is input to the target arithmetic unit so that the arithmetic module can determine the signal analysis result of the debugging signal based on the target control matching data and the debugging signal.

[0009] In one embodiment, command type analysis is performed on the target control matching data to determine the command type of the target control matching data, including:

[0010] The target control matching data is decoded to obtain decoded target control matching data, which includes command type information of the target control matching data.

[0011] Based on the command type information, the command type of the target control matching data is obtained.

[0012] In one embodiment, the decoded target control matching data further includes comparison type information and index information. The target control matching data is input to the target processing unit so that the processing module determines the signal analysis result of the debugging signal based on the target control matching data and the debugging signal, including:

[0013] The comparison type information and index information of the target control matching data are input to the target arithmetic unit; so that the arithmetic module can determine the matching data by indexing in the data register according to the index information and match the debugging signal and the matching data according to the comparison type information to determine the signal analysis result of the debugging signal.

[0014] In one embodiment, the arithmetic module further includes an output unit connected to multiple arithmetic units, and the decoded target control matching data further includes arithmetic control information. The method further includes:

[0015] The calculation control information of the target control matching data is output to the output unit. The calculation control information is used by the output unit to determine the signal analysis result of the debugging signal based on the output results of multiple calculation units and the calculation control information.

[0016] In one embodiment, determining the target computation unit from multiple computation units of the computation module based on the command type of the target control matching data includes:

[0017] Determine whether the step of obtaining target control matching data has been completed based on the command type of the target control matching data.

[0018] If the step of acquiring target control matching data is completed, then the number of target control matching data acquired simultaneously is obtained, and the same number of operation units are determined from the multiple operation units of the operation module as the target operation units.

[0019] In one embodiment, determining whether the step of acquiring the target control matching data has been completed based on the command type of the target control matching data includes:

[0020] Detect whether the command type of the target control matching data is a preset type;

[0021] If the command type of the target control matching data is a preset type, then the step of obtaining the target control matching data is complete;

[0022] If the command type of the target control matching data is not the preset type, then the next control matching data of the target control matching data will be obtained from the data receiving module as the target control matching data.

[0023] In one embodiment, before detecting whether the command type of the target control matching data is a preset type, the method further includes:

[0024] Get the number of matching data for the current target control;

[0025] If the number of target control matching data is greater than or equal to the preset threshold, the step of obtaining target control matching data is completed; the preset threshold is determined based on the number of processing units.

[0026] Secondly, this application also provides a signal analysis device, which includes a data receiving module, a decoding control module, and a calculation module; the input terminal of the data receiving module is used to receive control matching data, the output terminal of the data receiving module is connected to the input terminal of the decoding control module, and the output terminal of the decoding control module is connected to the input terminal of the calculation module.

[0027] The decoding control module, in response to signal analysis commands from the debug signal, acquires target control matching data from multiple control matching data sets in the data receiving module, performs command type analysis on the target control matching data, and determines the command type of the target control matching data. The multiple control matching data sets in the data receiving module include control matching data with various command types. The target control matching data is determined from the multiple control matching data sets based on the attribute information of the debug signal. Based on the command type of the target control matching data, the target arithmetic unit is determined from multiple arithmetic units in the arithmetic module.

[0028] The arithmetic module is used to receive debugging signals and target control matching data, and to determine the signal analysis results of the debugging signals based on the debugging signals and target control matching data.

[0029] In one embodiment, the arithmetic module includes a first arithmetic unit, a second arithmetic unit, a third arithmetic unit, and a fourth arithmetic unit; the input terminals of the first arithmetic unit, the second arithmetic unit, the third arithmetic unit, and the fourth arithmetic unit are respectively connected to the debugging signal and the decoding control module.

[0030] In one embodiment, the data receiving module further includes a data buffer unit and a data allocation unit. The input of the data buffer unit is used to receive control matching data, and the output of the data buffer unit is connected to the input of the data allocation unit. The output of the data allocation unit is connected to the input of the decoding control module.

[0031] A data caching unit is used to receive control matching data and cache the control matching data;

[0032] The data allocation unit is used to allocate control matching data and output one piece of control matching data to the decoding control module each time.

[0033] In one embodiment, the signal analysis device further includes a debug signal receiving module, the input of which is used to receive debug signals, and the output of which is connected to the input of the arithmetic module.

[0034] The debugging signal receiving module is used to output debugging signals to the arithmetic module.

[0035] In one embodiment, the debug signal receiving module includes a monitoring unit, a first selector, a signal buffer unit, and a second selector. The input terminal of the monitoring unit is used to receive debug signals. The output terminal of the monitoring unit is connected to the input terminal of the first selector. The output terminal of the first selector is connected to the input terminal of the signal buffer unit. The output terminal of the signal buffer unit is connected to the input terminal of the second selector. The output terminal of the second selector is connected to the input terminal of the arithmetic module.

[0036] The monitoring unit is used to receive debugging signals and output them to the signal buffer unit through the first selector;

[0037] The signal buffer unit is used to buffer debugging signals and output them to the arithmetic module through the second selector.

[0038] In one embodiment, the arithmetic module further includes an output unit, and the debug signal receiving module further includes a save control unit. The input terminal of the save control unit is connected to the output terminal of the output unit, and the output terminal of the save control unit is connected to the input terminal of the first selector and the input terminal of the second selector.

[0039] The storage control unit is used to control the first selector to output the debugging signal to the data receiving module when it receives the debugging signal storage signal output by the output unit, and to control the second selector to output the debugging signal to the data receiving module.

[0040] In one embodiment, the arithmetic module further includes an output unit, the input terminal of which is connected to the decoding control module and the output terminals of each arithmetic unit, and the output terminal of which is connected to the input terminal of the decoding control module.

[0041] The output unit is used to output the signal analysis results of the debugging signal based on the output results of each arithmetic unit.

[0042] Thirdly, this application also provides a chip including any of the signal analysis devices described in the second aspect above.

[0043] Fourthly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the methods described in the first aspect above.

[0044] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described in the first aspect above.

[0045] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the methods described in the first aspect above.

[0046] The aforementioned signal analysis methods, devices, chips, equipment, media, and program products are applied to a decoding control module. First, in response to the signal analysis command of the debug signal, target control matching data is obtained from multiple control matching data sets. Command type analysis is then performed on the target control matching data to determine its command type. These multiple control matching data sets include control matching data with various command types. The target control matching data is determined from among the multiple control matching data sets based on the attribute information of the debug signal. Then, based on the command type of the target control matching data, a target arithmetic unit is determined from among multiple arithmetic units in the arithmetic module. Finally, the target control matching data is input to the target arithmetic unit, enabling the arithmetic module to determine the signal analysis result of the debug signal based on the target control matching data and the debug signal. In this way, when matching the debug signal, the command type of the target control matching data determines whether concurrent matching is required. If concurrent matching is required, the target arithmetic unit is determined from among the multiple arithmetic units in the arithmetic module based on the determined target control matching data. There can be multiple target arithmetic units, enabling concurrent matching of multiple target control matching data sets, thus improving the flexibility of the signal matching process. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the signal analysis device in one embodiment;

[0049] Figure 2 This is a schematic diagram of the signal analysis device in another embodiment;

[0050] Figure 3 This is a schematic diagram of the signal analysis device in another embodiment;

[0051] Figure 4 This is a schematic diagram of the signal analysis device in another embodiment;

[0052] Figure 5 This is a schematic diagram of the signal analysis device in another embodiment;

[0053] Figure 6 This is a schematic diagram of the signal analysis device in another embodiment;

[0054] Figure 7 This is a flowchart illustrating a signal analysis method in one embodiment;

[0055] Figure 8 This is a flowchart illustrating the step of determining the command type of target control matching data in another embodiment;

[0056] Figure 9 This is a flowchart illustrating the signal analysis method in another embodiment;

[0057] Figure 10 This is a flowchart illustrating the signal analysis method in another embodiment;

[0058] Figure 11 This is a flowchart illustrating the signal analysis method in another embodiment;

[0059] Figure 12 This is a schematic diagram of the signal analysis device in another embodiment;

[0060] Figure 13 This is a structural block diagram of the computing module in one embodiment;

[0061] Figure 14 This is a schematic diagram of the encoding method of the control register in one embodiment;

[0062] Figure 15 This is a schematic diagram of concurrent matching in one embodiment;

[0063] Figure 16 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0065] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0066] Debug signals in a chip are signals that are predefined during the chip design process and can indicate the system status or fault conditions. Debug signals can be generated by various functional modules inside the chip. In related technologies, when analyzing the source of a chip fault, the chip's on-chip signal logic analyzer is usually used to perform logic analysis on the chip's debug signals. That is, by matching the debug signals with pre-set matching data, the chip fault can be located. However, current logic analysis methods usually match one matching data at a time and cannot match multiple matching data concurrently, resulting in low matching flexibility.

[0067] In view of this, this application proposes a signal analysis method applied to a decoding control module. First, in response to a signal analysis command for a debug signal, target control matching data is obtained from multiple control matching data sets. Command type analysis is then performed on the target control matching data to determine its command type. The multiple control matching data sets include control matching data with various command types. The target control matching data is determined from among the multiple control matching data sets based on the attribute information of the debug signal. Then, based on the command type of the target control matching data, a target arithmetic unit is determined from among multiple arithmetic units in the arithmetic module. Finally, the target control matching data is input to the target arithmetic unit, enabling the arithmetic module to determine the signal analysis result of the debug signal based on the target control matching data and the debug signal. Thus, when matching the debug signal, the command type of the target control matching data determines whether concurrent matching is required. If concurrent matching is required, the target arithmetic unit is determined from among the multiple arithmetic units in the arithmetic module based on the determined target control matching data. Multiple target arithmetic units can be used, enabling concurrent matching of multiple target control matching data sets and improving the flexibility of the signal matching process.

[0068] The signal analysis method provided in this application embodiment can be applied to, for example... Figure 1To facilitate understanding, this embodiment first describes the signal analysis device including the decoding control module 20. The signal analysis device 100 includes a data receiving module 10, a decoding control module 20, and a calculation module 30. The input terminal of the data receiving module 10 is used to receive control matching data, the output terminal of the data receiving module 10 is connected to the input terminal of the decoding control module 20, and the output terminal of the decoding control module 20 is connected to the input terminal of the calculation module 30.

[0069] The decoding control module 20, in response to signal analysis commands of the debugging signal, acquires target control matching data from multiple control matching data in the data receiving module 10, and performs command type analysis on the target control matching data to determine its command type. The multiple control matching data in the data receiving module 10 include control matching data with various command types. The target control matching data is determined from the multiple control matching data based on the attribute information of the debugging signal. Based on the command type of the target control matching data, the target arithmetic unit is determined from multiple arithmetic units in the arithmetic module 30. The arithmetic module 30 receives the debugging signal and the target control matching data, and determines the signal analysis result of the debugging signal based on the debugging signal and the target control matching data.

[0070] The data receiving module 10 receives control matching data via a debug bus. This control matching data can be sent by the CPU (Central Processing Unit) or other functional modules on the chip. After receiving the control matching data, the data receiving module 10 stores it in a buffer. When signal analysis is required, the decoding control module 20 retrieves the target control matching data from multiple control matching data in the buffer of the data receiving module 10. The target control matching data is the control matching data currently being matched against the debug signal. Then, the target control matching data is parsed to determine its command type. Based on the command type, it is determined whether multiple control matching data need to be matched concurrently. If so, the next target control matching data is retrieved; otherwise, the process ends.

[0071] After determining the target control matching data, a target operation unit is selected from among the multiple operation units of the operation module 30 of the signal analysis device. One target control matching data corresponds to one target operation unit. The number of target operation units is related to the number of control matching data that can be matched concurrently at one time. The input terminal of each operation unit is connected to the output terminal of the decoding control module 20 to obtain the decoded target control matching data output by the decoding control module 20. At the same time, debugging signals are received through other input terminals of each operation unit. Then, the debugging signals are matched according to the target control matching data to determine the signal analysis result of the debugging signals. Among them, the debugging signals are signals predefined in the chip design process to indicate the system status or error conditions. The debugging signals can be generated by various functional modules inside the chip and contain information such as whether the operation of the functional module is normal, whether the data is valid, and whether error conditions have occurred. The signal analysis device 100 can set control matching data to match the debugging signals, thereby determining the possible fault types and the system status that needs to be monitored.

[0072] In the above embodiments, the signal analysis device includes a data receiving module, a decoding control module, and a processing module. When matching the debugging signal, the decoding control module determines whether concurrent matching is required based on the command type of the target control matching data. If concurrent matching is required, the module determines the target processing unit based on the determined target control matching data. There can be multiple target processing units. Then, the multiple target control matching data are sent to the multiple target processing units to achieve concurrent matching of multiple target control matching data, which improves the flexibility of the signal matching process and enables matching of more complex application scenarios.

[0073] In one embodiment, such as Figure 2 As shown, the arithmetic module 30 may include a first arithmetic unit 31, a second arithmetic unit 32, a third arithmetic unit 33, and a fourth arithmetic unit 34; the input terminals of the first arithmetic unit 31, the second arithmetic unit 32, the third arithmetic unit 33, and the fourth arithmetic unit 34 are respectively connected to the debugging signal and the decoding control module 20.

[0074] For example, the embodiments of this application are illustrated using four arithmetic units. It can be understood that the number of arithmetic units can be determined based on the number of control matching data that the chip's debugging signal needs to match simultaneously. When the debugging signal needs to match more control matching data concurrently, more arithmetic units can be set to achieve concurrent matching of multiple control matching data.

[0075] In the above embodiments, by setting up multiple processing units, concurrent matching of multiple control matching data can be achieved, making it suitable for more complex signal analysis scenarios. Furthermore, separating the processing module from the data receiving module and the decoding control module facilitates expansion of the processing module, allowing it to be expanded according to the matching requirements of the debugging signals.

[0076] In the embodiments of this application, such as Figure 3 As shown, the data receiving module 10 also includes a data buffer unit 11 and a data distribution unit 12. The input terminal of the data buffer unit 11 is used to receive control matching data, the output terminal of the data buffer unit 11 is connected to the input terminal of the data distribution unit 12, and the output terminal of the data distribution unit 12 is connected to the input terminal of the decoding control module 20.

[0077] The data buffer unit 11 is used to receive and buffer control matching data, and the data allocation unit 12 is used to allocate control matching data and output one piece of control matching data to the decoding control module 20 each time.

[0078] For example, such as Figure 3 As shown, the data cache unit 11 may further include a memory access control unit 111 and a control data cache 112. The input terminal of the memory access control unit 111 is connected to the debug bus, and the memory access control unit 111 is connected to the control data cache 112. The memory access control unit 111 is used to receive control matching data and cache the received control matching data into the control data cache 112. The output terminal of the control data cache 112 is connected to the data allocation unit 12. The control data cache 112 is used to cache control matching data and output the cached data to the data allocation unit 12. The control data cache 112 can cache multiple sets of control matching data. The control data cache 112 can be a static random access memory (SRAM) or an existing SRAM in the signal analysis device 100, which is reused as a cache for caching control matching data.

[0079] For example, the control matching data may include control data and matching data. The data allocation unit 12 may further include a data allocation 121, a control register 122, and a data register 123. The input of the data allocation 121 is connected to the output of the control data buffer 112, receives the control matching data output by the control data buffer 112, and allocates the control data in the control matching data to the control register 122, while the matching data is allocated to the data register 123. The control register 122 may include control0 to controln, and the data register 123 may include R0 to Rm. Optionally, n can be 16, and m can be 32.

[0080] Optionally, for each group of control matching data, data allocation 121 allocates control data according to the sequence number to obtain index information, and then allocates matching data based on the index information. For example, data allocation 121 allocates control data to control register 122 and matching data to data register 123. Each control data includes the index information of the corresponding matching data in data register 123. Each control data in control register 122 may include five parts: fun, comp, index0, index1, index2, and next. Among them, fun is the matching function code of control register 122, containing 9 types of command types that can be matched. Comp is the comparison type, containing 4 comparison types, such as equal to, not equal to, greater than, and less than. index0, index1, and index2 are the indices of the matching data corresponding to the current control data in data register 123. index0 is the mask code index information, used to index the mask code; index1 is the matching code index information, used to index the matching code; index2 is the timer or counter index information, used to index the timer or counter information; and next is the index of the next control data.

[0081] For example, the control register has logical numbers 0 to n, and the data register has logical numbers 0 to m. In data allocation 121, control data with sequence number 0 is allocated to control register number 0. At this time, control register number 0 already stores index information, such as matching code index information and masking code index information. The matching code index information is read as 3, and the masking code index information is read as 5. Then, the matching data with sequence number 0, such as the matching code with sequence number 0, is allocated to data register number 3, and the masking code with sequence number 0 is allocated to data register number 5.

[0082] Optionally, the data allocation unit 12 can also implement a prefetch function for control matching data. After the signal analysis related to the first batch of control matching data with sequence numbers 0 to n is completed, the next batch of control matching data with sequence numbers 0 to n is fetched and allocated to the control register 122 and the data register 123. The prefetch function of the data allocation unit 12 can improve the continuity of the signal analysis device 100 and prevent the signal analysis device 100 from stopping operation due to the lack of control matching data after the signal analysis related to the previous batch of control matching data is completed.

[0083] In the embodiments of this application, such as Figure 4 As shown, the signal analysis device 100 also includes a debug signal receiving module 40. The input terminal of the debug signal receiving module 40 is used to receive debug signals, and the output terminal of the debug signal receiving module 40 is connected to the input terminal of the arithmetic module 30. The debug signal receiving module 40 is used to output debug signals to the arithmetic module 30.

[0084] Optionally, the debugging signal receiving module 40 includes a monitoring unit 41, a first selector 42, a signal buffer unit 43, and a second selector 44. The input terminal of the monitoring unit 41 is used to receive debugging signals. The output terminal of the monitoring unit 41 is connected to the input terminal of the first selector 42. The output terminal of the first selector 42 is connected to the input terminal of the signal buffer unit 43. The output terminal of the signal buffer unit 43 is connected to the input terminal of the second selector 44. The output terminal of the second selector 44 is connected to the input terminal of the arithmetic module 30.

[0085] The monitoring unit 41 is used to receive debugging signals and output them to the signal buffer unit through the first selector 42. The signal buffer unit 43 is used to buffer the debugging signals and output them to the arithmetic module 30 through the second selector 44.

[0086] The monitoring unit 41 receives debugging signals from various functional modules on the chip in real time. Upon receiving a debugging signal, it triggers a timer to record the timing information of the debugging signal and outputs the debugging signal to the signal buffer unit 43 after passing through the first selector 42. The signal buffer unit 43 buffers the received debugging signals and outputs them sequentially to the arithmetic module 30 through the second selector 44. Optionally, the signal buffer unit 43, similar to the control data buffer 112, can be a static random access memory (SRAM) or an existing SRAM in the signal analysis device 100, which is reused as a buffer for debugging signals.

[0087] The first selector 42 can output the debugging signal to different modules under different conditions, and the second selector 44 can output the unprocessed debugging signal in the signal buffer unit 43 to different modules under different conditions. For example, in this embodiment, the debugging signal is output to the arithmetic module 30 after passing through the monitoring unit 41, the first selector 42, the signal buffer unit 43, and the second selector 44.

[0088] In the embodiments of this application, such as Figure 5 As shown, the arithmetic module 30 also includes an output unit 50. The input terminal of the output unit 50 is connected to the output terminal of the decoding control module 20 and each arithmetic unit, and the output terminal of the output unit 50 is connected to the input terminal of the decoding control module 20. The output unit 50 is used to output the signal analysis result of the debugging signal according to the output result of each arithmetic unit.

[0089] The output unit 50 is used to output the signal analysis results of the signal analysis device 100. The output unit 50 receives control information output by the decoding control module 20 and the matching results of each arithmetic unit, determines the signal analysis results, and determines the output action based on the signal analysis results. Optionally, the output action may include state transition, debugging signal saving, or clock stopping. The state transition operation can be performed after the current control matching data is completed, jumping to the next control matching data based on the index of the next control data to continue matching. The debugging signal saving operation can be performed to save the current matching result and the debugging signals before and after matching. Clock stopping can be performed to stop the chip's clock to obtain the overall chip status information, thereby enabling fault location.

[0090] In the above embodiments, the output unit can determine the signal analysis result of the debugging signal based on different matching results and control information, and output the corresponding action to facilitate chip fault location.

[0091] like Figure 6 As shown, the signal analysis device 100 in this embodiment further includes an output unit 50, and the debug signal receiving module 40 further includes a storage control unit 45. The input terminal of the storage control unit 45 is connected to the output terminal of the output unit 50, and the output terminal of the storage control unit 45 is connected to the input terminal of the first selector 42 and the input terminal of the second selector 44. The storage control unit is used to control the first selector 42 to output the debug signal to the data receiving module 10 and control the second selector 44 to output the debug signal to the data receiving module 10 when it receives the debug signal storage signal output by the output unit 50.

[0092] For example, the input terminal of the save control unit 45 is connected to the output terminal of the output unit 50. When the output action of the output unit 50 is to save the debug signal, the save control unit 45 is used to control the first selector 42 and the second selector 44 to output the unprocessed debug signal to the data receiving module 10, so that the debug signal can be output through the data receiving module 10 and the debug bus, and the user can view the specific fault cause and status data.

[0093] Optionally, the output of the first selector 42 is connected to the control data buffer 112 of the data receiving module 10, and is used to switch the output of the debugging signal from the monitoring unit 41 to the control data buffer 112 under the control of the storage control unit 45. The output of the second selector 44 is connected to the memory access control unit 111, and is used to switch the output of the unmatched debugging signal in the signal buffer unit 43 to the memory access control unit 111 under the control of the storage control unit 45. Further, the control data buffer 112 outputs the received debugging signal to the memory access control unit 111, and the memory access control unit 111 outputs the debugging signal received through the second selector 44 and the debugging signal received through the control data buffer 112 through the debugging bus.

[0094] In one exemplary embodiment, such as Figure 7 As shown, a signal analysis method is provided, which can be applied to... Figure 1 The following description uses the decoding control module 20 in the signal analysis device as an example, including steps 701 to 703. The solution provided by this method is applied to the aforementioned signal analysis device; therefore, the specific limitations in one or more signal analysis method embodiments provided below can be found in the limitations of the signal analysis device described above, wherein:

[0095] Step 701: In response to the signal analysis command of the debugging signal, obtain the target control matching data from multiple control matching data, and perform command type analysis on the target control matching data to determine the command type of the target control matching data.

[0096] The data receiving module contains multiple control matching data sets, including control matching data of various command types. The signal analysis command for the debug signal is used to instruct the initiation of signal analysis for debug information. The signal analysis device monitors the debug signal in real time; when the debug signal successfully matches the control matching data, a corresponding fault may have occurred. Therefore, before matching, the data receiving module can receive control matching data via the debug bus and cache it in a register for the decoding control module to read and match with the debug signal. The data receiving module can cache multiple control matching data sets simultaneously, with the target control matching data being the control matching data currently being matched against the debug signal. The target control matching data is determined from among the multiple control matching data sets based on the attribute information of the debug signal. This attribute information can be the identifier information of the debug signal or the type information of the debug signal.

[0097] The command type for controlling the matching data, i.e. the matching function code, can include 9 types, such as matching command (M), matching count command (MC), matching timer (MT) command, UM, UMC, UMT, SM, SMC and SMT, etc. Among them, the matching command can be used to match the state transition signal in the debugging signal, the matching count command can be used to match the duration of a specific signal in the debugging signal, and the matching count command can be used to match the number of non-continuous specific signals in the debugging signal.

[0098] After determining the target control matching data, the command type of the target control matching data is determined by parsing the target control matching data.

[0099] Step 702: Determine the target operation unit from multiple operation units of the operation module according to the command type of the target control matching data.

[0100] In this module, the input terminals of multiple arithmetic units are connected to the output terminals of the decoding control module. The decoding control unit determines the target control matching data for a single matching process based on the command type of the target control matching data. In a single matching process, there can be one or more target control matching data. Then, based on the number of target control matching data, a target arithmetic unit is determined from the multiple arithmetic units. Each target arithmetic unit corresponds one-to-one with a target control matching data, and the target arithmetic unit matches the debugging signal according to the target control matching data.

[0101] Step 703: Input the target control matching data into the target arithmetic unit so that the arithmetic module can determine the signal analysis result of the debugging signal based on the target control matching data and the debugging signal.

[0102] The decoding control module outputs the determined target control matching data to the target processing unit. One target control matching data is output to one target processing unit, so that the processing module can determine the signal analysis result of the debugging signal based on the target control matching data and the debugging signal.

[0103] In the above embodiments, in response to the signal analysis command of the debug signal, target control matching data is obtained from multiple control matching data sets, and command type analysis is performed on the target control matching data to determine its command type. The multiple control matching data sets include control matching data with various command types, and the target control matching data is the control matching data used to match the debug signal. Then, based on the command type of the target control matching data, a target computation unit is determined from multiple computation units of the computation module. Finally, the target control matching data is input to the target computation unit, enabling the computation module to determine the signal analysis result of the debug signal based on the target control matching data and the debug signal. Thus, when matching the debug signal, the command type of the target control matching data determines whether concurrent matching is required. If concurrent matching is required, the target computation unit is determined from multiple computation units of the transportation module based on the determined target control matching data. Multiple target computation units can be used, enabling concurrent matching of multiple target control matching data sets, thus improving the flexibility of the signal matching process.

[0104] In the embodiments of this application, step 701 above determines the command type of the target control matching data, such as... Figure 8 As shown, it may include:

[0105] Step 801: Decode the target control matching data to obtain the decoded target control matching data.

[0106] The decoded target control matching data includes command type information. Decoding the target control matching data involves parsing it according to the encoding format of the control data, resulting in decoded target control matching data. This decoded data may include the command type, comparison type, and index information of the target control matching data.

[0107] Step 802: Obtain the command type of the target control matching data based on the command type information.

[0108] Based on the command type information, the command type of the target control matching data is determined, as described above. Optionally, the decoding process also includes comparison type information and index information. The target control matching data is input to the target arithmetic unit, so that the arithmetic module can determine the matching data by indexing in the data register according to the index information and match the debug signal and the matching data according to the comparison type information to determine the signal analysis result of the debug signal.

[0109] For example, the comparison type Comp, index information index0, index1, and index2 of the target matching data are output to the target processing unit. The target processing unit filters the matching data in the data register of the signal analysis device according to the index information index0, index1, and index2 for matching the debugging signal. The target processing unit matches the debugging signal with the filtered matching data according to the comparison type information. The processing module determines the signal analysis result of the debugging signal based on the matching results of each target processing unit.

[0110] In embodiments of this application, the calculation module further includes an output unit connected to multiple calculation units, the decoding processing result further includes calculation control information, and the method further includes: outputting the calculation control information of the target control matching data to the output unit.

[0111] The input terminal of the output unit is connected to the output terminal of the decoding control module and the output terminals of each arithmetic unit. The arithmetic control information is used by the output unit to determine the signal analysis result of the debug signal based on the output results of multiple target arithmetic units and the arithmetic control information. The arithmetic control information indicates the correspondence between the matching result combinations of each arithmetic unit and different output actions. During concurrent matching, multiple target arithmetic units output their respective matching results. The output unit determines the signal analysis result of the debug signal based on the matching results of each target arithmetic unit and the arithmetic control information, and outputs an action. The output action may include state transition, debug signal saving, and clock stopping.

[0112] In one embodiment, determining the target processing unit from multiple processing units of the processing module based on the command type of the target control matching data includes: determining whether the step of acquiring the target control matching data has been completed based on the command type of the target control matching data. Optionally, such as Figure 9 As shown, the steps for determining whether the acquisition of target control matching data has been completed include:

[0113] Step 901: Detect whether the command type of the target control matching data is a preset type.

[0114] Optionally, as described above, the command type for target control matching data may include M, MC, MT commands, UM, UMC, UMT, SM, SMC, and SMT, wherein the default type is defined as M, MC, or MT commands.

[0115] Step 902: If the command type of the target control matching data is a preset type, then the step of obtaining the target control matching data is completed.

[0116] When the command type is M, MC, or MT, it is not necessary to obtain the next control matching data at the same time, thus completing the step of obtaining the target control matching data.

[0117] Step 903: If the command type of the target control matching data is not a preset type, then continue to obtain the next control matching data from the data receiving module as the target control matching data.

[0118] When the command type is not the above-mentioned preset type, and the command type is UM, UMC, UMT, SM, SMC and SMT, the next control matching data needs to be obtained at the same time. That is, the step of obtaining the target control matching data is not completed, and the decoding control module continues to obtain the next control matching data of the target control matching data in the data receiving module as the target control matching data.

[0119] For example, since the number of processing units in the processing module of the signal analysis device is fixed, before detecting whether the command type of the target control matching data is a preset type, such as... Figure 10 As shown, the method also includes:

[0120] Step 1001: Obtain the number of matching data for the current target control.

[0121] Step 1002: If the number of target control matching data is greater than or equal to the preset threshold, then the step of obtaining target control matching data is completed.

[0122] The preset threshold is determined based on the number of processing units. The process involves acquiring the number of currently identified target control matching data points. The preset threshold can be the number of processing units in the signal analysis device. If the current number of target control matching data points is greater than or equal to the preset threshold (meaning no more processing units are allocated to target control matching data), the step of acquiring target control matching data is complete. If the current number of target control matching data points is less than the preset threshold, the process continues by checking whether the command type of the target control matching data is a preset type.

[0123] If the step of acquiring target control matching data is completed, then determine the number of target control matching data acquired simultaneously, and select the same number of operation units from the multiple operation units of the operation module as the target operation units.

[0124] In embodiments of this application, a signal analysis method is provided, such as... Figure 11 As shown, it includes:

[0125] Step 1101: Obtain target control matching data from multiple control matching data in the data receiving module.

[0126] Step 1102: Decode the target control matching data to obtain the decoded target control matching data.

[0127] Step 1103: Obtain the command type of the target control matching data based on the command type information.

[0128] Step 1104: Obtain the number of matching data for the current target control.

[0129] Step 1105: If the number of target control matching data is greater than or equal to the preset threshold, then the step of obtaining target control matching data is completed.

[0130] Step 1106: Detect whether the command type of the target control matching data is a preset type.

[0131] Step 1107: If the command type of the target control matching data is a preset type, then the step of obtaining the target control matching data is completed.

[0132] Step 1108: If the command type of the target control matching data is not a preset type, then continue to obtain the next control matching data from the data receiving module as the target control matching data.

[0133] Step 1109: Determine the target operation unit from multiple operation units of the operation module according to the command type of the target control matching data.

[0134] Step 1110: Output the target control matching data to the target computing unit.

[0135] In the embodiments of this application, please refer to Figure 12This is a schematic diagram of the signal analysis device according to an embodiment of this application. The flow of the signal analysis method will be described in conjunction with this signal analysis device. For example, the determination and output of target control matching data to the target arithmetic unit in the above embodiment will be illustrated. To achieve concurrent matching, the decoding control module obtains the control data corresponding to the target matching control data from the control register control, and decodes the control data. It determines whether to simultaneously obtain the next control data based on the command type of the currently decoded control data. If the command type is M, MT, or MC, the decoding control module obtains only one control data and outputs the index0, index1, index2, and arithmetic type of the control data to the first arithmetic unit 31, sending the arithmetic control to the output unit. If it is UM, UMT, UMC, SM, SMT, or SMC, the decoding control module simultaneously obtains and decodes the control data corresponding to the next target matching control data pointed to by this target control matching data. The current control data's index0, index1, index2, and operation type are output to the first operation unit 31, and the operation control is sent to the output unit. The next control data's index0, index1, index2, and operation type are output to the second operation unit 31, and the operation control is sent to the output unit. This process continues until four control data are acquired simultaneously, or until the command type of the control data is M, MT, or MC.

[0136] The first arithmetic unit 31, the second arithmetic unit 32, the third arithmetic unit 33, and the fourth arithmetic unit 34 output their respective matching results to the output unit. The output unit determines the output action based on the arithmetic control information output by the decoding control module and the matching results of each arithmetic unit. If the output action is a state transition, a state transition signal is output to the decoding control module. The decoding control module reads the next control matching data based on the state transition signal and performs the next matching. If the output action is a debug signal save, the output unit outputs a debug signal save signal to the save control unit. The save control unit saves subsequent debug signals to the control data buffer through the first selector. At the same time, the save control unit outputs the debug signals that have been cached but not matched in the signal buffer unit to the memory access control unit through the second selector. When it is necessary to read the debug signal, the second selector is used to read the debug signal before the matching error from the signal buffer unit, and then the control data buffer is used to read the debug signal after the matching error.

[0137] The arithmetic module retrieves matching data from data registers R0~Rm based on index0, index1, index2, and the arithmetic type output by the decoding control module, and performs matching on the debug signals. The specific implementation of any arithmetic unit is as follows: Figure 13As shown, the specific workflow of the arithmetic unit is as follows: A bitwise AND operation is performed between the masking code selected at index0 in MUX0 and the debugging signal, and then the result is sent to the arithmetic subunit for computation. A bitwise AND operation is performed between the matching code selected at index1 in MUX1 and the masking code selected at index0 in MUX0, and then the result is sent to the arithmetic subunit for computation. A counter or timer threshold selected at index2 in MUX2 is sent to the arithmetic subunit for computation. Each arithmetic unit has its own separate arithmetic subunit and counter, and each type of command executes independent counting and independent computation.

[0138] For example, the encoding method of the control register in the above-mentioned signal analysis device can be as follows: Figure 14 As shown, a command is also a piece of control data. Bits 24 to 19 of the control register are the "fun" part, which represents the command type of the control data, including the matching mode encoding, parallel mode encoding, and comparison operation encoding. Bits 24 to 23 are the matching mode encoding: 2'b00 represents an invalid command, 2'b01 represents M-type matching mode (match jump), 2'b10 represents MT-type matching mode (match timer jump), and 2'b11 represents MC-type matching mode (match count jump). Bits 22 to 21 represent the concurrency mode encoding: 2'b00 means no execution of the next command concurrently, and 2'b01 means the current command and the next command are executed concurrently. Success is achieved when both commands match successfully. The prefix "U" is added before the matching mode codes M, MT, and MC, which are the command types UM, UMT, and UMC in the above embodiment. 2'b10 indicates that the current command and the next command are executed concurrently. Success is achieved if one of the executed commands matches successfully. The matching methods M, MT, and MC are indicated by adding the prefix S, which corresponds to the command types SM, SMT, and SMC in the above embodiments. The encoding of 2'b11 is a reserved format. Bits 20 to 19 represent the comparison type: 2'b00 represents inequality (=!), 2'b01 represents less than (<), 2'b10 represents greater than (>), and 2'b11 represents equality (=).

[0139] Optionally, index0 is the index of the masking code in data registers R0 to Rm, and index1 is the index of the matching code in data registers R0 to Rm. According to different command types, the index meaning of index2 is different. For example, index2 for the M-type matching method is a reserved bit and is not used temporarily. Index2 for the MT-type matching method is the timer threshold index, index2 for the MC-type matching method is the counter threshold index, and the encoding method of the index information for command types with U and S prefixes is the same as that without them. Next is the index of the next control data of the current control data. If it is a U and S concurrent command, then according to the next index, the decoding control module fetches and decodes the next control data simultaneously.

[0140] Exemplarily, the matching processes of control matching data for different command types are as follows. For the operation of the matching (M) type command, the masking code is obtained by indexing according to index0 in data registers R0 to Rm, and the matching code is obtained by indexing according to index1 in data registers R0 to Rm. The result of the bitwise AND operation between the debug signal and the masking code is A, and the result of the bitwise AND operation between the matching code and the masking code is B. A and B are matched according to the comparison type. For example, the comparison operator can be A B or A = B, and then the matching result is output. If the comparison type is A = B, then when A = B is matched, it indicates a successful match.

[0141] For the operation of the matching timing (MT) type command, the matching process is the same as that of the above M type command. When the match is successful, the timer is started. The timing clock is the clock of the signal analysis device. The timer increments by 1 continuously according to the clock until it is reset to 0 after the match is unsuccessful. When the value of the timer exceeds the value fetched by the timer index information index2, it indicates a successful match and the matching result is output. This type of command is used to match the duration of a specific signal appearing in the debug signal.

[0142] For the operation of the matching counting (MC) type command, the matching process is the same as that of the above M type command. When the match is successful, the value of the counter increments by 1, and when the match is unsuccessful, the value of the counter remains unchanged. When the value of the counter exceeds the value fetched by the counter index information index2, it indicates a successful match and the matching result is output.

[0143] In one embodiment, such as Figure 15The diagram illustrates the parallel matching process of this signal analysis method. In the first matching, the target control matching data has an M-type command. Since M-type commands are a preset type, the step of acquiring the target control matching data is completed, and the target control matching data is output to the target processing unit for matching. If the matching is successful, the process jumps directly to the second matching. In the second matching, the target control matching data has a UM command, which is not a preset type. Therefore, the next control matching data is acquired simultaneously, and the command type of the next control matching data is an M command. At this point, the step of acquiring the target control matching data is completed, and the two target control matching data are output to two target processing units for matching. If both target processing units match successfully, the process jumps to the third matching based on the next step. Similarly, the target control matching data for the third matching consists of two SM commands and one M command. If any of the three commands matches successfully, the process jumps to the fourth matching, which is pointed to by the next step of the M command. The target control matching data for the fourth matching consists of three UM commands and one M command. If all four commands match successfully, the process jumps to the fifth matching. The target control for the 5th match is to match data UMT, SMT, UMT and MT. In this case, if UMT and SMT match successfully at the same time or if UMT and MT match successfully at the same time, it will trigger a jump to the next match.

[0144] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0145] In one exemplary embodiment, a chip is provided, including the signal analysis device 100 described in any of the above embodiments, which enables the chip fault to be located based on debugging signals on the chip.

[0146] In one exemplary embodiment, a computer device is provided, which may be a decoding controller, and its internal structure diagram may be as follows: Figure 16As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When executed by the processor, the computer program implements a signal analysis method.

[0147] Those skilled in the art will understand that Figure 16 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0148] In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps: in response to a signal analysis instruction for a debug signal, acquiring target control matching data from multiple control matching data, and performing command type analysis on the target control matching data to determine the command type of the target control matching data; the multiple control matching data includes control matching data of various command types, and the target control matching data is determined from the multiple control matching data based on the attribute information of the debug signal; determining a target arithmetic unit from multiple arithmetic units of an arithmetic module based on the command type of the target control matching data; and inputting the target control matching data to the target arithmetic unit so that the arithmetic module determines the signal analysis result of the debug signal based on the target control matching data and the debug signal.

[0149] In one embodiment, when the processor executes the computer program, it further performs the following steps: decoding the target control matching data to obtain decoded target control matching data, wherein the decoded target control matching data includes command type information of the target control matching data; and obtaining the command type of the target control matching data based on the command type information.

[0150] In one embodiment, the decoded target control matching data further includes comparison type information and index information. When the processor executes the computer program, it also performs the following steps: inputting the comparison type information and index information of the target control matching data into the target arithmetic unit; so that the arithmetic module can determine the matching data by indexing in the data register according to the index information and match the debug signal and the matching data according to the comparison type information to determine the signal analysis result of the debug signal.

[0151] In one embodiment, the arithmetic module further includes an output unit connected to multiple arithmetic units. The decoded target control matching data also includes arithmetic control information. When the processor executes the computer program, it also performs the following steps: outputting the arithmetic control information of the target control matching data to the output unit. The arithmetic control information is used by the output unit to determine the signal analysis result of the debugging signal based on the output results of multiple arithmetic units and the arithmetic control information.

[0152] In one embodiment, when the processor executes the computer program, it further performs the following steps: determining whether the step of acquiring target control matching data has been completed based on the command type of the target control matching data; if the step of acquiring target control matching data has been completed, acquiring the number of target control matching data acquired simultaneously, and determining the same number of arithmetic units from multiple arithmetic units of the arithmetic module as the target arithmetic units.

[0153] In one embodiment, when the processor executes the computer program, it further performs the following steps: detecting whether the command type of the target control matching data is a preset type; if the command type of the target control matching data is a preset type, then the step of obtaining the target control matching data is completed; if the command type of the target control matching data is not a preset type, then the next control matching data of the target control matching data is obtained from the data receiving module as the target control matching data.

[0154] In one embodiment, when the processor executes the computer program, it further performs the following steps: obtaining the number of current target control matching data; if the number of current target control matching data is greater than or equal to a preset threshold, then the step of obtaining target control matching data is completed; the preset threshold is determined based on the number of arithmetic modules.

[0155] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the signal analysis method described in any of the above method embodiments.

[0156] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the signal analysis method described in any of the above method embodiments.

[0157] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0158] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0159] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0160] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A signal analysis method, characterized in that, Applied to a decoding control module, the method includes: In response to a signal analysis command for a debug signal, target control matching data is obtained from multiple control matching data sets, and command type analysis is performed on the target control matching data to determine the command type of the target control matching data. The multiple control matching data sets include control matching data with various command types, and the target control matching data is determined from the multiple control matching data sets based on the attribute information of the debug signal. Based on the command type of the target control matching data, the target operation unit is determined from multiple operation units of the operation module; The target control matching data is input to the target computing unit so that the computing module determines the signal analysis result of the debugging signal based on the target control matching data and the debugging signal.

2. The method according to claim 1, characterized in that, The step of performing command type analysis on the target control matching data to determine the command type of the target control matching data includes: The target control matching data is decoded to obtain decoded target control matching data, which includes command type information of the target control matching data. Based on the command type information, the command type of the target control matching data is obtained.

3. The method according to claim 2, characterized in that, The decoded target control matching data also includes comparison type information and index information. The step of inputting the target control matching data to the target processing unit, so that the processing module determines the signal analysis result of the debugging signal based on the target control matching data and the debugging signal, includes: The comparison type information and index information of the target control matching data are input to the target arithmetic unit, so that the arithmetic module can determine the matching data by indexing in the data register according to the index information; and match the debugging signal and the matching data according to the comparison type information to determine the signal analysis result of the debugging signal.

4. The method according to claim 2, characterized in that, The computation module further includes an output unit connected to the plurality of computation units, and the decoded target control matching data further includes computation control information. The method further includes: The calculation control information of the target control matching data is output to the output unit. The calculation control information is used by the output unit to determine the signal analysis result of the debugging signal based on the output results of the multiple calculation units and the calculation control information.

5. The method according to claim 1, characterized in that, The step of determining the target computation unit from multiple computation units of the computation module based on the command type of the target control matching data includes: Determine whether the step of obtaining the target control matching data has been completed based on the command type of the target control matching data. If the step of acquiring the target control matching data is completed, then the number of target control matching data acquired simultaneously is obtained, and the same number of operation units are determined from the multiple operation units of the operation module as the target operation unit.

6. The method according to claim 5, characterized in that, The step of determining whether the acquisition of the target control matching data has been completed based on the command type of the target control matching data includes: Detect whether the command type of the target control matching data is a preset type; If the command type of the target control matching data is the preset type, then the step of obtaining the target control matching data is completed.

7. The method according to claim 6, characterized in that, The step of determining whether the acquisition of the target control matching data is complete based on the command type of the target control matching data further includes: If the command type of the target control matching data is not the preset type, then the next control matching data of the target control matching data is obtained as the target control matching data.

8. The method according to claim 7, characterized in that, Before detecting whether the command type of the target control matching data is a preset type, the method further includes: Obtain the number of target control matching data currently being obtained; If the number of target control matching data is greater than or equal to a preset threshold, the step of obtaining the target control matching data is completed; the preset threshold is determined based on the number of computing units.

9. A signal analysis device, characterized in that, The signal analysis device includes a data receiving module, a decoding control module, and a computing module; the input terminal of the data receiving module is used to receive control matching data, the output terminal of the data receiving module is connected to the input terminal of the decoding control module, and the output terminal of the decoding control module is connected to the input terminal of the computing module. The decoding control module is configured to, in response to a signal analysis command of a debug signal, acquire target control matching data from multiple control matching data in a data receiving module, and perform command type analysis on the target control matching data to determine the command type of the target control matching data; the multiple control matching data in the data receiving module includes control matching data with various command types; the target control matching data is determined from the multiple control matching data based on the attribute information of the debug signal; and a target arithmetic unit is determined from multiple arithmetic units of the arithmetic module based on the command type of the target control matching data. The computing module is used to receive the debugging signal and the target control matching data, and determine the signal analysis result of the debugging signal based on the debugging signal and the target control matching data.

10. The signal analysis apparatus according to claim 9, characterized in that, The computing module includes a first computing unit, a second computing unit, a third computing unit, and a fourth computing unit; the input terminals of the first computing unit, the second computing unit, the third computing unit, and the fourth computing unit are respectively connected to the debugging signal and the decoding control module.

11. The signal analysis apparatus according to claim 9 or 10, characterized in that, The data receiving module further includes a data buffer unit and a data allocation unit. The input end of the data buffer unit is used to receive control matching data, the output end of the data buffer unit is connected to the input end of the data allocation unit, and the output end of the data allocation unit is connected to the input end of the decoding control module. The data caching unit is used to receive the control matching data and cache the control matching data; The data allocation unit is used to allocate the control matching data and output one piece of control matching data to the decoding control module each time.

12. The signal analysis apparatus according to claim 9 or 10, characterized in that, The signal analysis device further includes a debugging signal receiving module, the input of which is used to receive the debugging signal, and the output of which is connected to the input of the calculation module. The debugging signal receiving module is used to output the debugging signal to the computing module.

13. The signal analysis apparatus according to claim 12, characterized in that, The debugging signal receiving module includes a monitoring unit, a first selector, a signal buffer unit, and a second selector. The input terminal of the monitoring unit is used to receive the debugging signal. The output terminal of the monitoring unit is connected to the input terminal of the first selector. The output terminal of the first selector is connected to the input terminal of the signal buffer unit. The output terminal of the signal buffer unit is connected to the input terminal of the second selector. The output terminal of the second selector is connected to the input terminal of the arithmetic module. The monitoring unit is used to receive the debugging signal and output it to the signal buffer unit through the first selector; The signal buffer unit is used to buffer the debugging signal and output it to the arithmetic module through the second selector.

14. The signal analysis apparatus according to claim 13, characterized in that, The calculation module further includes an output unit, and the debugging signal receiving module further includes a save control unit. The input terminal of the save control unit is connected to the output terminal of the output unit, and the output terminal of the save control unit is connected to the input terminal of the first selector and the input terminal of the second selector. The save control unit is used to control the first selector to output the debug signal to the data receiving module when it receives the debug signal save signal output by the output unit, and to control the second selector to output the debug signal to the data receiving module.

15. The signal analysis apparatus according to claim 9 or 10, characterized in that, The arithmetic module further includes an output unit, the input terminal of which is connected to the decoding control module and the output terminals of each arithmetic unit, and the output terminal of which is connected to the input terminal of the decoding control module. The output unit is used to output the signal analysis result of the debugging signal based on the output result of each of the arithmetic units.

16. A chip, characterized in that, The signal analysis device includes any one of claims 9 to 15.

17. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

19. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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