Mask layout and device formation method

By introducing a multi-layer alignment mark design in the mask layout, precise splicing of large-size sensors can be achieved, solving the problems of large area occupied by alignment marks and insufficient alignment accuracy in the existing technology, and improving splicing accuracy and the utilization efficiency of functional circuits.

CN122131541APending Publication Date: 2026-06-02SEMICON MFG INT (BEIJING) CORP +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SEMICON MFG INT (BEIJING) CORP
Filing Date
2024-11-29
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

Existing chip splicing methods cannot accurately control the alignment between different parts in the manufacturing of large-size sensors. This can lead to defects such as deformation, discontinuity, and narrowing of circuits in adjacent spliced ​​chip circuit structures. Furthermore, the alignment marks occupy a large area, affecting the wiring of functional circuits.

Method used

The mask layout design includes several target layouts with different layers. Each sub-layout has first, second, and third alignment marks. Alignment within the same layer and between layers is achieved through the second alignment mark, reducing the area occupied by the alignment marks and improving the splicing accuracy.

Benefits of technology

It effectively splices large-size sensors, reduces the area occupied by alignment marks, increases the area used by functional circuits, improves the alignment accuracy of splicing exposure, and reduces the impact on the wiring of functional circuits.

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Abstract

This invention provides a method for forming a mask layout and a device, wherein the mask layout includes: a plurality of target layouts of different layers, the target layouts including a plurality of sub-layouts located on the same layer, the sub-layouts having a first alignment mark, a second alignment mark and a third alignment mark, after the plurality of sub-layouts of the same layer are stitched together, the second alignment mark in the sub-layout and the third alignment mark in the adjacent stitched sub-layouts are aligned at the same layer; after the plurality of target layouts of different layers are aligned, the first alignment mark in the previous layer sub-layout and the corresponding second alignment mark in the current layer sub-layout are aligned at different layers, saving the area occupied by alignment marks, increasing the usable area of ​​functional circuits, and improving the alignment accuracy of stitching exposure.
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