Computing storage device, system, and operating method for a memory device
By combining NAND and non-volatile memory arrays in near-nearest disk search, the problem of high DRAM usage is solved, achieving efficient search operations and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MACRONIX INTERNATIONAL CO LTD
- Filing Date
- 2024-12-17
- Publication Date
- 2026-06-02
AI Technical Summary
Existing technologies require extensive use of dynamic random access memory (DRAM) when performing near nearest point searches on disks, resulting in high costs and volatility, making it difficult to effectively reduce DRAM usage.
By combining NAND memory arrays and non-volatile memory arrays with processing units, a disk-based near nearest point search is performed, reducing reliance on DRAM. By storing node data blocks in NAND memory and product quantization vectors in non-volatile memory, the search operation is performed directly, reducing DRAM requirements.
It effectively reduces DRAM usage and cost, improves search efficiency, reduces data movement between the processor and storage device, and lowers system resource requirements.
Smart Images
Figure CN122131967A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a computational storage device for disk approximate nearest point search, and more particularly to a computational storage system for disk approximate nearest point search and a method of operation for a memory device. Background Technology
[0002] In current database searches, Approximate Nearest Neighbor Search (ANNs) techniques are used, such as vector searches using ANN algorithms. Image-based ANN methods, such as HNSW (Hierarchical Navigable Small World) or NSG (Navigating Spread-out Graph), typically require significant amounts of dynamic random-access memory (DRAM) to achieve their performance. Microsoft's DiskANN technology, which executes ANNs on disk devices like solid-state drives (SSDs), reduces DRAM usage. However, due to the high cost and volatility of DRAM, processing very large databases or managing multiple databases on an SSD can lead to DiskANN still requiring significant DRAM usage or frequent DRAM accesses, such as repeatedly loading data from the SSD to DRAM, increasing DRAM costs. Therefore, there is a need for techniques to reduce DRAM usage in DiskANN search (DiskANN search can be referred to as DiskANNs). Summary of the Invention
[0003] A system of one or more computers is used to perform specific operations and / or actions by having software, firmware, hardware, or a combination thereof installed on it, which, when in operation, enables the system to perform and / or control the operations and / or actions. A system of one or more computer programs is used to perform specific operations and / or actions by containing instructions, which, when executed, enable a device to perform the operations and / or actions.
[0004] A first aspect of the present invention provides a computing storage device for performing a Disk Approximate Nearest Point (DiskANN) search. The computing storage device includes a NAND memory array for storing multiple node chunks corresponding to multiple nodes in a disk approximate nearest point. The computing storage device also includes a non-volatile memory array for storing multiple product quantization (PQ) vectors corresponding to multiple nodes in the multiple node chunks. The computing storage device also includes a processing unit coupled to the NAND memory array and the non-volatile memory. The processing unit is configured to perform a disk approximate nearest point search on the multiple node chunks in the NAND memory array and the multiple product quantization vectors in the non-volatile memory array according to a received search instruction, and output the search results. Other embodiments of this aspect include corresponding computer systems, apparatuses, and computer programs recorded in one or more computer storage devices, each for implementing the operation of this method.
[0005] A second aspect of the present invention provides a computing storage system for performing a DiskANN search. The computing storage system includes a computing SSD. The computing SSD includes a NAND memory array for storing multiple node data blocks corresponding to multiple nodes in a DiskANN. The computing SSD also includes a processing unit coupled to the NAND memory array. The computing storage system also includes a non-volatile memory device. The non-volatile memory device includes a non-volatile memory array for storing multiple PQ vectors corresponding to multiple nodes in the multiple node data blocks. The non-volatile memory device is coupled to the processing unit. The processing unit is configured to perform a DiskANN search on the multiple node data blocks in the NAND memory array of the computing SSD and the multiple PQ vectors in the non-volatile memory array of the non-volatile memory device according to a received search instruction, and output a search result. Other embodiments of this aspect include corresponding computer systems, apparatuses, and computer programs recorded on one or more computer storage devices, each for performing the actions of this method.
[0006] A third aspect of the present invention provides an operating method for a memory device. The operating method includes storing multiple node data blocks of multiple nodes generated by DiskANN from a database in a NAND memory array of the memory device. The operating method also includes storing multiple PQ vectors corresponding to multiple nodes in the multiple node data blocks in a non-volatile memory array of the memory device. The operating method also includes performing a DiskANN search on the multiple node data blocks in the NAND memory array and the multiple PQ vectors in the non-volatile memory array according to a received search instruction by a processing unit of the memory device, and outputting the search results. Other embodiments of this aspect include corresponding computer systems, devices, and computer programs recorded in one or more computer storage devices, each for implementing the operation of this method.
[0007] Other features, aspects, and advantages will become clearer from the embodiments, drawings, and claims. To provide a better understanding of the above and other aspects of the invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description
[0008] Figure 1 A schematic diagram illustrating an example computing system having a computing storage device according to one or more embodiments of the present invention is shown.
[0009] Figure 2 The illustrations depict one or more embodiments of the present invention. Figure 1 This diagram illustrates how DiskANN's functions are implemented using storage devices.
[0010] Figure 3A and Figure 3B Schematic diagrams illustrating different examples of a computational storage device according to one or more embodiments of the present invention are shown.
[0011] Figure 4A and Figure 4B Schematic diagrams are shown for different examples of a computational storage system according to one or more embodiments of the present invention.
[0012] Figure 5 A flowchart illustrating a program for executing DiskANN on a memory device according to one or more embodiments of the present invention is shown.
[0013] Explanation of reference numerals in the attached figures:
[0014] 100: Computing System
[0015] 110: CPU
[0016] 112, 122: Temporary registers, caches, and internal memory
[0017] 120: GPU
[0018] 130: System DRAM
[0019] 140, 240: Storage devices for computation
[0020] 141,241: Processing Unit
[0021] 142,242: NAND memory array
[0022] 143,283: Non-volatile memory array
[0023] 144,244: Dynamic Memory Array
[0024] 150: Traditional storage devices
[0025] 160: I / O
[0026] 170: Bus / Interface
[0027] 280: Non-volatile memory device
[0028] 500: Program
[0029] S510~S540: Steps Detailed Implementation
[0030] This document describes one or more flowcharts. The processes illustrated in the flowcharts are implementable and / or directly programmable processors that use computer programs stored in accessible memory of a computer system and executable by the processor, using dedicated logic hardware (including field-programmable integrated circuits (FPGAs)) and various combinations thereof. Multiple actions are composable, can be executed in parallel, and / or can be executed in different orders without affecting the achieved process. In some cases, rearranged actions will achieve the same result only if certain other changes are also made simultaneously. In other cases, rearranged actions will achieve the same result only if specific conditions are met. Furthermore, for clarity, some flowcharts in this document omit certain unnecessary actions to understand the disclosed techniques. Multiple additional actions may be performed before, after, and / or between the illustrated actions.
[0031] Based on computing storage devices or computing storage systems, as described herein, technologies reduce processor usage and / or bus bandwidth usage. The system can utilize the resources of computing storage devices, such as computing SSDs, to perform computational techniques (e.g., searching (such as DiskANN searches, or DiskANNs), calculations, and / or access) instead of processor and / or bus resources, thus reducing or minimizing information movement between processing elements and storage devices. Computing storage technologies can manage, organize, select, and analyze the ever-increasing volume of real-time data. Computing storage devices can store and manipulate data locally. Therefore, by using computing storage devices, the system's processing, storage, and bandwidth requirements can be reduced.
[0032] Furthermore, using computing storage devices allows CPU and / or GPU resources to be used for other tasks, resulting in faster results. In some use cases, computing storage devices reduce the need to purchase additional processors and / or servers. In other use cases, they reduce the need to purchase additional power supplies and / or cooling systems. In still other use cases, computing storage devices open up new understandings and opportunities to accelerate various applications using their own processing technology. Example applications of computing storage device technology include image processing, database management, and artificial intelligence.
[0033] The example computing storage device or system DiskANN provided by this invention performs a search and outputs the search results. For example, some components of the computing storage device, such as the processing unit, are used for the calculation (search) function, while other components of the computing storage device, such as various types of memory arrays, are used for the data storage function.
[0034] Figure 1 A schematic diagram illustrating an example computing system 100 having a computing storage device 140 according to one or more embodiments of the present invention is shown. The computing system 100 includes a CPU 110, a GPU 120, RAM 130, a computing storage device 140, a conventional storage device 150, and I / O 160, all coupled via a bus / interface 170. In some embodiments, the computing storage device 140 may include a computing SSD. In some embodiments, the computing storage device 140 may be replaced by a computing storage system similar to the computing storage device 140, for example… Figure 4A and 4B The graph processing storage system 200. An example of the processing storage device 140 can perform functions related to the processing storage device, such as performing disk near nearest point (DiskANN) searches (or DiskANNs).
[0035] CPU 110 includes one or more processing units, such as any combination of hardware units capable of executing programmable instructions, microprocessors, signal processors, AI processors, and other similar entities. The one or more processing units selectively include one or more internal registers (some of which are selectively architecturally visible), one or more cache memories, and / or one or more internal memories (e.g., relating to buffering and / or merging), as indicated by registers, caches, and internal memories 112.
[0036] GPU 120 includes one or more processing units, such as any combination of units, capable of accelerating processing for relatively high parallel processing such as graphics processing, signal processing, and / or AI processing. Similar to the registers, caches, and internal memory 112 of CPU 110, one or more processing units selectively include one or more internal registers (some of which are selectively architecturally visible), one or more cache memories, and / or one or more internal memories (e.g., relating to buffering and / or merging), as represented by registers, caches, and internal memory 122.
[0037] The system DRAM 130 includes one or more DRAM devices for storing instructions and / or data, the amount of which is greater than the memory of the CPU 110 and / or GPU 120.
[0038] The computing storage device 140 can be enabled to perform a disk near nearest point (DiskANN) search on the data stored on the computing storage device 140 without transferring the data to the CPU 110, system DRAM 130 and / or GPU 120.
[0039] Conventional storage device 150 includes one or more storage elements, such as an SSD based on flash-based storage elements or an HHD based on rotating magnetic and / or optical non-volatile storage elements (e.g., platters), for storing instructions and / or data. Compared to HDDs, SSDs can have lower access latency but can store less data.
[0040] I / O 160 includes components that can connect any combination of CPU 110, GPU 120, system DRAM 130, computing storage device 140, and / or conventional storage device 150 to external components of computing system 100. Examples of external components include a wide range of storage devices, local or wide area networks (e.g., the Internet), human-machine interface components (e.g., keyboard, mouse, and / or monitor), and other components that provide the ability to extend and / or enhance capabilities not provided by computing system 100.
[0041] Bus / interface 170 enables communication between components coupled to it (e.g., CPU 110, GPU 120, system DRAM 130, computing storage device 140, conventional storage device 150, and / or I / O 160). Bus / interface 170 includes one or more serial and / or parallel communication channels in various ways, as well as selective protocol conversion and / or adaptation capabilities to enhance communication between components coupled to it.
[0042] The computing system 100, which includes computing storage device 140, can reduce or minimize the movement of data between conventional processing elements (e.g., CPU 110 and / or GPU 120) and computing storage elements (e.g., computing storage device 140). A disk near nearest neighbor (DiskANN) search operation is performed on computing storage device 140, using stored data that can be obtained from computing storage device 140.
[0043] Depending on the application requirements, additional partitioning of the components shown in the diagram, coupling between components, component capabilities and / or capacity, and other additional components may be considered.
[0044] The resources of computing storage devices can be used in multiple systems (e.g., systems using computing storage devices), such as personal computers, computing servers, database servers, and AI accelerators. The computing storage device technology provided by this invention can be used to store information generated by Disk Nearest Point (DiskANN) and to search for this information stored locally on the computing storage device. Searches related to DiskANN and the operation of DiskANN on the computing storage device will be coordinated... Figures 2 to 4B The following explanation is provided.
[0045] Figure 2 The illustrations depict one or more embodiments of the present invention. Figure 1 This is a schematic diagram illustrating the DiskANN-related functions implemented using the storage device 140. In DiskANN applications (e.g., by...) Figure 1The computing system 100 executes the algorithm, for example, the DiskANN algorithm, to create an index on the target database and generate a graph index (e.g., a randomly generated Vamana graph). Corresponding to the graph index, the index includes data of each node in the graph, allowing for searching of the database data based on the graph index, such as a vector search. Specifically, the index generated by the DiskANN algorithm for the database may include node chunks (including node vector data of each node (e.g., including complete vectors representing the length and amount of data), the number of neighboring nodes, and neighboring node numbers), and PQ vectors of each node corresponding to the neighboring node numbers in the node chunks. The graph index and the related node data (including node chunks and PQ vectors) in these indexes can be stored in the computing storage device 140 for further DiskANN searches on this index data stored in the computing storage device 140. The graph index and related node data in these indexes can be stored in the NAND memory array of the computing storage device 140. However, when performing a DiskANN search or when the system restarts, it may be necessary to read a large amount of PQ vector data into DRAM for subsequent processing. This increases the DRAM requirements and usage cost in the computing storage device 140. In response, the computing storage device technology provided by this invention, by changing the storage method of related node data in the index through the architecture of the computing storage device or computing storage system, can reduce the amount of DRAM required and used in the computing storage device or computing storage system. The following will be discussed in conjunction with… Figures 3A to 4B Detailed explanation.
[0046] Figure 3A and Figure 3B Schematic diagrams illustrating different examples of a computational storage device 140 according to one or more embodiments of the present invention are shown. For example... Figure 3A and Figure 3B As shown, the computing storage device 140 includes a processing unit 141, a NAND memory array 142, and a non-volatile memory array 143.
[0047] Processing unit 141 is coupled to NAND memory array 142 and non-volatile memory array 143. Processing unit 141 may be a field programmable integrated circuit (FPGA) with a processor, and can access NAND memory array 142 and non-volatile memory array 143 through multiple controllers respectively.
[0048] NAND memory array 142 is used to store multiple node data blocks corresponding to multiple nodes in DiskANN. As discussed above, the node data block contains node vector data of each node (e.g., including a complete vector representing the length and amount of data), the number of neighboring nodes, and the neighboring node numbers.
[0049] Non-volatile memory array 143 is used to store multiple PQ vectors for corresponding nodes with neighboring node numbers in multiple node data blocks. In some embodiments, non-volatile memory array 143 may be a phase-change memory (PCM) array, a NOR memory array, a 3D NOR memory array, a magnetoresistive random access memory (MRAM) array, a resistive random access memory (RRAM) array, or other non-volatile memory arrays. In some embodiments, non-volatile memory array 143 includes non-volatile memory with access speeds faster than NAND memory. Since non-volatile memory, such as PCM, has a faster access speed than NAND memory, by storing PQ vectors in non-volatile memory, the PQ vectors in the non-volatile memory can be quickly accessed directly during DiskANN searches or when the system is restarted, for example, through processing unit 141, without the need for additional DRAM to access the PQ vectors, thus reducing DRAM requirements. Furthermore, since non-volatile memory such as PCM is less expensive than DRAM, hardware costs can be reduced simultaneously.
[0050] Accordingly, the processing unit 141 can perform a disk approximate nearest point search on multiple node data blocks in the NAND memory array 142 and multiple product quantization vectors in the non-volatile memory array 143 according to the received search instructions (e.g. from the bus / interface 170), and output the search results (e.g. to the bus / interface 170).
[0051] At Figure 3A In the example, the graph index (e.g., a randomly generated Vamana graph) is stored directly in the non-volatile memory array 143. Conversely, in... Figure 3B In the example, the graph index (e.g., a randomly generated Vamana graph) is stored in a dynamic memory array 144 disposed in the computing storage device 140. In some embodiments, the dynamic memory array 144 may be a dynamic random-access memory (DRAM) array instead of a non-volatile memory array. In such cases, only a small amount of DRAM is used to store the generated graph index.
[0052] Specifically, when the computing storage device 140 performs a DiskANN search, the processing unit 141 can, according to the received search instruction, such as a Top-K search instruction, compare the graph index with the search conditions (e.g., query vector) in the search instruction to obtain the nearest nodes among the multiple nodes in the node data block corresponding to the graph index. Next, the processing unit 141 can, according to the corresponding neighbor node numbers of the near nodes in the node data block stored in the NAND memory array 142, obtain the PQ vectors of multiple neighbor nodes corresponding to the neighbor node numbers from the PQ vectors in the non-volatile memory array 143. Then, the processing unit 141 compares the PQ vectors of the multiple neighbor nodes to obtain the nearest node among the neighbor nodes that is closest to the search conditions. Next, the processing unit 141 can use the nearest node as a near node and repeat the above steps until the k nodes closest to the search conditions are found, which are then used as the search results of the Top-K search. k is an integer greater than or equal to one.
[0053] Figure 4A and Figure 4B Schematic diagrams illustrating different examples of a computational storage system 200 according to one or more embodiments of the present invention are shown. Figure 4A or Figure 4B The computing storage system 200 and Figure 3A or Figure 3B The difference between the computational storage device 140 and the non-volatile memory array 283 for storing PQ phasors is that the non-volatile memory array 283 is separately disposed in the non-volatile memory device 280, rather than in the computational storage device 240. The non-volatile memory device 280 is coupled to the processing unit 241 of the computational storage device 240. In some embodiments, the non-volatile memory array 283 may be a PCM array, a NOR memory array, a 3D NOR memory array, an MRAM array, or an RRAM array. Similar to Figure 3A ,At Figure 4A In the example, the graph index (e.g., a randomly generated Vamana graph) is stored directly in the non-volatile memory array 283 without setting up additional dynamic memory, such as DRAM. Conversely, similar to... Figure 3B ,At Figure 4B In the example, the graph index (e.g., a randomly generated Vamana graph) is stored in a dynamic memory array 244 disposed in the computing storage device 240. In some embodiments, the dynamic memory array 244 may be a dynamic random-access memory (DRAM) array. In such cases, only a small amount of DRAM is used to store the generated graph index.
[0054] Similar to Figure 3A or Figure 3B The storage device 140 for computation, Figure 4A or Figure 4B The processing unit 241 of the computing storage device 240 in the computing storage system 200 can perform a disk approximate nearest-point search on multiple node data blocks in the NAND memory array 242 and multiple PQ vectors in the volatile memory array 283 of the non-volatile memory device 280 according to a received search instruction (e.g., from the bus / interface 170), and output the search results (e.g., to the bus / interface 170). Figure 4A or Figure 4B The DiskANN search is performed in the storage system 200, similar to the above reference. Figure 3A and Figure 3B The explanation will not be repeated here.
[0055] Figure 5 Illustrations of a memory device (e.g., according to one or more embodiments of the present invention) Figure 1 , Figure 2 , Figure 3A or Figure 3B The storage device 140 for computation, or Figure 4A or Figure 4B The flowchart shows the program 500 that executes the DiskANN function using the storage system 200. In step S510, for example, via... Figure 1 The computing system 100 stores multiple node data blocks generated by DiskANN from a database in a NAND memory array (e.g., ...) of the memory device. Figure 3A or Figure 3B NAND memory array 142, or Figure 4A or Figure 4B NAND memory array 242).
[0056] In step S520, for example by Figure 1 The computing system 100 stores multiple PQ vectors corresponding to multiple nodes in multiple node data blocks in a non-volatile memory array (e.g., ...) memory device. Figure 3A or Figure 3B The non-volatile memory array 143, or Figure 4A or Figure 4B (Non-volatile memory array 283).
[0057] In step S530, the processing unit of the memory device (e.g., Figure 3A or Figure 3B The processing unit 141, or Figure 4A and Figure 4BThe processing unit 241 performs DiskANN search on multiple node data blocks in the NAND memory array and multiple PQ vectors in the non-volatile memory array according to the received search instructions.
[0058] In step S540, the search results are output through the processing unit of the memory device.
[0059] In some specific settings, each of the multiple node data blocks includes the node vector data of each of the multiple nodes, the number of neighboring nodes, and the number of the multiple neighboring nodes.
[0060] In certain configurations, the processing unit performs a DiskANN search by: comparing the graph indexes of multiple node data blocks with the search criteria in the search instruction to identify the nearest nodes among the nodes corresponding to the graph indexes in the multiple node data blocks; obtaining multiple corresponding PQ vectors for the multiple neighboring nodes corresponding to the multiple neighboring node numbers from multiple PQ vectors in the non-volatile memory array based on the corresponding neighboring node numbers of the nearest nodes in the multiple node data blocks in the NAND memory array; comparing the multiple corresponding PQ vectors of the multiple neighboring nodes to identify the nearest node among the multiple neighboring nodes that is closest to the search criteria; and repeating the above steps with the nearest node as the nearest node until the k nodes closest to the search criteria are found. The search results include k nodes as the first k search results. k is an integer greater than or equal to one.
[0061] In some specific setups, the graphics index is stored in a non-volatile memory array. The non-volatile memory array can be a PCM array, a NOR memory array, a 3D NOR memory array, an MRAM array, or an RRAM array.
[0062] In some specific settings, the graphics index is stored in a dynamic memory array of a memory device, which is coupled to the processing unit.
[0063] In certain configurations, non-volatile memory arrays are PCM arrays, NOR memory arrays, 3D NOR memory arrays, MRAM arrays, or RRAM arrays. Dynamic memory arrays are DRAM arrays.
[0064] The example memory technologies described herein, applicable to various memory arrays of computing storage devices or systems, such as computing SSDs, include floating gate, discrete gate, SONOS, floating dot memory, DRAM, DRAM-like (e.g., 2T0C), FeFET, and any memory technology compatible with word line and bit line searches. Example SONOS memory technology (sometimes called charge-recovery memory) uses an insulating layer (e.g., silicon nitride) with traps to capture and retain charge emitted from the channel. Example floating-point memory technology conceptually replaces the floating gate with floating silicon nanodots, or embedded floating silicon nanodots, within a polysilicon gate. Example 2T0C memory technology uses the parasitic capacitance of the read transistor to store charge instead of an external storage capacitor. Example FeFET memory technology uses permanent electric field polarization of a ferroelectric material embedded between the gate and source-gate conduction regions to store information. Example memory structures applicable to various memory arrays of computing storage devices, such as computing SSDs, include two-dimensional structures (e.g., 2D flash memory structures) and three-dimensional structures (e.g., 3D flash memory structures). Example array architectures of various memory arrays applicable to computing storage devices, such as computing SSDs, include NOR / OR type array architectures and AND / NAND type array architectures.
[0065] It is understood that although the present invention has been disclosed above in terms of implementations, variations, embodiments, and examples, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A computing storage device for performing a disk approximate nearest neighbor (DiskANN) search, comprising: A NAND memory array is used to store multiple node chunks that correspond to multiple nodes in the nearest point of the disk. A non-volatile memory array for storing multiple product quantization (PQ) vectors for these nodes in the corresponding node data blocks; and A processing unit is coupled to the NAND memory array and the non-volatile memory. The processing unit is used for: Based on a received search instruction, perform a disk approximate nearest point search on these node data blocks in the NAND memory array and these product quantization vectors in the non-volatile memory array, and output a search result.
2. The storage device for computation according to claim 1, wherein each of these node data blocks includes a node vector data of each of these nodes, a number of neighboring nodes, and a plurality of neighboring node numbers.
3. The computing storage device according to claim 2, wherein when the processing unit receives the search instruction, performing a disk approximate nearest point search includes: By comparing a graph index corresponding to these node data blocks with a search condition in the search instruction, a similar node among the nodes in these node data blocks that correspond to the graph index is obtained. Based on the corresponding neighboring node numbers of the nearby nodes in the node data blocks stored in the NAND memory array, the corresponding product quantization vectors of the neighboring nodes are derived from the product quantization vectors in the non-volatile memory array. Compare the corresponding product quantization vectors of these neighboring nodes to find the nearest node that is closest to the search condition among these neighboring nodes; as well as The nearest node is used as the nearest neighbor node, and the above steps are repeated until the k nodes that are closest to the search criteria are found. The search results include these k nodes as a Top-K search result, where k is an integer greater than or equal to one.
4. The storage device for computation according to claim 3, wherein the graphics index is stored in the non-volatile memory array. The non-volatile memory array can be a phase change memory (PCM) array, a NOR memory array, a 3D NOR memory array, a magnetoresistive random access memory (MRAM) array, or a resistive random access memory (RRAM) array.
5. The computing storage device according to claim 3 further includes a dynamic memory array coupled to the processing unit and for storing the graphics index.
6. The computing storage device according to claim 5, wherein the non-volatile memory array is a phase-change memory array, a NOR memory array, a 3D NOR memory array, a magnetoresistive random access memory array, or a resistive memory array. This dynamic memory array is a dynamic random-access memory (DRAM) array.
7. A computational storage system for performing DiskANN searches, comprising: A computational storage device, comprising: A NAND memory array is used to store multiple node data blocks corresponding to multiple nodes in the DiskANN; and A processing unit coupled to the NAND memory array; and A non-volatile memory device includes a non-volatile memory array for storing multiple PQ vectors corresponding to these nodes in data blocks of these nodes. The non-volatile memory device is coupled to the processing unit, and the processing unit is used for: Based on a received search instruction, a DiskANN search is performed on the node data blocks in the NAND memory array of the computing storage device and the PQ vectors in the non-volatile memory array of the non-volatile memory device, and a search result is output.
8. The storage system for computation according to claim 7, wherein each of these node data blocks includes a node vector data of each of these nodes, a number of neighboring nodes, and a plurality of neighboring node numbers.
9. The storage system for computation according to claim 8, wherein when the processing unit receives the search instruction, performing a DiskANN search includes: By comparing a graph index corresponding to these node data blocks with a search condition in the search instruction, a similar node among the nodes in these node data blocks that correspond to the graph index is obtained. Based on the corresponding neighboring node numbers of the nearby nodes in the data blocks of these nodes in the NAND memory array, the corresponding PQ vectors of the multiple neighboring nodes with the corresponding neighboring node numbers are derived from the PQ vectors in the non-volatile memory array. Compare the corresponding PQ vectors of these neighboring nodes to determine the nearest node among them that best matches the search condition; and The nearest node is taken as the nearest node and the above steps are repeated until the k nodes that are closest to the search condition are found. The search results include the k nodes as the first k search results, where k is an integer greater than or equal to one.
10. The computational storage system of claim 9, wherein the graphics index is stored in the non-volatile memory array. The non-volatile memory array can be a PCM array, a NOR memory array, a 3D NOR memory array, an MRAM array, or an RRAM array.
11. The computing storage system of claim 9, wherein the computing storage device further comprises a dynamic memory array coupled to the processing unit and for storing the graphics index.
12. The computing storage device according to claim 11, wherein the non-volatile memory array is a PCM array, a NOR memory array, a 3D NOR memory array, an MRAM array, or an RRAM array. The dynamic memory array is a DRAM array.
13. A method of operating a memory device, comprising: A NAND memory array in the memory device stores multiple node data blocks generated by a DiskANN based on a database from multiple nodes; A non-volatile memory array in a memory device stores multiple PQ vectors corresponding to these nodes in the data blocks of these nodes. as well as A processing unit of the memory device performs a DiskANN search on the node data blocks in the NAND memory array and the PQ vectors in the non-volatile memory array according to a received search instruction, and outputs a search result.
14. The method of operation according to claim 13, wherein each of these node data blocks includes a node vector data of each of these nodes, a number of neighboring nodes, and a plurality of neighboring node numbers.
15. The method of operation according to claim 14, wherein the processing unit performs a DiskANN search comprising: By comparing a graph index corresponding to these node data blocks with a search condition in the search instruction, a similar node among the nodes in these node data blocks that correspond to the graph index is obtained. Based on the corresponding neighboring node numbers of the nearby nodes in the data blocks of these nodes in the NAND memory array, the corresponding PQ vectors of the multiple neighboring nodes with the corresponding neighboring node numbers are derived from the PQ vectors in the non-volatile memory array. Compare the corresponding PQ vectors of these neighboring nodes to determine the nearest node among them that best matches the search condition; and The nearest node is taken as the nearest node and the above steps are repeated until the k nodes that are closest to the search condition are found. The search results include the k nodes as the first k search results, where k is an integer greater than or equal to one.
16. The method of operation according to claim 15, wherein the graphic index is stored in the non-volatile memory array. The non-volatile memory array can be a PCM array, a NOR memory array, a 3D NOR memory array, an MRAM array, or an RRAM array.
17. The method of operation according to claim 15, wherein the graphic index is stored in a dynamic memory array of the memory device, the dynamic memory array being coupled to the processing unit.
18. The operating method of claim 17, wherein the non-volatile memory array is a PCM array, a NOR memory array, a 3D NOR memory array, an MRAM array, or an RRAM array. The dynamic memory array is a DRAM array.