A reference counting method and related apparatus
By establishing multiple counters corresponding to CPU cores in the data blocks of the storage space, the cache line invalidation problem caused by the reference counting method is solved, the speed of Pin/Unpin operations is improved, and system performance is enhanced.
CN122132153APending Publication Date: 2026-06-02HUAWEI TECH CO LTD
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Patent Information
- Application Number
- CN202411750962.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-30
- Publication Date
- 2026-06-02
AI Technical Summary
Technical Problem
In a multi-core CPU environment, the frequent cache line invalidation and synchronization overhead caused by the reference counting method make Pin/Unpin operations a performance bottleneck.
Method used
Multiple counters corresponding to CPU cores are established in the data blocks of the storage space. Each reference count corresponds to a set of counters to reduce the number of cache line misses. Pin/Unpin operations are performed through multiple counters.
Benefits of technology
This effectively reduces the number of cache line invalidations caused by reference counting operations, improves the overall performance of the system, and avoids the decrease in throughput caused by frequent loading of memory data.
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Abstract
This application discloses a reference counting method and related apparatus. The method includes: acquiring a free target data block in storage space; establishing multiple counters in the target data block, the number of counters corresponding to the grouping of multiple cores of a central processing unit (CPU); determining the target core corresponding to the pin / unpin operation in response to a pin / unpin operation on the target data block, wherein the target core belongs to multiple cores; determining the corresponding target counter based on the target core, wherein the target counter belongs to multiple counters; and performing reference counting corresponding to the pin / unpin operation using the target counter. This method can be used to improve the speed of pin / unpin on multi-core CPUs, thereby improving the overall system performance.
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