A method for address allocation of an intelligent pdu internal module
By dynamically allocating addresses based on the duty cycle difference of PWM signals, the problem of complex and error-prone address allocation within intelligent PDU modules is solved, enabling automated and flexible address management and device expansion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI XINGYUANTONG ELECTRIC CO LTD
- Filing Date
- 2026-03-03
- Publication Date
- 2026-06-02
AI Technical Summary
The existing intelligent PDU internal modules require manual setting of fixed addresses during address allocation, which leads to complex and error-prone design and makes dynamic adjustment impossible.
Addresses are dynamically allocated by using the duty cycle difference of PWM signals. The main control module generates PWM signals with different duty cycles, and the sub-modules capture and set their own addresses to achieve automatic address allocation and detection.
It enables dynamic address allocation, reduces manual intervention, avoids hardware setting errors, supports rapid adjustment and remote management when devices change, and ensures normal communication.
Smart Images
Figure CN122132325A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of address allocation technology for internal modules of intelligent PDUs, and in particular to an address allocation method for internal modules of intelligent PDUs. Background Technology
[0002] A typical intelligent PDU contains two or more sub-modules that communicate with the main control module via a RS-485 bus. The main control module monitors and controls the communication of each sub-module through the RS-485 bus, including information from the power module, relay control, and sensor data collection. To enable the main control module to correctly communicate with each module by recognizing its RS-485 address, it needs to dynamically and flexibly assign RS-485 addresses to each sub-module. Without dynamic address assignment, fixed addresses must be set on the modules using DIP switches, and the main control module code must accurately correspond to each module's address, making the design extremely complex. Furthermore, operators on the production line may accidentally use the wrong DIP switches.
[0003] To enable the main control module to dynamically allocate addresses to each sub-module each time, and to ensure that no duplicate addresses are used on different modules on the 485 bus, this invention utilizes PWM duty cycle allocation to assign module addresses. Its core principle is to distinguish different devices based on the difference in the duty cycle of the PWM signal. Summary of the Invention
[0004] One of the objectives of this application is to address the problem that, in the current market, when PDU internal modules are copied and allocated, fixed addresses need to be set on the modules using DIP switches, and the addresses of each module need to be matched when writing the main control module code, which makes the design very complex. This application provides a method for address allocation of internal modules in a smart PDU.
[0005] To achieve the above objectives, the technical solution adopted in this application is: an address allocation method for an internal module of an intelligent PDU, comprising the following steps: Step 1: The main control module inside the PDU generates a fixed-value PWM signal with a duty cycle of 1 through a timer; Step 2: Each submodule within the PDU captures the PWM signal 1 generated by the main control module, triggering each submodule to enter configuration mode; Step 3: The main control module inside the PDU generates PWM signals with different duty cycles 2 through a timer and sends them to submodule 1; Step 4: After receiving and capturing the duty cycle PWM signal 2, submodule 1 uses the duty cycle value of PWM signal 2 as its own unique address; Step 5: After setting the address, submodule 1 generates PWM signals with different duty cycles 3 through a timer and sends them to submodule 2; Step 6: After receiving and capturing the duty cycle PWM signal 3, submodule 2 uses the duty cycle value of the PWM signal 3 as its own unique address; Step 7: If there is a submodule 3, repeat steps 5 and 6, adjusting the PWM duty cycle value each time to complete the address allocation for all submodules. Each time a new PWM signal is generated, the PWM duty cycle value will increase or decrease by 5% or 10% depending on the number of submodules.
[0006] Preferably, the modules inside the intelligent PDU include a main control module and two or more sub-modules, wherein the main control module is connected to two or more sub-modules respectively via a 485 bus.
[0007] Preferably, the 485 bus interface uses differential signal transmission to enhance anti-interference capability, and a 120-ohm resistor can be added to the bus termination, allowing for a maximum distance of up to 1200 meters, which fully meets the requirements of the entire 485 bus length within the PDU. The 485 baud rate is set to 9600bps or higher to ensure fast command transmission.
[0008] Preferably, in steps one, three, and five, the duty cycle values generated by the main control module and sub-module through the timer are typically in the range of 5%-95% (corresponding to addresses 1-255), with an accuracy of 1% to meet the address differentiation requirements. At the same time, the duty cycle values of PWM signal 1 in step one, PWM signal 2 in step three, and PWM signal 3 in step five are also different.
[0009] Preferably, the module in step four needs to integrate PWM capture function to parse the duty cycle in real time and convert it into an address value.
[0010] Compared with existing technologies, the advantages of this application are as follows: It uses the duty cycle of PWM for dynamic address allocation, which can be adjusted in real time. The intelligent PDU can dynamically allocate addresses according to actual needs. For example, when equipment in the computer room is added, removed, or adjusted, addresses can be quickly reassigned without manual changes to hardware settings. In contrast, hardware DIP switches have fixed addresses, requiring re-switching when devices change, which is error-prone and cumbersome. Furthermore, the PWM duty cycle can be remotely monitored and managed via network, allowing for real-time viewing and adjustment of address allocation. When new devices are added, the intelligent PDU can automatically allocate addresses without reconfiguring existing hardware DIP switches, facilitating system expansion. A conflict resolution mechanism is set up. After the PDU's main control module and each submodule perform a 485 handshake protocol, if the submodule does not respond, the address will be reassigned. The mechanism automatically detects and corrects address allocation errors to ensure normal device communication. Attached Figure Description
[0011] Figure 1 This is a diagram of the 485 bus of the present invention.
[0012] Figure 2 This is a flowchart of the PWM allocation process of the present invention. Detailed Implementation
[0013] The present application will be further described below with reference to specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.
[0014] In the description of this application, it should be noted that the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., which indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of this application.
[0015] It should be noted that the terms "first," "second," etc., in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0016] One preferred embodiment of this application, such as Figures 1 to 2 As shown, an address allocation method for an internal module of a smart PDU includes the following steps: Step 1: The main control module inside the PDU generates a fixed-value PWM signal with a duty cycle of 1 through a timer; Step 2: Each submodule within the PDU captures the PWM signal 1 generated by the main control module, triggering each submodule to enter configuration mode; Step 3: The main control module inside the PDU generates PWM signals with different duty cycles 2 through a timer and sends them to submodule 1; Step 4: After receiving and capturing the duty cycle PWM signal 2, submodule 1 uses the duty cycle value of PWM signal 2 as its own unique address; Step 5: After setting the address, submodule 1 generates PWM signals with different duty cycles 3 through a timer and sends them to submodule 2; Step 6: After receiving and capturing the duty cycle PWM signal 3, submodule 2 uses the duty cycle value of the PWM signal 3 as its own unique address; Step 7: After setting the address, submodule 2 generates PWM signals 4 with different duty cycles through a timer and sends them to submodule 3; Step 8: After receiving and capturing the duty cycle PWM signal 4, submodule 3 uses the duty cycle value of PWM signal 4 as its own unique address.
[0017] The intelligent PDU includes a main control module and two or more sub-modules, wherein the main control module is connected to two or more sub-modules via a 485 bus.
[0018] The 485 bus interface employs differential signal transmission to enhance anti-interference capability. A 120-ohm resistor can be added to the bus termination, allowing for a maximum distance of 1200 meters, which is sufficient for the entire 485 bus length within the PDU. The 485 baud rate is set to 9600bps or higher to ensure fast command transmission.
[0019] In steps one, three, five, and seven, the duty cycle values generated by the main module and sub-modules through the timer are typically in the range of 5%-95% (corresponding to addresses 1-255), with an accuracy of 1% to meet the address differentiation requirements. Furthermore, the duty cycle value of the PWM signal generated in each step is different, and the duty cycle value will increase or decrease sequentially according to the number of sub-modules.
[0020] In step four, the module needs to integrate PWM capture functionality to parse the duty cycle in real time and convert it into an address value. The above describes the basic principles, main features, and advantages of this application.
[0021] In summary: When dynamically allocating addresses using the PWM duty cycle, automatic detection can also be performed. When the main control module sends a 40% duty cycle PWM signal to sub-module 1, the address of sub-module 1 is defined as 4. If there is no feedback when the main control module communicates with sub-module 1 via the 485 handshake protocol, it can be repaired in time. Secondly, when a new device needs to be added, simply control the main control module to send another PWM signal with a different duty cycle, 2, to the new device. The new device will automatically capture the PWM signal 2 and define it as the new address, without needing to manually change the hardware settings.
[0022] Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this application. Various changes and modifications can be made to this application without departing from the spirit and scope thereof, and all such changes and modifications fall within the scope of this application as claimed. The scope of protection claimed by this application is defined by the appended claims and their equivalents.
Claims
1. A method for address allocation of internal modules of an intelligent PDU, characterized in that, Includes the following steps: Step 1: The main control module inside the PDU generates a fixed-value PWM signal with a duty cycle of 1 through a timer; Step 2: Each submodule within the PDU captures the PWM signal 1 generated by the main control module, triggering each submodule to enter configuration mode; Step 3: The main control module inside the PDU generates PWM signals with different duty cycles 2 through a timer and sends them to submodule 1; Step 4: After receiving and capturing the duty cycle PWM signal 2, submodule 1 uses the duty cycle value of PWM signal 2 as its own unique address; Step 5: After setting the address, submodule 1 generates PWM signals with different duty cycles 3 through a timer and sends them to submodule 2; Step 6: After receiving and capturing the duty cycle PWM signal 3, submodule 2 uses the duty cycle value of the PWM signal 3 as its own unique address; Step 7: If there is a submodule 3, repeat steps 5 and 6, adjusting the PWM duty cycle value each time to complete the address allocation for all submodules. Each time a new PWM signal is generated, the PWM duty cycle value will increase or decrease by 5% or 10% depending on the number of submodules.
2. The address allocation method for an internal module of a smart PDU as described in claim 1, characterized in that: The intelligent PDU includes a main control module and two or more sub-modules, wherein the main control module is connected to two or more sub-modules via a 485 bus.
3. The address allocation method for an internal module of a smart PDU as described in claim 2, characterized in that: The 485 bus interface uses differential signal transmission to enhance anti-interference capability. A 120-ohm resistor can be added to the bus terminal, and the maximum distance can reach 1200 meters, which can fully meet the entire length of the 485 bus inside the PDU. The 485 baud rate is set to above 9600bps to ensure fast command transmission.
4. The address allocation method for an internal module of a smart PDU as described in claim 3, characterized in that: In steps one, three, and five, the duty cycle values generated by the control module through the timer are typically in the range of 5%-95% (corresponding to addresses 1-255), with an accuracy of 1% to meet the address differentiation requirements. At the same time, the duty cycle values of PWM signal 1 in step one, PWM signal 2 in step three, and PWM signal 3 in step five are also different.
5. The address allocation method for an internal module of a smart PDU as described in claim 4, characterized in that: In step four, the module needs to integrate PWM capture functionality to parse the duty cycle in real time and convert it into an address value.