A PCB debugging interface automatic identification method and system based on multi-feature fusion

Abstract

This invention discloses an automatic identification method for PCB debug interfaces based on multi-feature fusion, comprising: establishing electrical connections between the debug interface pins of the PCB under test and a parameter measurement unit and a programmable protocol generator respectively through a multiplexed switch matrix; performing static electrical feature measurements on the debug interface pins using the parameter measurement unit to obtain electrical feature data; comparing and matching the electrical feature data with a pre-stored interface feature database to generate at least one candidate interface type hypothesis; automatically configuring a corresponding protocol excitation signal for each generated candidate interface type hypothesis, and applying the protocol excitation signal to the corresponding candidate pin through the multiplexed switch matrix; monitoring the response signal of the candidate pin under excitation, and confirming or excluding the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification of the current candidate interface type; and outputting the finally confirmed interface type and its corresponding pin definition.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement and testing technology, specifically to an automatic identification method and system for PCB debugging interfaces based on multi-feature fusion. Background Technology

[0002] While existing technologies have achieved automated identification of PCB debugging interfaces based on multi-feature fusion to a certain extent, they still have several systemic defects, making it difficult to achieve efficient, accurate and scalable identification in practical applications.

[0003] The core limitation of current methods lies in their inability to effectively handle different interface types with high static feature similarity, and their reliance on the completeness and accuracy of pre-stored feature databases. In engineering practice, debugging interfaces from different manufacturers (such as UART, SWD, JTAG, etc.) often have highly overlapping static electrical characteristics (e.g., multiple interfaces have specific pull-up / pull-down resistor ranges). Matching only static features easily generates a large number of false positive candidate interface type assumptions, triggering unnecessary protocol probing and significantly reducing recognition efficiency. Furthermore, if the pre-stored feature database does not cover specific new or non-standard interfaces, the entire recognition process will fail to generate valid hypotheses, leading to recognition failure. Existing methods have not effectively resolved the inherent contradiction between static feature similarity and dynamic protocol probing efficiency. Their feature fusion mechanism is essentially a simple, serial comparison, lacking the ability to collaboratively optimize the ambiguity of static features and the cost of protocol probing, making it difficult to achieve rapid recognition in complex and ever-changing real-world scenarios.

[0004] Therefore, existing technologies urgently need an interface identification method that can deeply integrate static electrical characteristics and dynamic protocol responses, and has the ability to learn and update autonomously, in order to fundamentally solve the problems of mismatch of highly similar interfaces and failure to identify unknown interfaces. Summary of the Invention

[0005] To overcome the above-mentioned technical defects, the present invention provides a method and system for automatic identification of PCB debugging interfaces based on multi-feature fusion.

[0006] To solve the above problems, the present invention is implemented according to the following technical solution:

[0007] In a first aspect, the present invention provides an automatic identification method for PCB debugging interfaces based on multi-feature fusion, comprising the following steps:

[0008] S100: The debug interface pins of the PCB under test are electrically connected to the parameter measurement unit and the programmable protocol generator respectively through a multiplexed switch matrix;

[0009] S200: The parameter measurement unit is used to perform static electrical characteristic measurement on the pin of the debugging interface to obtain electrical characteristic data; wherein, the electrical characteristics include at least two of the following: DC resistance to ground, resistance to power supply, pin capacitance to ground, diode characteristics, and power-on transient voltage;

[0010] S300: Compare and match the electrical feature data with the pre-stored interface feature database to generate at least one candidate interface type hypothesis;

[0011] S400: For each generated candidate interface type assumption, automatically configure the corresponding protocol excitation signal, and apply the protocol excitation signal to the corresponding candidate pin through the multiplexing switch matrix;

[0012] S500: Monitor the response signal of the candidate pin under excitation, and confirm or exclude the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification of the current candidate interface type;

[0013] S600: Outputs the final confirmed interface type and its corresponding pin definitions.

[0014] In conjunction with the first aspect, the present invention provides a first specific implementation of the first aspect, specifically, the step of using the parameter measurement unit to perform static electrical characteristic measurement on the debug interface pins to obtain electrical characteristic data includes the following steps:

[0015] Identify the power and ground pins, measure and determine the pins among all pins that exhibit extremely low resistance to the power and ground networks of the PCB under test;

[0016] Plot a resistance spectrum and, for the selected signal pins, measure the DC resistance of each signal pin to the identified ground pin and to the identified power pin.

[0017] Measure pin capacitance, specifically the parasitic capacitance value of each signal pin to the identified ground pin;

[0018] Perform diode characteristic tests to check whether there is a voltage-current relationship between each signal pin and the identified power and ground pins that conforms to the forward conduction characteristics of the protection diode;

[0019] Monitor the transient voltage upon power-on. During the simulated power-on or reset process of the PCB under test, monitor and record the voltage change waveforms of each signal pin over time to capture startup information or initial level status.

[0020] In conjunction with the first aspect, the present invention provides a second specific implementation of the first aspect. Specifically, the step of comparing and matching the electrical feature data with a pre-stored interface feature database to generate at least one candidate interface type hypothesis includes the following steps:

[0021] The electrical characteristic data is organized into a standardized feature vector for each pin set to be analyzed. The feature vector contains at least electrical parameters that characterize the overall pin set and / or the relationships between internal pins.

[0022] The feature vector is matched with multiple feature templates pre-stored in the interface feature database, corresponding to different known debugging interface types, to calculate similarity; wherein, the feature template stores the electrical parameter range or distribution pattern of typical pin functions under the corresponding interface type;

[0023] Based on the similarity calculation results, interface types with similarity higher than a preset threshold are selected, and each selected interface type and its corresponding pin function allocation scheme are taken as a candidate interface type hypothesis; wherein, a confidence score based on similarity calculation is associated with each candidate interface type hypothesis.

[0024] The generated candidate interface type hypothesis list is sorted according to the confidence score.

[0025] In conjunction with the first aspect, the present invention provides a third specific implementation of the first aspect. Specifically, for each generated candidate interface type assumption, automatically configuring a corresponding protocol excitation signal and applying the excitation signal to the corresponding candidate pin through the multiplexing switch matrix specifically includes:

[0026] Based on the current candidate interface type assumption to be verified, the functional signal channels under the standard definition of the interface type are parsed out;

[0027] Based on the pre-allocated pin function definitions in the candidate interface type assumption, each functional signal channel is logically mapped to a specific physical pin number in the pin group under test.

[0028] Based on the candidate interface type, the programmable protocol generator is controlled to configure its internal state machine and timing parameters to generate an excitation signal sequence that conforms to the standard protocol specification of that interface type; the excitation signal sequence includes at least a specific timing sequence for interface initialization or a standard instruction stream for reading device identification information;

[0029] Control the multiplexed switch matrix to perform dynamic switching: connect each output channel of the programmable protocol generator to the mapped target pin, and connect the pin that is assumed to be the signal input to the input monitoring channel of the programmable protocol generator or the parameter measurement unit.

[0030] In conjunction with the first aspect, the present invention provides a fourth specific implementation of the first aspect. Specifically, the step of monitoring the response signal of the candidate pin under excitation, and confirming or excluding the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification of the current candidate interface type, specifically includes the following steps:

[0031] During the application of the protocol excitation signal, the response signal on the pin mapped to the signal input function is acquired in real time through the input channel of the parameter measurement unit or the programmable protocol generator.

[0032] According to the protocol specification corresponding to the currently verified interface type, the response signal is decoded to attempt to extract valid data or identify a specific protocol state;

[0033] The decoded signal content, timing features, or state transition sequence are compared and analyzed with the expected standard response pattern or state machine of the interface type stored in the interface feature database.

[0034] If the response signal is successfully decoded, and the decoded content, timing characteristics, and state transition sequence fully meet the expected specifications and satisfy the preset validity verification conditions, then the assumption of the current candidate interface type is confirmed, and its pin definition is recorded.

[0035] If the response signal cannot be successfully decoded, or the decoding result fundamentally conflicts with the expected specification, or no valid response is observed within the preset timeout period, then the current candidate interface type hypothesis is excluded.

[0036] In conjunction with the first aspect, the present invention provides a fifth specific implementation of the first aspect, specifically, the final confirmed interface type of the output and its corresponding pin definition specifically includes the following steps:

[0037] If only one candidate interface type hypothesis is confirmed by step S500, the interface type and pin definition of the candidate interface type hypothesis will be output as the final identification result.

[0038] If multiple candidate interface type hypotheses are confirmed by step S500, arbitration is performed based on the confidence scores corresponding to each candidate interface type hypothesis, and the interface type and pin definition of the candidate interface type hypothesis with the highest confidence score are output as the final identification result.

[0039] If step S500 fails to confirm any candidate interface type hypothesis, it outputs a result indicating identification failure, along with key electrical characteristic data or protocol response anomaly information that caused the identification failure.

[0040] In conjunction with the first aspect, the present invention provides a sixth specific implementation of the first aspect, specifically, after outputting the final recognition result, automatically generating a technical report containing the recognition process, and visually displaying it on a human-computer interaction interface;

[0041] The technical report shall include at least the type of the confirmed interface, the complete pin definitions, a comparison of key electrical characteristic data used to make the judgment, and a successful protocol interaction verification log.

[0042] Secondly, the present invention also provides an automatic identification system for PCB debugging interfaces based on multi-feature fusion, including: a multiplexed switch matrix, a parameter measurement unit, a programmable protocol generator, an interface feature database, and a central control unit;

[0043] The multiplexed switch matrix is ​​used to establish electrical connections between the debug interface pins of the PCB under test and the parameter measurement unit and the programmable protocol generator, respectively.

[0044] The parameter measurement unit is used to perform static electrical characteristic measurements on the debugging interface pins to obtain electrical characteristic data; wherein, the electrical characteristic data includes at least two of the following: DC resistance to ground, resistance to power supply, pin capacitance to ground, diode characteristics, and power-on transient voltage;

[0045] The interface feature database pre-stores standard electrical feature data and corresponding protocol specifications for different interface types;

[0046] The programmable protocol generator is used to generate a protocol excitation signal corresponding to a specific interface type assumption based on the received configuration instructions.

[0047] The central control unit is connected to the multiplexing switch matrix, the parameter measurement unit, the programmable protocol generator, and the interface feature database, respectively; the central control unit is configured to execute:

[0048] Control the multiplexer switch matrix to establish corresponding electrical connections;

[0049] Acquire the electrical characteristic data measured by the parameter measurement unit;

[0050] The electrical feature data is compared and matched with the standard electrical feature data in the interface feature database to generate at least one candidate interface type hypothesis;

[0051] For each candidate interface type assumption generated, a corresponding configuration instruction is sent to the programmable protocol generator, and the multiplexing switch matrix is ​​controlled to apply the generated protocol excitation signal to the corresponding candidate pin.

[0052] Monitor the response signal of the candidate pin under excitation, and confirm or exclude the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification corresponding to the current candidate interface type in the interface feature database;

[0053] The output will finally confirm the interface type and its corresponding pin definitions.

[0054] Thirdly, the present invention provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform an automatic identification method for PCB debugging interfaces.

[0055] Fourthly, the present invention provides a computer-readable storage medium storing a computer program for causing a processor to execute an automatic identification method for PCB debugging interfaces.

[0056] Compared with the prior art, the beneficial effects of the present invention are:

[0057] The entire identification process is completed automatically by the system, eliminating the need for operators to have extensive hardware debugging experience or repeatedly operate different instruments manually. The system automatically switches connections via a switch matrix, sequentially completing electrical measurements, feature comparisons, and protocol probing, reducing the manual investigation work that previously took hours to just minutes.

[0058] The system performs objective comparisons based on a pre-stored interface feature database, avoiding the subjectivity and arbitrariness inherent in manual interpretation of electrical parameters. Simultaneously, a closed-loop confirmation mechanism, employing both "static feature matching" and "dynamic protocol verification," effectively mitigates the risk of misjudgment based on a single feature.

[0059] The system applies a controllable excitation signal through a programmable protocol generator and can monitor pin responses in real time. Compared to the risk of equipment damage due to incorrect connections or improper signal parameters during manual probing, this method can perform automated verification within safe voltage and protocol specifications. If an abnormal response (such as overcurrent or incorrect response) is detected during the test, it can be stopped immediately, thus effectively protecting the safety of the PCB board under test and its chips. Attached Figure Description

[0060] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0061] Figure 1 This is a flowchart of an automatic identification method for PCB debugging interfaces based on multi-feature fusion according to the present invention.

[0062] Figure 2 This is a flowchart of an automatic identification system for PCB debugging interfaces based on multi-feature fusion, according to the present invention.

[0063] Figure 3 This is a block diagram of an electronic device used to implement embodiments of the present invention.

[0064] In the picture:

[0065] 100 - Electronic device, 101 - Computing unit, 102 - ROM, 103 - RAM, 104 - Bus, 105 - I / O interface, 106 - Input unit, 107 - Output unit, 108 - Storage unit, 109 - Communication unit. Detailed Implementation

[0066] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0067] like Figures 1-3 As shown, this invention provides an automatic identification method and system for PCB debugging interfaces based on multi-feature fusion.

[0068] Example 1

[0069] like Figure 1 As shown, an automatic identification method for PCB debug interfaces based on multi-feature fusion includes the following steps: establishing electrical connections between the debug interface pins of the PCB under test and a parameter measurement unit and a programmable protocol generator respectively through a multiplexed switch matrix; performing static electrical characteristic measurements on the debug interface pins using the parameter measurement unit to obtain electrical characteristic data; wherein, the electrical characteristic data includes at least two of the following: DC resistance to ground, resistance to power supply, pin capacitance to ground, diode characteristics, and power-on transient voltage; comparing and matching the electrical characteristic data with a pre-stored interface characteristic database to generate at least one candidate interface type hypothesis; automatically configuring a corresponding protocol excitation signal for each generated candidate interface type hypothesis, and applying the protocol excitation signal to the corresponding candidate pin through the multiplexed switch matrix;

[0070] Monitor the response signal of the candidate pin under excitation, and confirm or exclude the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification of the current candidate interface type; output the finally confirmed interface type and its corresponding pin definition.

[0071] Specifically, this invention effectively overcomes the shortcomings of single-feature identification methods, which are prone to misjudgment, by combining a "static electrical feature matching" and "protocol behavior verification" identification mechanism. Static electrical feature comparison provides preliminary hypotheses about candidate interface types, and final confirmation is then performed from the functional and communication logic levels, reducing the risk of manual intervention and misjudgment. This method eliminates the need for engineers to manually measure, consult documentation, or engage in repeated trial and error from pin connection to result output. The system can quickly complete feature measurement, database comparison, and protocol verification processes, enabling the identification and definition of unknown debugging interfaces in a short time, thus shortening the preparation time for product debugging, reverse engineering, or troubleshooting. The final output of this method includes not only a simple interface name but also complete pin definitions, judgment criteria (feature data comparison process), and verification logs.

[0072] In a preferred embodiment, S100: The debug interface pins of the PCB under test are electrically connected to the parameter measurement unit and the programmable protocol generator respectively through a multiplexed switch matrix.

[0073] Specifically, the total number of physical pins of the debug interface of the PCB under test is obtained, and the connection status of the multiplexer matrix is ​​initialized. The multiplexer matrix contains a set of relay arrays, whose common terminal is connected to the signal source / measurement channel of the parameter measurement unit and each input / output channel of the programmable protocol generator.

[0074] In a preferred embodiment, after the electrical connection is established in step S100, a safety pre-check is performed:

[0075] The safety pre-inspection specifically includes: scanning the impedance between all connected pins and the potential to reference ground using a parameter measurement unit in a low-voltage, low-current mode to identify whether there is a short circuit between pins or an abnormally high voltage.

[0076] Specifically, the specific steps for implementing safety pre-inspection are as follows:

[0077] The system configures the parameter measurement unit to a measurement mode with high input impedance, low voltage (e.g., not exceeding 0.5V), and low current (e.g., current limited to within 1mA). All measured pins are disconnected from other units via a multiplexed switch matrix.

[0078] Pin-to-pin short circuit detection: The measurement unit sequentially applies a small test voltage between any two pins under test and measures the impedance between them. If the measured impedance value is lower than a preset low impedance threshold (e.g., less than 50 ohms), the system determines that there is a low-impedance short circuit between the two pins.

[0079] Abnormal ground potential detection: Using the system's reference ground as a reference, the parameter measurement unit scans the DC voltage of each measured pin relative to ground. If the absolute value of the potential of any pin exceeds a preset safe voltage threshold (e.g., ±0.7V or as set according to the device safety specifications), the system determines that the pin is abnormal.

[0080] Power / Ground Network Conflict Verification: Verify whether there is an abnormally low impedance (direct short circuit) between the initially identified power and ground pins.

[0081] If a risk state is detected, pause and issue an alarm; if no risk state is detected, record the initial safety state of each pin and proceed to step S200.

[0082] More specifically, if any pin is short-circuited or an abnormally high voltage is detected, the system will immediately pause. An alarm will be issued through the human-machine interface, and the pin number and type of the abnormality will be displayed on the interface (e.g., "Pin2 and Pin3 short-circuited", "Pin5 detected with 3.3V voltage"). All test channels will be in a safe disconnected state.

[0083] If the system determines that the electrical connection environment is safe, it will record the initial floating or static potential of each pin. The system will then deactivate the safe mode and proceed to step S200 for static electrical characteristic measurement.

[0084] In a preferred embodiment, S200: The parameter measurement unit is used to perform static electrical characteristic measurement on the debug interface pin to obtain electrical characteristic data; wherein, the electrical characteristics include at least two of the following: DC resistance to ground, resistance to power supply, pin capacitance to ground, diode characteristics, and power-on transient voltage.

[0085] Specifically, after completing the safety pre-check and establishing a stable electrical connection, the system enters the electrostatic discharge (ESD) electrical characteristic measurement phase. Without actively sending communication protocols, the inherent electrical characteristic parameters of the debug interface pins are obtained simply by applying safe test signals.

[0086] 1. Power and ground network identification

[0087] The power (VCC / VDD) and ground (GND) pins are located from all pins to establish reference points for signal pin measurements. The system control parameter measurement unit scans the DC resistance between any two pins using a low-resistance measurement mode, such as a four-wire Kelvin connection. Since power and ground networks typically have extremely low impedance on the PCB, when the measured resistance between a pair of pins is below a preset first threshold (e.g., less than 10 ohms), it can be determined that this pair of pins belongs to the same low-impedance network. Furthermore, the system injects a known, minute test current into the identified low-impedance network and measures its voltage relative to the system reference ground, thus ultimately determining which is the power network and which is the ground network (with a voltage approximately zero), and marking the identified power and ground pins.

[0088] 2. Plot the DC resistance spectrum of the signal pins.

[0089] After labeling the power and ground pins, the remaining pins are defined as signal pins. For each signal pin, the parameter measurement unit performs the following two DC resistance measurements:

[0090] DC resistance of signal pin to ground: Measure the resistance between this pin and the identified ground pin.

[0091] Signal pin to power supply DC resistance: Measure the resistance between this pin and the identified power supply pin.

[0092] The system records these two DC resistance values ​​for all signal pins, forming the DC resistance spectrum of the interface. The DC resistance spectrum can reflect the static bias characteristics of the pins, such as the internal pull-up / pull-down resistor configuration and open-drain output structure.

[0093] 3. Measure the parasitic capacitance of the pin to ground.

[0094] The parameter measurement unit switches to capacitance measurement mode, typically employing the conventional AC small-signal method or charge-time measurement method. With the identified ground pin reference, the parasitic capacitance value (i.e., composed of the pin's own package capacitance, trace capacitance, and the equivalent capacitance of the chip's internal input circuitry) is measured sequentially for each signal pin. Different interface types and pin functions may result in different capacitance values. For example, clock pins (such as JTAG's TCK) may have slightly higher capacitance than data pins due to their strong drive capability and frequent connection to multiple devices.

[0095] 4. Perform diode characteristic test

[0096] The system detects the presence of an integrated ESD protection diode between the signal pin and power / ground. The parameter measurement unit operates in curve tracer mode, applying a scan voltage from negative to positive between the signal pin and ground (or power) while simultaneously measuring the current flowing through it. If a sudden and significant increase in current is detected at a certain forward voltage point (typically 0.3V–0.7V), it indicates the presence of a forward-conducting PN junction (diode), and this forward voltage drop (Vf) characteristic is recorded.

[0097] 5. Monitor power-on / reset transient voltage

[0098] The system simulates the power-on or reset process of the PCB under test, capturing the initial state of the signal pins. It controls an external power supply module via a multiplexed switch matrix, or utilizes a programmable voltage source within the parameter measurement unit to apply a slowly rising ramp voltage (or a step voltage) to the identified power and ground pins, simulating the power-on process. Simultaneously, the measurement unit's sampling ADC monitors and records the waveforms of voltage changes over time on all signal pins. During chip startup, certain debug interface pins (such as the BOOT pin and reset pin) will exhibit specific level change sequences; some interface data lines (such as SWD) may have specific pulses at the moment of power-on.

[0099] In a preferred embodiment, the step of using the parameter measurement unit to perform static electrical characteristic measurements on the debug interface pins to obtain electrical characteristic data specifically includes the following steps:

[0100] Step S210: Identify the power and ground pins, measure and determine the pins among all pins that exhibit extremely low resistance to the power network and ground network of the PCB under test.

[0101] Specifically, the parameter measurement unit measures the pairwise DC resistance between all pins in a low-voltage, current-limiting mode. When the resistance between any two pins is lower than a first preset threshold (e.g., less than 10Ω), the two pins are determined to belong to the same low-impedance network. A small test current is applied to the identified low-impedance network, and its potential relative to the system reference ground is measured: if the potential is close to zero volts, all pins of the network are marked as ground pins; if the potential is a stable positive value (e.g., 1.8V, 3.3V, or 5V), it is marked as a power supply pin.

[0102] Step S220: Plot a resistance spectrum and measure the DC resistance of each selected signal pin to the identified ground pin and to the identified power pin.

[0103] Specifically, after excluding the identified power and ground pins, the remaining pins are defined as signal pins. For each signal pin, the parameter measurement unit performs two DC resistance measurements:

[0104] DC resistance of signal pin to ground: Measure the resistance between this pin and the identified ground pin.

[0105] Signal pin to power supply DC resistance: Measure the resistance between this pin and the identified power supply pin.

[0106] The system records these two sets of resistance values ​​for all signal pins, forming the DC resistance spectrum of the interface. This resistance spectrum can effectively reflect the static bias characteristics of the pins, such as the internal pull-up / pull-down resistor configuration and open-drain output structure.

[0107] Step S230: Measure pin capacitance, measure the parasitic capacitance value of each signal pin to the identified ground pin.

[0108] Specifically, the parameter measurement unit switches to capacitance measurement mode, employing either the AC small-signal method or the charge-time measurement method. Using the identified ground pin as a reference, the parasitic capacitance to ground of each signal pin is measured sequentially. This value comprehensively reflects the parasitic capacitance of the pin itself and the equivalent capacitance of the chip's internal input circuitry. Pins with different functions (such as clock, data, and control) may exhibit capacitance differences.

[0109] Step S240: Perform diode characteristic test to test whether there is a voltage-current relationship between each signal pin and the identified power supply pin and ground pin that conforms to the forward conduction characteristics of the protection diode.

[0110] Specifically, the parameter measurement unit operates in semiconductor characteristic analysis mode. For each signal pin, the following tests are performed:

[0111] Apply a scanning voltage from negative to positive between the pin and the identified ground pin, while simultaneously measuring the current to generate an IV curve. Repeat the above scan between the pin and the identified power pin. Analyze the resulting IV curve. If a sharp rise in current (forward conduction characteristic) is detected in the forward voltage range (typically 0.3V to 0.8V), record the forward conduction voltage value and determine that a protection diode or clamping diode exists between the pin and the corresponding power or ground network.

[0112] Step S240: Monitor the power-on transient voltage. During the simulated power-on or reset process of the PCB under test, monitor and record the voltage change waveform of each signal pin over time to capture startup information or initial level state.

[0113] Specifically, the system applies a ramp voltage (or a fast step voltage) simulating a power-on process to the power and ground pins of the PCB under test by controlling an external controllable power supply or the programmable power supply built into the parameter measurement unit. Simultaneously, the analog-to-digital converter (ADC) of the parameter measurement unit synchronously acquires and records the complete waveforms of voltage changes over time on all signal pins. This captures specific level sequences, pulses, or steady-state initial values ​​that may appear on the debug interface pins during the chip's startup initialization phase. For example, the reset (nRST) pin of some microcontrollers or the data lines of certain debug interfaces (such as SWDIO) will exhibit easily identifiable waveforms at the moment of power-on.

[0114] In a preferred embodiment, S300: The electrical feature data is compared and matched with a pre-stored interface feature database to generate at least one candidate interface type hypothesis.

[0115] Specifically, the electrical characteristic data is transformed into one or more candidate interface type hypotheses. The system first preprocesses the electrical characteristic data. For the currently tested set of pins, the system extracts and processes the electrical characteristic data of that set of pins to generate a standardized feature vector. This feature vector typically includes, but is not limited to, the following characteristics:

[0116] Topology characteristics: total number of pins; number of identified power pins and ground pins.

[0117] Numerical characteristics: "resistance to ground", "resistance to power supply", and "capacitance to ground" for each signal pin.

[0118] Relationship characteristics: maximum, minimum and distribution statistics of all resistance values; whether there are paired pins with similar resistance and capacitance values ​​(differential pairs or data line pairs); in diode testing, which pins have diodes to ground, which pins have diodes to power supply, and which pins have both or none.

[0119] Transient characteristics: Key parameters extracted from the power-on waveform, such as the initial steady-state level (high / low / high impedance), and whether there are obvious rising or falling edge pulses.

[0120] Number each physical pin with all characteristic values ​​and record its normalized resistance to ground, resistance to power supply, capacitance to ground, diode characteristic identifier (e.g., only to ground, only to power supply, both, neither) and initial steady-state level upon power-up in sequence.

[0121] The system calculates the similarity between the constructed feature vector and each pre-stored feature template in the interface feature database. Each feature template corresponds to a known debug interface type (such as JTAG, SWD, UART, I2C, SPI, etc.) and contains typical feature information of that type of interface, such as: the number of standard pins and their function definitions; the typical electrical parameter range of each functional pin (such as the resistance to ground of the TMS pin is usually between 10kΩ and 100kΩ, and the capacitance of the TCK pin is usually less than 50pF); the characteristic relationship pattern between pins (such as the SDA and SCL pins of I2C are usually open-drain structures, and both have pull-up resistors and diodes to the power supply); and typical power-on transient behavior (such as the SWDIO pin of some ARM chips briefly remaining high after power-on).

[0122] Similarity calculation can employ various algorithms, such as Euclidean distance, cosine similarity, or weighted matching algorithms (assigning different importance weights to different feature dimensions). After calculation, the system obtains a list of similarity scores between the currently tested interface and various known interface types in the interface feature database.

[0123] The system filters all interface types with scores higher than a preset similarity threshold from the similarity score list. For each filtered interface type, the system attempts to assign the most probable function to each physical pin being tested based on the "pin function - electrical characteristic" mapping relationship in its feature template (for example, a pin with a resistance of around 45kΩ and a diode to ground is assumed to be "TMS"; a pin with the smallest capacitance and medium resistance is assumed to be "TCK"). Therefore, each filtered interface type and its corresponding pin function assignment scheme together constitute a candidate interface type hypothesis. Each hypothesis is associated with a confidence score derived from its similarity score. Finally, the system generates a list of candidate interface type hypotheses sorted by confidence level from highest to lowest. The hypothesis with the highest confidence level represents one whose electrical characteristic data is most similar to a known interface in the interface feature database.

[0124] In a preferred embodiment, the step of comparing and matching the electrical feature data with a pre-stored interface feature database to generate at least one candidate interface type hypothesis specifically includes the following steps:

[0125] Step S310: Organize the electrical characteristic data into a standardized feature vector for each pin set to be analyzed. The feature vector contains at least electrical parameters that characterize the overall pin set and / or the relationships between internal pins.

[0126] Specifically, for the set of pins of the debug interface currently under test, the system extracts and calculates parameters that can characterize the electrical features of the interface, processes them, and generates a standardized feature vector.

[0127] This feature vector includes, but is not limited to, information in the following dimensions:

[0128] Topology characteristics: total number of pins; number of identified power pins and ground pins.

[0129] Numerical characteristics: "resistance to ground", "resistance to power supply", and "capacitance to ground" for each signal pin.

[0130] Relationship characteristics: maximum, minimum and distribution statistics of all resistance values; whether there are paired pins with similar resistance and capacitance values ​​(differential pairs or data line pairs); in diode testing, which pins have diodes to ground, which pins have diodes to power supply, and which have both or none.

[0131] Transient characteristics: Key parameters extracted from the power-on waveform, such as the initial steady-state level (high / low / high impedance), and whether there are obvious rising or falling edge pulses.

[0132] Number each physical pin with all characteristic values ​​and record its normalized resistance to ground, resistance to power supply, capacitance to ground, diode characteristic identifier (e.g., only to ground, only to power supply, both, neither) and initial steady-state level upon power-up in sequence.

[0133] Step S320: Perform similarity matching calculation between the feature vector and multiple feature templates pre-stored in the interface feature database, corresponding to different known debugging interface types; wherein, the feature template stores the electrical parameter range or distribution pattern of typical pin functions under the corresponding interface type.

[0134] Specifically, the system compares the constructed feature vector V_test with each pre-stored feature template V_template_i in the interface feature database. Each feature template V_template_i corresponds to a known debug interface type (e.g., standard 4-wire JTAG, 2-wire SWD, 2-wire UART, I2C, SPI, etc.) and stores the typical electrical parameter range (e.g., minimum-maximum) or theoretical parameter distribution pattern (e.g., expected value) of each functional pin under that type of interface in the same vector dimension and structure.

[0135] Similarity matching is calculated using Euclidean distance, cosine similarity, or weighted distance metric algorithms. This embodiment preferably uses a weighted distance metric algorithm, which assigns different weights W_j to different dimensions of the feature vector to reflect the importance of the feature in distinguishing different interface types (e.g., diode characteristic patterns may have a higher weight than absolute resistance values). Subsequently, the weighted distance D_i between V_test and each V_template_i is calculated. The smaller this distance value, the higher the similarity. The system converts this distance value into a similarity score Score_i (e.g., Score_i = 1 / (1 + D_i)).

[0136] Step S330: Based on the similarity calculation results, filter out the interface types with similarity higher than the preset threshold, and take each filtered interface type and its corresponding pin function allocation scheme as a candidate interface type hypothesis; wherein, a confidence score based on similarity calculation is associated with each candidate interface type hypothesis.

[0137] Specifically, the system sets a preset similarity threshold, Score_threshold. All interface types (Type_i) that satisfy Score_i > Score_threshold are filtered out. For each filtered interface type (Type_i), the system performs a pin function mapping: based on the typical feature patterns of each functional pin in the feature template of Type_i, it performs an optimal match with the actual features of the currently tested pin, thereby assigning each physical pin a most likely function (e.g., assigning the pin with the best feature match to "TCK", and the next best match to "TMS"). "Interface type (Type_i) + its corresponding pin function allocation scheme" constitutes a complete candidate interface type hypothesis (Hypothesis_i). The system associates this hypothesis (Hypothesis_i) with a confidence score (Confidence_i), which is directly derived from its similarity score (Score_i).

[0138] Step S340: Sort the generated candidate interface type hypothesis list according to the confidence score.

[0139] Specifically, the system collects all generated candidate interface type hypotheses {Hypothesis_1, Hypothesis_2, ...} and their corresponding confidence scores {Confidence_1, Confidence_2, ...}, sorts them from high to low confidence scores, and forms an ordered list of candidate interface type hypotheses.

[0140] In a preferred embodiment, S400: For each generated candidate interface type assumption, automatically configure the corresponding protocol excitation signal, and apply the protocol excitation signal to the corresponding candidate pin through the multiplexing switch matrix.

[0141] Specifically, the candidate interface type is assumed to contain two parts of information: 1) Interface type (e.g., "standard 4-wire JTAG"); 2) Pin function allocation scheme (e.g., "pin 1->TDI, pin 2->TDO, pin 3->TCK, pin 4->TMS").

[0142] Based on the interface type, the system calls the standard communication protocol specifications for that interface from the protocol library, including: electrical standards (such as voltage level and signal polarity), timing parameters (such as clock frequency and setup / hold time), link state machine (such as the TAP state transition of JTAG), and standard instruction sequences for initial interaction (such as the JTAG instruction to read IDCODE).

[0143] Simultaneously, based on the pin function allocation scheme, the system logically establishes a function-to-pin mapping table. This mapping table specifies which physical pin the programmable protocol generator's "clock output channel" should be connected to, which physical pin its "data output channel" should be connected to, and which physical pin should be connected to its "data input channel" to monitor the return signal during this test.

[0144] The system sends configuration instructions to the programmable protocol generator (PPG), including:

[0145] Electrical parameters: Output high / low level voltage values ​​to match the expected level of the interface under test (e.g., 1.8V LVCMOS, 3.3V CMOS).

[0146] Timing parameters: clock signal frequency, duty cycle; data signal setup time, hold time.

[0147] Protocol Content: Loads a predefined, standard stimulus sequence for verification. This sequence is typically a generic, harmless command used within the interface protocol to read device identification or status. For example, for the JTAG hypothesis, the standard stimulus sequence might be to put the TAP controller into "Shift-DR" state and send an instruction code to read the IDCODE; for the UART hypothesis, the standard stimulus sequence might be to send an AT command frame at a specific baud rate to query the firmware version.

[0148] After PPG configuration is complete, the system controls the multiplexing switch matrix to perform rapid physical connection reconfiguration:

[0149] According to the mapping table, the multiplexing switch matrix accurately connects each output channel of the PPG to the pin assumed to have the corresponding function (e.g., connecting the PPG's CLK OUT to the pin assumed to be TCK).

[0150] The multiplexed switch matrix will be assumed to have pins for receiving functions (such as TDO) connected to the input monitoring channel of the PPG or the digital sampling channel of the parameter measurement unit.

[0151] For pins not used in this assumption (e.g., if the assumption is a 4-wire JTAG but the interface has 6 pins, then the remaining 2 pins), the switch matrix sets them to no load or connects them to a high-impedance measurement terminal. Step 4: Apply protocol excitation and synchronously trigger monitoring.

[0152] After the connection is established and confirmed, the programmable protocol generator begins generating protocol stimulus signals according to a pre-configured standard stimulus sequence and applies them to the corresponding pins of the PCB under test through the established connection. Protocol verification testing for a specific candidate interface type hypothesis is prepared and initiated. The system enters step S500, analyzing the acquired response signals to determine if the current hypothesis is valid. Each candidate interface type hypothesis in the candidate interface type hypothesis list is executed sequentially until a candidate interface type hypothesis is confirmed or all candidate interface type hypotheses are eliminated.

[0153] In a preferred embodiment, the step of automatically configuring a corresponding protocol excitation signal for each generated candidate interface type assumption, and applying the excitation signal to the corresponding candidate pin through the multiplexing switch matrix, specifically includes:

[0154] Step S410: Based on the assumption of the candidate interface type to be verified, parse out the functional signal channels under the standard definition of the interface type.

[0155] Specifically, based on the explicit interface type identifier in the candidate interface type hypothesis to be verified, the system calls the corresponding complete specification from the pre-built protocol library. This specification defines all the standard functional signal channels of the interface. For example, for a "standard 5-wire SWD" hypothesis, its functional channels include: SWDIO (bidirectional data), SWCLK (clock), and optional nRESET (reset), etc.

[0156] Step S420: Based on the pre-allocated pin function definitions in the candidate interface type assumption, logically map each functional signal channel to the specific physical pin number in the pin group under test.

[0157] Specifically, based on the conclusions drawn from electrical characteristic matching, the function of each physical pin on the interface under test is specified. The system then performs a logic-to-physical mapping accordingly: mapping the "SWCLK" channel abstracted in the specification to the specific physical pin marked as "SWCLK function" in the allocation scheme (e.g., pin 3 of the interface under test).

[0158] Step S430: Based on the candidate interface type, control the programmable protocol generator to configure its internal state machine and timing parameters to generate an excitation signal sequence that conforms to the standard protocol specification of the interface type; the excitation signal sequence includes at least a specific timing sequence for interface initialization or a standard instruction stream for reading device identification information.

[0159] Specifically, after determining "which pins to send which signals," the system enters the signal content generation phase. Based on the interface type, the system determines the optimal standard instruction stream or initialization sequence for verification. For example, for a JTAG interface, a typical verification sequence is sending a complete TAP controller operation stream that enters the "Test-Logic-Reset" state and shifts into the "IDCODE" instruction; for an I2C interface, it might be a sequence of stimulus signals sending "START condition + general broadcast address + READ bit."

[0160] The configuration commands are sent to the programmable protocol generator (PPG). The specific configuration commands include:

[0161] Physical layer parameters include the high / low voltage level of the output signal, drive strength, and signal slope.

[0162] Link layer timing: including clock frequency, duty cycle, and relative timing of data and clock (setup / hold time).

[0163] Protocol layer content: Load or program the specific excitation signal sequence bit stream and configure the state machine inside the PPG to correctly generate the control signals required for the sequence (such as frame start and end flags).

[0164] Step S440: Control the multiplexer switch matrix to perform dynamic switching: connect each output channel of the programmable protocol generator to the mapped target pin, and connect the pin that is assumed to be the signal input to the input monitoring channel of the programmable protocol generator or the parameter measurement unit.

[0165] Specifically, sending a switching command to the multiplexing switch matrix includes:

[0166] The multiplexing switch matrix connects the individual physical output channels of the PPG (e.g., CH1, CH2) to the target physical pins specified in the "Connection Table" separately and synchronously. For example, the PPG's "CLK output channel" is connected to a physical pin mapped to a clock function.

[0167] The multiplexer switch matrix will assume physical pins as inputs or bidirectional functions and connect them to the designated monitoring unit. Typically, this includes: pins assumed to be data inputs connected to the input channel of the PPG; pins assumed to be control signals (such as reset) or pins requiring waveform capture connected to the ADC channel of the parameter measurement unit. For other pins not used in the current assumption, the multiplexer switch matrix will switch them to a safe high-impedance state or to ground.

[0168] In a preferred embodiment, S500: Monitor the response signal of the candidate pin under excitation, and confirm or exclude the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification of the current candidate interface type.

[0169] In a preferred embodiment, monitoring the response signal of the candidate pin under excitation, and confirming or excluding the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification of the current candidate interface type, specifically includes the following steps:

[0170] Step S510: During the application of the protocol excitation signal, the response signal on the pin mapped to the signal input function is acquired in real time through the input channel of the parameter measurement unit or the programmable protocol generator.

[0171] Specifically, during the entire duration of the applied protocol excitation signal and for a configurable period after its end, the system initiates multi-channel synchronous data acquisition. The multiplexer switch matrix has been connected to different monitoring units based on the current assumptions of the pin under test:

[0172] For pins mapped to critical control signals (such as reset nRST), clock signals (such as TCK, SWCLK), or pins where the full signal quality needs to be observed, the system synchronously captures the analog waveform of the voltage changing over time through the analog-to-digital converter (ADC) channel of the parameter measurement unit.

[0173] For pins mapped as primary data inputs / outputs (such as TDO, SWDIO, RXD), the system performs real-time digital sampling of the signals through the digital input capture channel of the programmable protocol generator (PPG).

[0174] Step S520: Decode the response signal according to the protocol specification corresponding to the currently verified interface type, and attempt to extract valid data or identify a specific protocol state.

[0175] Specifically, the system parses the collected raw signals according to the standard protocol specifications corresponding to the candidate interface types currently being verified:

[0176] The PPG's built-in decoding logic converts the level sequence into a bit stream according to the interface's timing rules (such as UART's baud rate and start bit detection, SPI's clock phase and edge sampling, and JTAG's TCK rising edge sampling TDO). It then assembles the bit stream into data words, commands, or response packets according to the interface's frame structure (data bit width, parity check, frame header and trailer).

[0177] Analyze analog waveforms and digital control signals (such as TMS) to identify specific protocol states or events. For example, by analyzing TMS and TCK sequences, determine whether the JTAG TAP controller has followed the expected state transition path (such as moving from Run-Test / Idle to Shift-DR) according to the excitation command.

[0178] Step S530: Compare and analyze the decoded signal content, timing features, or state transition sequence with the expected standard response pattern or state machine of the interface type stored in the interface feature database.

[0179] Specifically, the system compares the decoded and extracted results with the expected response patterns for that candidate interface type stored in the interface feature database. The expected response pattern defines a definite or expected response that a compliant device should return after sending a standard verification stimulus.

[0180] The dimensions of the comparison specifically include:

[0181] Content validity check: Is the decoded data meaningful? For example, does the read IDCODE contain valid vendor and device numbers? Does the response to the query command conform to a standard format?

[0182] Timing compliance analysis: Do the timing parameters of the response signal (such as the position of the data valid window relative to the clock and the pulse width of the response signal) fall within the time range specified in the protocol specification?

[0183] State machine logic verification: Does the observed state transition sequence completely conform to the state diagram defined by the protocol standard? Are there any illegal state transitions?

[0184] Electrical compliance check: Do the electrical parameters of the response signal, such as voltage amplitude and rise / fall time, comply with the electrical standards of the interface (such as LVTTL, LVCMOS)?

[0185] Step S540: If the response signal is successfully decoded, and the decoded content, timing characteristics and state transition sequence fully meet the expected specifications and satisfy the preset validity verification conditions, then the assumption of the current candidate interface type is confirmed, and its pin definition is recorded.

[0186] Specifically, if the response signal can be successfully decoded, and the decoded content, timing, and status fully conform to the expected specifications and satisfy all preset validity verification conditions (e.g., receiving multiple consistent and valid responses consecutively), then the system determines that the current candidate interface type hypothesis is valid. The system immediately records the interface type and corresponding pin definition scheme at this moment as a "confirmed" result, and can choose to terminate the verification process for the remaining low-confidence hypotheses in the list.

[0187] If all of the following preset validity check conditions are met, the system determines that the assumption of the current candidate interface type is true:

[0188] Decoding successful: The response signal can be decoded.

[0189] Content compliance: The decoded data content meets expectations in terms of semantics and format, and passes all built-in checks (such as CRC check).

[0190] Timing and state compliance: All timing measurements and state transition paths comply with the protocol specifications.

[0191] Validity conditions are met: the preset enhanced confidence conditions are met (e.g., three consecutive valid response frames are successfully decoded; or a complete protocol interaction process is successfully completed).

[0192] Once confirmed, the system immediately records the current candidate interface type as the final identification result and saves its complete pin definition mapping. This result has the highest priority.

[0193] Step S550: If the response signal cannot be successfully decoded, or the decoding result fundamentally conflicts with the expected specification, or no valid response is observed within the preset timeout period, then the current candidate interface type hypothesis is excluded.

[0194] Specifically, if the response signal cannot be successfully decoded and any of the following conditions are met, the system will make an exclusion decision:

[0195] Decoding failed: After multiple attempts, it was still impossible to parse any valid, coherent data or status from the response signal in accordance with the current protocol specifications.

[0196] Fundamental conflict: The decoding result clearly contradicts the expectation (for example, UART decoding produces garbled text, but JTAG decoding shows some regularity in the signal).

[0197] No response: No valid level change or signal activity was detected on the monitoring channel within the preset timeout window after the excitation was applied.

[0198] Consistency check failed: The decoded data failed any of the checks specified by the protocol, or the response content between different frames contradicted each other.

[0199] The system marks the currently excluded hypothesis as invalid and immediately removes it from the processing queue. It then switches to the next item to be verified in the candidate interface type hypothesis list and returns to step S400 to continue the process looping until all invalid hypothesis markings are eliminated.

[0200] In a preferred embodiment, S600: Output the finally confirmed interface type and its corresponding pin definition.

[0201] Specifically, the system can also perform the following actions based on the recognition results:

[0202] Automatic debugger configuration: Automatically writes or configures the identified interface type and pin definition parameters into the connected universal debugger / programmer, making it immediately usable for firmware download or debugging sessions.

[0203] Generate test adapter files: Automatically generate test programs or adapter connection files for automated test equipment (ATE).

[0204] Interface feature database update suggestion: If a slight but reasonable difference is found between the current interface features and the database template during the identification process, the user can be prompted to use the result as a new sample to optimize or update the interface feature database.

[0205] In a preferred embodiment, the final confirmed interface type and its corresponding pin definitions for the output specifically include the following steps:

[0206] Step S610: If only one candidate interface type hypothesis is confirmed by step S500, then the interface type and pin definition of the candidate interface type hypothesis are output as the final identification result.

[0207] Specifically, when the dynamic protocol verification process in step S500 is completed, and the system determines that only one candidate interface type hypothesis has been successfully confirmed (i.e., all confirmation conditions are met), the system uses the complete information contained in that hypothesis as the final identification result. The system extracts the interface type and pin function mapping table defined in the hypothesis, encapsulates it according to a predetermined standardized format, and prepares it for output.

[0208] Step S620: If multiple candidate interface type hypotheses are confirmed by step S500, arbitration is performed based on the confidence scores corresponding to each candidate interface type hypothesis, and the interface type and pin definition of the candidate interface type hypothesis with the highest confidence score are output as the final identification result.

[0209] Specifically, in certain specific situations, step S500 may successfully confirm multiple candidate interface type hypotheses (e.g., both interfaces pass the underlying protocol check). To determine a unique result, the system initiates an arbitration mechanism:

[0210] Retrieve confidence data: The system retrieves the initial confidence score calculated for each candidate interface type hypothesis in step S300.

[0211] Confidence arbitration: Among all confirmed hypotheses, their confidence scores are compared. The system determines the candidate interface type hypothesis with the highest confidence score as the final and optimal identification result.

[0212] Package Output: The system outputs the interface type and pin definition of the winning assumption in the arbitration as the final result. The arbitration event is recorded in the generated detailed technical report, along with information on the confirmed but lower-confidence assumptions.

[0213] Step S630: If step S500 fails to confirm any candidate interface type hypothesis, the result of identification failure is output, along with the key electrical characteristic data or protocol response anomaly information that caused the identification failure.

[0214] Specifically, if no candidate interface type hypothesis is confirmed after the verification loop in step S500, the system determines that the automatic identification has failed. Failure analysis mode:

[0215] Output status: The system outputs a "recognition failed" status indicator.

[0216] Additional diagnostic information: The system automatically packages and outputs a key diagnostic data package, which provides engineers with direct troubleshooting clues and typically includes:

[0217] Electrical characteristic data: Highlights abnormal or mismatched measurements (such as an unexpected resistance or capacitance on a pin).

[0218] Protocol response anomaly: Summary of abnormal data detected under all candidate interface type assumptions (such as no response under all assumptions, abnormal response level, or invalid decoded data).

[0219] Decision support: Diagnostic information can be displayed on the human-machine interface or stored in a log file to help engineers quickly locate problems caused by interface damage, non-standard interfaces, or measurement connection failures.

[0220] In a preferred embodiment, in step S500, if all generated candidate interface type assumptions are excluded, or step S300 fails to generate any candidate interface type assumptions with similarity higher than a preset threshold, then it is determined that the debugging interface may be an unknown type or a non-standard interface.

[0221] In response to this determination, the method enters an unknown interface learning mode, including the following steps:

[0222] S700: Based on the electrical characteristic data, and combined with the various standard protocol stimuli that were attempted to be applied in step S400 and their corresponding no-response or abnormal response signals, a characteristic dataset of the unknown interface is constructed.

[0223] Specifically, the system integrates and structures all relevant information acquired in the main identification process to construct the initial feature dataset for this unknown interface. This dataset includes:

[0224] Static characteristic data: Obtain complete initial electrical characteristic data (resistance spectrum, capacitance value, diode characteristics, power-on transient waveform) from step S200.

[0225] Dynamic interaction history: The historical log of verification attempts for all candidate standard protocol hypotheses recorded in steps S400 and S500, including the specific parameters of each standard protocol stimulus applied, and the characteristics of the corresponding no response or abnormal response signal.

[0226] S710: Initiate an adaptive exploration excitation sequence, control the programmable protocol generator to generate basic digital or analog excitation signals covering a typical electrical parameter range, and apply them sequentially to each signal pin through the multiplexed switch matrix.

[0227] Specifically, in this mode, the system no longer generates specific standard protocol instructions. Instead, it produces a series of basic test signals based on a preset or dynamically generated exploration strategy. These signals are designed to systematically probe the possible responses of interface pins to different electrical conditions and simple timing patterns in order to discover their potential functional logic. Typical exploration stimuli include trying combinations of the following parameters:

[0228] Electrical parameter scan: Try different output levels (e.g., 1.8V, 3.3V, 5V) and signal edge change rates.

[0229] Timing parameter scanning: Generate clock pulses with different duty cycles over a wide frequency range (e.g., from 1kHz to 10MHz); generate single or repetitive pulses with different widths; simulate simple timing units for basic synchronous (clock + data) or asynchronous (start bit + data) communication.

[0230] Signal pattern attempts: Generate pseudo-random bit streams, specific synchronization preambles (such as 0xAA, 0x55), or simple handshake pulse pairs.

[0231] S720: When applying each adaptive exploration stimulus, the parameter measurement unit synchronously monitors and records the dynamic response signals on all pins, and extracts the effective feature patterns in the response signals.

[0232] Specifically, when each exploration excitation signal is sequentially applied to each signal pin or pin combination through a multiplexed switch matrix, the system synchronously monitors and records the voltage response on all pins (including pins with and without excitation). From the recorded dynamic response waveforms, the system extracts key features, such as whether there are synchronous regular changes on specific pins, the amplitude and width of the response pulse, or whether there is a stable level offset.

[0233] S730: Analyze and summarize the association rules between static electrical characteristics and dynamic response characteristics in the feature dataset, and generate inferential descriptions of the possible pin functions of the unknown interface and hypotheses about its non-standard communication modes.

[0234] Specifically, the system performs multi-dimensional correlation analysis on the static feature set constructed in step S700 and the dynamic response feature set extracted in step S720. Through machine learning algorithms (such as cluster analysis and association rule learning) or rule-based inference engines, the system attempts to identify hidden correlation rules between static electrical parameters and dynamic behavior. For example:

[0235] If a pin with moderate resistance to ground and parasitic capacitance produces regular bit transitions whenever a clock pulse of a specific frequency is applied to another pin, then the latter is likely a clock pin and the former is likely a synchronous data output pin.

[0236] If a pin with unique diode characteristics is significantly pulled low after a specific voltage step is applied, it can be inferred that it is an open-drain output or a reset control pin.

[0237] Based on these association rules, the system generates an inferential description report about the unknown interface, including assumptions about the possible functions of each pin (e.g., "suspected clock CLK", "suspected bidirectional data line DATA", "suspected enable EN"), and makes preliminary assumptions about the non-standard communication mode it may follow (e.g., "suspected clock-based synchronous serial interface, data is valid on the rising edge of the clock").

[0238] S740: Encapsulate and store the feature dataset, inferential pin function description, and non-standard communication mode assumptions of the unknown interface as a new interface feature template.

[0239] Specifically, the system standardizes and encapsulates the complete initial feature dataset, adaptive exploration stimulus sequence and response records, and inferential description report to form a new interface feature template. This template is stored in a specific area of ​​the interface feature database (such as the "user-defined library" or the "learning library").

[0240] In a preferred embodiment, after the final recognition result is output, a technical report containing the recognition process is automatically generated and displayed visually on the human-computer interaction interface.

[0241] The technical report shall include at least the type of the confirmed interface, the complete pin definitions, a comparison of key electrical characteristic data used to make the judgment, and a successful protocol interaction verification log.

[0242] Specifically, the system uses its report generation function to integrate and identify data and events recorded throughout the entire process, compiling them into a structured document or data file. This technical report typically includes the following parts:

[0243] Results overview: The final confirmed interface type (e.g., “SWD (Serial Wire Debug) v2”) and the complete pin definitions listed in tabular form (e.g., “Pin 1: VDD (3.3V)”, “Pin 2: GND”, “Pin 3: SWCLK”, “Pin 4: SWDIO”).

[0244] Static feature matching analysis: Displays the measured key electrical feature data of the interface under test (such as typical values ​​of resistance and capacitance of each pin) with the corresponding standard range of the interface template that has been successfully matched in the database in the form of comparison charts or data tables, and highlights the feature items that match highly.

[0245] Protocol Interaction Verification Log: Records the successful protocol verification process in detail, either chronologically or in assumed order. Log entries include: the candidate interface type verified, a description of the specific stimulus signal sequence applied (e.g., "Send JTAG IDCODE read command stream"), the decoding result of the detected response signal (e.g., "Successfully received IDCODE: 0x4BA00477"), and the "confirmation" decision made accordingly.

[0246] Optional, it may also include:

[0247] Complete raw data or summary of static electrical characteristic measurements.

[0248] A list of all generated candidate interface type hypotheses and their confidence scores.

[0249] The candidate interface types that were excluded are assumed to be those that were excluded and the main reasons for their exclusion (e.g., "protocol no response", "decoding verification failed").

[0250] Any warnings or notes during system execution.

[0251] On the human-computer interaction interface, the content of the technical report is displayed dynamically and interactively in a user-friendly manner:

[0252] Results visualization panel: In the form of a virtual connector diagram, each physical pin and its identified function are intuitively labeled with different colors, labels, or icons. For example, power pins are displayed in red and labeled VCC, ground pins are in black and labeled GND, and clock pins have a pulse icon.

[0253] Interactive Data View: Provides browsing and exporting functions for report text; for key data comparison sections, it supports interactive viewing of charts (such as bar charts and scatter plots), allowing users to view specific values; for protocol verification logs, users can expand to view hexadecimal stimulus and response data streams.

[0254] Status and Navigation: The interface clearly displays the status of the recognition task (e.g., "Completed" or "Recognition Successful") and provides navigation, allowing users to review intermediate data at each stage of the recognition process (e.g., static measurement results or candidate interface type hypothesis generation).

[0255] Example 2

[0256] An automatic identification system for PCB debugging interfaces based on multi-feature fusion includes: a multiplexed switch matrix, a parameter measurement unit, a programmable protocol generator, an interface feature database, and a central control unit;

[0257] The multiplexed switch matrix is ​​used to establish electrical connections between the debug interface pins of the PCB under test and the parameter measurement unit and the programmable protocol generator, respectively.

[0258] The parameter measurement unit is used to perform static electrical characteristic measurements on the debugging interface pins to obtain electrical characteristic data; wherein, the electrical characteristic data includes at least two of the following: DC resistance to ground, resistance to power supply, pin capacitance to ground, diode characteristics, and power-on transient voltage;

[0259] The interface feature database pre-stores standard electrical feature data and corresponding protocol specifications for different interface types;

[0260] The programmable protocol generator is used to generate a protocol excitation signal corresponding to a specific interface type assumption based on the received configuration instructions.

[0261] The central control unit is connected to the multiplexing switch matrix, the parameter measurement unit, the programmable protocol generator, and the interface feature database, respectively; the central control unit is configured to execute:

[0262] Control the multiplexer switch matrix to establish corresponding electrical connections;

[0263] Acquire the electrical characteristic data measured by the parameter measurement unit;

[0264] The electrical feature data is compared and matched with the standard electrical feature data in the interface feature database to generate at least one candidate interface type hypothesis;

[0265] For each candidate interface type assumption generated, a corresponding configuration instruction is sent to the programmable protocol generator, and the multiplexing switch matrix is ​​controlled to apply the generated protocol excitation signal to the corresponding candidate pin.

[0266] Monitor the response signal of the candidate pin under excitation, and confirm or exclude the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification corresponding to the current candidate interface type in the interface feature database;

[0267] The output will finally confirm the interface type and its corresponding pin definitions.

[0268] Example 3

[0269] According to embodiments of the present invention, the present invention also provides an electronic device, a readable storage medium, and a computer program product.

[0270] Figure 3 A schematic block diagram of an example electronic device 100 that can be used to implement embodiments of the present invention is shown. Electronic device 100 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic device 100 may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their links and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0271] like Figure 3As shown, the electronic device 100 includes a computing unit 101, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 102 or a computer program loaded from a storage unit 108 into a random access memory (RAM) 103. The RAM 103 may also store various programs and data required for the operation of the electronic device 100. The computing unit 101, ROM 102, and RAM 103 are interconnected via a bus 104. An input / output (I / O) interface 105 is also linked to the bus 104.

[0272] Multiple components in electronic device 100 are linked to I / O interface 105, including: input unit 106, such as keyboard, mouse, etc.; output unit 107, such as various types of displays, speakers, etc.; storage unit 108, such as disk, optical disk, etc.; and communication unit 109, such as network card, modem, wireless transceiver, etc. Communication unit 109 allows electronic device 100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0273] The computing unit 101 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 101 performs the various methods and processes described above, such as a method for automatically identifying PCB debugging interfaces based on multi-feature fusion. For example, in some embodiments, a method for automatically identifying PCB debugging interfaces based on multi-feature fusion can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 108. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 100 via ROM 102 and / or communication unit 109. When the computer program is loaded into RAM 103 and executed by the computing unit 101, one or more steps of the method for automatically identifying PCB debugging interfaces based on multi-feature fusion described above can be performed. Alternatively, in other embodiments, the computing unit 101 may be configured by any other suitable means (e.g., by means of firmware) to perform an automatic identification method for PCB debug interfaces based on multi-feature fusion.

[0274] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0275] The program code used to implement the methods of the present invention can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0276] In the context of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical links based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0277] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0278] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0279] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0280] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0281] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Therefore, any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for automatic identification of PCB debugging interfaces based on multi-feature fusion, characterized in that, Includes the following steps: S100: The debug interface pins of the PCB under test are electrically connected to the parameter measurement unit and the programmable protocol generator respectively through a multiplexed switch matrix; S200: The parameter measurement unit is used to perform static electrical characteristic measurements on the debug interface pins to obtain electrical characteristic data; wherein, the electrical characteristic data includes at least two of the following: DC resistance to ground, resistance to power supply, pin capacitance to ground, diode characteristics, and power-on transient voltage; S300: Compare and match the electrical feature data with the pre-stored interface feature database to generate at least one candidate interface type hypothesis; S400: For each generated candidate interface type assumption, automatically configure the corresponding protocol excitation signal, and apply the protocol excitation signal to the corresponding candidate pin through the multiplexing switch matrix; S500: Monitor the response signal of the candidate pin under excitation, and confirm or exclude the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification of the current candidate interface type; S600: Outputs the final confirmed interface type and its corresponding pin definitions.

2. The automatic identification method for PCB debugging interfaces based on multi-feature fusion according to claim 1, characterized in that, The step of using the parameter measurement unit to perform static electrical characteristic measurements on the debug interface pins to obtain electrical characteristic data specifically includes the following steps: Identify the power and ground pins, measure and determine the pins among all pins that exhibit extremely low resistance to the power and ground networks of the PCB under test; Plot a resistance spectrum and, for the selected signal pins, measure the DC resistance of each signal pin to the identified ground pin and to the identified power pin. Measure pin capacitance, specifically the parasitic capacitance value of each signal pin to the identified ground pin; Perform diode characteristic tests to check whether there is a voltage-current relationship between each signal pin and the identified power and ground pins that conforms to the forward conduction characteristics of the protection diode; Monitor the transient voltage upon power-on. During the simulated power-on or reset process of the PCB under test, monitor and record the voltage change waveforms of each signal pin over time to capture startup information or initial level status.

3. The automatic identification method for PCB debugging interfaces based on multi-feature fusion according to claim 1, characterized in that, The step of comparing and matching the electrical feature data with a pre-stored interface feature database to generate at least one candidate interface type hypothesis specifically includes the following steps: The electrical characteristic data is organized into a standardized feature vector for each pin set to be analyzed. The feature vector contains at least electrical parameters that characterize the overall pin set and / or the relationships between internal pins. The feature vector is matched with multiple feature templates pre-stored in the interface feature database, corresponding to different known debugging interface types, to calculate similarity; wherein, the feature template stores the electrical parameter range or distribution pattern of typical pin functions under the corresponding interface type; Based on the similarity calculation results, interface types with similarity higher than a preset threshold are selected, and each selected interface type and its corresponding pin function allocation scheme are taken as a candidate interface type hypothesis; wherein, a confidence score based on similarity calculation is associated with each candidate interface type hypothesis. The generated candidate interface type hypothesis list is sorted according to the confidence score.

4. The automatic identification method for PCB debugging interfaces based on multi-feature fusion according to claim 1, characterized in that, For each generated candidate interface type assumption, the corresponding protocol excitation signal is automatically configured, and the excitation signal is applied to the corresponding candidate pin through the multiplexed switch matrix. Specifically, this includes: Based on the current candidate interface type assumption to be verified, the functional signal channels under the standard definition of the interface type are parsed out; Based on the pre-allocated pin function definitions in the candidate interface type assumption, each functional signal channel is logically mapped to a specific physical pin number in the pin group under test. Based on the candidate interface type, the programmable protocol generator is controlled to configure its internal state machine and timing parameters to generate an excitation signal sequence that conforms to the standard protocol specification of that interface type; the excitation signal sequence includes at least a specific timing sequence for interface initialization or a standard instruction stream for reading device identification information; Control the multiplexed switch matrix to perform dynamic switching: connect each output channel of the programmable protocol generator to the mapped target pin, and connect the pin that is assumed to be the signal input to the input monitoring channel of the programmable protocol generator or the parameter measurement unit.

5. The automatic identification method for PCB debugging interfaces based on multi-feature fusion according to claim 1, characterized in that, The process of monitoring the response signal of the candidate pin under excitation, and confirming or excluding the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification of the current candidate interface type, specifically includes the following steps: During the application of the protocol excitation signal, the response signal on the pin mapped to the signal input function is acquired in real time through the input channel of the parameter measurement unit or the programmable protocol generator. According to the protocol specification corresponding to the currently verified interface type, the response signal is decoded to attempt to extract valid data or identify a specific protocol state; The decoded signal content, timing features, or state transition sequence are compared and analyzed with the expected standard response pattern or state machine of the interface type stored in the interface feature database. If the response signal is successfully decoded, and the decoded content, timing characteristics, and state transition sequence fully meet the expected specifications and satisfy the preset validity verification conditions, then the assumption of the current candidate interface type is confirmed, and its pin definition is recorded. If the response signal cannot be successfully decoded, or the decoding result fundamentally conflicts with the expected specification, or no valid response is observed within the preset timeout period, then the current candidate interface type hypothesis is excluded.

6. The automatic identification method for PCB debugging interfaces based on multi-feature fusion according to claim 1, characterized in that, The final confirmed interface type and corresponding pin definitions for the output specifically include the following steps: If only one candidate interface type hypothesis is confirmed by step S500, the interface type and pin definition of the candidate interface type hypothesis will be output as the final identification result. If multiple candidate interface type hypotheses are confirmed by step S500, arbitration is performed based on the confidence scores corresponding to each candidate interface type hypothesis, and the interface type and pin definition of the candidate interface type hypothesis with the highest confidence score are output as the final identification result. If step S500 fails to confirm any candidate interface type hypothesis, it outputs a result indicating identification failure, along with key electrical characteristic data or protocol response anomaly information that caused the identification failure.

7. The automatic identification method for PCB debugging interfaces based on multi-feature fusion according to claim 1, characterized in that, Also includes: After the final recognition result is output, a technical report containing the recognition process is automatically generated and displayed visually on the human-computer interaction interface; The technical report shall include at least the type of the confirmed interface, the complete pin definitions, a comparison of key electrical characteristic data used to make the judgment, and a successful protocol interaction verification log.

8. An automatic identification system for PCB debugging interfaces based on multi-feature fusion, characterized in that, include: Multiplexer switch matrix, parameter measurement unit, programmable protocol generator, interface feature database, and central control unit; The multiplexed switch matrix is ​​used to establish electrical connections between the debug interface pins of the PCB under test and the parameter measurement unit and the programmable protocol generator, respectively. The parameter measurement unit is used to perform static electrical characteristic measurements on the debugging interface pins to obtain electrical characteristic data; wherein, the electrical characteristic data includes at least two of the following: DC resistance to ground, resistance to power supply, pin capacitance to ground, diode characteristics, and power-on transient voltage; The interface feature database pre-stores standard electrical feature data and corresponding protocol specifications for different interface types; The programmable protocol generator is used to generate a protocol excitation signal corresponding to a specific interface type assumption based on the received configuration instructions. The central control unit is connected to the multiplexing switch matrix, the parameter measurement unit, the programmable protocol generator, and the interface feature database, respectively; the central control unit is configured to execute: Control the multiplexer switch matrix to establish corresponding electrical connections; Acquire the electrical characteristic data measured by the parameter measurement unit; The electrical feature data is compared and matched with the standard electrical feature data in the interface feature database to generate at least one candidate interface type hypothesis; For each candidate interface type assumption generated, a corresponding configuration instruction is sent to the programmable protocol generator, and the multiplexing switch matrix is ​​controlled to apply the generated protocol excitation signal to the corresponding candidate pin. Monitor the response signal of the candidate pin under excitation, and confirm or exclude the candidate interface type hypothesis based on whether the response signal conforms to the expected protocol specification corresponding to the current candidate interface type in the interface feature database; The output will finally confirm the interface type and its corresponding pin definitions.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the PCB debug interface automatic identification method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that enables a processor to execute the automatic identification method for PCB debugging interfaces as described in any one of claims 1-7.

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