A digital instruction release control method, chip, and system based on physical disturbance characteristics and device intrinsic fingerprints

Abstract

This invention discloses a digital instruction release control method, chip, and system based on physical disturbance characteristics and device-intrinsic fingerprints. The method acquires real-time physical state information related to the execution object, execution environment, or execution node corresponding to the digital instruction to be verified; acquires the device-intrinsic fingerprint parameters or their derived response values ​​of the execution node; and acquires the digital feature information of the digital instruction to be verified. Based on the real-time physical state information, the device-intrinsic fingerprint parameters or their derived response values, and the digital feature information, a judgment value is generated to characterize whether the digital instruction meets preset release conditions. When the judgment value indicates that the digital instruction does not meet the preset release conditions, a blocking control signal is output to prevent the digital instruction from being executed, propagated, or written to the target link. In some embodiments, the real-time physical state information can be represented by a spatial residual component D1 and a temporal variation component D2, and the device-intrinsic fingerprint parameters can be represented by a static fingerprint, a digest value, or a challenge-response value. This invention can bind the execution qualification of digital instructions to the real-time physical state of the execution node and the inherent non-cloning characteristics of the device, thereby upgrading the verification conditions of digital instructions from logically executable to physically passable. It is applicable to scenarios such as warehouse settlement, industrial control, content authenticity verification, scientific instruments, unmanned equipment and energy scheduling.

Description

Technical Field

[0001] This invention relates to the fields of information security, embedded systems, distributed control, physical layer security, trusted computing, and digital instruction execution link protection. Specifically, it relates to a method, chip, and system for releasing digital instructions and outputting blocking control before execution based on physical disturbance characteristics and device intrinsic fingerprints. Background Technology

[0002] Current methods for verifying the authenticity of digital instructions typically rely on digital signatures, access control, authentication, software logs, and centralized auditing mechanisms. While these mechanisms can prove the legitimacy of the instruction's source or the integrity of the data format to some extent, they primarily remain at the software or network layer and cannot directly prove whether the digital instruction is consistent with the current physical environment, the actual state of the object being executed, or the authenticity of the execution node itself.

[0003] In high-risk scenarios such as payment disbursement, equipment startup and shutdown, industrial switchover, content publishing, and scheduling control, once an erroneous instruction enters the execution chain and is executed, losses have often already occurred, and subsequent accountability is difficult to replace preventative measures. Meanwhile, attackers can forge the verification process through emulation, forwarding, replay, man-in-the-middle substitution, or software / hardware cloning, allowing seemingly legitimate erroneous instructions to be executed.

[0004] Furthermore, under multi-node deployment conditions, while existing systems can perform cross-validation through network consistency, their handling of physical state deviations, clock drift, sensor noise, and device differences is inconsistent, making it difficult to establish a stable, reliable, and scalable release threshold before execution. Therefore, a new technical solution is needed to ensure that digital instructions not only meet logically executable conditions but also physically release conditions consistent with the current physical state, device intrinsic fingerprints, and time constraints. Purpose of the invention

[0005] The purpose of this invention is to provide a digital instruction release control method, chip, and system based on physical disturbance characteristics and device intrinsic fingerprints, so as to solve the problem that in the prior art, digital instruction verification mainly stays at the logic layer and it is difficult to verify its consistency with the physical world before execution.

[0006] A further objective of this invention is to provide a physical pass threshold mechanism that can be embedded in the front end of the execution link, so that digital instructions undergo physical consistency verification before being executed, propagated, written, or triggering critical actions, and trigger blocking control when verification fails.

[0007] The core of this invention does not lie in limiting a specific physical quantity, a specific device fingerprint extraction method, a specific judgment algorithm, a specific mapping model, or a specific blocking structure, but rather in binding the execution qualification of a digital instruction with the real-time physical state of the execution node and the device's inherent non-cloning characteristics, and determining whether to allow the digital instruction to proceed based on the binding result before the digital instruction enters the subsequent execution unit.

[0008] In some implementations, the real-time physical state can be represented by a physical feature vector; the physical feature vector can be further represented by a spatial residual component D1, a time-varying component D2, or other equivalent physical state representation quantities.

[0009] In some implementations, the device-inherent unclonable characteristics can be represented by device-inherent fingerprint parameters, fingerprint digests, derived response values, or challenge-response values.

[0010] In some implementations, the determination can be achieved through rule mapping, alignment mapping, projection mapping, training model mapping or other equivalent methods; the blocking can be achieved through one or more methods such as interface closure, execution link shutdown, buffer invalidation, suppression of signal output, isolation or circuit breaking.

[0011] Therefore, the focus of protection of this invention is on the pre-execution control logic of the above-mentioned "binding-determination-release / blocking", and is not limited to a specific sensor type, a specific parameter expression form, a specific hardware circuit or a specific software algorithm for implementing the logic.

[0012] In this invention, the binding relationship between the digital instructions and the real-time physical state of the execution node and the device's inherent non-clonable characteristics can be established by one or more of the following: device rules, scene templates, authorization rules, reference baseline models, and historical statistical models.

[0013] In some implementations, the binding relationship can be statically preset during system deployment; in other implementations, the binding relationship can be dynamically adjusted based on device operating status, environmental changes, changes in authorization conditions, or the results of reference baseline model updates.

[0014] To ensure the trustworthiness of the binding relationship, in some implementations, the establishment, updating or replacement of the binding relationship must meet local trust confirmation conditions or multi-node consistency confirmation conditions; when an abnormal change in the binding relationship is detected, the source is untrustworthy or is obviously mismatched with the current scenario, the system may refuse to adopt the new binding relationship and enter the blocking, downgrade operation or manual review process. Technical solution

[0015] To achieve the above objectives, this invention provides a digital instruction release control method based on physical disturbance characteristics and device-intrinsic fingerprints. The method acquires real-time physical state information related to the execution object, execution environment, or execution node corresponding to the digital instruction to be verified; acquires the device-intrinsic fingerprint parameters or their derived response values ​​of the execution node; and acquires the digital feature information of the digital instruction to be verified. Based on the real-time physical state information, the device-intrinsic fingerprint parameters or their derived response values, and the digital feature information, a judgment value is generated to characterize whether the digital instruction meets preset release conditions.

[0016] When the determination value indicates that the digital instruction does not meet the preset release conditions, a blocking control signal is output to prevent the digital instruction from being executed, propagated, or written to the target link, or to put the system into a safe mode. When the determination value indicates that the digital instruction meets the preset release conditions, the digital instruction is allowed to enter the subsequent execution unit. Thus, the execution eligibility of a digital instruction is bound to the real-time physical state of the execution node and the device's inherent non-cloning characteristics, thereby elevating the digital instruction from logically executable to physically releaseable.

[0017] In some embodiments, the real-time physical state information can be represented by a physical feature vector, which includes at least a spatial residual component D1 and a time-varying component D2. In some embodiments, the device-inherent fingerprint parameters can be generated by at least one of leakage current distribution, threshold voltage deviation, gate oxide thickness fluctuation, ring oscillator frequency difference, and initial power-on state of the memory cell, and can be further generated by a challenge-response method to produce derived response values. The judgment value can be generated by a joint feature space mapping model, preferably representing the degree of deviation of the current digital instruction to be verified from the preset release conditions; when a consistency metric M is used as the judgment value, the larger M is, the greater the deviation and the higher the risk.

[0018] In some embodiments, the physical disturbance signal includes at least one of current fluctuations, magnetic field changes, vibration signals, temperature changes, phase deviations, clock deviations, position changes, pressure changes, optical changes, and thermal radiation changes. In highly sensitive applications, the physical disturbance signal may further include weak gravitational disturbance signals.

[0019] In some implementations, the joint feature space mapping model includes a reference baseline model, which can be constructed from one or more of the following: historical sampling windows, device calibration parameters, scene templates, and reference states issued by trusted nodes, and can be statically or dynamically updated at a preset period. The joint feature space mapping model can uniformly represent the physical feature vector and the digital feature vector through one or more of the following: rule-based weighted mapping, time- or phase-based alignment mapping, event window-based projection mapping, and feature embedding mapping based on a trained model.

[0020] M = f(D1, D2, P_puf, T_sync, S_ref, I_cmd) Where T_sync represents the time synchronization parameter, S_ref represents the reference baseline model parameter, I_cmd represents the digital feature parameter obtained from the parsing of digital instructions, and f represents the mapping, alignment, and decision function.

[0021] M = sqrt(α·||D1||² + β·||D2||² + γ·||ΔP_puf||² + δ·||ΔT||² +ε·||ΔE||²) Where α, β, γ, δ, and ε are weighting parameters, ΔP_puf represents the device's intrinsic fingerprint deviation, ΔT represents the time synchronization deviation, and ΔE represents the difference between the expected state of the digital instruction and the current physical state.

[0022] In some implementations, the blocking control signal is used to trigger at least one of the following actions: closing the instruction output interface, controlling the blocking circuit to shut down the execution link, marking the target instruction as invalid, resetting the target buffer, switching to safe mode, triggering the differential suppression branch to output a suppression signal, triggering a fuse or isolation device, and outputting status feedback information after blocking to trigger audit log recording, alarm notification, or manual review process.

[0023] This invention also provides a digital command release control chip, including a physical sensing front-end, a device fingerprint extraction unit, an audit core, a blocking control unit, and an command output interface. The audit core is configured to execute the above-described method. This invention also provides a digital command release control system, including multiple chip nodes, a time synchronization module, and a result aggregation module; the system is configured to receive local verification results output by multiple nodes and form a system-level judgment result according to preset rules. Effect

[0024] The verification conditions for digital instructions are upgraded from simple logical validity to a combination of logical and physical conditions, thus forming a physical release threshold before execution.

[0025] By introducing physical perturbation features and device-inherent fingerprint parameters, the resistance to replay, forgery, cloning, simulation, and man-in-the-middle substitution is improved.

[0026] By moving consistency determination to the front end of the execution chain, pre-execution blocking can be achieved in high-risk scenarios, reducing the losses caused by retrospective tracing.

[0027] By referencing baseline models, dynamic thresholds, and time synchronization mechanisms, the stability and scalability of judgments under multi-node deployment conditions can be improved.

[0028] Through chip-based and system-based implementation, this invention can be used in multiple scenarios such as warehouse settlement, industrial control, content authenticity verification, scientific research instruments, unmanned equipment and energy dispatch, and has good industrial applicability. Attached Figure Description

[0029] Figure 1 This is an overall flowchart of the digital command release control method of the present invention.

[0030] Figure 2 This is a structural block diagram of the digital instruction release control chip of the present invention.

[0031] Figure 3 This is a schematic diagram showing the connection between the sensor node and the device fingerprint extraction unit of the present invention.

[0032] Figure 4 This is a schematic diagram of the joint feature space mapping and consistency determination of the present invention.

[0033] Figure 5 This is a schematic diagram illustrating the application of the present invention in warehousing and settlement scenarios.

[0034] Figure 6 This is a schematic diagram illustrating the application of the present invention in a high-security-level execution system.

[0035] Figure 7 This is a schematic diagram illustrating the application of the present invention in content acquisition and authenticity verification scenarios.

[0036] Figure 8 This is a schematic diagram of the structure of the multi-node distributed verification system of the present invention.

[0037] Figure 9 This diagram illustrates the parallel applications of the present invention in industrial control and unmanned equipment scenarios.

[0038] Figure 10 This diagram illustrates the parallel applications of the present invention in scientific research instruments and power energy dispatching scenarios. Detailed Implementation

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the following embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Various equivalent substitutions and modifications can be made by those skilled in the art without departing from the concept of the present invention, and these should all fall within the scope of protection of the present invention. Terms and Definitions

[0040] "Digital instructions" refer to digital inputs that can cause data flow, control flow, execution flow, write flow, or state switching. These include control instructions, as well as transaction instructions, content publishing instructions, device action instructions, scheduling instructions, and other data flows to be verified.

[0041] "Physical disturbance signal" refers to a change in a physical quantity that is related to the digital instruction to be verified and can be obtained by a sensor node or an execution node, including but not limited to the measured value or change of signals such as current, magnetic field, vibration, temperature, phase, clock, position, pressure, and thermal radiation.

[0042] "Spatial residual component D1" refers to the deviation of the currently acquired physical state from the reference baseline model, which can be in scalar, vector or tensor form.

[0043] "Time variation component D2" refers to the variation characteristics, differential characteristics, slope characteristics, momentum characteristics, or time offset characteristics of the physical disturbance signal in the time dimension.

[0044] "Device-inherent fingerprint parameter P_puf" refers to a physical difference parameter formed by the device manufacturing process that is difficult to clone and can be repeatedly extracted, or a digital digest generated from the physical difference parameter.

[0045] A "joint feature space" refers to a mapping space that simultaneously carries physical and digital feature vectors, and its dimensions can be adjusted according to the application scenario. The joint feature space may include at least one or more of the following dimensions: spatial dimension, temporal dimension, state dimension, and device feature dimension.

[0046] "Joint feature space mapping model" refers to a model used to uniformly represent physical feature vectors, digital feature vectors, and optional device intrinsic fingerprint parameters into the joint feature space, preferably including a reference baseline model.

[0047] The "consistency metric M" refers to the judgment value obtained after jointly mapping and aligning the physical feature vector, digital feature vector, and optional device intrinsic fingerprint parameter P_puf. Preferably, M represents the degree of deviation of the current digital instruction to be verified from the preset consistency judgment condition; the larger M is, the greater the deviation between the current digital instruction to be verified and the reference baseline model, device intrinsic fingerprint constraints, or time constraints, and the higher the risk. When M exceeds the preset threshold T, the system outputs a blocking control signal.

[0048] A “reference baseline model” is a model used to represent the reference state of a device, scenario, node, or link under normal operating conditions. It can be established from historical sampling windows, device calibration parameters, scenario templates, and reference states issued by trusted nodes.

[0049] "Blocking control signal" refers to the control signal output by the audit core and applied to the execution link when the consistency determination fails. It is used to trigger one or more actions such as shutdown, suppression, invalidation, isolation, circuit breaking, clearing, or security degradation. Overall Approach

[0050] The core of this invention lies in binding the execution eligibility of digital instructions with the real-time physical state of the execution node and the device's inherent non-clonable characteristics, and determining whether to allow the digital instructions to proceed based on the binding result before the digital instructions enter the subsequent execution unit.

[0051] like Figure 1 As shown, the digital command release control method of the present invention includes steps such as real-time physical state information acquisition, acquisition of device intrinsic fingerprint parameters or their derived response values, digital command parsing, reference baseline model invocation or update, judgment value generation, and release or blocking control. In some embodiments, the real-time physical state information can be further obtained through physical disturbance signal acquisition and physical feature extraction.

[0052] To facilitate understanding of the feasibility of this invention, a minimal implementation path is given below.

[0053] In this minimum implementation path, the system first acquires at least one physical disturbance signal related to the digital instruction to be verified, and generates real-time physical state information based on the physical disturbance signal; at the same time, it extracts the device intrinsic fingerprint parameters or their derived response values ​​of the execution node, and obtains the digital feature information of the digital instruction to be verified.

[0054] Subsequently, based on the real-time physical state information, the device's intrinsic fingerprint parameters or their derived response values, and the digital feature information, the system generates a judgment value to characterize whether the digital instruction meets the preset release conditions.

[0055] When the determination value indicates that the digital instruction does not meet the preset release conditions, the system outputs a blocking control signal to prevent the digital instruction from entering the subsequent execution unit; when the determination value indicates that the digital instruction meets the preset release conditions, the digital instruction is allowed to enter the subsequent execution unit.

[0056] In this minimum implementation path, the physical disturbance signal can be selected from only one physical quantity, the device intrinsic fingerprint parameter can be selected from only one device difference source, the judgment value can be generated by simple rule comparison, weighted calculation or threshold judgment, and the blocking control signal can be implemented by simply closing the output interface or marking the target instruction as invalid.

[0057] This demonstrates that the present invention can be implemented without relying on complex scenarios, complex models, or complex hardware structures. Instead, it can achieve pre-execution release control of digital instructions with minimal configuration. Furthermore, it can be extended to scenarios involving multiple physical quantities, multiple nodes, multiple layers of blocking, and distributed collaboration.

[0058] In a minimal binding example, the system collects the instantaneous current fluctuation of the target device as real-time physical state information, extracts the frequency difference of the ring oscillator of the target device as the device's intrinsic fingerprint parameter, parses the target device identifier and execution time window in the start command as digital feature information, and generates a judgment value based on a preset scenario template to characterize whether the start command meets the preset release conditions.

[0059] When the determination value indicates that the current instantaneous current fluctuation, the device's intrinsic fingerprint parameters, and the digital feature information of the start command do not satisfy the preset binding relationship, the system outputs a blocking control signal to close the command output interface or mark the target command as invalid; when the determination value indicates that the three satisfy the preset binding relationship, the start command is allowed to enter the subsequent execution unit.

[0060] The above minimal binding example is only used to illustrate the basic implementation logic of the present invention and does not constitute a limitation on the scope of protection of the present invention.

[0061] The above-mentioned general principles and minimum implementation path together illustrate that this invention can both summarize its core protection logic at a higher level of abstraction and achieve practical implementation with minimal technical configuration, thus taking into account both the scope of protection and feasibility.

[0062] The above-mentioned binding relationship sources and minimum binding examples further demonstrate that the focus of this invention is on the pre-execution binding and release control logic between digital instruction execution qualification and real-time physical state and device intrinsic characteristics, rather than being limited to a specific physical quantity, a specific fingerprint extraction method or a specific judgment algorithm.

[0063] Step S101: Acquire physical disturbance signals. At least one sensor node is used to acquire physical disturbance signals related to the execution object, execution environment, or execution node corresponding to the digital instruction to be verified. The sensor node can be a standalone node or integrated within the verification chip. Different types of physical signals can be acquired in different application scenarios. For example, in industrial control scenarios, current, vibration, and temperature can be acquired; in warehousing scenarios, weight-related signals, magnetic fields, and temperature can be acquired; in content acquisition scenarios, magnetic fields, clock deviations, and device status can be acquired. In some highly sensitive application scenarios, the physical disturbance signals may also include weak gravity disturbance signals.

[0064] Step S102: Extract the physical feature vector. The physical disturbance signal undergoes analog-to-digital conversion, filtering, denoising, time alignment, normalization, and feature extraction to obtain the physical feature vector. The spatial residual component D1 represents the deviation of the current physical state relative to the reference baseline model, which can be obtained from the difference, distance, residual vector, or its normalized representation between the current sampled value and the output of the reference baseline model. The temporal variation component D2 represents the variation characteristics of the physical disturbance signal in the time dimension, which can be obtained from the difference value, rate of change, sliding window slope, time offset, or other time-related characteristics. D1 and D2 can be used individually or in combination to construct the physical feature vector.

[0065] Step S103: Extract the device's intrinsic fingerprint parameters. In some embodiments, P_puf is extracted by an on-chip device fingerprint extraction unit. P_puf can be obtained through methods such as ring oscillator array, memory cell power-on state, current leakage testing, and threshold voltage deviation detection. To enhance replay resistance, a challenge-response method can also be used to obtain dynamic fingerprint response values.

[0066] Step S104: Parse the digital instruction to obtain a digital feature vector. Obtain the digital instruction to be verified and parse it into a digital feature vector. The digital feature vector may include: instruction type, target object identifier, target parameters, source identifier, permission tag, execution time window, target location identifier, expected physical state, expected device state, etc.

[0067] Step S105: Establish or invoke a reference baseline model. The reference baseline model can be constructed from historical sampling windows, pre-calibrated parameters, scene templates, and reference states issued by trusted nodes. In some implementations, the reference baseline model can be adaptively updated over time to offset the effects of sensor drift, slow environmental changes, and equipment aging.

[0068] Step S106: Map and calculate the consistency metric M. Input the physical feature vector, digital feature vector, and optional P_puf into the preset joint feature space mapping model, perform projection, alignment, and comparison in the same feature space, and calculate the consistency metric M.

[0069] Step S107: Perform allow or block. When M does not exceed a preset threshold T, the digital instruction is allowed to enter the subsequent execution unit; when M exceeds the preset threshold T, a blocking control signal is output. The blocking control signal can trigger one or more of the following actions: close the output interface, shut down the execution link, reset the buffer, mark the instruction as invalid, switch the security mode, output a suppression signal, or perform circuit breaking or isolation.

[0070] Step S108: Record the verification results. In some implementations, the verification results, device fingerprint summary, timestamp summary, reference baseline model version number, and blocking action identifier can be recorded as an audit log for subsequent traceability. Node-level implementation and joint mapping mechanism

[0071] like Figure 3 As shown, in the node-level implementation, the sensor node 110 may include a physical sensing front-end 120 and a device fingerprint extraction unit 130. The audit core 140 calls the reference baseline model 300 and performs joint processing of physical features and digital instruction features.

[0072] like Figure 4 As shown, the physical feature vector, digital feature vector, and device-inherent fingerprint parameters are input into the joint feature space mapping module 150, which performs alignment and comparison in a unified feature space to obtain a consistency metric value M, and then compares it with a preset threshold T to determine whether to allow or block access.

[0073] In some implementations, the joint feature space mapping model includes a reference baseline model and outputs a consistency metric M by uniformly representing physical feature vectors, digital feature vectors, and optional device-inherent fingerprint parameters. The joint feature space mapping model can be implemented in one or more of the following ways: rule-based weighted mapping, time- or phase-based alignment mapping, event window-based projection mapping, and feature embedding mapping based on a trained model. For example, in a time-aligned implementation, the peak value of the physical disturbance can be aligned and compared with the time of issuance of the digital command using timestamps, phase edges, pulse windows, or the order of event occurrence. Chip Structure

[0074] like Figure 2As shown, the digital instruction release control chip of the present invention includes at least a physical sensing front end 120, a device fingerprint extraction unit 130, an audit core 140, a blocking control unit 160, and an instruction output interface 170.

[0075] The physical sensing front-end 120 is used to collect physical disturbance signals such as current, magnetic field, vibration, temperature, phase deviation, clock deviation, and position change. The physical sensing front-end 120 may include a sensor interface, an amplifier circuit, a filter circuit, and an analog-to-digital conversion circuit. The device fingerprint extraction unit 130 is used to extract P_puf. This unit may include one or more of the following: a ring oscillator array, a counter, a comparator, a memory array readout circuit, a leakage current detection circuit, or a threshold deviation detection circuit.

[0076] In some implementations, the device-intrinsic fingerprint parameter P_puf is not extracted statically, but dynamically generated through a challenge-response mechanism. Specifically, the system can input challenge information into the device fingerprint extraction unit and generate a response value based on the challenge information to trigger non-clonable physical differences within the device; the response value can be associated with a portion of the current digital instruction, a timestamp digest, a scene label, or a random number, thereby improving resistance to replay, simulation, and cloning.

[0077] The audit core 140 is used to perform physical feature extraction, digital instruction parsing, reference baseline model invocation, joint feature space mapping, M-value calculation, and threshold determination. The audit core 140 can be implemented by a processor, accelerator, programmable logic, memory, and firmware.

[0078] The blocking control unit 160 is used to generate a blocking control signal when a decision fails. The blocking control unit 160 may include one or more of the following: gating logic, level isolation circuitry, differential suppression branch 500, fuse drive circuitry, interface shutdown circuitry, and buffer clearing control circuitry. The instruction output interface 170 is used to output verified digital instructions, or, in the blocking state, to stop forwarding, stop writing, stop execution, or switch to a security degradation path.

[0079] In some embodiments, the blocking control unit 160, in addition to performing output interface shutdown, link shutdown, buffer reset, and security mode switching, may also include a differential suppression branch 500 for outputting a suppression signal when a failure is detected. It should be understood that the differential suppression branch 500 is only one optional enhancement implementation and does not constitute the sole limitation on the blocking method of the present invention.

[0080] In some embodiments, the chip may further include a multi-valued state unit array 400. The multi-valued state unit array 400 has at least an excited state, an inhibited state, and a resting state, and is used to cooperate in performing at least one of the following actions: shutdown, suppression, isolation, or differential cancellation, when the blocking control unit 160 outputs a blocking control signal. It should be understood that the multi-valued state unit array 400 is a preferred enhancement structure, but not the only essential implementation of the present invention.

[0081] In some implementations, after outputting the blocking control signal, the blocking control unit also outputs status feedback information. This status feedback information can be sent to an audit log module, a monitoring terminal, an upper-level controller, or a manual review terminal to record the blocking reason, blocking time, feature summary of the decision-making process, and the current system status. This forms a closed-loop control link from decision-making to blocking to feedback. System Structure

[0082] like Figure 8 As shown, the multi-node distributed verification system of the present invention includes multiple verification chip nodes, a time synchronization module 180 and a result aggregation module 190. After each node outputs a local verification result, the result aggregation module 190 forms a system-level judgment result.

[0083] The time synchronization module 180 is used to provide a unified time reference for multiple nodes. Preferably, an external unified time signal can be used; when external time signal is unavailable, a local high-stability clock can be used; if further required, relative time calibration between nodes can also be used to reduce the impact of time deviation between different nodes on the D2 comparison results.

[0084] In some implementations, when the result aggregation module forms a system-level decision, it may employ at least one of the following: majority voting, weighted voting, or a fusion decision rule based on node credibility. The node credibility can be determined based on the stability of the node's historical decisions, the consistency of the device's intrinsic fingerprint, timing stability, sensor health status, or role level. When some nodes are damaged, out of sync, or interfered with, the system can reduce the weight of the corresponding nodes, thereby improving the robustness of the system-level decision.

[0085] In some implementations, the update of the reference baseline model does not directly overwrite the original baseline, but instead first generates candidate update results. These candidate update results are then written into the valid baseline after meeting preset credible confirmation conditions. These credible confirmation conditions may include: local self-calibration passed, multi-node consistency confirmation passed, device status within a credible operating range, and deviation changes conforming to a preset trend over multiple consecutive sampling periods. When abnormally slow drift, suspected induced updates, or multi-node confirmation failures are detected, the system refuses to execute the baseline update, retains the original valid baseline, and simultaneously outputs an alarm message or triggers a manual review process.

[0086] When the proportion of inconsistent local verification results exceeds a preset threshold, the system may enter a system-level blocking state, a degraded operation state, a state awaiting manual confirmation, or restrict the continued passage of certain links. The degraded operation state refers to the restricted operation mode executed on the target link when the system cannot reach a stable release conclusion or detects a local anomaly. The degraded operation state may include at least one of the following: allowing only queries and not writes, allowing only low-risk commands to pass, suspending the execution of high-risk actions, restricting external output, requiring secondary confirmation, or waiting for manual review. Example 1: Hardware Implementation of Physical Layer Audit Chip

[0087] like Figure 2 As shown, a digital command release control chip includes a physical sensing front-end 120, a device fingerprint extraction unit 130, an audit core 140, a blocking control unit 160, and a command output interface 170. The physical sensing front-end 120 can integrate high-precision sensors to capture physical signals such as current fluctuations, magnetic field changes, vibrations, temperature, and weak gravitational disturbances in highly sensitive application scenarios.

[0088] The device fingerprint extraction unit 130 can be implemented using a ring oscillator array, a counter, and a comparator to obtain a device fingerprint summary by measuring the difference in oscillation frequency; alternatively, it can use leakage current distribution, threshold voltage deviation, or the initial state of the memory cell upon power-up to form P_puf. The audit core 140 receives input from the physical sensing front end 120 and the device fingerprint extraction unit 130, extracts D1, D2, and P_puf, and simultaneously parses the instruction type, target object identifier, execution time window, and permission label of the digital instruction to be verified, thereby calculating the consistency metric M.

[0089] The blocking control unit 160 is connected to the audit core 140 and can achieve blocking by methods such as shutting down the instruction output interface 170, controlling the execution link gating unit to enter the shutdown state, clearing the pending execution buffer, triggering the differential suppression branch 500 to output a suppression signal, and triggering physical isolation or fuse breaking in high-risk scenarios. In some embodiments, the chip may also include a multi-valued state unit array 400, which has at least an excited state, a suppressed state, and a resting state, and is used to cooperate in performing at least one of the actions of shutdown, suppression, isolation, or differential cancellation when the blocking control unit 160 outputs a blocking control signal. Example 2: Authenticity Verification in Warehousing and Financial Settlement Scenarios

[0090] like Figure 5 As shown, in the warehousing and settlement scenario, multiple sensor nodes 110 are deployed in the warehousing area to collect physical disturbance signals related to the inventory status. The verification results are used to determine whether the target digital instruction in the settlement platform can continue to enter the loan disbursement, outbound confirmation or warehouse receipt registration link.

[0091] In a warehousing scenario, the digital instructions to be verified are loan release instructions, outbound confirmation instructions, warehouse receipt registration instructions, or settlement instructions related to stored goods. The system deploys multiple sensor nodes 110 within the warehouse to collect physical signals related to stored goods, such as weight-related signals, vibration, magnetic fields, temperature, and optional weak gravitational disturbances, and establishes a reference baseline model.

[0092] In this embodiment, the spatial residual component D1 can specifically represent the deviation of the current load distribution, local magnetic field distribution, or temperature distribution at the storage site from the reference baseline model; the time variation component D2 can represent the rate of change or differential characteristics of the load distribution, magnetic field distribution, or temperature distribution within a preset time window. Therefore, the real-time physical state of the storage site can be uniformly compared with the settlement instructions to be verified.

[0093] In a specific implementation, the consistency metric M can be expressed as: M = sqrt(α·(ΔW)² + β·(ΔΦ)² + γ·(ΔTemp)² + λ·(D² - D²_ref)²) Where ΔW represents weight or load deviation, ΔΦ represents electromagnetic response deviation, ΔTemp represents thermal response deviation, and D2_ref represents reference time series variation characteristics. When M exceeds the preset threshold T, the system can block payment gateway disbursement, block outbound confirmation, block warehouse receipt registration, or mark the transaction as pending manual review. Example 3: Verification of Control Commands in a High-Security Execution System

[0094] like Figure 6 As shown, in a high-security execution system, the verification chip is located between the control terminal and the execution unit 200. Before entering the execution unit 200, digital instructions are first processed by the audit core 140 to calculate the consistency metric value M, and the blocking control unit 160 decides whether to allow them.

[0095] For execution systems subject to strict authorization constraints, such as high-risk industrial start-up and shutdown systems, special equipment control systems, restricted execution units, and critical facility start-up links, the logical legality of digital instructions is not sufficient to constitute the execution conditions. It is also necessary to verify whether the current physical state, time constraints, and the authenticity of the execution nodes meet the requirements.

[0096] In one specific implementation, the system collects physical disturbance signals such as local device current, vibration, temperature, position, phase deviation, and clock synchronization status, and establishes a local reference baseline model. Simultaneously, digital instructions are parsed into the target object, action type, authorization tag, execution time window, and expected device state. In some high-security scenarios, an external trusted node can provide an authorization state summary or reference state summary as additional input for joint feature space mapping. Instructions are only released when the local physical state, the execution node P_puf, and the external authorization summary all meet preset conditions. Example 4: Content Acquisition and Authenticity Verification Scenario

[0097] like Figure 7 As shown, when the content acquisition terminal generates original content such as images, videos, audio, or text, the verification chip simultaneously generates an authenticity tag, and the platform side verifies the consistency between the authenticity tag and the content metadata.

[0098] At the moment of content acquisition, the chip simultaneously collects the magnetic field, clock deviation, device attitude, current characteristics, temperature characteristics, and the device's intrinsic fingerprint parameter P_puf from the environment in which the device is located. These parameters are then used to generate an authenticity tag, which is bound and stored with the content file. The authenticity tag can be saved as metadata, an independent index, or an encrypted digest. Subsequently, during content uploading, distribution, decoding, or authentication, the platform system verifies the consistency between the authenticity tag and the content's own characteristics, device registration information, and the reconstructed characteristics of the verification node. Example 5: Multi-node Distributed Verification System

[0099] like Figure 8 As shown, the multi-node distributed verification system of the present invention includes multiple verification chip nodes, a time synchronization module 180, and a result aggregation module 190. After each node outputs its local verification results, the result aggregation module 190 forms a system-level judgment result. The time synchronization module 180 can adopt external unified time synchronization, a local high-stability clock, or a relative calibration mechanism between nodes to reduce the impact of time deviations between different nodes on the D2 comparison results.

[0100] The result aggregation module 190 receives local judgment results from multiple nodes. In one embodiment, if the majority of nodes make consistent judgments, a system-level judgment is formed based on the majority results; in another embodiment, the results can be weighted and aggregated according to node trustworthiness weight, geographical location, role level, or device fingerprint stability. When the proportion of inconsistent local judgment results exceeds a preset threshold, the system can enter a system-level blocking state, a degraded operation state, a state awaiting manual confirmation, or restrict the continued passage of some links. Thus, this embodiment can improve the tolerance to local forgery, node cloning, local drift, and communication anomalies in complex systems. Example 6: Verification before industrial control execution

[0101] like Figure 9 As shown, in industrial control scenarios, the verification chip is located between the controller and the controlled device, and is used to complete consistency verification before the action command enters the drive execution link. The digital commands to be verified include start / stop commands, switch switching commands, valve opening adjustment commands, relay action commands, etc.

[0102] The system collects signals such as current, vibration, temperature, speed feedback, position feedback, and clock deviation during equipment operation and establishes a reference baseline model. Digital commands are parsed into target equipment identifier, action type, target parameters, and execution time window. If the current physical state of the equipment does not match the command requirements, such as the equipment being in an abnormal vibration state, exceeding the load current limit, inconsistent position feedback, or an abnormal time window, then M exceeds the preset threshold T.

[0103] For example, in power or industrial control scenarios, the spatial residual component D1 can represent the deviation of the current bus current, voltage, phase, or equipment position signal from the reference baseline model; the time variation component D2 can represent the rate of change, differential slope, or timing offset of the physical quantity within the sliding time window. This allows for the verification of the consistency between the target action required by the digital command and the actual operating state on-site. Example 7: Anti-hijacking verification of unmanned and mobile devices

[0104] like Figure 9 As shown, in unmanned equipment scenarios, the verification chip is located at the front end of the control link and is used to determine the release of control commands by combining the device's attitude, position, clock deviation, and device-inherent fingerprint parameters. In the control links of drones, unmanned vehicles, robots, remote inspection equipment, and mobile terminals, the system collects physical information such as the device's attitude, acceleration, vibration, current, geomagnetism, position, clock deviation, and link status, while extracting the P_puf of the execution node.

[0105] If the system detects inconsistencies in the source of control commands, discrepancies between the current and expected positions, conflicts between attitude changes and control modes, abnormal device P_puf values, or abnormal time deviations, it will refuse to execute the command and may further enter hover, speed limit, safe stop, lock control, or request re-authentication modes. Example 8: Verification of the authenticity of raw data from scientific instruments

[0106] like Figure 10 As shown, in scientific instrument scenarios, the verification chip is deployed at the front end of raw data generation to bind physical perturbation characteristics and device-inherent fingerprint parameters to the authenticity label of the raw data. The verification chip of this invention can be integrated into mass spectrometers, sequencers, microscopic imaging devices, data acquisition cards, and experimental terminals.

[0107] When outputting raw data, the instrument simultaneously collects local magnetic field, equipment vibration, temperature, power supply fluctuations, clock deviation, and P_puf data to generate a raw data authenticity label. This authenticity label can be linked to each piece of raw data, each data slice, each batch of experimental records, or each set of instrument operation logs. Before subsequent data export, uploading, sharing, modeling analysis, or publication, the system re-verifies the consistency of the authenticity label with the instrument registration information, operation logs, and content structure characteristics. Example 9: Verification of Power and Energy Dispatch Commands

[0108] like Figure 10 As shown, in power and energy dispatching scenarios, the verification chip is deployed at the front end of the dispatching link to verify the consistency with the physical state of the equipment before dispatching instructions enter the target equipment. The verification chip of this invention can be deployed in power distribution units, energy storage management units, station control layer equipment, or at the front end of the energy dispatching link.

[0109] The system collects physical information such as current, voltage, phase, frequency deviation, temperature rise, equipment vibration, and local time synchronization status, and establishes a reference baseline model. Digital commands to be verified include switching commands, start / stop commands, grid connection / disconnection commands, power regulation commands, and load control commands. After parsing the digital commands, the system aligns and compares them with the actual physical state of the equipment. When the equipment is overloaded, has abnormal frequency offset, phase mismatch, or an abnormal execution time window, the system refuses to release the relevant commands and may trigger delayed confirmation, partial isolation, or manual review processes. Additional Description of Optional Implementation Methods

[0110] In some implementations, P_puf is used not only for node identity uniqueness identification, but also for the calibration of consistency metric M, challenge response verification, or device binding, thereby enhancing anti-replay and anti-cloning capabilities.

[0111] In some implementations, the preset threshold T can be dynamically adjusted based on the scenario risk level, environmental noise level, sensor drift degree, historical error statistics, and self-calibration results.

[0112] In some implementations, the method can be executed by a general-purpose processor, or by a dedicated hardware circuit, an on-chip state machine, programmable logic, or a combination of the above.

[0113] In some implementations, the blocking control applies not only to physical execution units, but also to cache writes, instruction relays, service gateways, decoding paths, distribution paths, or other links awaiting permission. Table of Labels in the Drawing

[0114] 100: Digital command release control method; 110: Sensor node; 120: Physical sensing front end; 130: Device fingerprint extraction unit; 140: Audit core; 150: Joint feature space mapping module; 160: Blocking control unit; 170: Command output interface; 180: Time synchronization module; 190: Result aggregation module; 200: Execution unit; 300: Reference baseline model; 400: Multi-valued state unit array; 500: Differential suppression branch.

Claims

1. A digital command release control method based on physical disturbance characteristics and device intrinsic fingerprints, characterized in that, include: Obtain real-time physical state information related to the execution object, execution environment, or execution node corresponding to the digital instruction to be verified; obtain the device intrinsic fingerprint parameters or their derived response values ​​of the execution node; The system acquires a digital instruction to be verified and parses it to obtain digital feature information. Based on the real-time physical state information, the device's intrinsic fingerprint parameters or their derived response values, and the digital feature information, it generates a judgment value to characterize whether the digital instruction meets preset release conditions. When the judgment value indicates that the digital instruction does not meet the preset release conditions, it outputs a blocking control signal to prevent the digital instruction from being executed, propagated, written to the target link, or to put the system into a safe mode. When the judgment value indicates that the digital instruction meets the preset release conditions, it allows the digital instruction to enter the subsequent execution unit.

2. The method according to claim 1, characterized in that, The real-time physical state information is represented by a physical feature vector, which includes at least a spatial residual component D1 and a temporal variation component D2. The spatial residual component D1 represents the deviation of the current physical state from the reference baseline model, and the temporal variation component D2 represents the variation characteristics of the physical disturbance signal in the time dimension.

3. The method according to claim 1, characterized in that, The device-inherent fingerprint parameters or their derived response values ​​originate from non-clonable physical differences formed during chip manufacturing. These non-clonable physical differences include at least one of leakage current distribution, threshold voltage deviation, gate oxide thickness fluctuation, ring oscillator frequency difference, and initial power-on state of the memory cell. In some embodiments, the derived response values ​​are generated through a challenge-response method and serve as one of the inputs to the determination value generation process.

4. The method according to claim 1, characterized in that, The determination value is generated through a joint feature space mapping model, which includes a reference baseline model and uses one or more of the following methods: rule-based weighted mapping, time- or phase-based alignment mapping, event window-based projection mapping, and feature embedding mapping based on a training model to uniformly represent the real-time physical state information, the device intrinsic fingerprint parameters or their derived response values, and the digital feature information.

5. The method according to claim 4, characterized in that, The reference baseline model is constructed from one or more of the following: historical sampling window, device calibration parameters, scene template, and reference state issued by trusted nodes. It is statically or dynamically updated according to a preset period. The dynamic update is triggered when environmental changes, device drift, long-term deviation accumulation, or model mismatch conditions are detected, and is subject to local trusted confirmation or multi-node consistency confirmation before the update.

6. The method according to claim 1, characterized in that, The blocking control signal is used to trigger at least one of the following actions: closing the instruction output interface, controlling the blocking circuit to shut down the execution link, marking the target instruction as invalid, resetting the target buffer, switching to safe mode, triggering the differential suppression branch to output suppression signal, and triggering a fuse or isolation device. It outputs status feedback information after blocking, which can be used to trigger audit log recording, alarm notification or manual review process.

7. A digital instruction release control chip based on physical disturbance characteristics and device-inherent fingerprints, characterized in that, include: A physical sensing front-end is used to acquire real-time physical state information related to the execution object, execution environment, or execution node corresponding to the digital instruction to be verified; a device fingerprint extraction unit is used to extract the device-inherent fingerprint parameters or their derived response values ​​of the execution node; an audit core is connected to the physical sensing front-end and the device fingerprint extraction unit, used to acquire the digital instruction and parse it to obtain digital feature information, and generate a judgment value based on the real-time physical state information, the device-inherent fingerprint parameters or their derived response values, and the digital feature information to characterize whether the digital instruction meets the preset release conditions; a blocking control unit is connected to the audit core, used to output a blocking control signal when the judgment value indicates that the digital instruction does not meet the preset release conditions. The instruction output interface is used to output a released digital instruction when the determination value indicates that the digital instruction meets the preset release conditions; wherein, the chip may further include a multi-value state unit array and / or a differential suppression branch, used to cooperate in performing at least one of the following actions: shutdown, suppression, isolation or differential cancellation when blocking the output of the control signal.

8. A digital command release control system, characterized in that, The system includes multiple chips as described in claim 7, a time synchronization module, and a result aggregation module; the time synchronization module is used to provide a unified time reference or relative time calibration for multiple chips; the result aggregation module is used to receive local judgment results output by multiple chips and form a system-level release result or a system-level blocking result according to preset rules, wherein the preset rules include at least one of majority voting, weighted voting, or fusion judgment rules based on node credibility; when the proportion of inconsistent local judgment results exceeds a preset threshold, the system outputs a system-level blocking command, switches to a degraded operation state, or triggers a manual review process.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 6.

Images