Board card design method and electronic device

Abstract

The application discloses a board card design method and electronic equipment, and relates to the field of printed circuit board design. The method comprises the following steps: obtaining a design file of a board card, wherein the design file comprises first electrical parameters and first structural parameters of a first component on the board card; processing the first electrical parameters and the first structural parameters to obtain a first identifier corresponding to the first component; obtaining current second electrical parameters, second structural parameters and a second identifier of the first component in a feature library; determining that the first component in the design file has been updated in the feature library when the first identifier is different from the second identifier; determining first difference information between the first electrical parameters and the second electrical parameters, and second difference information between the first structural parameters and the second structural parameters; and determining risk information of the first component that is not updated in the design file based on the first difference information and the second difference information. The method can solve the problem that the packaging update cannot be identified in time in the related art.

Description

Technical Field

[0001] This application relates to the field of printed circuit board design, and more particularly to a board design method and electronic device. Background Technology

[0002] In the modern electronic product development process, printed circuit board (PCB) design is the core link connecting circuit schematics and physical implementation. Component packaging serves as the foundational data for PCB layout and routing, and its accuracy directly affects the manufacturability, electrical performance, and reliability of the product. With dynamic adjustments in the supply chain, iterative engineering optimizations, and the introduction of alternative components, component packaging information (such as pad size and pin arrangement) may be frequently updated.

[0003] Currently, design engineers frequently rely on package names in PCB design tools to verify whether the packages referenced in the design files are consistent with the latest version of the packages in the central library, ensuring that the latest packages are used in the design files. However, this method cannot identify heterogeneous packages with the same name but updated internal parameters. This means that the design files may still reference outdated packages, failing to completely eliminate the low product reliability and manufacturability caused by untimely package updates. Summary of the Invention

[0004] This application provides a board design method and an electronic device to at least solve the problem of failing to identify package updates in a timely manner in related technologies.

[0005] This application provides a board design method, including:

[0006] Obtain the design file of the board, which includes the first electrical parameters and first structural parameters of the first component on the board;

[0007] The first electrical parameters and the first structural parameters are processed to obtain the first identifier corresponding to the first component;

[0008] Obtain the current second electrical parameters, second structural parameters, and second identifier of the first component determined based on the second electrical parameters and second structural parameters from the feature library;

[0009] When the first identifier and the second identifier are different, it is determined that the first component in the design file has been updated in the feature library;

[0010] Determine the first difference information between the first electrical parameter and the second electrical parameter, and the second difference information between the first structural parameter and the second structural parameter; based on the first difference information and the second difference information, determine the risk information of the first component that has not been updated in the design document.

[0011] This application also provides a circuit board design apparatus, including: a first acquisition module, a first processing module, a second acquisition module, a first determination module, a second determination module, and a third determination module, wherein,

[0012] The first acquisition module is used to acquire the design file of the board, which includes the first electrical parameters and first structural parameters of the first component on the board.

[0013] The first processing module is used to process the first electrical parameters and the first structural parameters to obtain the first identifier corresponding to the first component;

[0014] The second acquisition module is used to acquire the current second electrical parameters, second structural parameters, and second identifier of the first component determined based on the second electrical parameters and second structural parameters from the feature library.

[0015] The first determining module is used to determine that the first component in the design file has been updated in the feature library when the first identifier and the second identifier are different.

[0016] The second determining module is used to determine the first difference information between the first electrical parameter and the second electrical parameter, and the second difference information between the first structural parameter and the second structural parameter;

[0017] The third determination module is used to determine the risk information of the first component that has not been updated in the design file based on the first difference information and the second difference information.

[0018] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described board design methods.

[0019] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described board design methods.

[0020] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described board design methods.

[0021] This application enables the comparison of the first identifier of the first component in the design file with the current second identifier in the feature library, and then the location of differences by combining the first electrical parameters, the first structural parameters, the second electrical parameters and the second structural parameters. Based on the difference dimension, risk information can be dynamically assessed, which can overcome the limitations of traditional reliance on package name or manual verification, accurately identify hidden package updates such as homonymous heterogeneous packages, and solve the problem of failing to identify package updates in a timely manner in related technologies. Attached Figure Description

[0022] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart illustrating the board design method provided in this application embodiment;

[0024] Figure 2 A flowchart illustrating a method for determining third difference information provided in an embodiment of this application;

[0025] Figure 3 A flowchart illustrating a method for determining risk information provided in an embodiment of this application;

[0026] Figure 4 A flowchart illustrating another method for determining risk information provided in an embodiment of this application;

[0027] Figure 5 This is a schematic diagram of the board design device provided in the embodiments of this application;

[0028] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, other embodiments obtained by those of ordinary skill in the art without creative effort are all within the protection scope of this application.

[0030] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] In the modern electronic product development process, PCB design is the core link connecting circuit schematics and physical implementation. Component packaging serves as the foundational data for PCB layout and routing, and its accuracy directly affects the manufacturability, electrical performance, and reliability of the product. With dynamic adjustments in the supply chain, iterative engineering optimizations, and the introduction of alternative components, component packaging information (such as pad size and pin arrangement) may be frequently updated.

[0032] Currently, design engineers frequently rely on package names in PCB design tools to verify whether the packages referenced in the design files are consistent with the latest version of the packages in the central library, ensuring that the latest packages are used in the design files. However, this method cannot identify heterogeneous packages with the same name but updated internal parameters. This means that the design files may still reference outdated packages, failing to completely eliminate the low product reliability and manufacturability caused by untimely package updates.

[0033] To address the aforementioned issues, this embodiment of the application obtains the design file of the circuit board, which includes the first electrical parameters and first structural parameters of the first component on the board. The first electrical parameters and first structural parameters are processed to obtain the first identifier corresponding to the first component. The current second electrical parameters, second structural parameters, and second identifier of the first component are obtained from a feature library. When the first identifier and the second identifier differ, it is determined that the first component in the design file has been updated in the feature library. First difference information between the first electrical parameters and the second electrical parameters, and second difference information between the first structural parameters and the second structural parameters are determined. Based on the first and second difference information, risk information of the first component in the design file that has not been updated is determined. In this method, by comparing the first identifier of the first component in the design file with the current second identifier in the feature library, and then combining the first electrical parameters, first structural parameters, second electrical parameters, and second structural parameters to locate differences, and dynamically assessing risk information based on the difference dimension, the limitations of traditional reliance on package names or manual verification can be overcome. This allows for accurate identification of hidden package updates, such as homonymous heterogeneous components, solving the problem of failing to identify package updates in a timely manner in related technologies.

[0034] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Figure 1 This is a flowchart illustrating the board design method provided in the embodiments of this application, such as... Figure 1 As shown, embodiments of this application provide a board design method, which is described in detail below:

[0036] S101. Obtain the design file of the board. The design file includes the first electrical parameters and the first structural parameters of the first component on the board.

[0037] The execution subject of this application embodiment can be an electronic device or a board design device disposed in an electronic device. The board design device can be implemented by software or by a combination of software and hardware.

[0038] In one possible implementation, a lightweight smart plugin deployed in the PCB design tool can read the currently open design file. This lightweight smart plugin can export data through the scripting interface provided by the PCB design tool.

[0039] In one possible implementation, the design file format can be a board file (brd) or a PCB project file (PrjPCB).

[0040] In one possible implementation, the design document may include first electrical parameters and first structural parameters, which may include parameters related to the following attributes: basic attributes, manufacturing attributes, structural attributes, electrical attributes, rule attributes, and topology attributes. Among these, basic attributes may include, for example, package type, manufacturer, version number, release date, and identifier.

[0041] Structural attributes include, for example: number of pads, pad size (including length, width and / or diameter of pads), pad spacing (including center distance or edge distance), package outline dimensions (including length, width and / or height of package wheel), positioning hole coordinates and diameter, pin arrangement, designer information, and hash value of three-dimensional (3D) model.

[0042] Electrical properties include, for example, signal layer properties, reference layer information, pin impedance, rated current, withstand voltage, operating temperature range, and signal transmission rate.

[0043] Manufacturing attributes include, for example, solder mask extension values, silkscreen layer information, and stencil layer openings;

[0044] Rule attributes include, for example: package and PCB layer matching rules, minimum spacing rules between pads and traces, package avoidance of mechanical structure dimensions rules, and thermal design compatibility rules;

[0045] Topology attributes include, for example, pin network connections and differential pair definitions.

[0046] The identifier of the first component (the third identifier in the following embodiments) can be generated by a preset encoding rule, and the identifier of the first component can be used to uniquely identify the component.

[0047] S102. Process the first electrical parameters and the first structural parameters to obtain the first identifier corresponding to the first component.

[0048] In one possible implementation, the first electrical parameters and the first structural parameters can be processed by a preset feature encoding rule to obtain the first identifier corresponding to the first component. The first identifier corresponding to the first component can also be used to uniquely identify the component, and the first identifier corresponding to the first component is irreversible.

[0049] The feature encoding rules can be hash algorithms, etc.

[0050] S103. Obtain the current second electrical parameters, second structural parameters, and second identifier of the first component determined based on the second electrical parameters and second structural parameters from the feature library.

[0051] In one possible implementation, the current second electrical parameters and second structural parameters of the first component refer to the electrical parameters and structural parameters of the latest version of the first component. The second identifier of the first component can also be used to uniquely identify the component, and the second identifier of the first component is irreversible.

[0052] In some implementations, the current second electrical parameters, second structural parameters, and second identifiers of the first component determined based on the second electrical parameters and second structural parameters are obtained from a feature library, including:

[0053] Send a first request to the feature library, the first request including a third identifier and a first identifier of the first component; receive a response to the first request sent by the feature library, the response to the first request including a third identifier of the first component, a second electrical parameter, a second structural parameter, and a second identifier of the first component determined based on the second electrical parameter and the second structural parameter.

[0054] In one possible implementation, the third identifier of the first component is used to uniquely identify the component, and the format of the third identifier of the first component can be a string, etc.

[0055] In one possible implementation, smart plug-ins can be deployed in PCB design tools to enable electronic devices to communicate with feature libraries.

[0056] In one possible implementation, the deployment smart plugin in the PCB design tool can send a first request to the feature library at a preset time. Upon receiving the first request, the feature library can obtain the second electrical parameters, second structural parameters, and a second identifier of the first component determined based on the third identifier of the first component. It then sends the third identifier, second electrical parameters, second structural parameters, and the second identifier of the first component to the PCB design tool in the electronic device. It should be noted that the second electrical parameters and second structural parameters of the first component are the parameters of the latest version of the first component, and the second identifier of the first component is a feature generated by processing the second electrical parameters and second structural parameters through preset feature encoding rules.

[0057] The preset time can be the moment when the user opens the design file in the PCB design tool, or it can be the time at which the user opens the design file every preset period, for example, 5 minutes.

[0058] It should be noted that if the response to the first request sent by the feature library fails, a failure message can be provided to the user in the PCB design tool, so that the user can check the reason for the failure based on the message.

[0059] S104. When the first identifier and the second identifier are different, determine that the first component in the design file has been updated in the feature library.

[0060] In one possible implementation, since the first identifier is determined based on the first electrical parameters and the first structural parameters, and the second identifier is determined based on the second electrical parameters and the second structural parameters, it can be determined that the first component in the design file has been updated in the feature library when the first identifier and the second identifier are different.

[0061] S105. Determine the first difference information between the first electrical parameter and the second electrical parameter, and the second difference information between the first structural parameter and the second structural parameter.

[0062] In one possible implementation, upon receiving a response to the first request sent by the feature library, the electronic device can standardize the first electrical parameters and first structural parameters of the first component by calling a preset first function, and then extract the first electrical parameters and first structural parameters of the first component.

[0063] In this process, the first electrical parameters and first structural parameters of the first component are standardized. In other words, the units, precision and format of each value in the first electrical parameters and first structural parameters of the first component can be unified.

[0064] The first preset function can be a multi-dimensional attribute standardization processing function. This function has a built-in unit conversion module, accuracy calibration module and format unification module, which can automatically process different types of parameters in the first electrical parameters and the first structural parameters according to preset standardization rules.

[0065] The preset standardization rules may include: converting the units of dimensional parameters in the current design file to mils (with a conversion accuracy of ±0.01mil), converting the units of electrical attribute parameters to international standard units (e.g., current to amperes (A), voltage to volts (V), impedance to ohms (Ω), and temperature to degrees Celsius (°C)), converting the time format to year-month-day hour:minute:second (YYYY-MM-DD HH:MM:SS), retaining the accuracy of structural attribute parameters to 3 decimal places (e.g., pad size is 0.800mil), retaining the accuracy of electrical attribute parameters to 2 decimal places (e.g., rated current is 1.50A), and retaining the accuracy of basic attribute parameters to 3 decimal places (e.g., version number is V2.1.0).

[0066] In one possible implementation, extracting the first electrical parameters and first structural parameters of the first component may include:

[0067] Call the script interface; extract the first electrical parameters and first structural parameters of the first component in the design file through the preset second function in the script interface.

[0068] For example, when the PCB design tool is Cadence, the script interface is SKILL, and the default second function is the axlDBGetComponent function.

[0069] S106. Based on the first difference information and the second difference information, determine the risk information of the first component that has not been updated in the design document.

[0070] In one possible implementation, the risk information may include a risk value and first information, wherein the risk value can be determined by first difference information and second difference information.

[0071] In this embodiment, the design file of the circuit board is obtained, which includes the first electrical parameters and the first structural parameters of the first component on the board. The first electrical parameters and the first structural parameters are processed to obtain the first identifier corresponding to the first component. The current second electrical parameters, second structural parameters, and second identifier of the first component are obtained from the feature library. When the first identifier and the second identifier are different, it is determined that the first component in the design file has been updated in the feature library. The first difference information between the first electrical parameters and the second electrical parameters, and the second difference information between the first structural parameters and the second structural parameters are determined. Based on the first difference information and the second difference information, the risk information of the first component in the design file that has not been updated is determined. In the above method, by comparing the first identifier of the first component in the design file with the current second identifier in the feature library, and then combining the first electrical parameters, the first structural parameters, the second electrical parameters, and the second structural parameters to locate the differences, and dynamically assessing the risk information based on the difference dimension, the limitations of traditional reliance on package name or manual verification can be overcome. This method can accurately identify hidden package updates such as homonymous heterogeneous components, and solve the problem of failing to identify package updates in a timely manner in related technologies.

[0072] Based on the above embodiments, the third difference information can be used to indicate whether the first component has been updated, and the third difference information can also be used to indicate specific updated parameters in the first component.

[0073] Based on any of the above embodiments, the following, in conjunction with Figure 2 The method for determining the third difference information is explained in detail.

[0074] Figure 2 A flowchart illustrating a method for determining third difference information provided in this application embodiment is shown below. Figure 2 The method may include:

[0075] S201. Based on the first electrical parameter and the second electrical parameter, determine the first difference information; based on the first structural parameter and the second structural parameter, determine the second difference information.

[0076] In one possible implementation, the first difference information can be used to indicate whether there is a difference between the first electrical parameter and the second electrical parameter, and the first difference information can also be used to indicate which specific parameter of the first electrical parameter and the second electrical parameter is different.

[0077] In one possible implementation, the second difference information can be used to indicate whether there are differences between the first structural parameter and the second structural parameter, and the second difference information can also be used to indicate which specific parameter of the first structural parameter and the second structural parameter is different.

[0078] For example, the first electrical parameter and the second electrical parameter include: a rated current of 2.00A and a pin impedance of 50.00Ω.

[0079] For example, the first structural parameters and the second structural parameters include: the number of pads is 64 and the pad size is 13.780mil × 13.780mil.

[0080] It should be noted that the values ​​in the first electrical parameter and the first structural parameter have been standardized.

[0081] It should be noted that the units, precision, and format of each value in the first electrical parameter are consistent with those in the second electrical parameter; the units, precision, and format of each value in the first structural parameter are consistent with those in the second structural parameter.

[0082] In one possible implementation, a first deviation value between the first electrical parameter and the second electrical parameter can be calculated. This first deviation value is then compared with a preset difference range. If the first deviation value exceeds or falls outside the difference range, a difference is determined between the first electrical parameter and the second electrical parameter, thereby determining the first difference information. The first deviation value can be the difference between the second electrical parameter and the first electrical parameter (e.g., if the current in the first electrical parameter is 1.5A and the current in the second electrical parameter is 2A, then the second deviation value is 0.5A). For example, the difference range for the current parameter is greater than 0.5A, the difference range for the voltage parameter is greater than 10V, and the difference range for the impedance parameter is greater than 5Ω.

[0083] In one possible implementation, a second deviation value between the first structural parameter and the second structural parameter can be calculated. This second deviation value is then compared with a preset difference threshold. If the second deviation value exceeds the difference threshold, a difference is determined between the first structural parameter and the second structural parameter, thereby determining the second difference information. The second deviation value can be the difference between the second structural parameter and the first structural parameter. For example, when the design file is used for high-precision PCB / Ball Grid Array (BGA) packaging, the difference threshold is ±0.02 mm; when the design file is used for conventional precision PCB / BGA packaging, the difference threshold is ±0.05 mm.

[0084] S202. Determine the constraint information corresponding to the first component. The constraint information is used to indicate the constraint conditions for the first component to be installed on the board.

[0085] In one possible implementation, before determining the constraint information corresponding to the first component, the first structural parameters and the second structural parameters of the first component can be mapped to the same coordinate system in the design file. The origin of the coordinate system is the center coordinate of the first component in the design file. The horizontal axis of the coordinate system is parallel to the long side of the PCB board (or the reference side preset in the design file). The horizontal axis of the coordinate system is used to quantify the structural parameters of the first component in the horizontal direction (such as the horizontal spacing of the pads, the horizontal outline size of the package, the horizontal arrangement spacing of the pins, etc.). The vertical axis of the coordinate system is used to quantify the structural parameters of the first component in the vertical direction (such as the vertical spacing of the pads, the vertical outline size of the package, the vertical coordinate of the positioning hole, etc.).

[0086] It should be noted that when there are multiple components in the design file, the coordinate system of multiple components can be mapped sequentially. In this way, the interference caused by position offset can be effectively offset by the mapping operation of a unified coordinate system. This ensures that the comparison of structural parameters (such as pad spacing and solder ball position) focuses on the difference of the parameters themselves, rather than position error, thereby improving the reliability of the results when multiple components are tested in parallel.

[0087] In one possible implementation, the constraint information corresponding to the first component can be determined through a preset rule base. The preset rule base can be established by the user based on experience and manufacturing requirements.

[0088] For example, the constraint information corresponding to the first component includes: the minimum distance between the capacitor and other components, etc.

[0089] S203. Based on the first difference information, the second difference information, and the constraint information, determine the third difference information.

[0090] In some implementations, a third difference information is determined based on the first difference information, the second difference information, and the constraint information, including:

[0091] Based on the first difference information, a first result is obtained; based on the second difference information, a second result is obtained; it is determined whether the second structural parameters and the second electrical parameters satisfy the constraint information, and a third result is obtained; based on the first result, the second result, and the third result, the third difference information is determined.

[0092] In one possible implementation, the first result could be the potential impact of changes in electrical parameters analyzed based on an electrical performance correlation model. For example, if the rated current increases from 1.5A to 2A, it is necessary to determine whether the PCB trace width meets the standard (according to the IPC-2221 standard, the PCB trace width for a 2A current must be ≥0.5mm). If it does not meet the standard, it can be marked as "electrical performance change, trace risk".

[0093] In one possible implementation, the second result can be a two-dimensional (2D) / 3D comparison chart generated based on a parameter representing a second deviation value exceeding a difference threshold, and this comparison chart can be displayed to the user. This comparison chart can be rendered using an Open Graphics Library (OpenGL). For example, the parameter representing the second deviation value exceeding the difference threshold can be annotated using a heatmap (e.g., if the second deviation value is greater than 0.05 mm, it is marked in red on the heatmap; if the second deviation value is between 0.02 mm and 0.05 mm, it is marked in yellow). If the solder ball spacing changes from 0.5 mm to 0.48 mm, the position of the solder ball can be marked in red on the heatmap.

[0094] In one possible implementation, it can be determined whether the second structural parameter and the second electrical parameter satisfy the constraint information through a rule matching algorithm (such as a forward reasoning algorithm).

[0095] In one possible implementation, the third result can be entries that do not meet the constraint information, determined based on a rule base. For example, according to the IPC-2221 standard, the minimum requirement for pad-to-trace spacing is 0.1mm, and the pad-to-trace spacing in the second structural parameter is 0.08mm. Then, the parameter and standard basis for the pad-to-trace spacing that does not meet the constraint can be marked.

[0096] In one possible implementation, the third difference information may include the first result, the second result, and the third result.

[0097] In this embodiment, by determining the differences between the first and second structural parameters, the differences between the first and second electrical parameters, and constraint information, the limitations of traditional testing that focuses only on a single dimension of parameters can be overcome. For example, structurally, it can accurately identify subtle deviations such as reduced solder ball spacing; electrically, it can predict routing risks caused by increased rated current; and constraint verification can promptly detect compliance issues such as non-compliance of pad and trace spacing. Simultaneously, the embedding of industry standards provides a systematic approach to risk assessment, avoiding biases from subjective judgments, ensuring that test results comply with industry manufacturing and safety regulations, and reducing the probability of product failures due to design violations.

[0098] Based on any of the above embodiments, the following, in conjunction with Figure 3 and Figure 4 Each section provides a detailed explanation of the methods for determining risk information.

[0099] Figure 3 A flowchart illustrating a method for determining risk information provided in this application embodiment is shown below. Figure 3 The method may include:

[0100] S301. Determine the first weight, which is used to indicate the degree of influence of the first result, the second result, and the third result on the level of risk.

[0101] In one possible implementation, the first weight may include the weight corresponding to the first result, the weight corresponding to the second result, and the weight corresponding to the third result.

[0102] In some implementations, determining the first weight may include:

[0103] Obtain fault data caused by unidentified component updates from historical time periods. The fault data includes the correlation between the difference types of multiple component updates and the fault occurrence rate. Determine the first weight based on the correlation between the difference types and the fault occurrence rate.

[0104] For example, the correlation between the type of difference after component update and the failure rate is as follows: changes in structural parameters lead to a 15% welding failure rate.

[0105] In one possible implementation, fault data caused by unidentified component updates from historical periods can be input into the random forest algorithm to iteratively optimize the weight coefficients. The iteration converges when the model's prediction error rate is less than or equal to a preset error rate, thus determining the final weight coefficients. The preset error rate could be, for example, 3%.

[0106] S302. Based on the third difference information and the first weight, determine the risk information.

[0107] In one possible implementation, if the first result includes potential negative impacts that electrical parameter changes can bring, then the first sub-result can be 1; otherwise, the first sub-result can be 0. If the second result includes a 2D / 3D comparison chart generated based on parameters that exceed the difference threshold, then the second sub-result can be 1; otherwise, the second sub-result can be 0. If the third result includes entries that do not meet the constraint information, then the third sub-result can be 1; otherwise, the third sub-result can be 0.

[0108] In one possible implementation, the risk value can be obtained by weighting and summing the first sub-result, the second sub-result, and the third sub-result based on the weights corresponding to the first result, the second result, and the third result.

[0109] In one possible implementation, risk information may include risk value and third difference information.

[0110] In this embodiment, by quantizing the first, second, and third results into binary values ​​of 0 or 1, there is no need for complex multi-level scoring. Only the presence or absence of risk correlation characteristics is determined. Combined with a simple weighted summation algorithm, the computational complexity is greatly reduced, enabling the intelligent plug-in to output risk values ​​in real time. This meets the need for real-time verification during PCB design and avoids the time-consuming evaluation affecting the design schedule.

[0111] Figure 4 For a detailed flowchart illustrating another method for determining risk information provided in this application embodiment, please refer to [link / reference needed]. Figure 4 The method may include:

[0112] S401. In the first weight, determine the first sub-weight corresponding to the first result, the second sub-weight corresponding to the second result, the third sub-weight corresponding to the third result, and the fourth sub-weight corresponding to the version iteration.

[0113] In one possible implementation, the first weight can also be determined by the following method:

[0114] Method 1: Dynamically adjust weights based on the PCB design scenario: Weights for structural parameter changes, electrical parameter changes, version update changes, and unmet constraint information can be preset. It should be noted that the sum of these weights is 1.

[0115] For example, the weight for structural parameter changes is 0.35, the weight for electrical parameter changes is 0.25, the weight for non-compliance of constraint information is 0.15, and the weight for version iteration updates is 0.25.

[0116] Method 2, User-defined: Users can manually adjust the weights based on experience (e.g., in high-frequency RF PCB scenarios, the weight for signal transmission rate changes can be increased to 0.45).

[0117] In one possible implementation, the first sub-weight corresponding to the first result can be the electrical parameter change weight, the second sub-weight corresponding to the second result can be the structural parameter change weight, the third sub-weight corresponding to the third result can be the unmet constraint information weight, and the fourth sub-weight corresponding to the version iteration can be the version iteration update weight.

[0118] S402. Based on the first result, the first sub-weight, the second result, the second sub-weight, the third result, the third sub-weight, the version iteration result, and the fourth sub-weight, determine the risk information.

[0119] In one possible implementation, if a version update exists, the version iteration result is 1; otherwise, the version iteration result is 0.

[0120] In one possible implementation, the risk value can be obtained by weighted summation of the first sub-result, the second sub-result, the third sub-result, and the version iteration result based on the first sub-weight, the second sub-weight, the third sub-weight, and the fourth sub-weight.

[0121] For example, if the first sub-weight is S1, the second sub-weight is S2, the third sub-weight is S3, the fourth sub-weight is S4, the first sub-result is A, the second sub-result is B, the third sub-result is C, and the version iteration result is D, then the risk value H can be expressed by the following formula:

[0122] H = S1×A + S2×B + S3×C + S4×D

[0123] In this embodiment of the application, by expanding the risk assessment dimensions to four dimensions—structural differences, electrical differences, constraint conflicts, and version iterations—and adopting a weight configuration mechanism that combines dynamic scenario adaptation with user customization, the risk information is accurately quantified and scenario-based assessed. This can comprehensively cover the potential risks of component updates in board design and provide a more practical decision-making basis for design optimization.

[0124] Based on the above embodiments, after determining the risk information, the following can also be done:

[0125] Based on the risk information, generate a prompt message, which includes at least one of the following: the risk level of updating the first component, the difference information between the first component in the design file and the first component in the feature library; and display the prompt message.

[0126] In one possible implementation, the risk level can be updated based on the risk value. For example, if the risk value is greater than or equal to 85%, the risk level is updated to high risk, triggering a red emergency warning; if the risk value is greater than or equal to 60% and less than or equal to 85%, the risk level is updated to medium risk, triggering a yellow emergency warning; and if the risk value is less than 60%, the risk level is updated to low risk, triggering a blue emergency warning.

[0127] In one possible implementation, the difference information between the first component in the design file and the first component in the feature library can be represented in the form of text, matrix table, or graphical comparison chart.

[0128] For example, the difference information is a message that "the package has been updated to version V2.1.0";

[0129] The difference information is a feature difference matrix table (including parameter names, parameter values ​​of the first electrical parameter and the first structural parameter in the design file, parameter values ​​of the second electrical parameter and the second structural parameter in the feature library, the difference between each parameter value in the feature library and each parameter value in the design file, and verification results, such as "pad spacing: pad spacing in the feature library 0.48mm / pad spacing in the design file 0.5mm / difference between pad spacing in the feature library and pad spacing in the design file -0.02mm / exceeding the threshold (±0.02mm) / marked change"); the difference information is a graphical comparison view (showing old and new version package renderings side by side, with the difference areas highlighted).

[0130] One possible implementation is to display the prompt information in the property panel of the PCB design tool, or in a pop-up window.

[0131] In this embodiment, risk levels are defined as high, medium, and low based on risk values ​​ranging from 0% to 100%, corresponding to red, yellow, and blue emergency warnings, respectively. This enables a visual distinction of risk levels. Compared to a single numerical risk value, color-coded warnings allow engineers to quickly identify core risks during the design process. A red warning can immediately pause the current design and prioritize addressing critical issues; a yellow warning can be included in the subsequent optimization list; and a blue warning requires no further attention. This effectively reduces risk neglect caused by information overload and improves the timeliness of risk response.

[0132] In addition, the difference information supports text prompts, feature difference matrix tables, and graphical comparisons. Figure Three This multi-format approach caters to the diverse information needs of different roles and scenarios. For example, novice designers can quickly locate problems using graphical comparison charts, experienced engineers can conduct in-depth analysis of parameter deviations using matrix tables, and managers can grasp update overviews through text prompts. This multi-format presentation breaks the limitation of a single information format adapting to all scenarios, enhancing the practicality and ease of use of information.

[0133] Based on the above embodiments, the electronic device can provide operation options: ignore, update to the latest version, view details, so that the user can choose whether to update the first component.

[0134] Based on the above embodiments, users can operate on the intelligent judgment results. They can choose to view the details and then click the ignore option or click the update to the latest version option to adjust the data to be automatically synchronized to the result database for reference by other boards.

[0135] Based on the above embodiments, after the user clicks the option to update to the latest version, the electronic device automatically downloads the latest package, replaces the old package in the design, and verifies the integrity of the replaced design (such as network connection); the detection, prompt, and update operations are all recorded in the design change log, including time, user, package fingerprints before and after the change, and operation type, supporting audit traceability.

[0136] Based on the above embodiments, electronic devices can support exporting reports in Microsoft Excel (including raw data), Portable Document Format (PDF) (including charts), and Microsoft Word (including analysis conclusions). The reports automatically generate unique numbers (such as REPORT-20240510-001) for easy traceability.

[0137] In some implementations, before obtaining the current second electrical parameters, second structural parameters, and the second identifier of the first component determined based on the second electrical parameters and second structural parameters from the feature library, the following steps are also included:

[0138] The system receives a request to put a second component into storage. The request includes the storage conditions for the second component and the third electrical parameters and third structural parameters of the second component. When the third electrical parameters and third structural parameters meet the storage conditions, a fourth identifier for the second component is generated, and a fifth identifier for the second component is generated based on the third electrical parameters and third structural parameters. The fourth identifier, fifth identifier, third electrical parameters, and third structural parameters are stored in the feature library.

[0139] In one possible implementation, the third electrical parameter and the third structural parameter can be input by the user. The entry conditions are determined based on the instruction manual corresponding to the second component provided by the manufacturer. The instruction manual corresponding to the second component can be parsed by a feature extraction algorithm (such as PDFBox, a PDF parsing tool) to extract the parameter fields in the instruction manual.

[0140] In one possible implementation, if the third electrical parameter and / or the third structural parameter does not meet the entry conditions, a reminder is issued to the user. After the user reviews and confirms, the final feature parameter information can be entered into the feature library, and the package file can be moved to a preset path for the user to use when performing PCT design.

[0141] It is important to understand that the second component corresponds to multiple different versions of the package file. The name of the package file can include the fourth identifier of the second component and the version number of the second component. The package file corresponding to the second component includes the fourth identifier of the second component. The latest version of the package file can be moved and stored in a preset path, and the older version of the package file can be moved and stored in another preset path.

[0142] In one possible implementation, if the packaging of a component that has already been put into storage needs to be updated, the user needs to initiate a material change request. The electronic device searches for the identifier of the material to be changed, automatically retrieves historical parameter information from the feature database, and fills in the parameter information to be changed, including basic attributes, structural attributes, electrical attributes, manufacturing attributes, rule attributes, topology attributes, and the instruction manual corresponding to the component.

[0143] Next, after receiving the change request, the electronic device makes changes to the packaging design of the relevant components, puts the changed packaging file into the designated temporary path of the library, receives the warehousing request sent by the material requisition system, fills in the actual packaging design parameters online, and then after the user reviews and confirms, automatically moves the changed packaging file to the preset path, and the original packaging file to another preset path. Engineers can call the changed version when designing.

[0144] In one possible implementation, if the instruction manual corresponding to a component and the parameters corresponding to other attributes are changed simultaneously, the updated information entered by the user can be verified. For the updated information that passes the verification, the electronic device can use a feature extraction algorithm to parse the changed specification manual and compare it with the entered parameter information. If there is a difference, it will automatically remind you if there is an error. After review and confirmation, the final parameter information will be automatically entered into the feature library. When updating, the historical version (such as V2.0.0, V2.1.0) and the original package file path are retained, the update timestamp and version information are recorded, and the changed package file is moved to the preset path.

[0145] Based on the above embodiments, different versions of the same package are associated through the material identifier (such as the third identifier in the above embodiments), supporting the backtracking of historical versions (e.g., to view the parameter differences between V2.0.0 and V2.1.0).

[0146] In one possible implementation, for the updated parameter information, a new identifier (such as the second identifier in the above embodiment) can be generated using feature encoding rules (such as hash algorithms such as SHA-256), and the new identifier, change time, operator, and other information are stored in the feature database to achieve complete traceability. It should be noted that the old identifier is also stored in the feature database, and the old identifier and the new identifier can be distinguished by version number.

[0147] Next, the currently valid identifier of the encapsulation in the feature library can be updated (such as the second identifier in the above embodiment).

[0148] It should be noted that after each new identifier is generated, the system automatically performs a consistency check: the original features can be used to reverse-verify the identifier to ensure the stability of the feature encoding rules.

[0149] In one possible implementation, the electronic device may include a heartbeat detection module, a PCB feature parsing module, a feature library communication module, an intelligent verification module, and a result visualization module.

[0150] The heartbeat detection module can continuously send requests to the PCB feature parsing module to obtain the identifiers of components in the design file (such as the first identifier and the third identifier in the above embodiment). The heartbeat detection module can also send requests to the feature library communication module to obtain the identifiers of components in the feature library (such as the first identifier and the third identifier in the above embodiment), electrical parameters, and structural parameters. The PCB feature parsing module can be used to parse the identifiers of components in the design file (such as the first identifier and the third identifier in the above embodiment).

[0151] The feature library communication module can send a request to the feature library to obtain identifiers (such as the first and third identifiers in the above embodiment) to obtain the identifiers (such as the first and third identifiers in the above embodiment), electrical parameters, and structural parameters of the components in the feature library. After receiving the identifiers (such as the first and third identifiers in the above embodiment), electrical parameters, and structural parameters of the components in the feature library, the feature library communication module can also determine whether the identifiers (such as the first and third identifiers in the above embodiment) of the components in the feature library are consistent with the identifiers (such as the first and third identifiers in the above embodiment) in the design file. If the feature library communication module determines that the identifiers (such as the first and third identifiers in the above embodiment) of the components in the feature library are inconsistent, it can also send a request to the intelligent verification module to obtain the differences between the components in the design file and the components in the feature library. This request includes: the identifiers (such as the first and third identifiers in the above embodiment) of the components in the design file, the identifiers (such as the first and third identifiers in the above embodiment), electrical parameters, and structural parameters of the components in the feature library. The intelligent verification module can input the obtained differences between the components in the design file and the components in the feature library into the result visualization module.

[0152] The results visualization module can determine whether the components in the feature library are valid updates. If so, the results visualization module can perform encapsulation replacement and log the changes upon receiving a user's request to update the components. If not, the results visualization module can add annotation data and log the changes.

[0153] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0154] Figure 5 This is a schematic diagram of the board design device provided in an embodiment of this application. Figure 5 As shown, embodiments of this application also provide a board design apparatus 500, including: a first acquisition module 501, a first processing module 502, a second acquisition module 503, a first determination module 504, a second determination module 505, and a third determination module 506, wherein,

[0155] The first acquisition module 501 is used to acquire the design file of the board, which includes the first electrical parameters and first structural parameters of the first component on the board.

[0156] The first processing module 502 is used to process the first electrical parameters and the first structural parameters to obtain the first identifier corresponding to the first component;

[0157] The second acquisition module 503 is used to acquire the current second electrical parameters, second structural parameters, and second identifier of the first component determined based on the second electrical parameters and second structural parameters from the feature library.

[0158] The first determining module 504 is used to determine that the first component in the design file has been updated in the feature library when the first identifier and the second identifier are different.

[0159] The second determining module 505 is used to determine the first difference information between the first electrical parameter and the second electrical parameter, and the second difference information between the first structural parameter and the second structural parameter;

[0160] The third determination module 506 is used to determine the risk information of the first component that has not been updated in the design file based on the first difference information and the second difference information.

[0161] The board design device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0162] In one possible implementation, the second determining module 505 is specifically used for:

[0163] Based on the first electrical parameter and the second electrical parameter, determine the first difference information; based on the first structural parameter and the second structural parameter, determine the second difference information.

[0164] Determine the constraint information corresponding to the first component. The constraint information is used to indicate the constraint conditions for the first component to be installed on the board.

[0165] Based on the first difference information, the second difference information, and the constraint information, the third difference information is determined.

[0166] In one possible implementation, the second determining module 505 is specifically used for:

[0167] Based on the first difference information, the first result is obtained;

[0168] Based on the second difference information, a second result is obtained;

[0169] Determine whether the second structural parameters and the second electrical parameters satisfy the constraint information to obtain the third result;

[0170] Based on the first, second, and third results, the third difference information is determined.

[0171] In one possible implementation, the third determining module 506 is specifically used for:

[0172] Determine the first weight, which is used to indicate the degree of influence of the first, second, and third outcomes on the level of risk;

[0173] Risk information is determined based on the third difference information and the first weight.

[0174] In one possible implementation, the third determining module 506 is specifically used for:

[0175] In the first weight, determine the first sub-weight corresponding to the first result, the second sub-weight corresponding to the second result, the third sub-weight corresponding to the third result, and the fourth sub-weight corresponding to the version iteration;

[0176] Risk information is determined based on the first result, the first sub-weight, the second result, the second sub-weight, the third result, the third sub-weight, the version iteration result, and the fourth sub-weight.

[0177] In one possible implementation, the third determining module 506 is specifically used for:

[0178] Acquire fault data from historical periods caused by updates of unidentified components. The fault data includes the correlation between the types of differences after multiple component updates and the fault occurrence rate.

[0179] The first weight is determined based on the correlation between the difference type and the failure rate.

[0180] In one possible implementation, the second acquisition module 503 is specifically used for:

[0181] Send a first request to the feature library. The first request includes the third identifier and the first identifier of the first component.

[0182] The response to the first request sent by the feature library includes a third identifier of the first component, a second electrical parameter, a second structural parameter, and a second identifier of the first component determined based on the second electrical parameter and the second structural parameter.

[0183] In one possible implementation, the board design apparatus further includes a second processing module 507, which is configured to:

[0184] Receive a warehouse entry request for a second component, the warehouse entry request including the warehouse entry conditions for the second component and the third electrical parameters and third structural parameters of the second component;

[0185] When the third electrical parameters and the third structural parameters meet the warehousing conditions, a fourth identifier for the second component is generated, and a fifth identifier for the second component is generated based on the third electrical parameters and the third structural parameters.

[0186] The fourth identifier, fifth identifier, third electrical parameter, and third structural parameter are stored in the feature library.

[0187] In one possible implementation, the board design apparatus further includes a third processing module 508, which is configured to:

[0188] Based on the risk information, generate a prompt message, which includes at least one of the following: the risk level of updating the first component, and the difference information between the first component in the design file and the first component in the feature library;

[0189] A prompt message will be displayed.

[0190] The board design device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0191] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device 600 provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the electronic device 600 further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus.

[0192] In the specific implementation process, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to execute the above-described board design method embodiment.

[0193] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0194] In the above embodiments, it should be understood that the processor can be a CPU, or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules within the processor.

[0195] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0196] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0197] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described board design method embodiments at runtime.

[0198] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0199] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described board design method embodiments.

[0200] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described board design method embodiments.

[0201] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0202] The foregoing has provided a detailed description of a board design method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A circuit board design method, characterized in that, include: Obtain the design file of the board, the design file including the first electrical parameters and the first structural parameters of the first component on the board; The first electrical parameters and the first structural parameters are processed to obtain the first identifier corresponding to the first component; Obtain the current second electrical parameters, second structural parameters, and second identifier of the first component determined based on the second electrical parameters and second structural parameters from the feature library; When the first identifier is different from the second identifier, it is determined that the first component in the design file has been updated in the feature library; Determine the first difference information between the first electrical parameter and the second electrical parameter, and the second difference information between the first structural parameter and the second structural parameter; Based on the first difference information and the second difference information, the risk information of the first component that has not been updated in the design file is determined.

2. The method according to claim 1, characterized in that, Determining the first difference information between the first electrical parameter and the second electrical parameter, and the second difference information between the first structural parameter and the second structural parameter, includes: Based on the first electrical parameter and the second electrical parameter, determine the first difference information; based on the first structural parameter and the second structural parameter, determine the second difference information. Determine the constraint information corresponding to the first component, wherein the constraint information is used to indicate the constraint conditions under which the first component is installed on the board; Based on the first difference information, the second difference information, and the constraint information, the third difference information is determined.

3. The method according to claim 2, characterized in that, Determining the third difference information based on the first difference information, the second difference information, and the constraint information includes: Based on the first difference information, a first result is obtained; Based on the second difference information, a second result is obtained; Determine whether the second structural parameters and the second electrical parameters satisfy the constraint information to obtain a third result; Based on the first result, the second result, and the third result, the third difference information is determined.

4. The method according to claim 3, characterized in that, The step of determining the risk information of the first component that has not been updated in the design file based on the first difference information and the second difference information includes: A first weight is determined, which is used to indicate the degree of influence of the first result, the second result, and the third result on the level of risk. The risk information is determined based on the third difference information and the first weight.

5. The method according to claim 4, characterized in that, The first weight also indicates the degree of impact of the version iteration of the first component on the risk level; Based on the third difference information and the first weight, the risk information is determined, including: In the first weight, a first sub-weight corresponding to the first result, a second sub-weight corresponding to the second result, a third sub-weight corresponding to the third result, and a fourth sub-weight corresponding to the version iteration are determined; The risk information is determined based on the first result, the first sub-weight, the second result, the second sub-weight, the third result, the third sub-weight, the version iteration result, and the fourth sub-weight.

6. The method according to claim 4 or 5, characterized in that, Determine the first weight, including: Acquire fault data caused by unidentified component updates in historical time periods, including the correlation between the types of differences after multiple component updates and the fault occurrence rate; The first weight is determined based on the correlation between the difference type and the failure rate.

7. The method according to any one of claims 1-5, characterized in that, The step of obtaining the current second electrical parameters, second structural parameters, and second identifier of the first component determined based on the second electrical parameters and second structural parameters from the feature library includes: Send a first request to the feature library, the first request including the third identifier of the first component and the first identifier; The response to the first request sent by the feature library includes a third identifier of the first component, a second electrical parameter, a second structural parameter, and a second identifier of the first component determined based on the second electrical parameter and the second structural parameter.

8. The method according to any one of claims 1-5, characterized in that, Before obtaining the current second electrical parameters, second structural parameters, and second identifier of the first component determined based on the second electrical parameters and second structural parameters from the feature library, the method further includes: Receive a warehouse entry request for a second component, the warehouse entry request including the warehouse entry conditions for the second component and the third electrical parameters and third structural parameters of the second component; When the third electrical parameter and the third structural parameter meet the warehousing conditions, a fourth identifier for the second component is generated, and a fifth identifier for the second component is generated based on the third electrical parameter and the third structural parameter. The fourth identifier, the fifth identifier, the third electrical parameter, and the third structural parameter are stored in the feature library.

9. The method according to claim 8, characterized in that, After determining the risk information, the method further includes: Based on the risk information, a prompt message is generated, which includes at least one of the following: the update risk level of the first component, and the difference information between the first component in the design file and the first component in the feature library; The aforementioned prompt message will be displayed.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the board design method as described in any one of claims 1 to 9.

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