Solution method and device for K-SAT problem and solver

Abstract

This application provides a method, apparatus, and solver for solving the K-SAT problem, relating to the field of K-SAT problem solving technology. The method includes: determining whether the formula to be solved meets preset computational conditions and obtaining a determination result; if the formula meets the preset computational conditions, then performing inference and solving the formula based on a branch-parallel mode; otherwise, performing inference and solving the formula based on a collaborative inference mode until a preset termination condition is met; wherein, the preset computational conditions are used to determine the computational scale of the formula to be solved; the preset termination condition includes any one of the following: any solution space among the multiple solution spaces of the formula to be solved has a feasible solution; or none of the multiple solution spaces of the formula to be solved have a feasible solution. The method, apparatus, and solver for solving the K-SAT problem provided in this application greatly improve the adaptability to different application scenarios by introducing an event-driven task scheduling mechanism, a reconfigurable buffer management mechanism, and a cross-core coordination analysis mechanism.

Description

Technical Field

[0001] This application relates to the field of K-SAT problem solving technology, and in particular to a method, apparatus and solver for K-SAT problems. Background Technology

[0002] The Boolean satisfiability problem (K-SAT, K≥3) is one of the most representative NP-complete problems in computer science. Its core task is to determine whether there exists a set of truth assignments for Boolean variables such that all clauses expressed in conjunctive normal form (CNF) are satisfied.

[0003] In related technologies, solvers for the K-SAT problem only support fixed-mode solutions. These solvers can achieve efficient solutions for SAT problems near the design size.

[0004] However, while the solvers in related technologies reduce the design complexity of storage and computation by eliminating the need to consider the collaborative operation between multiple cores, they limit their adaptability to different application scenarios and cannot flexibly adapt to solving SAT problems of different scales. Summary of the Invention

[0005] The purpose of this application is to provide a solution method, apparatus and solver for the K-SAT problem. By introducing an event-driven task scheduling mechanism, a reconfigurable buffer management mechanism and a cross-core coordination analysis mechanism, the adaptability to different application scenarios is greatly improved.

[0006] This application provides a method for solving the K-SAT problem, including: The process involves obtaining a formula to be solved and determining whether it meets preset calculation conditions, thus obtaining a determination result. If the determination result indicates that the formula meets the preset calculation conditions, the process controls multiple computing cores to perform inference and solution on the formula based on the branch-parallel mode. Otherwise, the process controls multiple computing cores to perform inference and solution on the formula based on the collaborative inference mode until a preset termination condition is met. The preset calculation conditions are used to determine the computational scale of the formula to be solved. The preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, but none of the computing cores trigger the target signal. The target signal is triggered when a feasible solution exists in any of the multiple solution spaces of the formula to be solved.

[0007] Optionally, determining whether the formula to be solved meets the preset calculation conditions and obtaining the determination result includes: if any one of the plurality of calculation cores meets the calculation requirements of the formula to be solved, determining whether the formula to be solved meets the preset calculation conditions; if any one of the plurality of calculation cores does not meet the calculation requirements of the formula to be solved, determining whether the formula to be solved does not meet the preset calculation conditions.

[0008] Optionally, controlling the multiple computing cores to perform inference and solution on the formula to be solved based on the branch parallel mode until a preset termination condition is met includes: dividing the calculation task of the formula to be solved into multiple subtasks according to different solution spaces; one subtask corresponds to one solution space; and assigning the multiple subtasks to the multiple computing cores for inference and solution until the preset termination condition is met.

[0009] Optionally, the step of assigning the plurality of subtasks to the plurality of computing cores for inference and solution until the preset termination condition is met includes: determining that the formula to be solved has a feasible solution when the target signal triggered by any computing core is received; wherein, the target signal is triggered when the calculation result of any computing core among the plurality of computing cores indicates that the corresponding subtask is judged to be satisfyable.

[0010] Optionally, the step of assigning the multiple subtasks to the multiple computing cores for inference and solution until the preset termination condition is met includes: if the multiple computing cores have completed the inference and solution of the multiple subtasks and have not received the target signal, determining that the formula to be solved has no feasible solution.

[0011] Optionally, the step of reasoning and solving the formula to be solved based on the collaborative reasoning mode until a preset termination condition is met includes: dividing the formula to be solved into multiple formula clauses and assigning the multiple formula clauses to the multiple computing cores for reasoning and solving; assigning one formula clause to each computing core; and cyclically executing the target reasoning operation based on the calculation result of each computing core until the preset termination condition is met; wherein, the target reasoning operation includes: an implication graph construction operation performed when no conflict is determined, and a conflict analysis operation performed when a conflict is determined; the implication graph construction operation is used to assign values ​​to unassigned text in the clauses of the computing cores and broadcast the assigned texts to other computing cores; the conflict analysis operation is used to determine the source of the conflict and backtrack all cores to the node before the source of the conflict.

[0012] Optionally, the implication graph construction operation includes: obtaining the clause state of the clause corresponding to each of the plurality of computing cores, and selecting a non-satisfied clause based on the clause state; the non-satisfied clause contains at least one unassigned literal; assigning a value to any one of the at least one unassigned literal, and broadcasting the assigned literal to all computing cores to update the value of the corresponding literal in each computing core; wherein, the clause corresponding to any computing core includes at least one of the following: a formula clause, a learning clause; the non-satisfied clause is: the clause contains a variable that has not been assigned a value, and the result of the clause is not 1.

[0013] Optionally, the conflict analysis operation includes: determining a globally unique implication point based on the unique implication point information of each computational core, and generating a learning clause and a non-temporally ordered backtracking hierarchy based on the globally unique implication point; sending the learning clause to the computational core corresponding to the globally unique implication point, and backtracking all cores to the node preceding the conflict source based on the non-temporally ordered backtracking hierarchy; wherein, the unique implication point information is used to represent: the first and only implication point in the computational core; the learning clause is used to represent the key text combination that induces the conflict.

[0014] This application also provides a solution apparatus for the K-SAT problem, comprising: A judgment module is used to obtain the formula to be solved and determine whether the formula to be solved meets the preset calculation conditions, and obtain a judgment result. A reasoning module is used to control the multiple computing cores to perform reasoning and solving on the formula to be solved based on the branch parallel mode if the judgment result indicates that the formula to be solved meets the preset calculation conditions; otherwise, it controls the multiple computing cores to perform reasoning and solving on the formula to be solved based on the collaborative reasoning mode until a preset termination condition is met. The preset calculation conditions are used to determine the computational scale of the formula to be solved. The preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, but none of the computing cores trigger the target signal. The target signal is triggered when a feasible solution exists in any of the multiple solution spaces of the formula to be solved.

[0015] Optionally, the judgment module is specifically used to determine whether the formula to be solved meets the preset calculation conditions when any one of the plurality of computing cores meets the calculation requirements of the formula to be solved; the judgment module is also specifically used to determine whether the formula to be solved does not meet the preset calculation conditions when any one of the plurality of computing cores does not meet the calculation requirements of the formula to be solved.

[0016] Optionally, the reasoning module is specifically used to divide the calculation task of the formula to be solved into multiple sub-tasks according to different solution spaces; one sub-task corresponds to one solution space; the reasoning module is also specifically used to assign the multiple sub-tasks to the multiple computing cores for reasoning and solving until the preset termination condition is met.

[0017] Optionally, the inference module is specifically configured to determine that the formula to be solved has a feasible solution when it receives the target signal triggered by any computing core; wherein the target signal is triggered when the calculation result of any of the plurality of computing cores indicates that the corresponding subtask is judged to be satisfyable.

[0018] Optionally, the inference module is specifically used to determine that the formula to be solved does not have a feasible solution when the multiple computing cores have completed the inference and solution of the multiple sub-tasks and have not received the target signal.

[0019] Optionally, the inference module is specifically used to divide the formula to be solved into multiple formula clauses and assign the multiple formula clauses to the multiple computing cores for inference and solution; one formula clause is assigned to each computing core; the inference module is further used to cyclically execute the target inference operation based on the calculation result of each computing core until the preset termination condition is met; wherein, the target inference operation includes: an implication graph construction operation performed when no conflict is determined, and a conflict analysis operation performed when a conflict is determined; the implication graph construction operation is used to assign values ​​to the unassigned text in the clauses of the computing cores and broadcast the assigned texts to other computing cores; the conflict analysis operation is used to determine the source of the conflict and backtrack all cores to the node before the source of the conflict.

[0020] Optionally, the inference module is specifically used to obtain the clause state of the clause corresponding to each of the plurality of computing cores, and select the unsatisfied clause based on the clause state; the unsatisfied clause contains at least one unassigned literal; the inference module is further used to assign a value to any one of the at least one unassigned literal, and broadcast the assigned literal to all computing cores to update the value of the corresponding literal in each computing core; wherein, the clause corresponding to any computing core includes at least one of the following: a formula clause, a learning clause; the unsatisfied clause is: the clause contains a variable that has not been assigned a value, and the result of the clause is not 1.

[0021] Optionally, the inference module is specifically used to determine a globally unique implication point based on the unique implication point information of each computing core, and to generate a learning clause and a non-temporally ordered backtracking hierarchy based on the globally unique implication point; the inference module is further used to send the learning clause to the computing core corresponding to the globally unique implication point, and to backtrack all cores to the node preceding the source of the conflict based on the non-temporally ordered backtracking hierarchy; wherein, the unique implication point information is used to represent: the first and only implication point in the computing core; the learning clause is used to represent the key text combination that induces the conflict.

[0022] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the solution method for the K-SAT problem as described above.

[0023] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the above-described methods for solving the K-SAT problem.

[0024] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the solution method for the K-SAT problem as described above.

[0025] The method, apparatus, and solver for solving the K-SAT problem provided in this application first obtain the formula to be solved and determine whether the formula satisfies preset calculation conditions, obtaining a judgment result. Then, if the judgment result indicates that the formula satisfies the preset calculation conditions, the multiple computing cores are controlled to perform inference and solution on the formula based on the branch-parallel mode; otherwise, the multiple computing cores are controlled to perform inference and solution on the formula based on the collaborative inference mode until a preset termination condition is met. The preset calculation conditions are used to determine the computational scale of the formula to be solved. The preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, but all computing cores not triggering the target signal; the target signal is triggered when a feasible solution exists in any of the multiple solution spaces of the formula to be solved. Thus, by introducing an event-driven task scheduling mechanism, a reconfigurable buffer management mechanism, and a cross-core coordination analysis mechanism, the adaptability to different application scenarios is greatly improved. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the multi-core architecture solver provided in this application; Figure 2 This is a schematic diagram of the circuit structure of the solver provided in this application in branch-parallel mode; Figure 3 This is a flowchart illustrating the solution method for the K-SAT problem provided in this application; Figure 4 This is a schematic diagram of the inference logic flow in the branch parallel mode provided in this application; Figure 5 This is a schematic diagram of the circuit structure under the collaborative reasoning mode provided in this application; Figure 6 This is a schematic diagram of the reasoning logic flow under the collaborative reasoning mode provided in this application; Figure 7 This is a schematic diagram of the structure of the solver for the K-SAT problem provided in this application; Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] 3-SAT is a typical form of the K-SAT problem, and this embodiment uses the 3-SAT problem as an example for description. Specifically, the input to the 3-SAT problem is a Boolean formula F(x), which consists of several clauses C, each of which is a disjunctive expression containing three Boolean variables. If it is possible to find a variable assignment such that all clauses in F(x) are true, then F(x) is said to be satisfiable (SAT); if no such assignment exists, then it is said to be unsatisfiable.

[0031] In related technologies, all ASIC solutions for the 3-SAT problem only support fixed-mode solutions. These solvers can efficiently solve SAT problems near the design scale. Since they do not require consideration of multi-core coordination, they significantly reduce storage and computational design complexity. However, this design philosophy limits their adaptability to different application scenarios. Modal reconfigurable multi-core architectures differ. They integrate event-driven task scheduling mechanisms, reconfigurable buffer management mechanisms, and cross-core coordination and analysis mechanisms, thereby reusing core resources on demand to support efficient solutions to SAT problems of different scales. Therefore, they face higher storage and management requirements in hardware design. How to efficiently switch between problem-solving modes can fill the gap in modal reconfigurable hardware acceleration in solution architectures, providing strong support for reconfigurable solutions in complex applications such as formal verification, EDA, and fault diagnosis.

[0032] Existing ASIC hardware designs for the 3-SAT problem are all fixed-mode single-core architectures. While simple and easy to implement, this architecture cannot handle SAT problems of varying sizes and has poor adaptability. When accelerating SAT formula solving, if the formula size is less than the design limit, many internal hardware resources remain idle, leading to a significant decrease in hardware resource utilization. Conversely, if the formula size far exceeds the hardware capacity, the formula must be split and solved in blocks. This results in frequent memory accesses and result verification during sub-block solving, leading to a significant decrease in overall performance.

[0033] To address the aforementioned technical problems in related technologies, this application provides a multi-core architecture solver, which includes multiple computing cores; the solver's operating modes include a branch-parallel mode and a collaborative reasoning mode; the branch-parallel mode is used to control the multiple cores to solve different solution spaces of Boolean formulas in parallel; the collaborative reasoning mode is used to control the multiple cores to collaboratively solve Boolean formulas.

[0034] For example, such as Figure 1The diagram illustrates the solver's operating mechanism in different modes. Taking 3-SAT as an example, to adapt to input formulas F(x) of different scales, the solver adopts a mode-reconfigurable quad-core architecture. In this architecture, for smaller-scale SAT problems, the solver is configured in branch-parallel mode, where the four cores store the same complete input formula. Each core explores different branches of the solution space in parallel according to the task scheduler (i.e., the aforementioned control unit), achieving thread-level parallel solving. For larger-scale SAT problems, the solver switches to collaborative reasoning mode, where the complete input formula is divided into four parts and stored in the four cores respectively. Data between the cores is broadcast communication, and collaborative reasoning among the four cores is completed with the help of the global result integrator (i.e., the aforementioned control unit), achieving data-level parallel solving.

[0035] For example, such as Figure 2 The diagram shows the circuit structure of the solver in branch-parallel mode. The system introduces an event-driven task scheduling mechanism. Each of the four cores communicates with the task scheduler, which schedules and allocates tasks based on the state of each core through an arbitrator.

[0036] The following description, in conjunction with the accompanying drawings, details the solution method for the K-SAT problem provided in this application through specific embodiments and application scenarios.

[0037] like Figure 3 As shown in the embodiment of this application, a method for solving the K-SAT problem is provided, which may include the following steps 301 and 302: Step 301: Obtain the formula to be solved and determine whether the formula to be solved meets the preset calculation conditions, and obtain the judgment result.

[0038] The preset calculation conditions are used to determine the calculation scale of the formula to be solved.

[0039] For example, by determining whether preset calculation conditions are met, the size of the formula to be solved can be determined, and then the corresponding mode can be selected for reasoning and solving.

[0040] Specifically, step 301 above may also include the following steps 301a1 and 301a2: Step 301a1: If any one of the plurality of computing cores satisfies the computational requirements of the formula to be solved, determine whether the formula to be solved satisfies the preset computational conditions.

[0041] Step 301a2: If any one of the multiple computing cores does not meet the computational requirements of the formula to be solved, determine whether the formula to be solved does not meet the preset computational conditions.

[0042] For example, if the above-mentioned preset calculation conditions are met, it means that the size of the formula to be solved is small, and the calculation can be completed using a single computing core. If the above-mentioned preset calculation conditions are not met, it means that the size of the formula to be solved is large, and multiple computing cores are required for collaborative reasoning to solve it.

[0043] Step 302: If the judgment result indicates that the formula to be solved meets the preset calculation conditions, then control the multiple computing cores to perform reasoning and solving on the formula to be solved based on the branch parallel mode; otherwise, control the multiple computing cores to perform reasoning and solving on the formula to be solved based on the collaborative reasoning mode until the preset termination condition is met.

[0044] The preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, and none of the computing cores trigger the target signal; the target signal is triggered when a feasible solution exists in any of the multiple solution spaces of the formula to be solved.

[0045] For example, after determining the operating mode based on the scale, reasoning can be performed to solve the K-SAT problem.

[0046] Specifically, for inference and solution based on the branch-parallel mode, step 302 above may further include the following steps 302a and 302b: Step 302a: Divide the calculation task of the formula to be solved into multiple sub-tasks according to the different solution spaces.

[0047] Each subtask corresponds to a solution space.

[0048] Step 302b: Assign the multiple subtasks to the multiple computing cores for inference and solution until the preset termination condition is met.

[0049] Specifically, step 302b above may also include step 302b1, or step 302b2: Step 302b1: Upon receiving the target signal triggered by any computing core, determine that the formula to be solved has a feasible solution.

[0050] The target signal is triggered when the subtask corresponding to the calculation result of any one of the plurality of computing cores is determined to be satisfactory.

[0051] Step 302b2: If the multiple computing cores have completed the inference and solution of the multiple sub-tasks and have not received the target signal, it is determined that the formula to be solved does not have a feasible solution.

[0052] For example, such as Figure 4 As shown, in branch-parallel mode, for a relatively small formula F(x), the system stores the same complete input formula on all four cores. The task scheduler divides the solution space into 32 sub-branches, each corresponding to an initial sequence of five characters, indicating a solution task. When a core receives a task and begins solving, each core independently maintains its own local buffer region for constructing the implication graph and performing conflict analysis for its respective task. In the initial stage of solving the SAT problem, the task scheduler loads a task for each core sequentially, and each core solves the task in parallel to verify its satisfiability. 1. If the current task is determined to be UNSAT (unsatisfiable) by a single core, it means that no feasible solution can be found for the current task. At this time, the core returns a local UNSAT signal and requests a new task from the task scheduler.

[0053] 2. If the current task is determined to be SAT (Satisfiable) by a single core, it means that there is a feasible solution in the solution space corresponding to the task. This means that the problem is satisfiable. At this time, the corresponding core will return a local SAT signal (i.e. the target signal mentioned above) to trigger the global SAT signal to be issued.

[0054] When all tasks have been verified and no solution has been found, the task scheduler will determine that the problem is unsolvable and unsatisfiable, and at this time the task scheduler will issue a global UNSAT signal.

[0055] For example, such as Figure 4 As shown, after the four cores receive their respective tasks, the task scheduler enters an idle state, and each core enters its own solution phase. Cores 0-2 return local UNSAT signals to the task scheduler at different times. At this point, the scheduler re-enters the working state and reassigns new tasks to the cores according to the order in which they returned the signals. After receiving a new task, the cores re-enter the solution phase. When core 0 returns a local SAT signal, it confirms that the problem is satisfiable. At this point, all cores stop working, and the scheduler issues a global SAT signal.

[0056] Specifically, for reasoning solutions based on collaborative reasoning patterns, step 302 above may further include the following steps 302c and 302d: Step 302c: Divide the formula to be solved into multiple formula clauses, and assign the multiple formula clauses to the multiple computing cores for reasoning and solving.

[0057] One calculation core is assigned one formula clause.

[0058] Step 302d: Based on the calculation results of each computing core, perform the target inference operation repeatedly until the preset termination condition is met.

[0059] The target reasoning operation includes: an implication graph construction operation performed when no conflict is determined, and a conflict analysis operation performed when a conflict is determined; the implication graph construction operation is used to assign values ​​to unassigned literals in the clauses of the computational cores and broadcast the assigned literals to other computational cores; the conflict analysis operation is used to determine the source of the conflict and backtrack all cores to the node preceding the source of the conflict.

[0060] Specifically, for the implication graph construction operation, step 302d above may also include the following steps 302d1 and 302d2: Step 302d1: Obtain the clause state of each clause corresponding to the multiple computing cores, and select the clauses that are not satisfied based on the clause state.

[0061] The unsatisfied clause contains at least one unassigned literal.

[0062] Step 302d2: Assign a value to any of the at least one unassigned characters, and broadcast the assigned character to all computing cores to update the value of the corresponding character in each computing core.

[0063] The clause corresponding to any calculation core includes at least one of the following: a formula clause, a learning clause; the clause that does not meet the requirements is: there is a variable in the clause that has not been assigned a value, and the result of the clause is not 1.

[0064] For example, combined Figure 5 ,like Figure 6 As shown, the hardware implements cross-core problem coordination reasoning through a global result integrator. The four cores communicate via broadcast through the global result integrator, which integrates the states of all formula clauses and the states of learning clauses. Based on the clause state, a clause that does not meet the requirements (the clause contains unassigned variables and the clause is not 1) is selected, and an unassigned text in the clause (variables are divided into positive and negative texts) is assigned a value and broadcast, thereby promoting the decision-making and propagation of text.

[0065] It should be noted that after selecting the unsatisfied clauses, the global result integrator informs the computation core to which the unsatisfied clauses belong. The computation core then assigns a value to the unsatisfied clause and broadcasts the assignment result to other computation cores. If the same text exists in other computation cores, they will update it based on the received assignment result.

[0066] Specifically, for performing conflict analysis, step 302d above may also include the following steps 302d3 and 302d4: Step 302d3: Based on the unique entailment information of each computational core, determine the globally unique entailment point, and generate learning clauses and non-temporally sequential backtracking levels based on the globally unique entailment point.

[0067] Step 302d4: Send the learning clause to the computational core corresponding to the globally unique implication point, and backtrack all cores to the node preceding the source of the conflict based on the non-temporal backtracking hierarchy.

[0068] The unique implication point information is used to represent the first and only implication point in the computational core; the learning clause is used to represent the key text combination that induces the conflict.

[0069] For example, combined Figure 5 ,like Figure 6 As shown, during conflict analysis, the global result integrator monitors the first unique implication point information of each core, thereby determining the global first unique implication point and ending the conflict analysis to generate the key text combination (i.e., the learning clause) that triggered the conflict and the non-temporally ordered backtracking hierarchy. To ensure that the four cores can complete the implication graph construction and conflict analysis in an orderly manner, the system merges the cache units of each core into a shared cache unit, realizing the integration of storage resources and centralized management of global inference data.

[0070] In one possible implementation, this application embodiment also provides a cache access strategy that employs sequential write / read control: During the implication graph construction phase, the system will only switch to the next cache unit once the current cache unit is full. During the conflict analysis phase, the system will only switch to the previous cache unit once all data in the current cache unit has been read (i.e., the cache is empty).

[0071] For example, the aforementioned collaborative reasoning mode can guarantee data consistency and access order during multi-core collaborative solving. The pattern-aware reconfigurable cache management mechanism ensures independent and efficient execution of the system in branch-parallel mode, as well as stable and efficient operation in collaborative reasoning mode, thereby achieving unified storage management and resource scheduling across modes.

[0072] Through the aforementioned mechanism, the modally reconfigurable multi-core architecture in this application embodiment can flexibly adjust the solution mode according to the scale of the formula of the problem to be solved. Under different working modes, this design effectively improves the utilization of hardware resources, enhances the system's adaptability to problems of different scales, provides solid hardware support for achieving completeness analysis of non-time-sequential backtracking in various application scenarios, and accelerates the practical application of SAT solution hardware acceleration technology.

[0073] The solution method for the K-SAT problem provided in this application differs significantly in its implementation mechanism from the fixed-mode single-core architecture of traditional SAT hardware acceleration: 1. Pattern-aware reconfigurable cache management design Pattern-aware, reconfigurable cache management design employs differentiated cache management strategies under different operating modes, enabling each core cache unit to efficiently complete implication graph construction and conflict analysis independently or in a shared manner. In branch-parallel mode, each core independently maintains its local cache, enabling parallel access; while in collaborative reasoning mode, multiple core cache units are merged into a shared cache, achieving centralized storage and consistency management of global data. During this process, cache units can record and retrieve structural information with extremely low storage overhead and computational latency, providing efficient storage support and a structural foundation for completeness analysis of non-time-sequential backtracking under different modes.

[0074] 2. Event-driven task scheduling design To improve resource utilization and accelerate the solution of small-scale problems, this invention proposes an event-driven task scheduling mechanism. This mechanism divides the solution space search into multiple parallel subtasks and assigns them to various cores for solving based on their state. When a core completes a task or returns a result, the system immediately triggers a new scheduling event, assigning it a new branch task. Through this event-triggered dynamic scheduling method, multiple cores can explore different solution search spaces in parallel, thereby significantly improving the overall solution efficiency of the system.

[0075] 3. Cross-core system analysis and design To ensure the stable collaborative operation of multiple cores during large-scale problem solving, this invention proposes a cross-core system analysis mechanism. This mechanism unifies and integrates the clause states and conflict information of each core, centrally executes conflict analysis termination condition judgments and non-temporally sequential backtracking hierarchy generation, thereby achieving collaborative reasoning and global consistency control among multiple cores and effectively guaranteeing the stability and completeness of the system under large-scale problem solving tasks.

[0076] Through the above design, the solver in this embodiment utilizes a pattern-reconfigurable multi-core architecture, achieving higher solving speeds and flexibly adapting to 3-SAT problems of different scales, supporting completeness analysis with non-time-sequential backtracking. This architecture balances performance and adaptability, providing an efficient and flexible approach to hardware acceleration of SAT solving, and accelerating the practical application of related technologies.

[0077] The method for solving the K-SAT problem provided in this application first obtains the formula to be solved and determines whether the formula satisfies preset calculation conditions, obtaining a judgment result. Then, if the judgment result indicates that the formula satisfies the preset calculation conditions, the multiple computing cores are controlled to perform inference and solution on the formula based on the branch-parallel mode; otherwise, the multiple computing cores are controlled to perform inference and solution on the formula based on the collaborative inference mode until a preset termination condition is met. The preset calculation conditions are used to determine the computational scale of the formula to be solved. The preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, but none of the computing cores trigger the target signal; the target signal is triggered when a feasible solution exists in any of the multiple solution spaces of the formula to be solved. Thus, by introducing an event-driven task scheduling mechanism, a reconfigurable buffer management mechanism, and a cross-core coordination analysis mechanism, the adaptability to different application scenarios is greatly improved.

[0078] It should be noted that the method for solving the K-SAT problem provided in this application embodiment can be executed by a K-SAT problem solving device, or by an inference module within that K-SAT problem solving device for executing the K-SAT problem solving method. This application embodiment uses the execution of the K-SAT problem solving method by a K-SAT problem solving device as an example to illustrate the K-SAT problem solving device provided in this application embodiment.

[0079] It should be noted that, in the embodiments of this application, the methods shown in the accompanying drawings for solving the K-SAT problem are all illustrated using one accompanying drawing from one of the embodiments of this application as an example. In specific implementation, the methods for solving the K-SAT problem shown in the accompanying drawings can also be implemented in conjunction with any other accompanying drawings illustrated in the above embodiments, which will not be elaborated here.

[0080] The following describes the apparatus for solving the K-SAT problem provided in this application. The methods for solving the K-SAT problem described below can be referred to in conjunction with those described above.

[0081] Figure 7This is a schematic diagram of the structure of the solver for the K-SAT problem provided in the embodiments of this application, as shown below. Figure 7 As shown, it specifically includes: The judgment module 701 is used to obtain the formula to be solved and determine whether the formula to be solved meets the preset calculation conditions, and obtain a judgment result; the reasoning module 702 is used to control the multiple computing cores to perform reasoning and solving on the formula to be solved based on the branch parallel mode if the judgment result indicates that the formula to be solved meets the preset calculation conditions, otherwise, control the multiple computing cores to perform reasoning and solving on the formula to be solved based on the collaborative reasoning mode until the preset termination condition is met; wherein, the preset calculation conditions are used to determine the calculation scale of the formula to be solved; the preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, and all computing cores not triggering the target signal; the target signal is triggered when any solution space in the multiple solution spaces of the formula to be solved has a feasible solution.

[0082] Optionally, the judgment module 701 is specifically used to determine whether the formula to be solved meets the preset calculation conditions when any one of the plurality of computing cores meets the calculation requirements of the formula to be solved; the judgment module 701 is also specifically used to determine whether the formula to be solved does not meet the preset calculation conditions when any one of the plurality of computing cores does not meet the calculation requirements of the formula to be solved.

[0083] Optionally, the reasoning module 702 is specifically used to divide the calculation task of the formula to be solved into multiple subtasks according to different solution spaces; one subtask corresponds to one solution space; the reasoning module 702 is also specifically used to assign the multiple subtasks to the multiple computing cores for reasoning and solving until the preset termination condition is met.

[0084] Optionally, the inference module 702 is specifically used to determine that the formula to be solved has a feasible solution when the target signal triggered by any computing core is received; wherein, the target signal is triggered when the calculation result of any of the plurality of computing cores indicates that the corresponding subtask is judged to be satisfyable.

[0085] Optionally, the inference module 702 is specifically used to determine that the formula to be solved does not have a feasible solution when the plurality of computing cores have completed the inference and solution of the plurality of sub-tasks and have not received the target signal.

[0086] Optionally, the inference module 702 is specifically used to divide the formula to be solved into multiple formula clauses and assign the multiple formula clauses to the multiple computing cores for inference and solution; one formula clause is assigned to each computing core; the inference module 702 is further used to cyclically execute the target inference operation based on the calculation result of each computing core until the preset termination condition is met; wherein, the target inference operation includes: an implication graph construction operation performed when no conflict is determined, and a conflict analysis operation performed when a conflict is determined; the implication graph construction operation is used to assign values ​​to the unassigned text in the clauses of the computing cores and broadcast the assigned texts to other computing cores; the conflict analysis operation is used to determine the source of the conflict and backtrack all cores to the node before the source of the conflict.

[0087] Optionally, the inference module 702 is specifically used to obtain the clause state of the clause corresponding to each of the plurality of computing cores, and select the unsatisfied clause based on the clause state; the unsatisfied clause contains at least one unassigned literal; the inference module 702 is further used to assign a value to any one of the at least one unassigned literal, and transmit the assigned literal to all computing cores through broadcasting, so as to update the value of the corresponding literal in each computing core; wherein, the clause corresponding to any computing core includes at least one of the following: formula clause, learning clause; the unsatisfied clause is: there is a variable in the clause that has not been assigned a value, and the result of the clause is not 1.

[0088] Optionally, the inference module 702 is specifically used to determine a globally unique implication point based on the unique implication point information of each computing core, and to generate a learning clause and a non-temporally ordered backtracking hierarchy based on the globally unique implication point; the inference module 702 is further used to send the learning clause to the computing core corresponding to the globally unique implication point, and to backtrack all cores to the node preceding the source of the conflict based on the non-temporally ordered backtracking hierarchy; wherein, the unique implication point information is used to represent: the first and only implication point in the computing core; the learning clause is used to represent the key text combination that induces the conflict.

[0089] The K-SAT problem solving apparatus provided in this application first obtains the formula to be solved and determines whether the formula satisfies preset calculation conditions, obtaining a judgment result. Then, if the judgment result indicates that the formula satisfies the preset calculation conditions, the apparatus controls multiple computing cores to perform inference and solution on the formula based on the branch-parallel mode; otherwise, it controls the multiple computing cores to perform inference and solution on the formula based on the collaborative inference mode until a preset termination condition is met. The preset calculation conditions are used to determine the computational scale of the formula to be solved. The preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, but none of the computing cores trigger the target signal. The target signal is triggered when a feasible solution exists in any of the multiple solution spaces of the formula to be solved. Thus, by introducing an event-driven task scheduling mechanism, a reconfigurable buffer management mechanism, and a cross-core coordination analysis mechanism, the adaptability to different application scenarios is greatly improved.

[0090] Figure 8 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 8 As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other through the communications bus 840. The processor 810 can call logical instructions in the memory 830 to execute a solution method for the K-SAT problem. This method includes: first, acquiring the formula to be solved and determining whether the formula satisfies preset computational conditions, obtaining a determination result; then, if the determination result indicates that the formula satisfies the preset computational conditions, controlling the multiple computing cores to perform inference and solution on the formula based on the branch-parallel mode; otherwise, controlling the multiple computing cores to perform inference and solution on the formula based on the collaborative inference mode until a preset termination condition is met; wherein, the preset computational conditions are used to determine the computational scale of the formula to be solved; the preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, and all computing cores not triggering the target signal; the target signal is triggered when any feasible solution exists in any of the multiple solution spaces of the formula to be solved. Thus, by introducing an event-driven task scheduling mechanism, a reconfigurable buffer management mechanism, and a cross-core coordination analysis mechanism, the adaptability to different application scenarios is greatly improved.

[0091] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0092] On the other hand, this application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can execute the solution method for the K-SAT problem provided by the above methods. The method includes: first, obtaining the formula to be solved and determining whether the formula to be solved meets a preset calculation condition, and obtaining a judgment result; then, if the judgment result indicates that the formula to be solved meets the preset calculation condition, controlling the multiple computing cores to perform inference and solution on the formula to be solved based on the branch parallel mode, otherwise controlling the multiple computing cores to perform inference and solution on the formula to be solved based on the collaborative inference mode until a preset termination condition is met; wherein, the preset calculation condition is used to determine the computational scale of the formula to be solved; the preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, and all computing cores not triggering the target signal; the target signal is triggered when any solution space in the multiple solution spaces of the formula to be solved has a feasible solution. Thus, by introducing an event-driven task scheduling mechanism, a reconfigurable buffer management mechanism, and a cross-core coordination and analysis mechanism, the adaptability to different application scenarios is greatly improved.

[0093] On another front, this application also provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the aforementioned methods for solving the K-SAT problem. The method includes: first, obtaining a formula to be solved and determining whether the formula satisfies preset computational conditions, obtaining a determination result; then, if the determination result indicates that the formula satisfies the preset computational conditions, controlling the multiple computing cores to perform inference and solution on the formula based on the branch-parallel mode; otherwise, controlling the multiple computing cores to perform inference and solution on the formula based on the collaborative inference mode until a preset termination condition is met; wherein, the preset computational conditions are used to determine the computational scale of the formula to be solved; the preset termination condition includes any one of the following: receiving a target signal triggered by any computing core, and all computing cores not triggering the target signal; the target signal is triggered when any feasible solution exists in any of the multiple solution spaces of the formula to be solved. Thus, by introducing an event-driven task scheduling mechanism, a reconfigurable buffer management mechanism, and a cross-core coordination analysis mechanism, the adaptability to different application scenarios is greatly improved.

[0094] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0095] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for solving the K-SAT problem, characterized in that, A control unit is applied in the solver, which further includes: multiple computing cores; the solver's operating modes include: branch parallel mode and cooperative reasoning mode; the branch parallel mode is used to control the multiple cores to solve different solution spaces of Boolean formulas in parallel; the cooperative reasoning mode is used to control the multiple cores to solve Boolean formulas collaboratively. The method includes: Obtain the formula to be solved, and determine whether the formula to be solved meets the preset calculation conditions, and obtain the judgment result; If the judgment result indicates that the formula to be solved meets the preset calculation conditions, then the multiple computing cores are controlled to perform reasoning and solving on the formula to be solved based on the branch parallel mode; otherwise, the multiple computing cores are controlled to perform reasoning and solving on the formula to be solved based on the collaborative reasoning mode until the preset termination condition is met. The preset calculation conditions are used to determine the calculation scale of the formula to be solved; the preset termination conditions include any one of the following: receiving a target signal triggered by any calculation core, or none of the calculation cores trigger the target signal; the target signal is triggered when any of the multiple solution spaces of the formula to be solved has a feasible solution.

2. The method according to claim 1, characterized in that, The step of determining whether the formula to be solved meets the preset calculation conditions and obtaining the determination result includes: If any one of the plurality of computing cores satisfies the computational requirements of the formula to be solved, determine whether the formula to be solved satisfies the preset computational conditions. If any one of the plurality of computing cores does not meet the computational requirements of the formula to be solved, it is determined whether the formula to be solved does not meet the preset computational conditions.

3. The method according to claim 1 or 2, characterized in that, The control of the multiple computing cores to perform reasoning and solution on the formula to be solved based on the branch parallel mode until a preset termination condition is met includes: The calculation task of the formula to be solved is divided into multiple subtasks according to the different solution spaces; one subtask corresponds to one solution space. The multiple subtasks are assigned to the multiple computing cores for inference and solution until the preset termination condition is met.

4. The method according to claim 3, characterized in that, The step of assigning the multiple subtasks to the multiple computing cores for inference and solution until the preset termination condition is met includes: Upon receiving the target signal triggered by any computing core, it is determined that the formula to be solved has a feasible solution; The target signal is triggered when the subtask corresponding to the calculation result of any one of the plurality of computing cores is determined to be satisfactory.

5. The method according to claim 3, characterized in that, The step of assigning the multiple subtasks to the multiple computing cores for inference and solution until the preset termination condition is met includes: If the multiple computing cores have completed the inference and solution of the multiple sub-tasks and have not received the target signal, it is determined that the formula to be solved has no feasible solution.

6. The method according to claim 1 or 2, characterized in that, The step of reasoning and solving the formula to be solved based on the collaborative reasoning mode until a preset termination condition is met includes: The formula to be solved is divided into multiple formula clauses, and the multiple formula clauses are assigned to the multiple computing cores for reasoning and solving; one formula clause is assigned to one computing core. Based on the calculation results of each computing core, the target inference operation is executed cyclically until the preset termination condition is met; The target reasoning operation includes: an implication graph construction operation performed when no conflict is determined, and a conflict analysis operation performed when a conflict is determined; the implication graph construction operation is used to assign values ​​to unassigned literals in the clauses of the computational cores and broadcast the assigned literals to other computational cores; the conflict analysis operation is used to determine the source of the conflict and backtrack all cores to the node preceding the source of the conflict.

7. The method according to claim 6, characterized in that, The execution of the implication graph construction operation includes: Obtain the clause state of each clause corresponding to the plurality of computing cores, and select the unsatisfied clause based on the clause state; the unsatisfied clause contains at least one unassigned literal. Assign a value to any of the at least one unassigned characters, and broadcast the assigned character to all computing cores to update the value of the corresponding character in each computing core. The clause corresponding to any calculation core includes at least one of the following: a formula clause, a learning clause; the clause that does not meet the requirements is: there is a variable in the clause that has not been assigned a value, and the result of the clause is not 1.

8. The method according to claim 6, characterized in that, The conflict analysis operation includes: Based on the unique entailment information of each computational core, a globally unique entailment point is determined, and a learning clause and a non-temporally sequential backtracking hierarchy are generated based on the globally unique entailment point. The learning clause is sent to the computational core corresponding to the globally unique implication point, and all cores are backtracked to the node before the source of the conflict based on the non-temporal backtracking hierarchy; The unique implication point information is used to represent the first and only implication point in the computational core; the learning clause is used to represent the key text combination that induces the conflict.

9. A solution apparatus for the K-SAT problem, characterized in that, A control unit is applied in the solver, which further includes: multiple computing cores; the solver's operating modes include: branch parallel mode and cooperative reasoning mode; the branch parallel mode is used to control the multiple cores to solve different solution spaces of Boolean formulas in parallel; the cooperative reasoning mode is used to control the multiple cores to solve Boolean formulas collaboratively. The device includes: The judgment module is used to obtain the formula to be solved and to determine whether the formula to be solved meets the preset calculation conditions, and to obtain the judgment result; The reasoning module is used to control the multiple computing cores to perform reasoning and solving on the formula to be solved based on the branch parallel mode if the judgment result indicates that the formula to be solved meets the preset calculation conditions; otherwise, it controls the multiple computing cores to perform reasoning and solving on the formula to be solved based on the collaborative reasoning mode until the preset termination condition is met. The preset calculation conditions are used to determine the calculation scale of the formula to be solved; the preset termination conditions include any one of the following: receiving a target signal triggered by any calculation core, or none of the calculation cores trigger the target signal; the target signal is triggered when any of the multiple solution spaces of the formula to be solved has a feasible solution.

10. A solver, characterized in that, It includes multiple computing cores and a control unit, wherein the control unit executes the program to implement the steps of the solution method for the K-SAT problem as described in any one of claims 1 to 8.

Images