Condensed graph representation acquisition method for quantum circuits and related devices

Abstract

This invention discloses a method and related equipment for obtaining a condensed graph representation of a quantum circuit, relating to the field of quantum computing technology. The method includes: calculating the characteristic orientation of each quantum gate in the quantum circuit on each qubit it interacts with; creating a directed superedge for each qubit in the quantum bit set, and maintaining a nearest supernode pointer for each qubit in the quantum bit set, with all nearest supernode pointers initialized to null; iterating through each quantum gate in the quantum gate set according to the gate sequence order of the quantum circuit, and constructing the condensed graph representation of the quantum circuit by combining the supernode set and the superedge set. The construction process of this invention has low complexity and is applicable to various quantum circuits composed of multiple single-objective gates, exhibiting good versatility.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a method for obtaining condensed graph representations of quantum circuits and related equipment. Background Technology

[0002] Quantum circuits serve as the physical implementation of quantum algorithms, and the rationality of their structural representation directly impacts the efficiency of higher-level quantum computing applications (such as optimization, verification, and compilation). In the field of quantum computing, especially in the era of noisy medium-scale quantum (NISQ) devices, the requirements for representation methods in quantum circuit optimization and equivalence determination are becoming increasingly stringent: they need to accurately characterize the commutative properties of quantum gates (i.e., gate commutativity) while retaining the inherent connectivity and locality information of the circuit.

[0003] The mainstream representation of existing quantum circuits is the directed acyclic graph (DAG) representation. Its core logic is to treat each quantum gate as a node and use directed edges to represent the dependencies and noncommutativity between gates. This method can handle the gate commutativity problem well—all commutatively equivalent quantum circuits correspond to the same DAG structure, thus simplifying circuit analysis based on commutativity.

[0004] However, directed acyclic graph (DAG) representations suffer from insurmountable structural defects: First, they lose connectivity. For quantum gates that act on the same qubits but are commutative, DAGs remove the associated edges between them, treating them as independent nodes, as if these gates act on different qubits, thus disrupting the original qubit connectivity structure of the circuit. Second, they lose locality. Due to the disruption of connectivity, upper-level applications based on DAG representations (such as template matching and circuit simplification) cannot obtain relevant gate information through local neighborhood searches and must perform global traversals, leading to low application efficiency. Third, they distort structural information. DAGs decompose the set of commutative gates into isolated nodes, failing to intuitively reflect the algebraic equivalence class properties of quantum gates, increasing the complexity of structural analysis in upper-level applications. These defects prevent DAG representations from meeting the support requirements of large-scale quantum circuits for efficient upper-level applications, especially in scenarios such as circuit optimization and equivalence verification, increasing computational complexity and limiting the engineering implementation of quantum computing technology.

[0005] Therefore, a novel quantum circuit representation method is needed to overcome the above-mentioned defects, accurately characterize the gate commutative law, and fully preserve the connectivity and locality information of the circuit, thereby providing efficient and reliable basic representation support for upper-level applications. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to address the shortcomings of the prior art, and specifically provides a method for obtaining condensed graph representations of quantum circuits and related equipment, as detailed below: 1) In a first aspect, the present invention provides a method for obtaining a condensed graph representation of a quantum circuit, the specific technical solution of which is as follows: Calculate the characteristic orientation of each quantum gate in a quantum circuit on each qubit it interacts with; wherein, the quantum circuit includes the complete set of qubits and the set of quantum gates; Create a directed superedge for each qubit in the complete set of qubits, and maintain a nearest supernode pointer for each qubit in the complete set of qubits. All nearest supernode pointers are initialized to null. Following the gate sequence order of the quantum circuit, each quantum gate in the set of quantum gates is traversed and iteratively constructed. The iterative construction includes: for any quantum gate traversed, obtaining the set of active qubits of that quantum gate; for each qubit in the set of active qubits, performing a supernode processing operation, which will generate or update a supernode containing the identifier of that qubit, the characteristic direction of the quantum gate on that qubit, and the set of gates, and adding the supernode to the supernode set; collecting all supernodes containing that quantum gate, constructing a superedge connecting all supernodes containing that quantum gate, and adding the superedge to the superedge set; The set of supernodes and the set of superedges are used together to construct a condensed graph representation of the quantum circuit.

[0007] The beneficial effects of the condensed map representation method for quantum circuits provided by this invention are as follows: By calculating the characteristic orientation of each quantum gate on the acting qubit, an algebraic criterion is provided for subsequent construction. During iterative construction, a supernode processing operation is performed on the set of acting qubits for each quantum gate by creating directed superedges for each qubit and maintaining pointers to the nearest supernodes. This operation generates or updates supernodes containing qubit identifiers, characteristic orientations, and gate sets, and adds these supernodes to the supernode set. Simultaneously, the method collects all supernodes containing that quantum gate, constructs connecting superedges, and adds them to the superedge set. Finally, the supernode set and the superedge set are jointly constructed into a condensed graph representation. This process ensures that commutatively equivalent quantum circuits necessarily correspond to the same condensed graph representation, thus guaranteeing the canonicity of the representation. The condensed graph representation directly and completely preserves the gate commutativity property by encapsulating the largest commutative set of gates with the same characteristic orientation through supernodes. By maintaining temporal correlations within qubits through directed superedges and cross-qubit correlations between multi-qubit gates through connecting superedges, the original connectivity of the quantum circuit is preserved without loss. The neighborhood formed by a supernode and its associated superedges directly corresponds to the local structure of the circuit, enabling upper-layer applications to obtain relevant information through local neighborhood searches, avoiding global traversal, strictly maintaining locality, and improving application efficiency. Furthermore, the construction process has low complexity and is applicable to various quantum circuits composed of multiple controllable single-objective gates, demonstrating good versatility.

[0008] Based on the above scheme, the method for obtaining the condensed graph representation of quantum circuits of the present invention can be further improved as follows.

[0009] Furthermore, for each qubit in the set of active qubits, supernode processing operations are performed, including: For any qubit in the set of active qubits, if the nearest supernode pointer of the qubit is null, a first supernode is created. The first supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the gate set containing the currently traversed quantum gate. The first supernode is added to the supernode set, the nearest supernode pointer of the qubit is updated to the first supernode, and the first supernode is placed on the directed superedge created for the qubit. If the nearest supernode pointer of the qubit is not null, then it is determined whether the characteristic direction of the currently traversed quantum gate on the qubit is the same as the characteristic direction stored in the supernode pointed to by the nearest supernode pointer. If they are the same, the currently traversed quantum gate is added to the set of gates contained in the supernode pointed to by the nearest supernode pointer. If they are not the same, a second supernode is created. The second supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the set of gates containing the currently traversed quantum gate. The second supernode is added to the set of supernodes, placed on the directed superedge created for the qubit and after the supernode pointed to by the nearest supernode pointer, and the nearest supernode pointer of the qubit is updated to the second supernode.

[0010] The beneficial effects of adopting the above-mentioned further scheme are as follows: Supernode processing operations effectively solve the problems of connectivity loss and locality destruction in traditional representation methods by dynamically managing the supernodes on each qubit line. When the nearest supernode pointer is null, the first supernode is created and associated with the directed superedge, thus establishing the initial temporal structure of the qubit. When the pointer is not null, the current quantum gate is merged into an existing supernode or a new second supernode is created by judging whether the characteristic directions are the same. This judgment mechanism directly realizes the automatic aggregation of algebraic equivalence classes, encapsulating commutative gates with the same characteristic directions within the same supernode, thereby completely preserving the gate commutative law. At the same time, whether creating a new node or merging, the nearest supernode pointer is updated and the node is precisely placed at the corresponding position on the directed superedge, which strictly maintains the temporal correlation and topological order within the qubit. Finally, the sequence of supernodes formed on each qubit line completely preserves the execution order and adjacency relationship of the original circuit, providing direct support for efficient search and analysis based on local neighborhoods.

[0011] Furthermore, the characteristic orientation of each quantum gate in the quantum circuit on each qubit it operates upon is calculated, including: For a single-qubit gate in a quantum circuit, the characteristic direction is calculated based on the unitary matrix of the single-qubit gate. For a multi-controlled single-target qubit gate in a quantum circuit, the characteristic direction of each control qubit of the multi-controlled single-target qubit gate is fixed as the computation basis, and the characteristic direction of the target qubit of the multi-controlled single-target qubit gate is calculated based on the unitary transformation characteristics of the multi-controlled single-target qubit gate.

[0012] The beneficial effects of adopting the above-mentioned further scheme are as follows: By clearly distinguishing the methods for calculating the characteristic directions of single-qubit gates and multi-control single-target qubit gates, this technical feature provides an accurate and consistent algebraic criterion for the construction of condensed graph representations. For single-qubit gates, the characteristic directions are calculated directly based on their unitary matrix, ensuring that the algebraic properties of the basic gate transformations are accurately characterized. For multi-control single-target qubit gates, by fixing the characteristic directions of each control qubit as the computational basis and calculating the characteristic directions of the target qubits only based on the unitary transformation properties of the gate, this rule uniformly and efficiently handles the algebraic representation of complex gate operations. The characteristic directions generated by this classification calculation method are the absolute basis for subsequently determining whether quantum gates belong to the same algebraic equivalence class, and thus deciding whether to merge them within the supernode. It lays an accurate mathematical foundation for the entire condensed graph representation construction process, ensuring that the final generated supergraph representation can strictly and consistently reflect the algebraic structure of the gate commutative law in the quantum circuit.

[0013] Furthermore, a supernode is a triple containing the identifier, characteristic direction, and gate set of the qubit. The identifier of the qubit is used to represent the qubit corresponding to the supernode, the characteristic direction is used to represent the common characteristic direction of all quantum gates in the supernode on the qubit, and the gate set is the largest commutative gate set in the quantum circuit that acts on the qubit and has a common characteristic direction.

[0014] The beneficial effects of adopting the above-mentioned further scheme are as follows: The definition of supernode triples integrates the spatial affiliation, algebraic properties, and physical entities of quantum gates into a unified structure, resulting in multiple technical effects. The identification of qubits allows each supernode to be explicitly anchored to a specific qubit line, maintaining the spatial topological association of the circuit. The characteristic direction, as an algebraic fingerprint, defines the transformation basis common to all gates within a supernode, directly encoding the mathematical criterion for the gate commutative law, enabling explicit representation of algebraic equivalence classes. The gate set encapsulates the largest commutative set of gates satisfying the same characteristic direction condition. This "maximality" ensures that all commutative and adjacent gates are aggregated, avoiding information fragmentation. Through the structured encapsulation of triples, gates that were originally discretized in the directed acyclic graph due to commutativity are logically aggregated, allowing the local algebraic properties and topological associations of the circuit to be completely preserved within a single supernode. This provides a self-contained complete context for neighborhood-based queries and analysis, allowing upper-layer applications to directly obtain all algebraically equivalent gate operations within a local region without needing to piece together information across nodes.

[0015] 2) In a second aspect, the present invention also provides a system for obtaining condensed graph representations of quantum circuits, the specific technical solution of which is as follows: It includes a feature orientation determination module, a creation module, an iterative construction module, and an condensed graph representation acquisition module; The characteristic orientation determination module is used to: calculate the characteristic orientation of each quantum gate in a quantum circuit on each qubit it acts upon; wherein, the quantum circuit includes the complete set of qubits and the set of quantum gates; The creation module is used to: create a directed superedge for each qubit in the entire set of qubits, and maintain a nearest supernode pointer for each qubit in the entire set of qubits, with all nearest supernode pointers initialized to null; The iterative construction module is used to: traverse each quantum gate in the set of quantum gates according to the gate sequence of the quantum circuit, and perform iterative construction. The iterative construction includes: for any quantum gate traversed, obtaining the set of active qubits of that quantum gate; for each qubit in the set of active qubits, performing a supernode processing operation, which will generate or update a supernode containing the identifier of that qubit, the characteristic direction of the quantum gate on that qubit, and the set of gates, and add the supernode to the supernode set; collect all supernodes containing that quantum gate, construct a superedge connecting all supernodes containing that quantum gate, and add the superedge to the superedge set. The condensed graph representation acquisition module is used to: construct a condensed graph representation of a quantum circuit by combining the set of supernodes and the set of superedges.

[0016] Based on the above scheme, the quantum circuit condensed graph representation acquisition system of the present invention can be further improved as follows.

[0017] Furthermore, the iterative building module is also specifically used for: For any qubit in the set of active qubits, if the nearest supernode pointer of the qubit is null, a first supernode is created. The first supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the gate set containing the currently traversed quantum gate. The first supernode is added to the supernode set, the nearest supernode pointer of the qubit is updated to the first supernode, and the first supernode is placed on the directed superedge created for the qubit. If the nearest supernode pointer of the qubit is not null, then it is determined whether the characteristic direction of the currently traversed quantum gate on the qubit is the same as the characteristic direction stored in the supernode pointed to by the nearest supernode pointer. If they are the same, the currently traversed quantum gate is added to the set of gates contained in the supernode pointed to by the nearest supernode pointer. If they are not the same, a second supernode is created. The second supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the set of gates containing the currently traversed quantum gate. The second supernode is added to the set of supernodes, placed on the directed superedge created for the qubit and after the supernode pointed to by the nearest supernode pointer, and the nearest supernode pointer of the qubit is updated to the second supernode.

[0018] Furthermore, the feature orientation determination module is specifically used for: For a single-qubit gate in a quantum circuit, the characteristic direction is calculated based on the unitary matrix of the single-qubit gate. For a multi-controlled single-target qubit gate in a quantum circuit, the characteristic direction of each control qubit of the multi-controlled single-target qubit gate is fixed as the computation basis, and the characteristic direction of the target qubit of the multi-controlled single-target qubit gate is calculated based on the unitary transformation characteristics of the multi-controlled single-target qubit gate.

[0019] Furthermore, a supernode is a triple containing the identifier, characteristic direction, and gate set of the qubit. The identifier of the qubit is used to represent the qubit corresponding to the supernode, the characteristic direction is used to represent the common characteristic direction of all quantum gates in the supernode on the qubit, and the gate set is the largest commutative gate set in the quantum circuit that acts on the qubit and has a common characteristic direction.

[0020] 3) In a third aspect, the present invention also provides an electronic device, the electronic device including a processor coupled to a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor, so as to enable the electronic device to implement the above-mentioned method for obtaining the condensed graph representation of quantum circuits.

[0021] 4) In a fourth aspect, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the condensed graph representation acquisition method of any of the above-mentioned quantum circuits.

[0022] It should be noted that the beneficial effects of the technical solutions of the second to fourth aspects of the present invention and their corresponding possible implementations can be found in the above description of the technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below: Figure 1 Here is a flowchart illustrating a method for obtaining a condensed graph representation of a quantum circuit according to an embodiment of the present invention. Figure 2 Here is a schematic diagram of a quantum circuit containing four CX gates; Figure 3 For: with Figure 2 A schematic diagram of an equivalent quantum circuit; Figure 4 for: Figure 2 and Figure 3 A schematic diagram representing the corresponding condensation diagram; Figure 5 See: A schematic diagram of the structure of a quantum circuit condensed graph representation acquisition system according to an embodiment of the present invention. Detailed Implementation

[0024] The principles and features of the present invention are described below. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0025] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0026] like Figure 1 As shown, an embodiment of the present invention provides a method for obtaining a condensed graph representation of a quantum circuit, comprising the following steps: S1. Calculate the characteristic orientation of each quantum gate in the quantum circuit on each quantum bit it acts upon; wherein, the quantum circuit includes the complete set of quantum bits and the set of quantum gates.

[0027] In this context, the characteristic direction of a quantum gate on each qubit it interacts with refers to a descriptor of the transformation properties of the quantum gate on a specific qubit. A quantum gate may interact with one or more qubits, and on each interacted qubit, the quantum gate has a characteristic direction. The characteristic direction is the generalized eigenbase of the quantum gate on that qubit, i.e., a set of basis vectors that describe the intrinsic directions of the quantum gate's transformations on that qubit. In condensed graph representations, the characteristic direction is used to determine the commutativity between quantum gates: if two quantum gates have the same characteristic direction on the same qubit, then they are commutative on that qubit. The calculation of the characteristic direction depends on the unitary matrix representation of the quantum gate, and is obtained by analyzing the eigenvectors of the unitary matrix.

[0028] S1 specifically includes: (1) For a single-qubit gate in a quantum circuit, the characteristic direction is calculated based on the unitary matrix of the single-qubit gate. The specific implementation process is as follows: 1) Given a quantum circuit traversal gate set Each door in If the door If it is a single-qubit gate, then the number of qubits it operates on is determined. In quantum circuits, single-qubit gates are typically labeled with the index of the active qubit through circuit diagrams or gate sequences, such as qubits. Belongs to the complete set of quantum bits The identification process requires analyzing the representation of the quantum circuit and extracting the functional qubit information of each gate.

[0029] 2) For each single-qubit gate Its unitary matrix This is known. In quantum computing, single-qubit gates are typically composed of a standard set of gates, such as Pauli gates, Hadamard gates, and phase gates. The unitary matrices of these gates have a standard form. For example, the unitary matrix of a Pauli-X gate is: The unitary matrix of the Pauli-Z gate is: .

[0030] For non-standard single-qubit gates, such as rotation gates A unitary matrix can be given in parametric form. It is A complex matrix that satisfies the unitary condition ,in yes The conjugate transpose of . It is an identity matrix.

[0031] 3) Set a single-qubit gate The unitary matrix is Calculating its characteristic direction requires solving... The eigenvectors. Solve the characteristic equation: in, These are eigenvalues. These are eigenvectors. Because... It is a unitary matrix, with eigenvalues It is a complex number with a modulus of 1, and its eigenvectors are... This forms an orthogonal, normal basis. In specific calculations, the characteristic polynomial is solved. Obtain eigenvalues ,in Represents the determinant of a matrix. yes Identity matrix. For each eigenvalue Solve the system of linear equations Obtain the corresponding eigenvectors Eigenvectors typically need to be normalized, i.e., satisfy the following conditions: .

[0032] 4) Door In quantum bits Feature direction Defined as a unitary matrix The characteristic direction is the set of all eigenvectors. Since a single-qubit gate acts on a single qubit, the characteristic direction only involves that qubit. Therefore, the characteristic direction is expressed as: ,in, and yes Two eigenvectors. These eigenvectors are orthogonal and uniform, and span a quantum bit. A two-dimensional Hilbert space. Characteristic orientation. It is a set containing two basis vectors used to describe the gate. In quantum bits Transformation characteristics on.

[0033] 5) To ensure consistency in feature directions, eigenvectors need to be represented as vectors under the standard basis. The standard basis is typically calculated using a basis vector. ,in, For example, for the Pauli-X gate, the eigenvectors and In the computational basis, it is expressed as: Therefore, characteristic direction For the Pauli-Z gate, the eigenvectors are calculated by using the basis vectors. and Characteristic direction For general single-qubit gates, eigenvectors may require normalization and phase normalization to ensure the uniqueness of the representation.

[0034] 6) In the process of constructing the condensation diagram representation, the characteristic direction It is used in subsequent steps, such as supernode creation and comparison. Therefore, the calculated feature orientations need to be stored in a data structure, such as a mapping table, to represent the gates. and quantum bits Mapping to feature direction set When storing, feature directions can be represented as a list of vectors or symbolic expressions for fast access and comparison when traversing the gate sequence.

[0035] (2) For multi-control single-target qubit gates in quantum circuits, the characteristic direction of each control qubit of the multi-control single-target qubit gate is fixed as the computation basis, and the characteristic direction of the target qubit of the multi-control single-target qubit gate is calculated according to the unitary transformation characteristics of the multi-control single-target qubit gate. The specific implementation process is as follows: 1) Given a quantum circuit and its gate set traversal Each door in It is necessary to determine the door. Is it a multi-control, single-target qubit gate? These gates are usually clearly identified in quantum circuit descriptions; for example, a CNOT gate is labeled CX with indexes for both the control and target qubits, and a Tofoli gate is labeled CCX. The identification process requires resolving the gate's type and parameters to determine the set of control qubits. and target qubit .in, Represents the number of control qubits. It is the first The identifier for each control qubit. It is the identifier for the target qubit.

[0036] 2) For the identified doors For each of its control qubits Assigning characteristic directions. By convention, the characteristic direction of each control qubit is fixed as the computational basis. This is represented symbolically as: For all control qubits Its characteristic direction They are all the same set This step is deterministic and requires no calculation.

[0037] 3) Install a door Acting on If there are one control qubit and one target qubit, then its action is within a system composed of... On a subsystem consisting of qubits. The overall unitary matrix of this gate. It is The matrix. Taking the common two-qubit CX gate as an example, its control qubits... and target qubit unitary matrices in computational basis The following is represented as: For those with A generalized multi-control X-gate with control qubits has a permutation matrix, where all control bits are... At that time, an X-gate operation is performed on the target bit. The exact unitary matrix needs to be obtained from or generated from the standard quantum computing gate library, depending on the specific gate type. .

[0038] 4) In order to calculate the target qubit Feature direction It is necessary to analyze the unitary matrix. The efficient transformation induced on the target qubit. This analysis is conducted under the premise that the conditions for controlling the qubits are satisfied. Consider decomposing the state space of the entire system into the tensor product of the control qubit subspace and the target qubit subspace. When all control qubits are in... In this state, The effect on the target qubit is equivalent to a specific single-qubit unitary matrix. For the CX gate, when the control bit is At that time, the transformation of the target bit is a Pauli-X gate, i.e. For the CCZ gate, when both control bits are... At that time, the transformation of the target bit is a phase gate. Find this equivalent single-qubit transformation. It is the key to calculating the feature direction.

[0039] 5) Characteristic orientation of the target qubit From the equivalent single-qubit unitary matrix The eigenvectors determine this. Calculate... The eigenvectors need to be solved using the characteristic equation: ,in, These are eigenvalues. These are the corresponding eigenvectors. It is The unitary matrix. Solving for the characteristic polynomial. Obtain eigenvalues and ,in yes The identity matrix. Then, for each eigenvalue... Solve the system of linear equations The corresponding normalized eigenvectors are obtained. and The characteristic direction of the target qubit is the set of these two eigenvectors: .

[0040] Taking the CX gate as an example, its equivalent transformation . The eigenvalues ​​of a matrix and The corresponding eigenvectors are respectively and Therefore, the characteristic orientation of the CX gate target qubit is... .

[0041] 6) The calculated eigenvectors need to be computed using a standard computational basis. Normalization is performed to ensure consistency in feature orientation representation throughout the circuit processing. For example, and It needs to be explicitly stated as follows: For more general transformations The calculated eigenvectors may require adjustment of the global phase to conform to a predetermined representation specification. Normalized feature directions. It will be stored as an ordered list containing two two-dimensional complex vectors.

[0042] 7) Store all calculated feature directions in a global data structure. For gates... Each active qubit needs to have its characteristic orientation stored. Specifically, for each control qubit... Fixed storage and for the target qubit Store the calculated Typically, a mapping data structure is used. , making Return Door In quantum bits Feature direction set These data provide direct input for determining whether feature directions are the same during the iterative process when constructing the agglomeration graph representation.

[0043] In a multi-control single-target qubit gate, the control qubit is the qubit used to perform conditional judgments. A multi-control single-target qubit gate contains one or more control qubits and one target qubit. In the operational logic of quantum circuits, conditions are only met when all control qubits are in the prescribed computational ground state, typically... A specific unitary transformation only occurs on the target qubit when it is in a certain state. When calculating the characteristic directions, the characteristic directions of the control qubit are uniformly fixed as the computational basis. This rule stems from the classical judgment function that controls qubits, whose state is a condition for unitary transformation to occur, rather than directly participating in the nontrivial algebraic transformations on the target qubit.

[0044] In a multi-control single-target qubit gate, the target qubit is the qubit that undergoes the actual transformation within the gate. The state of the target qubit changes according to the unitary matrix of the gate if and only if all control qubits satisfy certain conditions. The characteristic direction of the target qubit cannot be predetermined and must be calculated by analyzing the unitary transformation characteristics of the entire multi-control single-target qubit gate. This characteristic direction describes the intrinsic algebraic direction of the target qubit's state transformation after the gate operation and is a key criterion for determining whether the gate on the target qubit is commutative with other gates.

[0045] S2. Create a directed superedge for each qubit in the complete set of qubits, and maintain a nearest supernode pointer for each qubit in the complete set of qubits. All nearest supernode pointers are initialized to null. The specific implementation process is as follows: S20, Given a quantum circuit Its complete set of qubits is denoted as Assume the number of qubits is... ,Right now The algorithm requires two core global data structures to represent the agglomerative graph representation being constructed: a set of hyperedges. Mapping of the nearest supernode pointer Hyperedge set This is used to store all created directed superedges and the superedges of connected supernodes created in subsequent steps. It also includes a recent supernode pointer map. It is a mapping from qubit identifiers to supernode references (or identifiers). In the program implementation, It can be defined as a list or a collection. This can be defined as an array or hash table, where the index or key is a qubit identifier. It's important to clarify that in this step, we only create directed hyperedges; hyperedges created in subsequent steps will be added to the set at different stages. .

[0046] S21. The algorithm requires the complete set of qubits. Each qubit in the array creates an independent directed hyperedge. A loop is executed to iterate through these hyperedges. Each qubit in For each quantum bit Perform the creation operation. Create a directed superedge, denoted as . . The data structure needs to be able to record two types of information: one is the identifier of the qubit it is associated with. Secondly, it is an ordered list of the supernodes it currently connects to (or will connect to). During initialization, this directed superedge has no connected supernodes, so this ordered list is empty. After creation, this directed superedge... Add to superedge set In the middle. Describe the loop process using pseudocode: For each... ,create ;Will Add to collection This step ensures that each qubit has its own dedicated "track" in the condensed graph representation, and subsequent supernodes will be strung on this track like beads, with their order determined by the gate sequence.

[0047] S22. Simultaneously or after creating the directed superedge, it is necessary to initialize the pointer used to track the latest supernode on each qubit. For each qubit... Maintain a pointer to the nearest supernode, denoted as . . It is a mapping function whose input is a qubit identifier. The output is a pointer or reference to a supernode. At the beginning of the algorithm, no supernode has been created on any qubit, so each pointer... All should be set to a special value representing "empty" or "invalid". In program implementation, this is usually done by... Initialize to NULL (in C / C++ / Java, etc.) or None (in Python, etc.). The initialization operation is also performed by traversing the entire set of qubits. To complete: for each Perform assignment operation After initialization is complete, pointer mapping... It is in a ready state and will be frequently queried and updated when processing each quantum gate to determine how to build or merge supernodes.

[0048] S23. It is necessary to ensure that the created directed superedges and the pointers to the nearest supernodes are correctly associated and saved in memory or storage. (Set of directed superedges) and pointer mapping It is the global state variable of the algorithm. (Directed hyperedge) As an object, it should include its associated qubits. The ID attribute and an ordered container for storing supernode references. Pointer mapping. You can directly use a size of Implemented using arrays, array indices Corresponding to the Each qubit is identified by its identifier, and the array elements store pointers to supernodes. Another implementation uses a dictionary (hash table) with the qubit identifier as the key. After initialization, the algorithm enters the main loop, traversing each qubit in gate sequence order. At this point, the data structure... and This code will be accessed and modified in subsequent steps.

[0049] In condensed graph representation, a directed superedge is a data structure used to organize supernodes and represent temporal relationships. In the condensed graph representation of quantum circuits, each directed superedge corresponds specifically to a single qubit in the complete set of qubits. The core function of a directed superedge is to connect all the supernodes acting on that qubit according to the logical order in which the quantum circuit executes. This edge is directional, pointing from the input to the output, defining the order in which the supernodes appear on that qubit. By creating an independent directed superedge for each qubit, condensed graph representation can fully preserve the original temporal connectivity of the circuit across all qubit lines, which is one of the key design features for overcoming the shortcomings of traditional directed acyclic graph representations.

[0050] The most recent supernode pointer is a dynamically maintained reference variable for each qubit. During the iterative construction of the condensed graph representation, the algorithm needs to track the most recently created or updated supernode on each qubit. The most recent supernode pointer is used to point to this "most recent" supernode. It is a temporary variable whose value is continuously updated as the algorithm sequentially processes quantum gates. When a quantum gate is processed, the algorithm checks the most recent supernode pointer of the affected qubit. Based on the pointer's state and the characteristic direction of the supernode it points to, it decides whether to merge the current gate into an existing supernode or create a new supernode for the qubit. All most recent supernode pointers are initialized to null, indicating that no supernodes have been built on each qubit line at the start of the algorithm.

[0051] S3. Following the gate sequence order of the quantum circuit, traverse each quantum gate in the set of quantum gates and perform iterative construction. The iterative construction includes: for any quantum gate traversed, obtaining the set of active qubits of that quantum gate; for each qubit in the set of active qubits, performing a supernode processing operation. The supernode processing operation will generate or update a supernode containing the identifier of that qubit, the characteristic direction of the quantum gate on that qubit, and the set of gates, and add the supernode to the supernode set. Collect all supernodes containing that quantum gate, construct a superedge connecting all supernodes containing that quantum gate, and add the superedge to the superedge set. The specific implementation process for obtaining the set of functional qubits of a quantum gate is as follows: S30. During the iterative construction process, the algorithm is sequentially traversing the set of quantum gates. Let the quantum gate currently being traversed be... It is a set of gates A specific element within. In program implementation, Typically, this is a data structure or object that encapsulates all the properties of the quantum gate. These properties include at least the type of gate (e.g., whether it's a Pauli-X gate, a controlled-NOT gate, or a Tofoli gate) and the parameters required to determine its target. The algorithm has now moved on to processing a single gate. The context needs to be understood from... Extract information from it.

[0052] S31, Quantum Gate The set of qubits that can be used is entirely determined by the definition of the gate. Implementation requires consideration of the gate... The type of the quantum gate determines the appropriate parsing logic. A quantum gate description typically includes a type identifier. and a set of parameters .parameter The code must include information that explicitly specifies the qubit index. For example, a gate might be represented as... or The numbers here That is, the quantum bit in the global quantum bit set The unique identifier in the database. The parsing process involves reading these unique identifiers stored in the database. The index value in the table.

[0053] S32, If quantum gate The type is a single-qubit gate, such as the Hadamard gate. Pauli- Gate, Pauli- Door, revolving door If so, then it only acts on one qubit. In this case, the set of acting qubits is a set containing only a single element. (From the gate) The identifier of this qubit is extracted from the parameters. Assume this identifier is... Then we can construct a set of active qubits. Represented mathematically, we define a gate. The functional qubit set is Then we have: ,in, It is a collection of quantum bits This step directly wraps the single index stored in the parameter into a collection.

[0054] S33, If quantum gate If the type is a multi-qubit gate, then multiple qubit identifiers need to be extracted. The most common is the two-qubit gate, such as the controlled NOT gate. ,controlled Door In addition, there are multi-control single-target gates, such as the Toffoli gate. .for The gate needs to extract the identifier of the control qubit from the parameters. and target qubit identifier .for The gate requires extracting identifiers for multiple control qubits. and a target qubit identifier All these mentioned qubits together constitute the set of action qubits for this gate. Therefore, for a multi-qubit gate, the set of action qubits... It can be represented as: ,in, Represents the number of control qubits. and They all belong to Specific elements. In implementation, it needs to be from the gate. These indexes are read one by one from the parameter list or attribute field and put into the same collection data structure.

[0055] S34. Regardless of whether the quantum gate is a single-qubit gate or a multi-qubit gate, after resolving all relevant qubit identifiers, they need to be organized into a unified data structure for use in subsequent steps. This data structure is a set, denoted as . In programming, this can be achieved using lists, arrays, or collection classes. Importantly, the collection should explicitly contain the current door. The identifiers of all the qubits involved are specified, with each identifier appearing only once. After the algorithm completes this step, the variables... It is ready, and it will be passed as input to the next sub-step, namely, "perform the supernode processing operation for each qubit in the set of active qubits".

[0056] In this context, the action qubits of a quantum gate refer to the set of all qubits whose quantum states are directly affected by the gate's transformations within a quantum circuit. Each quantum gate has a defined scope of action, specified by one or more qubit identifiers. For example, a single-qubit gate acts on only one specific qubit, and its action qubit set contains only one element; a two-qubit controlled-NOT gate acts on both qubits, including a control qubit and a target qubit, and its action qubit set includes the identifiers of both qubits. In the context of constructing a condensed graph representation, accurately obtaining the action qubit set of quantum gates is the fundamental input data for all subsequent operations such as supernode creation, merging, and superedge construction.

[0057] For each qubit in the set of active qubits, supernode processing operations are performed, including: For any qubit in the set of active qubits, if the nearest supernode pointer of that qubit is null, a first supernode is created. The first supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the gate set containing the currently traversed quantum gate. The first supernode is added to the supernode set, the nearest supernode pointer of the qubit is updated to the first supernode, and the first supernode is placed on the directed superedge created for that qubit. If the nearest supernode pointer of the qubit is not null, the characteristic direction of the currently traversed quantum gate on the qubit is compared with that of the nearest supernode. If the feature directions stored in the supernodes pointed to by the pointers are the same, and if they are the same, the currently traversed quantum gate is added to the set of gates contained in the supernode pointed to by the nearest supernode pointer. If they are different, a second supernode is created, which contains the identifier of the qubit, the feature direction of the currently traversed quantum gate on the qubit, and the set of gates containing the currently traversed quantum gate. The second supernode is added to the supernode set, placed on the directed superedge created for the qubit and after the supernode pointed to by the nearest supernode pointer, and the nearest supernode pointer of the qubit is updated to the second supernode. The specific implementation process is as follows: 1) Assume the quantum gate currently being processed is Furthermore, the set of its active qubits has already been obtained through previous steps. .set up ,in This is the number of qubits involved in the gate. The algorithm will start a loop, processing each qubit in the set sequentially. For each currently processed qubit Two key data points need to be prepared: one is the door In this quantum bit Pre-calculated feature directions Secondly, the quantum bit The corresponding nearest supernode pointer The current value. This data will drive subsequent conditional judgments and operations.

[0058] 2) For qubits First, query its nearest supernode pointer. . judge Is the value equal to the special value representing emptiness? This judgment determines whether the algorithm enters one of the two main branches. If This indicates that in quantum bits On the corresponding directed superedge, no supernode has been created so far, and the current gate... It's the first door we encounter on this route. If This indicates that at least one supernode already exists on the qubit line, and the pointer... It points to the most recent one, at which point it is necessary to further determine the similarities and differences in the feature directions.

[0059] 3) When At that time, the algorithm needs to provide qubits Create the first supernode. This newly created supernode is called the first supernode, denoted as . By definition, a supernode is a triple. Therefore, creating... It is necessary to assign values ​​to its three members, specifically including: ① the identifier of the qubit: i.e., the current identifier. ② Characteristic direction: i.e., gate exist Feature direction ③ Gate set: Initialized to a set containing only the current gate. The set, i.e. Represented by symbols: .

[0060] After creation, perform three association operations: First, associate the newly created supernode with the supernode. Add to the global set of supernodes Second, update the qubits. Set the pointer of the nearest supernode to point to this new node, i.e., perform the assignment operation. Third, supernodes "Place" into the previous qubit The directed superedge created Above. In implementation, the "placement" operation means placing the directed hyperedge. Tail insertion of the maintained ordered list of supernodes Thus far, the quantum bit... The first supernode has been created online, and the pointers and edges have been updated.

[0061] 4) When At that time, let the current supernode that the pointer is pointing to be ,Right now Next, we need to compare the current doors. In quantum bits Feature direction With existing supernodes Feature orientation stored in Are they the same? This is an equivalence judgment, which requires comparing whether the two feature direction sets are completely identical. If According to the definition of condensation diagram, the gate With supernode All existing gates belong to the same algebraic equivalence class, and because the traversal is in circuit order, the gates... and The gates in the sequence are sequentially adjacent. Therefore, a merge operation is performed: the gates are merged. Add to supernode Door collection In, that is No new nodes need to be created, nor do pointers need to be changed. The direction, because It remains the newest supernode on the network.

[0062] 5) If This indicates that the door Quantum bits were activated A new algebraic equivalence class is found online. At this point, a new supernode needs to be created, called the second supernode, denoted as . .same, It is a triple, specifically including: ① the identifier of the qubit: i.e., the current... ② Characteristic direction: i.e., gate exist Feature direction ③ Gate set: Initialized to contain only the current gate. The set, i.e. Represented by symbols: .

[0063] After creation, perform three association operations: First, associate... Add to global supernode set Second, "Place" on the directed superedge Up, and must ensure Located in the existing supernode Then. This is achieved through directed superedges. In the ordered list of supernodes, Insert after the node entry This is achieved by maintaining circuit timing. Third, updating the qubits. Set the pointer of the nearest supernode to point to this new, latest node, i.e., perform the assignment operation. .

[0064] 6) After completing the task for the current quantum bit After the above creation or merging operations, a supernode containing the qubit identifier, characteristic direction, and gate set has been generated or updated, and the supernode has been added to the supernode set. The set of active qubits is either in the newly created set or its contents have been updated (for merged sets). The algorithm then iteratively enters the set of active qubits. The process is repeated for the next qubit in the gate until the gate... All the active qubits have been processed.

[0065] In quantum computing, a qubit identifier is a symbol or number used to uniquely distinguish and refer to different qubits. In a quantum circuit, the complete set of qubits... It contains multiple qubits, each requiring a unique identifier for reference by algorithms and data structures. This identifier is typically an integer index, such as... Alternatively, it can be a string name. In condensed graph representation, a supernode needs to explicitly record which specific qubit it is associated with. Therefore, a core element in the triplet structure of a supernode is the identifier of that qubit, used to anchor the supernode to the specific qubit line of the circuit.

[0066] In this context, a gate set is a data structure contained within a supernode in a condensed graph representation. It gathers a group of quantum gates that share specific commonalities in a quantum circuit. Specifically, it refers to the set of gates belonging to the same supernode. This set contains all quantum gates that act on the corresponding qubit of the supernode in a quantum circuit, have the same characteristic orientation, and are sequentially adjacent (or commutatively related) to each other in the circuit sequence. This set is the "maximum commutative gate set," meaning that no other gates acting on the same qubit, having the same characteristic orientation, and being commutatively related to the gates in the set in the circuit sequence can be added to it. The gate set embodies the concept of algebraic equivalence classes encapsulated in supernodes and is the direct object of subsequent circuit optimization and analysis.

[0067] The process involves collecting all supernodes containing the quantum gate, constructing a superedge connecting all supernodes containing the quantum gate, and adding this superedge to the superedge set. The specific implementation process is as follows: 1) Before starting to process the current quantum gate Previously, the algorithm needed to prepare a temporary data structure for collecting supernodes. This could be a list or set, named... The purpose of this container is to be used in subsequent steps when the algorithm traverses the quantum gates. When the qubits are used to perform supernode processing operations, the AND gates on each qubit are dynamically collected. The associated supernode (whether newly created or existing). The container is initialized to empty.

[0068] 2) When the algorithm targets a gate Functional qubit set Each qubit in During the processing, whether a new supernode is created Or the general's family Merged into the existing supernode In, the supernode ( or All of these must contain the current quantum gate. The supernode. Therefore, while performing supernode processing operations, a reference to this supernode needs to be immediately added to the prepared container. In the middle. For example, after creating the first or second supernode, execute... ; in the general's family Merge into existing supernodes Then, execute It should be noted that, due to the door Acting on One quantum bit, ultimately The container will just collect There are 10 supernodes, and each supernode corresponds to an active qubit.

[0069] 3) When the door All supernode processing operations on all active qubits have been completed, and After all relevant supernodes have been collected in the container, the algorithm begins constructing the hyperedge. A new hyperedge object is created, denoted as... Hyperedge object It must contain at least two attributes: one is the quantum gate identifier it is associated with. (or The first is the index, used to record which gate generated this hyperedge; the second is the set of supernodes it connects to, denoted as . .Will All supernode references stored in the container are assigned to In mathematical notation, this can be concisely represented as: if the collected set of supernodes is... The constructed hyperedge satisfy: ,in, It is a door The effect of the number of qubits.

[0070] 4) Hyperedge objects Once constructed, it needs to be registered into the global data structure of the condensed graph representation. Add to the global set representing the entire set of hyperedges in the condensed graph representation In the middle. That is, to perform the operation: ,here It is a collection that stores all hyperedges (including directed hyperedges previously created for each qubit and similar hyperedges created for previously processed gates). This operation ensures that the newly generated, gate-representing... The superedges associated across qubits become part of the final condensed graph representation.

[0071] 5) In the superedge Successfully added to the set Then, a container temporarily used to collect supernodes. The task is now complete. The container can be emptied or released to prepare for the next quantum gate. At this point, the task for the current quantum gate is complete. The hyperedge construction process is now complete. The algorithm then continues iterating from the set of quantum gates. Take the next quantum gate from the set of active qubits and repeat the entire process from obtaining the set of active qubits.

[0072] In condensed graph representation, a hyperedge is a graph-theoretic structure used to connect one or more supernodes, reflecting higher-order associations between them. Unlike edges connecting two vertices in a traditional graph, a hyperedge can connect any number of vertices, which are supernodes in condensed graph representation. In this invention, hyperedges are divided into two types: one is a directed hyperedge created for each qubit to maintain the temporal relationship of supernodes on the same qubit; the other is a connecting hyperedge created for multi-qubit gates to explicitly identify all supernodes simultaneously associated with a multi-qubit gate. The latter type of hyperedge is crucial to ensuring that the connectivity of quantum circuits is not lost. It binds together multiple supernodes generated by a gate on different qubit lines, thus fully preserving the cross-qubit coupling information inherent in gate operations.

[0073] In this context, a supernode is a triple containing the identifier of the qubit, its characteristic direction, and its gate set. The identifier represents the qubit corresponding to the supernode, the characteristic direction represents the common characteristic direction of all quantum gates within the supernode acting on that qubit, and the gate set is the largest commutative set of gates in the quantum circuit that act on the qubit and share a common characteristic direction. Further explanation follows: 1) The identifier of a qubit is the first element in the supernode triplet, denoted as . Its function is to act as an anchor or association key, binding abstract graph nodes to specific physical (or logical) qubit lines in a quantum circuit. In a system containing... In a circuit with 100 qubits, each qubit has a unique identifier, usually an integer index (such as 0, 1, 2, ...). When a supernode... At that time, it means the set of all quantum gates represented by this supernode. All act on the same quantum bit Above. This label ensures that the condensed diagram representation clearly reflects the spatial layout of the circuit: the directed superedge corresponding to each qubit connects all... The supernodes thus fully preserve the operation sequence information on the qubit line. This is the basis for overcoming the loss of connectivity in traditional directed acyclic graphs, because even if the gates are commutative, they maintain connectivity by sharing the same supernodes. And they are associated with the same time chain.

[0074] 2) The feature direction is the second element in the supernode triplet, denoted as It is a mathematical set that describes supernodes. All quantum gates within a qubit The common transformation characteristics. Specifically, It is a specific, orthogonal, and normalized set of basis vectors on that qubit, usually consisting of two state vectors, for example... or The calculation rule is: for Each door in Calculate its value in qubits Feature direction ;because It is a set that satisfies the conditions, all of these gates They are all exactly the same; this common value is defined as... The fundamental significance of characteristic directions lies in defining the algebraic criterion for commutativity: if two gates have the same characteristic direction on the same qubit, then their operations on that qubit are commutative and interchangeable. Therefore, Essentially a supernode The "algebraic type label" categorizes the physical operations of quantum gates into different algebraic equivalence classes. By aggregating adjacent gates with the same characteristic orientation to the same supernode, the condensed graph representation directly and explicitly encodes the gate commutative law, eliminating the need for upper-level applications to handle commutative logic additionally.

[0075] 3) The gate set is the third element in the supernode triple, denoted as It is a collection of specific quantum gate objects, all of which originate from primitive quantum circuits. Door Collection The following strict conditions must be met simultaneously: ① Consistency of the target: Every door in the set Both act on qubits ② Consistency of feature direction: Each gate in the set In quantum bits Feature direction Both are related to the feature direction of the supernode Same. ③Maximum and connectivity: It is the "largest" set that satisfies the above conditions. This means that in the sequence of the original circuit, it is impossible to find any other circuit that acts on the same condition. Having the same characteristic direction And it can be used with the commutative law of gates. All other quantum gates that are temporally adjacent (i.e., connected together via a swapping operation) to each other. In other words, This represents the circuit in quantum bits. Above, a maximum contiguous block consisting of gates of the same algebraic type connected by a commutative law. This definition makes supernodes... It is no longer a simple node representing a single gate, but a composite node representing a local algebraic equivalence class cluster. A condensed graph representation may contain multiple gates that, in a traditional directed acyclic graph (DAG), would be represented as isolated nodes due to their commutativity, thus losing the crucial information that they all act on the same qubit and share the same algebraic properties. In condensed graph representation, these gates are aggregated into a supernode, perfectly preserving the local structure of the circuit. Any higher-level application requiring analysis of the circuit in this region (such as template matching or local optimization) can access this supernode and its neighborhood to obtain all relevant and algebraically equivalent quantum gate information at once, avoiding the global search required in traditional DAGs.

[0076] In summary, the triples of supernodes It is a data structure that integrates spatial location (qubit identifier), algebraic properties (characteristic orientation), and topological entity (maximum commutative gate set). It is the core carrier for achieving the three beneficial effects of this invention: "complete preservation of gate commutativity, lossless preservation of connectivity, and strict preservation of locality." Through this representation, the physical constraints and algebraic structure of quantum circuits are simultaneously and clearly mapped into the theoretical framework of the hypergraph.

[0077] S4. Construct a condensed graph representation of the quantum circuit by combining the set of supernodes and the set of superedges. The specific implementation process is as follows: S40. Obtain two global, fully populated datasets as input. The first dataset is the set of supernodes, denoted as... .gather Includes traversing the set of quantum gates All supernodes created during the process each They are all triples The second set is the hyperedge set, denoted as... .gather It includes two types of hyperedges: one is for each qubit during the initialization phase. Created directed superedge Secondly, in processing each multi-qubit gate Created at time for connecting containing Connect all supernodes with superedges. Ensure that these two sets... and It is the final output state of the algorithm and contains all the information necessary to construct a complete graph representation.

[0078] S41. To implement the construction operation, a data structure for carrying the agglomerative graph representation needs to be defined first. This data structure is a composite object, which can be named CondensedGraph or HypergraphRepresentation. This data structure needs to contain at least two core member variables to store the input data, specifically: ①vertex_set: used to store the set of supernodes. ②hyperedge_set: Used to store the set of hyperedges. Furthermore, this data structure can also contain some meta-information, such as the identifier of the original quantum circuit it represents and the total number of qubits. To enhance readability and usability, the definition of the data structure should ensure efficient support for upper-layer applications to access, traverse, and query supernodes and superedges.

[0079] S42. A concrete instance of the CondensedGraph representation object will be created. The operation is: instantiate the defined CondensedGraph data structure, generating a new object instance, denoted as... Then, the prepared set of supernodes... Assign to The `vertex_set` member will set the superedges. Assign to The hyperedge_set member. This assignment operation completes the data integration, making... and From independent sets, they become components of a unified graph structure. Symbolically, the constructed agglomerative graph is represented as: ,Right now .

[0080] S43. After integrating the set, optional verification steps can be performed to ensure the internal consistency of the agglomerative graph representation. Verification includes checking each directed hyperedge. Is the order of supernodes on the same as that of qubits? The door sequence is consistent; check that each one is a door. Does the created connecting hyperedge actually connect all and only those gates contained in the set? The graph structure can be normalized, for example, by assigning globally unique integer identifiers to supernodes and superedges, to facilitate isomorphic comparisons or serialized storage of the graph.

[0081] S44. After instantiation and verification The object is quantum circuits. The final condensed graph representation is obtained. The algorithm outputs this object. The output format can be determined according to application requirements: it can be returned directly to the caller in memory for subsequent template matching and optimization algorithms; or it can be serialized into a standard file format (such as JSON, GraphML, or a custom format) and stored on disk for persistent storage and exchange. Thus, from the original quantum circuit... To its condensation diagram representation The entire conversion process is now complete.

[0082] The technical solution of the present invention will be further described through embodiments, which provide a quantum circuit. The circuit contains the complete set of qubits. Door Collection The construction process of its condensation diagram representation includes: S101, Ergodic Quantum Circuit Each door in . Targeting the door Each quantum bit that is acted upon It is necessary to calculate the gate In this quantum bit Feature direction .in It is a door The function of a set of qubits.

[0083] The calculation rules vary depending on the type of gate: for single-qubit gates, the characteristic direction is calculated directly from the gate's unitary matrix. For example, the characteristic direction calculated from the unitary matrix of a Pauli-X gate is... The characteristic directions calculated from the unitary matrix of the Pauli-Z gate are: For multi-control single-objective qubit gates, the characteristic orientation of the control qubit is fixed as the computational basis. The characteristic orientation of the target qubit needs to be calculated based on the unitary transform properties of the gate. For example, the characteristic orientation of the CX gate target qubit is... .

[0084] S102. Initialize the supernode set It is an empty set, that is Initialize the hyperedge set. It is an empty set, that is For the complete set of quantum bits Each qubit in Perform the following operations: Create a directed superedge And add this directed superedge to the superedge set. ,Right now For the complete set of quantum bits Each qubit in Maintain an auxiliary variable called the "nearest supernode pointer", denoted as Set the initial value of all nearest supernode pointers to 0. .pointer Used for dynamic tracking of qubits The most recently created or updated supernode online.

[0085] S103, according to quantum circuit The gate sequence is traversed sequentially from the input to the output. For each door visited... Perform the following sub-steps: 1) Obtain the gate Functional qubit set ,in It is the number of qubits that the gate operates on.

[0086] 2) Set of interacting qubits Each qubit in Perform supernode processing operations: ①If the quantum bit pointer to the nearest supernode equal This indicates that in quantum bits No supernodes have been built online yet. At this point, a new supernode needs to be created. This new supernode The triplet is defined as follows: qubit identifier Set as ; Characteristic direction Set as a door Feature direction on this bit ; door set Initialize to include only the current gate set Then, the newly created supernode Add to the set of supernodes In the middle; updating qubits Set the pointer to the nearest supernode to point to ,Right now Finally, this new supernode Placed as a qubit Created directed superedge superior.

[0087] ②If the quantum bit pointer to the nearest supernode Not equal to Let the existing supernode it points to be At this point, it is necessary to determine the door. exist Feature direction Is it compatible with existing supernodes? Feature orientation stored in If they are equal, then the current door will be selected. Merge into existing supernodes In the set of doors, that is Recent supernode pointer Keep pointing The supernode remains unchanged. If they are not equal, a new supernode needs to be created. This new supernode The triplet is defined as: , , .Will Add to supernode set ;Will Place on the directed superedge Above, and must be adjacent to the node. Then; finally update the pointer. .

[0088] 3) Construct connecting hyperedges. Collect all processed gates whose set contains the current gate. The supernode. Specifically, for each What is collected is the supernode after processing in case one or case two (it may be a newly created one). It may have been updated. Construct a new connecting superedge using these collected supernodes, connecting all of them. Add this new connecting superedge to the superedge set. middle.

[0089] S104, Gathering at the Door After all doors have been processed in sequence, the algorithm iteration ends. At this point, the set of supernodes... and superedge set The entire structure has been built. These two sets will be used as a pair. The output is the quantum circuit. The final condensation diagram represents .

[0090] In this context, the condensed graph of a quantum circuit is represented as a hypergraph. For any quantum circuit... Its condensation diagram is represented as a binary tuple, denoted as The pair is defined as follows: In this definition, Represents the set of supernodes. This represents a set of superedges. This representation is used to fully preserve the gate commutativity, connectivity, and locality information of quantum circuits.

[0091] Each supernode They all belong to the set of supernodes. ,Right now Each supernode is a triplet structure containing a qubit identifier, a characteristic orientation, and a set of gates. Formalized as follows: Each element is defined as: a) This is a supernode. The corresponding qubit identifier. Belongs to quantum circuits The complete set of quantum bits ,Right now It is used to determine which specific qubit line in a quantum circuit a supernode is associated with. (b) This is a supernode. The characteristic orientation, also referred to as algebraic fingerprint in some descriptions, characterizes the supernode. All quantum gates within a qubit The common transformation direction on the qubit is a set of generalized eigenbases. Its core property is: if two quantum gates have the same characteristic direction on the same qubit, then the two quantum gates are commutative on that qubit. This is a supernode. It contains a set of quantum gates. It originates from quantum circuits. The extracted set of maximum gates that satisfies the following condition: all gates in the set act on qubits. All gates are in this quantum bit The feature directions on are all with They are identical; and these gates are adjacent in the original circuit sequence, or can become adjacent through gate commutativity. Therefore, It represents the largest commutative set of gates in the same algebraic equivalence class, to which no other gates satisfying the same conditions can be added.

[0092] Among them, the hyperedge set It includes two types of hyperedges used to characterize various relationships between supernodes, thereby ensuring that the integrity of the overall circuit structure is preserved in the graph. Specifically, these include: a) directed hyperedges corresponding to qubits: for quantum circuits. Each qubit in Create a directed superedge independently, denoted as This edge is used to organize qubits located in the same quantum bit in chronological order. All supernodes on the quantum bit line are used to maintain the temporal connectivity of that quantum bit line. b) Connecting superedges corresponding to quantum gates: for quantum circuits. Each multi-qubit gate in Construct a connecting hyperedge. This hyperedge will connect all gates contained in the set. A supernode. Because of a multi-qubit gate. Simultaneously acting on multiple qubits, during the processing, each affected qubit line generates or associates a qubit containing... The supernode. The role of this superedge is to explicitly maintain the cross-qubit correlation brought about by the multi-qubit gate, preventing the loss of this connectivity information.

[0093] like Figure 2 As shown, the quantum circuit comprises a structure of four controlled NOT gates acting on two qubits. Each controlled NOT gate is a multi-control single-target qubit gate, containing one control qubit and one target qubit. The order of the gate sequence defines the execution logic of the quantum circuit; as... Figure 3 As shown, another quantum circuit, although the gate sequence order is the same as... Figure 2 The two quantum circuits shown are different, but they are functionally equivalent in the sense of gate commutativity. This equivalence stems from the commutative property of controlled NOT gates under certain conditions. Figure 4 It shows Figure 2 and Figure 3 The corresponding quantum circuit is represented by a condensed graph, which is a hypergraph formed by merging commutative gate components. This representation is unique for commutatively equivalent circuits, so two circuits share a single condensed graph representation. Specifically, the condensed graph representation construction process begins by calculating the characteristic orientation of each quantum gate. For controlled-NOT gates, the characteristic orientation of the control qubits is fixed as the computational basis, and the characteristic orientation of the target qubits is calculated using the unitary transformation properties of the gates. Next, the set of supernodes and the set of superedges are initialized, and a directed superedge is created for each qubit, along with a pointer to the nearest supernode. Then, each controlled-NOT gate is iteratively processed according to the gate sequence. For each qubit in the set of qubits acting on a gate, a supernode processing operation is performed: if the pointer to the nearest supernode of that qubit is empty, a new supernode is created. A supernode is defined as follows: it contains the identifier of the qubit, its characteristic direction, and a set of gates containing only the current gate. The supernode is then placed on the corresponding directed superedge, and the pointer is updated. If the pointer is not empty, the characteristic direction of the current gate on the qubit is compared with the characteristic direction stored in the supernode pointed to by the pointer. If they are the same, the current gate is merged into the gate set of the supernode. If they are different, a new supernode is created and placed on the directed superedge immediately after the original supernode, while the pointer is updated. After processing all the active qubits of a gate, all supernodes containing that gate are collected, and a connecting superedge is constructed and added to the superedge set. Since the supernodes of condensed graph representation encapsulate the largest commutative set of gates with the same characteristic orientation, and maintain temporal correlations within qubits through directed superedges and cross-qubit correlations of multi-qubit gates through connecting superedges, regardless of the order of controlled-NOT gates in the original circuit, as long as they satisfy the commutative law, they will eventually be merged into the same supernode, and the superedge connection mode remains consistent. This ensures that commutatively equivalent quantum circuits will necessarily produce isomorphic condensed graph representation structures, which reflects the canonical nature of condensed graph representation and provides an efficient foundation for verifying the equivalence of quantum circuits. Upper-level applications can directly compare whether the condensed graph representations of two quantum circuits are isomorphic to determine their functional equivalence without having to deal with complex gate commutation logic.

[0094] In another embodiment, the following steps are included: I. The quantum support vector machine (SVM) from quantum machine learning is chosen as the practical application area, specifically for binary image classification. Assume the image to be classified is a 2×2 pixel binary grayscale image, where each pixel value is either 0 or 1. The quantum support vector machine calculates the kernel function through a quantum circuit, thereby completing the image classification. To illustrate the implementation process of this invention, a simplified quantum circuit C is constructed, which is used to calculate the kernel function value between two classes of images. The quantum circuit C contains 4 qubits, corresponding to the 4 pixel positions of the image. The complete set of qubits is denoted as Q = { , , , The gate set G contains 6 quantum gates, arranged in the order of circuit execution as follows: gates : Action on qubits Single-qubit Hadamard gate H, gate : Action on qubits Single-qubit Hadamard gate H, gate : Action on qubits (Control) and The two qubits of the target are controlled NOT gate CX, and the gate... : Action on qubits Single-qubit Pauli-Z gate; : Action on qubits (Control) and (Target) Two-qubit controlled NOT gate CX; gate : Action on qubits (Control) and The target consists of two qubits controlled NOT gate CX. This quantum circuit encodes image features and performs the entanglement operations required for linear classification.

[0095] II. Constructing a condensed graph representation of a quantum circuit using the method of this application includes the following steps: 1) Traverse each gate in the gate set G and calculate its characteristic orientation on the acting qubit, specifically including: ①For the door (Single-qubit Hadama gate) The unitary matrix is Solve the characteristic equation This yields two eigenvectors: and Therefore, the door In quantum bits The characteristic direction on is .here, Indicates a door In quantum bits The characteristic direction on the axis is a set containing two eigenvectors; and These are specific eigenvectors; and It calculates the ground state.

[0096] ②Regarding the door (Single-qubit Hadama gate) Similarly, the characteristic direction can be calculated. .

[0097] ③For the door (Two-qubit controlled NOT gate) ): As a multi-control single-objective quantum bit gate (number of control bits) ), control qubits The characteristic orientation is fixed as the computational basis: Target qubit The characteristic direction is calculated through equivalent transformation: when the control bit is When the target bit performs Pauli- Gate transformation. Pauli- The characteristic direction of the door is ,in , Therefore .

[0098] ④ Regarding the door (Single-qubit Pauli) Door The unitary matrix is Its eigenvectors are the basis for computation, therefore the characteristic directions are... .

[0099] ⑤ Regarding the door (Two-qubit controlled NOT gate) ), control qubits The characteristic orientation is fixed as the computational basis: Target qubit The characteristic direction is based on Pauli- The equivalent transformation of the gate is obtained as follows: Therefore .

[0100] ⑥ Regarding the door (Two-qubit controlled NOT gate) ), control qubits The characteristic orientation is fixed as the computational basis: Target qubit The characteristic direction is also based on Pauli- The equivalent transformation of the gate is obtained as follows: Therefore .

[0101] All the feature directions calculated above are stored in the mapping data structure. In the middle, making Return Door In quantum bits Feature direction set .

[0102] 2) Initialize the set of supernodes An empty set: Initialize the hyperedge set An empty set: For the complete set of quantum bits Each qubit in the array creates a directed superedge; specifically, for each qubit... Create a directed superedge ,join in ; for qubit Create a directed superedge ,join in ; for qubit Create a directed superedge ,join in ; for qubit Create a directed superedge ,join in ; Initialize the nearest supernode pointer for each qubit, specifically, , , , .

[0103] 3) Traverse each gate in the gate set G according to the gate sequence order, specifically: ① Processing door (Single-qubit Hadamard gate acting on) ), the set of functional qubits Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Create the first supernode Its triple is: ;Will Add to supernode set Update the pointer to the most recent supernode. ;Will Place on the directed superedge Above. Collect information containing doors. All supernodes: Currently only Constructing connected hyperedges Connect the set of supernodes ;Will Add to superedge set .

[0104] ② Processing door (Single-qubit Hadamard gate acting on) ), the set of functional qubits Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Create the first supernode Its triple is: ;Will Add to supernode set Update the pointer to the most recent supernode. ;Will Place on the directed superedge Above. Collect information containing doors. All supernodes: Currently only Constructing connected hyperedges Connect the set of supernodes ;Will Add to superedge set .

[0105] ③ Processing door (Two qubits controlled NOT gate acting on) and ), the set of functional qubits Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Comparison of feature directions: , Create a second supernode if the feature directions are different. Its triple is: ;Will Add to supernode set ;Will Place on the directed superedge Above, and located Next; update the nearest supernode pointer. Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Comparison of feature directions: , Create a second supernode if the feature directions are different. Its triple is: ;Will Add to supernode set ;Will Place on the directed superedge Above, and located Next; update the nearest supernode pointer. Collecting information containing doors All supernodes: for for ,for for Constructing connected hyperedges Connect the set of supernodes ;Will Add to superedge set .

[0106] ④ Processing door (Single-qubit Pauli-) Gates act on ), the set of functional qubits Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Comparison of feature directions: , Create a second supernode if the feature directions are different. Its triple is: ;Will Add to supernode set ;Will Place on the directed superedge Above, and located Next; update the nearest supernode pointer. Collecting information containing doors All supernodes: Currently only Constructing connected hyperedges Connect the set of supernodes ;Will Add to superedge set .

[0107] ⑤ Processing door (Two qubits controlled NOT gate acting on) and ), the set of functional qubits Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Comparison of feature directions: , The features are in the same direction, so the door will be... Merge into supernode The collection of doors: The most recent supernode pointer remains unchanged: Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Create the first supernode Its triple is: ;Will Add to supernode set Update the pointer to the most recent supernode. ;Will Place on the directed superedge Above. Collect information containing doors. All supernodes: for for ,for for Constructing connected hyperedges Connect the set of supernodes ;Will Add to superedge set .

[0108] ⑥ Processing door (Two qubits controlled NOT gate acting on) and ), the set of functional qubits Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Comparison of feature directions: , Create a second supernode if the feature directions are different. Its triple is: ;Will Add to supernode set ;Will Place on the directed superedge Above, and located Next; update the nearest supernode pointer. Regarding qubits Perform supernode processing operations: pointer to the most recent supernode Create the first supernode Its triple is: ;Will Add to supernode set Update the pointer to the most recent supernode. ;Will Place on the directed superedge Above. Collect information containing doors. All supernodes: for for ,for for Constructing connected hyperedges Connect the set of supernodes ;Will Add to superedge set .

[0109] 4) Door set Once all gates have been processed, the iteration ends. The result is: a set of supernodes. Hyperedge set Quantum circuits Agglomeration diagrams are represented as binary pairs: .

[0110] III. In the image classification task using quantum support vector machines, condensed graph representation can be used for circuit optimization, equivalence verification, and locality analysis. The specific application process is as follows: 1) Circuit optimization application: Circuit optimization based on condensed graph representation reduces the number of quantum gates by identifying mergeable supernodes. Analysis of condensed graph representation HG(C): ① Examining qubits Directed hyperedge : Contains a sequence of supernodes . The characteristic direction is The gate set is . The characteristic direction is The gate set is Because their characteristic directions are different and there are no other commutative gates in between, these two supernodes cannot be merged. ② Check the qubits. Directed hyperedge : Contains a sequence of supernodes . The characteristic direction is The gate set is . The characteristic direction is The gate set is . The characteristic direction is The gate set is Adjacent supernodes have different characteristic directions and cannot be merged. ③ Check connecting superedges. Connecting to supernodes and Corresponding door By analyzing the connected hyperedges, we found that the gate... Simultaneously associated qubits and In circuit optimization, simpler two-qubit gates can be used as replacements, or the gate order can be adjusted to reduce circuit depth. Local neighborhood analysis using agglomeration graph representation can identify... Contains two doors and They act on different pairs of qubits but share control qubits. Under certain conditions, these two gates may be merged or reordered, thereby reducing the circuit depth. The optimization algorithm only needs to search within the local neighborhood, without traversing the entire circuit.

[0111] 2) Equivalence verification application, assuming there is another quantum circuit Claiming to be with Functionally equivalent in image classification tasks. To verify equivalence, specifically, constructing following the same steps... Agglomeration diagram representation This involves comparing whether two agglomerative graph representations are isomorphic. Specifically, this includes: one-to-one correspondence between supernodes: the triples of each supernode. The qubit identifiers, characteristic directions, and gate sets should all be identical. Hyperedges must also be matched one-to-one: the connection order of directed hyperedges should be consistent, and the sets of supernodes connecting the hyperedges should match. The specific comparison process includes: ① Number of supernodes: have One supernode, It should also be ① Supernodes. ② Characteristic direction distribution: Compare whether the characteristic direction sequences of the supernodes on each qubit line are consistent. Compare whether the modes of the qubits connected by superedges are consistent. If the two condensed graphs represent isomorphism, then the circuit... and They are equivalent in the sense of gate commutativity and have the same function in image classification tasks.

[0112] Compared with the prior art, the present invention has the following advantages: 1) The gate commutative law refers to the commutation relation between quantum gates, meaning that exchanging the order of certain quantum gates under specific conditions does not affect the final quantum state evolution. In condensed graph representation, supernodes are designed to encapsulate a set of commutative gates belonging to the same algebraic equivalence class. Specifically, each supernode... Characteristic directions in triples The common algebraic properties of all gates within this node are defined. If two quantum gates have the same characteristic orientation on the same qubit, they will be merged into the same supernode. This representation directly encodes the commutative properties between gates, eliminating the need for upper-level applications to design additional algorithms to handle the commutative logic of the gates during analysis, thus simplifying the implementation of upper-level applications and reducing complexity.

[0113] 2) Connectivity refers to the interconnections between quantum gates in a quantum circuit through the sharing of qubits. In traditional directed acyclic graph representations, edges between commutative gates are deleted, resulting in the loss of connectivity information. The condensed graph representation of this invention addresses this problem through two types of hyperedges: the first type is a directed hyperedge created for each qubit, which sequentially connects all supernodes on that qubit, maintaining temporal correlations within the same qubit; the second type is a connecting hyperedge created for each multi-qubit gate, which explicitly connects the supernodes corresponding to all qubits involved in that gate, maintaining cross-qubit correlations. These two types of hyperedges work together to ensure that the original, complete spatial and temporal connectivity of the quantum circuit is preserved intact in the condensed graph representation.

[0114] 3) Locality refers to the fact that in quantum circuits, the properties and effects of a gate or a group of gates are typically only related to its neighboring gates. In condensed graph representation, each supernode and its directly connected hyperedges constitute a local neighborhood. Since a supernode encapsulates the largest set of commutative gates, and the hyperedges accurately reflect the interactions between gates, any upper-level application that needs to analyze the local structure of the circuit (e.g., template matching or local circuit optimization) can obtain all relevant gate information by accessing the target supernode and its adjacent supernodes and hyperedges. This avoids the inefficient operation of global graph traversal required in traditional directed acyclic graph representations due to the isolation of commutative gates, thus significantly improving the execution efficiency of upper-level applications.

[0115] 4) Canonicity here refers to a standard and unique representation. The condensed graph representation of this invention is canonical, meaning that all quantum circuits equivalent in the sense of gate commutativity will be constructed as isomorphic hypergraphs. Two hypergraphs are isomorphic if there exists a one-to-one mapping such that the hypernodes and hyperedges in one hypergraph completely correspond to the hypernodes and hyperedges in the other hypergraph, and all associations remain unchanged. Based on this property, the problem of determining whether two quantum circuits are equivalent can be transformed into the problem of determining whether their corresponding condensed graph representations are isomorphic. Graph isomorphism determination is a problem that can be efficiently solved under specific conditions; therefore, this provides an efficient way to verify the equivalence of quantum circuits.

[0116] 5) Construction complexity refers to the time and computational resources required to generate a representation of a primal quantum circuit. The condensed graph representation construction algorithm of this invention has linear time complexity. Let the quantum circuit... The number of qubits is The number of doors is The complexity of constructing the algorithm is O(n). This is because the algorithm primarily involves one traversal of each quantum gate, requiring each qubit (at most) that interacts with the gate during the traversal. (Number) operations are performed in constant time. In contrast, the construction complexity of a traditional directed acyclic graph representation is typically O(n log n). This is because when building dependencies, it's necessary to check the pairwise relationships between gates. As the circuit size (i.e....) increases... and The expansion of linear complexity Compared to squared complexity The advantages will become more pronounced, making this method more suitable for handling large-scale quantum circuits.

[0117] 6) Universality refers to the fact that this representation method can cover a wide range of quantum circuit types and support various upper-level applications. The condensed graph representation of this invention is applicable to all quantum circuits composed of multiple controllable single-objective gates (including single-qubit gates as a special case), which is the gate set supported by current mainstream quantum algorithms and hardware. Simultaneously, as a fundamental data structure, this representation can provide unified support for various upper-level applications in the field of quantum computing, such as fast matching of circuit templates, verification of functional equivalence between different circuits, and circuit optimization during compilation. Because the representation itself completely preserves the key structural information of the circuit, upper-level applications can be developed efficiently based on it, exhibiting good compatibility and broad applicability.

[0118] In the above embodiments, although the steps are numbered S1, S2, etc., they are only specific embodiments given by the present invention. Those skilled in the art can adjust the execution order of S1, S2, etc. according to the actual situation. The scheme after adjusting the order is also within the protection scope of the present invention. It can be understood that in some embodiments, some or all of the above embodiments may be included.

[0119] like Figure 5 As shown, a quantum circuit condensed graph representation acquisition system 200 according to an embodiment of the present invention includes a feature direction determination module 201, a creation module 202, an iterative construction module 203, and a condensed graph representation acquisition module 204; The characteristic orientation determination module 201 is used to: calculate the characteristic orientation of each quantum gate in the quantum circuit on each quantum bit it acts on; wherein, the quantum circuit includes a complete set of quantum bits and a set of quantum gates; The creation module 202 is used to: create a directed superedge for each qubit in the complete set of qubits, and maintain a nearest supernode pointer for each qubit in the complete set of qubits, with all nearest supernode pointers initialized to null; The iterative construction module 203 is used to: traverse each quantum gate in the set of quantum gates according to the gate sequence order of the quantum circuit, and perform iterative construction. The iterative construction includes: for any quantum gate traversed, obtaining the set of active qubits of the quantum gate; for each qubit in the set of active qubits, performing a supernode processing operation, which will generate or update a supernode containing the identifier of the qubit, the characteristic direction of the quantum gate on the qubit, and the set of gates, and add the supernode to the supernode set, and collect all supernodes containing the quantum gate, construct a superedge connecting all supernodes containing the quantum gate, and add the superedge to the superedge set. The condensed graph representation acquisition module 204 is used to: construct a condensed graph representation of a quantum circuit by combining the set of supernodes and the set of superedges.

[0120] Optionally, in the above technical solution, the iterative construction module 203 is further specifically used for: For any qubit in the set of active qubits, if the nearest supernode pointer of the qubit is null, a first supernode is created. The first supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the gate set containing the currently traversed quantum gate. The first supernode is added to the supernode set, the nearest supernode pointer of the qubit is updated to the first supernode, and the first supernode is placed on the directed superedge created for the qubit. If the nearest supernode pointer of the qubit is not null, then it is determined whether the characteristic direction of the currently traversed quantum gate on the qubit is the same as the characteristic direction stored in the supernode pointed to by the nearest supernode pointer. If they are the same, the currently traversed quantum gate is added to the set of gates contained in the supernode pointed to by the nearest supernode pointer. If they are not the same, a second supernode is created. The second supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the set of gates containing the currently traversed quantum gate. The second supernode is added to the set of supernodes, placed on the directed superedge created for the qubit and after the supernode pointed to by the nearest supernode pointer, and the nearest supernode pointer of the qubit is updated to the second supernode.

[0121] Optionally, in the above technical solution, the feature direction determination module 201 is specifically used for: For a single-qubit gate in a quantum circuit, the characteristic direction is calculated based on the unitary matrix of the single-qubit gate. For a multi-controlled single-target qubit gate in a quantum circuit, the characteristic direction of each control qubit of the multi-controlled single-target qubit gate is fixed as the computation basis, and the characteristic direction of the target qubit of the multi-controlled single-target qubit gate is calculated based on the unitary transformation characteristics of the multi-controlled single-target qubit gate.

[0122] Optionally, in the above technical solution, a supernode is a triple containing the identifier of the qubit, the characteristic direction, and the gate set, wherein the identifier of the qubit is used to represent the qubit corresponding to the supernode, the characteristic direction is used to represent the common characteristic direction of all quantum gates in the supernode on the qubit, and the gate set is the largest commutative gate set in the quantum circuit that acts on the qubit and has a common characteristic direction.

[0123] It should be noted that the beneficial effects of the condensed graph representation acquisition system 200 for quantum circuits provided in the above embodiments are the same as those of the condensed graph representation acquisition method for quantum circuits described above, and will not be repeated here. Furthermore, the system provided in the above embodiments is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the system can be divided into different functional modules according to the actual situation to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, and will not be repeated here.

[0124] An electronic device according to an embodiment of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the above-described method for obtaining the condensed graph representation of a quantum circuit.

[0125] An embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described method for obtaining the condensed graph representation of any of the quantum circuits.

[0126] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0127] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for obtaining condensed graph representations of quantum circuits, characterized in that, include: Calculate the characteristic orientation of each quantum gate in a quantum circuit on each qubit it acts upon; wherein the quantum circuit includes a complete set of qubits and a set of quantum gates; Create a directed superedge for each qubit in the complete set of qubits, and maintain a nearest supernode pointer for each qubit in the complete set of qubits, with all nearest supernode pointers initialized to null; According to the gate sequence order of the quantum circuit, each quantum gate in the set of quantum gates is traversed and iteratively constructed. The iterative construction includes: for any quantum gate traversed, obtaining the set of active qubits of the quantum gate; for each qubit in the set of active qubits, performing a supernode processing operation, which generates or updates a supernode containing the identifier of the qubit, the characteristic direction of the quantum gate on the qubit, and the set of gates, and adds the supernode to the supernode set; collecting all supernodes containing the quantum gate, constructing a superedge connecting all supernodes containing the quantum gate, and adding the superedge to the superedge set. The set of supernodes and the set of superedges are used together to construct a condensed graph representation of the quantum circuit.

2. The method for obtaining a condensed graph representation of a quantum circuit according to claim 1, characterized in that, For each qubit in the set of active qubits, perform supernode processing operations, including: For any qubit in the set of active qubits, if the nearest supernode pointer of the qubit is null, a first supernode is created. The first supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the gate set containing the currently traversed quantum gate. The first supernode is added to the set of supernodes, the nearest supernode pointer of the qubit is updated to the first supernode, and the first supernode is placed on the directed superedge created for the qubit. If the nearest supernode pointer of the qubit is not null, then it is determined whether the characteristic direction of the currently traversed quantum gate on the qubit is the same as the characteristic direction stored in the supernode pointed to by the nearest supernode pointer. If they are the same, the currently traversed quantum gate is added to the gate set contained in the supernode pointed to by the nearest supernode pointer. If they are not the same, a second supernode is created. The second supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the gate set containing the currently traversed quantum gate. The second supernode is added to the supernode set, placed on the directed superedge created for the qubit and after the supernode pointed to by the nearest supernode pointer, and the nearest supernode pointer of the qubit is updated to the second supernode.

3. The method for obtaining a condensed graph representation of a quantum circuit according to claim 2, characterized in that, Calculate the characteristic orientation of each quantum gate in a quantum circuit on each qubit it operates on, including: For a single-qubit gate in a quantum circuit, the characteristic direction is calculated based on the unitary matrix of the single-qubit gate; for a multi-controlled single-target qubit gate in a quantum circuit, the characteristic direction of each control qubit of the multi-controlled single-target qubit gate is fixed as a computational basis, and the characteristic direction of the target qubit of the multi-controlled single-target qubit gate is calculated based on the unitary transformation characteristics of the multi-controlled single-target qubit gate.

4. A method for obtaining a condensed graph representation of a quantum circuit according to claims 1 to 3, characterized in that, The supernode is a triple containing the identifier of the qubit, the characteristic direction, and the gate set. The identifier of the qubit is used to represent the qubit corresponding to the supernode. The characteristic direction is used to represent the common characteristic direction of all quantum gates in the supernode on the qubit. The gate set is the largest commutative gate set in the quantum circuit that acts on the qubit and has the common characteristic direction.

5. A system for acquiring condensed graph representations of quantum circuits, characterized in that, It includes a feature orientation determination module, a creation module, an iterative construction module, and an condensed graph representation acquisition module; The characteristic orientation determination module is used to: calculate the characteristic orientation of each quantum gate in the quantum circuit on each quantum bit it acts upon; wherein, the quantum circuit includes a complete set of quantum bits and a set of quantum gates; The creation module is used to: create a directed superedge for each qubit in the complete set of qubits, and maintain a nearest supernode pointer for each qubit in the complete set of qubits, with all nearest supernode pointers initialized to null; The iterative construction module is used to: traverse each quantum gate in the set of quantum gates according to the gate sequence order of the quantum circuit, and perform iterative construction. The iterative construction includes: for any quantum gate traversed, obtaining the set of active qubits of the quantum gate; for each qubit in the set of active qubits, performing a supernode processing operation, which generates or updates a supernode containing the identifier of the qubit, the characteristic direction of the quantum gate on the qubit, and the set of gates, and adds the supernode to the supernode set, and collects all supernodes containing the quantum gate, constructs a superedge connecting all supernodes containing the quantum gate, and adds the superedge to the superedge set. The condensed graph representation acquisition module is used to: construct the condensed graph representation of the quantum circuit by combining the set of supernodes and the set of superedges.

6. The condensed graph representation acquisition system for quantum circuits according to claim 5, characterized in that, The iterative construction module is also specifically used for: For any qubit in the set of active qubits, if the nearest supernode pointer of the qubit is null, a first supernode is created. The first supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the gate set containing the currently traversed quantum gate. The first supernode is added to the set of supernodes, the nearest supernode pointer of the qubit is updated to the first supernode, and the first supernode is placed on the directed superedge created for the qubit. If the nearest supernode pointer of the qubit is not null, then it is determined whether the characteristic direction of the currently traversed quantum gate on the qubit is the same as the characteristic direction stored in the supernode pointed to by the nearest supernode pointer. If they are the same, the currently traversed quantum gate is added to the gate set contained in the supernode pointed to by the nearest supernode pointer. If they are not the same, a second supernode is created. The second supernode contains the identifier of the qubit, the characteristic direction of the currently traversed quantum gate on the qubit, and the gate set containing the currently traversed quantum gate. The second supernode is added to the supernode set, placed on the directed superedge created for the qubit and after the supernode pointed to by the nearest supernode pointer, and the nearest supernode pointer of the qubit is updated to the second supernode.

7. The condensed graph representation acquisition system for quantum circuits according to claim 6, characterized in that, The feature direction determination module is specifically used for: For a single-qubit gate in a quantum circuit, the characteristic direction is calculated based on the unitary matrix of the single-qubit gate; for a multi-controlled single-target qubit gate in a quantum circuit, the characteristic direction of each control qubit of the multi-controlled single-target qubit gate is fixed as a computational basis, and the characteristic direction of the target qubit of the multi-controlled single-target qubit gate is calculated based on the unitary transformation characteristics of the multi-controlled single-target qubit gate.

8. A condensed graph representation acquisition system for quantum circuits according to claims 5 to 7, characterized in that, The supernode is a triple containing the identifier of the qubit, the characteristic direction, and the gate set. The identifier of the qubit is used to represent the qubit corresponding to the supernode. The characteristic direction is used to represent the common characteristic direction of all quantum gates in the supernode on the qubit. The gate set is the largest commutative gate set in the quantum circuit that acts on the qubit and has the common characteristic direction.

9. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a method for obtaining a condensed graph representation of a quantum circuit as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements a method for obtaining a condensed graph representation of a quantum circuit as described in any one of claims 1 to 4.

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