A Universal Flash Memory (UFS) Temperature Control Circuit, Method, and Electronic Device

Abstract

This application discloses a universal flash memory (UFS) temperature control circuit, method, and electronic device, relating to the field of electronic technology, for reducing UFS failures and enabling electronic devices to successfully power on or restart. The UFS temperature control circuit includes a processor, a UFS, and a temperature sensor; the processor acquires first indication information of the UFS and obtains the temperature of the UFS through the temperature sensor; the first indication information is used to characterize whether the number of error corrections for the UFS stored data is greater than an error correction threshold; the processor is used to control the target module of the UFS to increase its temperature when the temperature of the UFS is less than the first temperature threshold and the number of error corrections for the UFS stored data is greater than the error correction threshold.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a temperature control circuit, method, and electronic device for universal flash memory (UFS). Background Technology

[0002] Currently, in extremely cold conditions, the temperature of the UFS (Ultra-Flash Storage) within electronic devices such as mobile phones is typically lower than their operating temperature. This can lead to data corruption and other malfunctions in the UFS, such as bad blocks, freezing, or response timeouts, causing the electronic device to shut down or become unable to power on or restart. Summary of the Invention

[0003] This application provides a universal flash memory (UFS) temperature control circuit, method, and electronic device to reduce UFS failures and enable the electronic device to successfully power on or restart.

[0004] To achieve the objective, the embodiments of this application employ the following technical methods:

[0005] In a first aspect, a universal flash memory (UFS) temperature control circuit is provided. The UFS temperature control circuit includes a processor, a UFS, and a temperature sensor. The processor acquires first indication information of the UFS and acquires the temperature of the UFS through the temperature sensor. The first indication information is used to characterize whether the number of error corrections for the UFS stored data is greater than the error correction number threshold. The processor is used to control the target module of the UFS to operate and increase the temperature when the temperature of the UFS is less than the first temperature threshold and the number of error corrections for the UFS stored data is greater than the error correction number threshold.

[0006] The aforementioned general-purpose flash memory (UFS) temperature control circuit controls the target module of the UFS to heat up when the UFS temperature is below a first temperature threshold and the number of error corrections for the stored data in the UFS exceeds the error correction count threshold. This allows the UFS to be heated even when the ambient temperature is below its operating temperature, thereby reducing UFS failures and enabling the electronic device to power on or restart successfully. In one possible implementation of the first aspect, the UFS includes a first central processing unit (CPU) core, and the target module includes SRAM. The first CPU core manages the reading and writing of the SRAM. Controlling the target module of the UFS to heat up includes controlling the first CPU core to heat up the SRAM during data reading and writing.

[0007] In this implementation, when the heating conditions are met, a heating method with lower heat generation efficiency is first used. That is, the first CPU core is controlled to read and write data to the SRAM to generate heat. This heating method does not consume processor bandwidth or UFS bandwidth, nor does it consume flash memory lifespan. At this time, both the first CPU core and the SRAM generate heat, resulting in lower heat generation efficiency.

[0008] In one possible implementation of the first aspect, the UFS further includes a second central processing unit (CPU) core, which is used to transmit data with the processor; controlling the target module of the UFS to run and heat up further includes: after controlling the first CPU core to heat up the SRAM read and write data for a first preset time, and if the temperature of the UFS is less than or equal to a second temperature threshold, controlling the second CPU core to process data from the processor and heat up the UFS.

[0009] In this implementation, after controlling the first CPU core to heat up the SRAM for a first preset time while reading and writing data, and if the UFS temperature is less than or equal to a second temperature threshold, the second CPU core is then controlled to process data from the processor to heat up. This indicates that controlling the first CPU core to heat up the SRAM by reading and writing data is insufficient to raise the temperature above the second temperature threshold. Therefore, further heating is required. A heating method with moderate heat dissipation efficiency can be used, meaning the second CPU core is again controlled to process data from the processor to heat up. This heating method does not consume the lifespan of the flash memory. At this point, the first CPU core, SRAM, and second CPU core all generate heat, with moderate heat dissipation efficiency.

[0010] In one possible implementation of the first aspect, the target module further includes flash memory, and the first CPU core is also used to manage the reading and writing of flash memory; controlling the target module of UFS to run and heat up also includes: after controlling the second CPU core to process data from the processor and heat up for a first preset time, and if the temperature of UFS is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory for reading and writing data.

[0011] In this implementation, after the second CPU core processes data from the processor and heats up for a first preset time, and the UFS temperature is less than or equal to a second temperature threshold, the first CPU core is then controlled to heat up the flash memory for reading and writing data. This indicates that controlling the second CPU core to process data from the processor to heat up the flash memory cannot achieve a temperature greater than the second temperature threshold. Therefore, further heating is required. A more efficient heating method can be used, meaning the first CPU core is again controlled to heat up the flash memory for reading and writing data. This heating method somewhat reduces the lifespan of the flash memory. At this point, the first CPU core, SRAM, second CPU core, and flash memory all generate heat, resulting in high heating efficiency.

[0012] In one possible implementation of the first aspect, the UFS includes a second central processing unit (CPU) core for data transmission with the processor; the processor is further configured to: acquire second indication information of the UFS when the temperature of the UFS is less than a first temperature threshold and the number of error corrections of the data stored in the UFS is less than or equal to the number of error corrections threshold; the second indication information is used to characterize whether the number of reads and writes to the UFS by the processor is greater than the number of reads and writes threshold; acquire the battery power level when the number of reads and writes to the UFS by the processor is less than or equal to the number of reads and writes threshold; and control the target module of the UFS to operate and heat up when the battery power level is greater than the power level threshold and the battery is not in super power saving mode.

[0013] In this implementation, when the UFS temperature is below a first temperature threshold and the number of error corrections performed on the UFS stored data exceeds a certain threshold, further factors such as the processor's read / write operations on the UFS, battery level, and battery mode are considered. If the processor's read / write operations on the UFS are less than or equal to a certain threshold, the battery level is greater than a certain threshold, and the battery is not in ultra-low power mode, the target module of the UFS is controlled to heat up. This allows the UFS to be heated when the ambient temperature is below its operating temperature, thereby reducing UFS failures and enabling electronic devices to power on or restart successfully. Furthermore, it avoids excessive power consumption during the heating process, which could lead to the electronic device shutting down, thus improving the user experience.

[0014] In one possible implementation of the first aspect, the UFS further includes a first central processing unit (CPU) core, the target module includes SRAM, the first CPU core is used to manage the reading and writing of SRAM; controlling the operation of the target module of the UFS to increase the temperature includes: controlling the first CPU core to increase the temperature of the SRAM for reading and writing data.

[0015] In this implementation, when the heating conditions are met, a heating method with lower heat generation efficiency is first used. That is, the first CPU core is controlled to read and write data to the SRAM to generate heat. This heating method does not consume processor bandwidth or UFS bandwidth, nor does it consume flash memory lifespan. At this time, both the first CPU core and the SRAM generate heat, resulting in lower heat generation efficiency.

[0016] In one possible implementation of the first aspect, controlling the target module of the UFS to run and heat up further includes: after controlling the first CPU core to heat up the SRAM read and write data for a first preset time, and if the temperature of the UFS is less than or equal to a second temperature threshold, controlling the second CPU core to process data from the processor and heat up the UFS.

[0017] In this implementation, after controlling the first CPU core to heat up the SRAM for a first preset time while reading and writing data, and if the UFS temperature is less than or equal to a second temperature threshold, controlling the second CPU core to process data in the UFS to heat up indicates that controlling the first CPU core to heat up the SRAM is insufficient to raise the temperature above the second temperature threshold. Therefore, further heating is required. A heating method with moderate heat dissipation efficiency can be used, meaning the second CPU core is also controlled to process data from the processor to heat up. This heating method does not consume the lifespan of the flash memory. At this point, the first CPU core, SRAM, and second CPU core all generate heat, with moderate heat dissipation efficiency.

[0018] In one possible implementation of the first aspect, the target module further includes flash memory, and the first CPU core is also used to manage the reading and writing of flash memory; controlling the target module of UFS to run and heat up includes: after controlling the second CPU core to process data from the processor to heat up for a first preset time, and when the temperature of UFS is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory for reading and writing data.

[0019] In this implementation, after the second CPU core processes data from the processor and heats up for a first preset time, and the UFS temperature is less than or equal to a second temperature threshold, the first CPU core is then controlled to heat up the flash memory for reading and writing data. This indicates that controlling the second CPU core to process data from the processor to heat up the flash memory cannot achieve a temperature greater than the second temperature threshold. Therefore, further heating is required. A more efficient heating method can be used, meaning the first CPU core is again controlled to heat up the flash memory for reading and writing data. This heating method somewhat reduces the lifespan of the flash memory. At this point, the first CPU core, SRAM, second CPU core, and flash memory all generate heat, resulting in high heating efficiency.

[0020] In one possible implementation of the first aspect, the UFS includes a second central processing unit (CPU) core for data transmission with the processor; the processor is further configured to: acquire second indication information of the UFS when the temperature of the UFS is less than a first temperature threshold and the number of error corrections of the data stored in the UFS is less than or equal to the number of error corrections threshold; the second indication information is used to characterize whether the number of reads and writes to the UFS by the processor is greater than the number of reads and writes threshold; and when the number of reads and writes to the UFS by the processor is greater than the number of reads and writes threshold, and the UFS prohibits the second CPU core from processing data from the processor, control the target module of the UFS to operate and increase its temperature.

[0021] In this implementation, when the UFS temperature is below a first temperature threshold and the number of error corrections performed on the UFS stored data exceeds a certain threshold, further factors such as the number of read / write operations performed by the processor on the UFS and the UFS's restriction on the second CPU core from processing data from the processor are considered. If the number of read / write operations performed by the processor on the UFS exceeds the threshold and the UFS restricts the second CPU core from processing data from the processor, the target module of the UFS is controlled to increase its temperature. This allows the UFS to be heated when the ambient temperature is below its operating temperature, thereby reducing UFS failures and enabling electronic devices to boot or restart successfully. While ensuring that the UFS heating does not consume processor processing power, it also improves the user experience.

[0022] In one possible implementation of the first aspect, the UFS further includes a first central processing unit (CPU) core, the target module includes SRAM, the first CPU core is used to manage the reading and writing of SRAM; controlling the operation of the target module of the UFS to increase the temperature includes: controlling the first CPU core to increase the temperature of the SRAM for reading and writing data.

[0023] In this implementation, when the heating conditions are met, a heating method with lower heat generation efficiency is first used. That is, the first CPU core is controlled to read and write data to the SRAM to generate heat. This heating method does not consume processor bandwidth or UFS bandwidth, nor does it consume flash memory lifespan. At this time, both the first CPU core and the SRAM generate heat, resulting in lower heat generation efficiency.

[0024] In one possible implementation of the first aspect, the target module further includes flash memory, and the first CPU core is also used to manage the reading and writing of flash memory; controlling the target module of UFS to operate and heat up includes: after controlling the first CPU core to heat up the SRAM reading and writing data for a first preset time, and when the temperature of UFS is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory reading and writing data.

[0025] In this implementation, after controlling the first CPU core to heat up the SRAM for a first preset time during SRAM read / write operations, and if the UFS temperature is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory during SRAM read / write operations indicates that this method cannot raise the temperature above the second threshold. Therefore, further heating is required. Since the UFS prohibits the second CPU core from processing data from the processor, the method of skipping the second CPU core's data processing during heating must be skipped. A heating method with higher heat dissipation efficiency can be used, meaning the first CPU core is still controlled to heat up the flash memory during read / write operations. This heating method somewhat reduces the lifespan of the flash memory. At this point, the first CPU core, SRAM, and flash memory all generate heat, resulting in high heat dissipation efficiency.

[0026] In one possible implementation of the first aspect, the UFS further includes multiple storage blocks, and the processor is further configured to: after controlling the first CPU core to heat up the flash memory for reading and writing data, acquire a target block from the multiple storage blocks, and control the UFS to heat up the target block through erase and write operations.

[0027] In this implementation, the first CPU core needs to find target blocks among multiple storage blocks to erase and write data to the flash memory, which generates heat. Therefore, UFS will scan the areas in the flash memory that are suitable for erasing and writing in order to find the target blocks for erasing and writing.

[0028] In one possible implementation of the first aspect, multiple storage blocks include initial bad blocks, and controlling the UFS to heat up through erase / write operations on the target blocks includes: controlling the UFS to heat up through erase / write operations on the initial bad blocks.

[0029] In this implementation, since the initial bad block refers to the storage block that was already damaged when the UFS was manufactured, erasing or writing the initial bad block will not consume the lifespan of the normal storage block, and therefore will not consume the lifespan of the UFS.

[0030] In one possible implementation of the first aspect, multiple storage blocks include running bad blocks but do not include initial bad blocks, and controlling the UFS to heat up through erase / write operations on target blocks includes: controlling the UFS to heat up through erase / write operations on running bad blocks.

[0031] In this implementation, since running bad blocks refer to bad storage blocks generated during normal operation after the UFS leaves the factory, when there are no initial bad blocks, running bad blocks can be found as replacements for the initial bad blocks for erasing and rewriting. Similarly, erasing and rewriting running bad blocks will not consume the lifespan of normal storage blocks, and therefore will not consume the lifespan of the UFS.

[0032] In one possible implementation of the first aspect, the multiple storage blocks do not include running bad blocks and do not include initialization blocks, and controlling the UFS to heat up the target block through erase and write operations includes: controlling the UFS to heat up the storage block with the fewest erase and write operations among the multiple storage blocks.

[0033] In this implementation, excluding both initial bad blocks and running bad blocks, the block with the fewest erase / write cycles is designated as the target block. This is because the higher the number of erase / write cycles a block has, the shorter its lifespan. If a block with a high number of erase / write cycles is erased, its lifespan will be quickly exhausted. Since the number of blocks is fixed, the lifespan of the UFS will also decrease when at least one block reaches the end of its lifespan. Therefore, selecting the block with the fewest erase / write cycles as the target block for erasing / writing will reduce the consumption of block lifespan, thereby reducing the consumption of UFS lifespan.

[0034] In one possible implementation of the first aspect, the processor is further configured to: after controlling the target module to heat up for a first preset time, if the temperature of the UFS is greater than a second temperature threshold, control the target module to stop operating to stop the heating; wherein the second temperature threshold is greater than the first temperature threshold.

[0035] In this implementation, after the processor controls the target module to heat up for a first preset time, if the temperature of the UFS is greater than a second temperature threshold, the processor controls the target module to stop running to stop the heating, thereby saving power consumption.

[0036] Secondly, a method for temperature control of a Universal Flash Memory (UFS) is provided. This method involves controlling the temperature of a UFS, with a temperature sensor positioned around the UFS. The method includes: acquiring first indication information of the UFS and acquiring the temperature of the UFS using the temperature sensor; the first indication information indicates whether the number of error corrections for the data stored in the UFS exceeds a threshold; if the temperature of the UFS is less than the first temperature threshold and the number of error corrections for the data stored in the UFS exceeds the threshold, controlling the target module of the UFS to operate and increase its temperature; after controlling the target module to increase its temperature for a first preset time, if the temperature of the UFS exceeds a second temperature threshold, controlling the target module to stop operating to stop the temperature increase; wherein the second temperature threshold is greater than the first temperature threshold.

[0037] The aforementioned general-purpose flash memory (UFS) temperature control method controls the target module of the UFS to heat up when the UFS temperature is below a first temperature threshold and the number of error corrections for the stored data in the UFS exceeds a certain threshold. This method can heat the UFS even when the ambient temperature is below its operating temperature, thereby reducing UFS failures and enabling electronic devices to power on or restart successfully. After controlling the target module to heat up for a first preset time, the processor stops the target module from operating when the UFS temperature exceeds a second temperature threshold, thus saving power.

[0038] In one possible implementation of the second aspect, the UFS includes a first central processing unit (CPU) core, the target module includes SRAM, the first CPU core is used to manage the reading and writing of SRAM; controlling the operation of the target module of the UFS to increase the temperature includes: controlling the first CPU core to increase the temperature of the SRAM for reading and writing data.

[0039] In this implementation, when the heating conditions are met, a heating method with lower heat generation efficiency is used first. That is, the first CPU core is controlled to heat up the SRAM by reading and writing data. This heating method does not occupy the processor bandwidth and UFS bandwidth, nor does it consume the flash memory lifespan. At this time, both the first CPU core and the SRAM generate heat, and the heat generation efficiency is low.

[0040] In one possible implementation of the second aspect, the UFS further includes a second central processing unit (CPU) core, which is used to transmit data with the processor; controlling the target module of the UFS to run and heat up also includes: after controlling the first CPU core to heat up the SRAM read and write data for a first preset time, and if the temperature of the UFS is less than or equal to a second temperature threshold, controlling the second CPU core to process data from the processor and heat up the UFS.

[0041] In this implementation, after controlling the first CPU core to heat up the SRAM for a first preset time while reading and writing data, and if the UFS temperature is less than or equal to the second temperature threshold, the second CPU core is then controlled to process data from the processor to heat up. This indicates that controlling the first CPU core to heat up the SRAM is insufficient to raise the temperature above the second temperature threshold. Therefore, it is necessary to heat up again. A heating method with moderate heat generation efficiency can be used, that is, the second CPU core is again controlled to process data from the processor to heat up. This heating method does not consume the lifespan of the flash memory. At this time, the first CPU core, SRAM, and second CPU core all generate heat, with moderate heat generation efficiency.

[0042] In one possible implementation of the second aspect, the target module further includes flash memory, and the first CPU core is also used to manage the reading and writing of flash memory; controlling the target module of UFS to run and heat up also includes: after controlling the second CPU core to process data from the processor and heat up for a first preset time, and if the temperature of UFS is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory for reading and writing data.

[0043] In this implementation, after the second CPU core processes data from the processor and heats up for a first preset time, and the UFS temperature is less than or equal to a second temperature threshold, the first CPU core is then controlled to heat up the flash memory for reading and writing data. This indicates that controlling the second CPU core to process data from the processor to heat up the flash memory cannot achieve a temperature greater than the second temperature threshold. Therefore, further heating is required. A more efficient heating method can be used, meaning the first CPU core is again controlled to heat up the flash memory for reading and writing data. This heating method somewhat reduces the lifespan of the flash memory. At this point, the first CPU core, SRAM, second CPU core, and flash memory all generate heat, resulting in high heating efficiency.

[0044] In one possible implementation of the second aspect, the UFS includes a second central processing unit (CPU) core for data transmission with the processor; the method further includes: obtaining second indication information of the UFS when the temperature of the UFS is less than a first temperature threshold and the number of error corrections of the data stored in the UFS is less than or equal to the error correction count threshold; the second indication information is used to characterize whether the number of reads and writes of the UFS by the processor is greater than the read and write count threshold; obtaining the battery power level when the number of reads and writes of the UFS by the processor is less than or equal to the read and write count threshold; and controlling the target module of the UFS to operate and heat up when the battery power level is greater than the power level threshold and the battery is not in super power saving mode.

[0045] In this implementation, when the UFS temperature is below a first temperature threshold and the number of error corrections performed on the UFS stored data exceeds a certain threshold, further factors such as the processor's read / write operations on the UFS, battery level, and battery mode are considered. If the processor's read / write operations on the UFS are less than or equal to a certain threshold, the battery level is greater than a certain threshold, and the battery is not in ultra-low power mode, the target module of the UFS is controlled to heat up. This allows the UFS to be heated when the ambient temperature is below its operating temperature, thereby reducing UFS failures and enabling electronic devices to power on or restart successfully. Furthermore, it avoids excessive power consumption during the heating process, which could lead to the electronic device shutting down, thus improving the user experience.

[0046] In one possible implementation of the second aspect, the UFS further includes a first central processing unit (CPU) core, the target module includes SRAM, the first CPU core is used to manage the reading and writing of SRAM; controlling the operation of the target module of the UFS to increase the temperature includes: controlling the first CPU core to increase the temperature of the SRAM for reading and writing data.

[0047] In this implementation, when the heating conditions are met, a heating method with lower heat generation efficiency is used first. That is, the first CPU core is controlled to heat up the SRAM by reading and writing data. This heating method does not occupy the processor bandwidth and UFS bandwidth, nor does it consume the flash memory lifespan. At this time, both the first CPU core and the SRAM generate heat, and the heat generation efficiency is low.

[0048] In one possible implementation of the second aspect, controlling the target module of the UFS to run and heat up further includes: after controlling the first CPU core to heat up the SRAM read and write data for a first preset time, and if the temperature of the UFS is less than or equal to a second temperature threshold, controlling the second CPU core to process data from the processor and heat up the UFS.

[0049] In this implementation, after controlling the first CPU core to heat up the SRAM for a first preset time while reading and writing data, and if the UFS temperature is less than or equal to a second temperature threshold, controlling the second CPU core to heat up the data processed by the processor indicates that controlling the first CPU core to heat up the SRAM is insufficient to raise the temperature above the second temperature threshold. Therefore, further heating is required. A heating method with moderate heat dissipation efficiency can be used, that is, controlling the second CPU core to heat up the data processed by the processor. This heating method does not consume the lifespan of the flash memory. At this point, the first CPU core, SRAM, and second CPU core all generate heat, with moderate heat dissipation efficiency.

[0050] In one possible implementation of the second aspect, the target module further includes flash memory, and the first CPU core is also used to manage the reading and writing of flash memory; controlling the target module of UFS to operate and heat up includes: after controlling the second CPU core to process data from the processor to heat up for a first preset time, and when the temperature of UFS is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory for reading and writing data.

[0051] In this implementation, after the second CPU core processes data from the processor and heats up for a first preset time, and the UFS temperature is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory for reading and writing data indicates that controlling the second CPU core to heat up the flash memory for processing data from the processor cannot achieve the goal of raising the temperature above the second temperature threshold. Therefore, further heating is required, and a heating method with higher heat dissipation efficiency can be used. In other words, controlling the first CPU core to heat up the flash memory for reading and writing data will consume some of the flash memory's lifespan. At this point, the first CPU core, SRAM, second CPU core, and flash memory all generate heat, resulting in high heat dissipation efficiency.

[0052] In one possible implementation of the second aspect, the UFS includes a second central processing unit (CPU) core for data transmission with the processor; the method further includes: acquiring second indication information of the UFS when the temperature of the UFS is less than a first temperature threshold and the number of error corrections of the data stored in the UFS is less than or equal to the number of error corrections threshold; the second indication information is used to characterize whether the number of reads and writes of the UFS by the processor is greater than the number of reads and writes threshold; when the number of reads and writes of the UFS by the processor is greater than the number of reads and writes threshold, and the UFS prohibits the second CPU core from processing data from the processor, controlling the target module of the UFS to run for temperature increase.

[0053] In this implementation, when the UFS temperature is below a first temperature threshold and the number of error corrections performed on the UFS stored data exceeds a certain threshold, further factors such as the number of read / write operations performed by the processor on the UFS and the UFS's restriction on the second CPU core from processing data from the processor are considered. If the number of read / write operations performed by the processor on the UFS exceeds the threshold and the UFS restricts the second CPU core from processing data from the processor, the target module of the UFS is controlled to increase its temperature. This allows the UFS to be heated when the ambient temperature is below its operating temperature, thereby reducing UFS failures and enabling electronic devices to boot or restart successfully. While ensuring that the UFS heating does not consume processor processing power, it also improves the user experience.

[0054] In one possible implementation of the second aspect, the UFS further includes a first CPU core, the target module includes SRAM, the first CPU core is used to manage the reading and writing of SRAM; controlling the operation of the target module of the UFS to increase the temperature includes: controlling the first CPU core to increase the temperature of the SRAM for reading and writing data.

[0055] In this implementation, when the heating conditions are met, a heating method with lower heat generation efficiency is first used. That is, the first CPU core is controlled to read and write data to the SRAM to generate heat. This heating method does not consume processor bandwidth or UFS bandwidth, nor does it consume flash memory lifespan. At this time, both the first CPU core and the SRAM generate heat, resulting in lower heat generation efficiency.

[0056] In one possible implementation of the second aspect, the target module further includes flash memory, and the first CPU core is also used to manage the reading and writing of flash memory; controlling the target module of UFS to operate and heat up includes: after controlling the first CPU core to heat up the SRAM reading and writing data for a first preset time, and when the temperature of UFS is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory reading and writing data.

[0057] In this implementation, after controlling the first CPU core to heat up the SRAM for a first preset time during SRAM read / write operations, and if the UFS temperature is less than or equal to a second temperature threshold, controlling the first CPU core to heat up the flash memory during SRAM read / write operations indicates that this method cannot raise the temperature above the second threshold. Therefore, further heating is required. Since the UFS prohibits the second CPU core from processing data from the processor, the method of skipping the second CPU core's data processing during heating must be adopted. A more efficient heating method can be used. In other words, controlling the first CPU core to heat up the flash memory during read / write operations consumes some of the flash memory's lifespan. At this point, the first CPU core, SRAM, and flash memory all generate heat, resulting in high heating efficiency.

[0058] In one possible implementation of the second aspect, the UFS further includes multiple storage blocks, and the method further includes: after controlling the first CPU core to heat up the flash memory for reading and writing data, obtaining a target block from the multiple storage blocks, and controlling the UFS to heat up the target block through erase and write operations.

[0059] In this implementation, the first CPU core needs to find target blocks among multiple storage blocks to erase and write data to the flash memory, which generates heat. Therefore, UFS will scan the areas in the flash memory that are suitable for erasing and writing in order to find the target blocks for erasing and writing.

[0060] In one possible implementation of the second aspect, multiple storage blocks include initial bad blocks, and controlling the UFS to heat up through erase / write operations on the target blocks includes: controlling the UFS to heat up through erase / write operations on the initial bad blocks.

[0061] In this implementation, since the initial bad block refers to the storage block that was already damaged when the UFS was manufactured, erasing or writing the initial bad block will not consume the lifespan of the normal storage block, and therefore will not consume the lifespan of the UFS.

[0062] In one possible implementation of the second aspect, multiple storage blocks include running bad blocks but do not include initial bad blocks, and controlling the UFS to heat up through erase / write operations on the target blocks includes: controlling the UFS to heat up through erase / write operations on the running bad blocks.

[0063] In this implementation, since running bad blocks refer to bad storage blocks generated during normal operation after the UFS leaves the factory, when there are no initial bad blocks, running bad blocks can be found as replacements for the initial bad blocks for erasing and rewriting. Similarly, erasing and rewriting running bad blocks will not consume the lifespan of normal storage blocks, and therefore will not consume the lifespan of the UFS.

[0064] In one possible implementation of the second aspect, the plurality of storage blocks do not include running bad blocks and do not include initialization blocks, and controlling the UFS to heat up the target block through erase and write operations includes: controlling the UFS to heat up the storage block with the fewest erase and write operations among the plurality of storage blocks.

[0065] In this implementation, excluding both initial bad blocks and running bad blocks, the block with the fewest erase / write cycles is designated as the target block. This is because the higher the number of erase / write cycles a block has, the shorter its lifespan. If a block with a high number of erase / write cycles is erased, its lifespan will be quickly exhausted. Since the number of blocks is fixed, the lifespan of the UFS will also decrease when at least one block reaches the end of its lifespan. Therefore, selecting the block with the fewest erase / write cycles as the target block for erasing / writing will reduce the consumption of block lifespan, thereby reducing the consumption of UFS lifespan.

[0066] In one possible implementation of the second aspect, the method further includes: after the target module has been heated for a first preset time, if the temperature of the UFS is greater than a second temperature threshold, controlling the target module to stop operating to stop the heating; wherein the second temperature threshold is greater than the first temperature threshold.

[0067] In this implementation, after the processor controls the target module to heat up for a first preset time, if the temperature of the UFS is greater than a second temperature threshold, the processor controls the target module to stop running to stop the heating, thereby saving power consumption.

[0068] Thirdly, an electronic device is provided, including the UFS temperature control circuit as described in the first aspect and any embodiment thereof.

[0069] Fourthly, an electronic device is provided, including a UFS and one or more processors. The UFS is used to store one or more processor-executable instructions. The UFS stores computer program code, which includes computer instructions. When the computer instructions are executed by the processor, the electronic device performs the UFS temperature control method as described in the second aspect and any embodiment thereof.

[0070] Fifthly, a computer-readable storage medium is provided that, when computer instructions are executed on an electronic device, causes the electronic device to perform the UFS temperature control method as described in the second aspect and any embodiment thereof.

[0071] In a sixth aspect, a computer program product is provided that, when run on an electronic device, causes the electronic device to perform the UFS temperature control method as described in the second aspect and any embodiment thereof.

[0072] The technical effects of the design methods in the third and sixth aspects can be found in the technical effects of the different design methods in the first and second aspects, and will not be repeated here. Attached Figure Description

[0073] Figure 1 This is a schematic diagram of a possible structure of an electronic device provided in an embodiment of this application;

[0074] Figure 2 A schematic diagram illustrating how a UFS (Ultra-Frequency Storage) device in a related technology, provided for the present invention, fails to power on or restart an electronic device due to damage under low-temperature conditions.

[0075] Figure 3 This is a schematic diagram of the structure of a UFS temperature control circuit provided in an embodiment of this application;

[0076] Figure 4 A flowchart illustrating a UFS temperature rise determination method executed by a processor, provided in an embodiment of this application;

[0077] Figure 5 This is a schematic diagram of the structure of a UFS provided in an embodiment of this application;

[0078] Figure 6 This is a flowchart illustrating a processor-executed UFS warm-up method provided in an embodiment of this application. Detailed Implementation

[0079] The technical methods in the embodiments of this application will be described below with reference to the accompanying drawings. In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can represent A or B. "And / or" in this application is merely a description of the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical methods in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the words "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design method described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design methods. Specifically, the use of "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding. The terms "coupling" and "connection" involved in the embodiments of this application should be interpreted broadly; for example, they can refer to a physical direct connection or an indirect connection implemented through electronic devices, such as connections implemented through resistors, inductors, capacitors, or other electronic devices.

[0080] Universal flash storage (UFS) uses serial data transmission technology. It has only two data channels but its speed exceeds that of the embedded multimedia card (eMMC) standard. It operates in full-duplex mode, allowing read and write transfers on the same channel, and read and write can occur simultaneously, thus improving transmission efficiency.

[0081] This application provides an electronic device with a UFS (Unified Field Storage) system. The electronic device can be mobile or fixed. It can be deployed on land (e.g., indoors or outdoors, handheld or vehicle-mounted), on water (e.g., on ships), or in the air (e.g., airplanes, balloons, and satellites). This electronic device can be referred to as user equipment (UE), access terminal, terminal unit, subscriber unit, terminal station, mobile station (MS), mobile station, terminal agent, or terminal device. For example, it can be a mobile phone, tablet computer, laptop computer, smart bracelet, smart screen, smartwatch, virtual reality (VR) device, augmented reality (AR) device, terminal in industrial control, terminal in self-driving, terminal in remote medical care, terminal in smart grid, terminal in transportation safety, terminal in smart city, terminal in smart home, etc. This application does not limit the specific type and structure of the electronic device. The following describes one possible structure of the electronic device.

[0082] Taking mobile phones as an example, the attached document... Figure 1 A possible structure of an electronic device 100 is shown. The electronic device 100 may include a processor 3, an external memory interface 220, an internal memory 221, a universal serial bus (USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, a mobile communication module 250, a wireless communication module 260, antennas 251 and 261, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone jack 270D, a sensor module 280, buttons 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc. Optionally, in some embodiments, it may also include an audio digital signal processor (ADSP) 243.

[0083] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0084] Processor 3 may include one or more processing units, such as: a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, and a neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors. For example, processor 3 may be an application processor (AP). Alternatively, processor 3 may be integrated into a system-on-chip (SoC). Or, processor 3 may be integrated into an integrated circuit (IC) chip. The processor 3 may include an analog front end (AFE) and a micro-controller unit (MCU) in an IC chip.

[0085] The processor 3 may also include a memory for storing computer instructions and data. In some embodiments, the memory in the processor 3 is a cache memory. This memory can store computer instructions or data that the processor 3 has just used or that are used repeatedly. If the processor 3 needs to use the computer instructions or data again, it can retrieve them directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 3, and thus improves the efficiency of the system.

[0086] In some embodiments, the processor 3 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface, etc.

[0087] The ADSP 243 can be coupled to the audio module 270 and the sensor module 280. The ADSP 243 can process audio signals and sensor data. Even when the processor 3 is in sleep mode, the ADSP 243 can remain operational, thereby reducing the power consumption of the electronic device.

[0088] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or a combination of multiple interface connection methods.

[0089] The external storage interface 220 can be used to connect an external memory card, such as a micro SanDisk (Micro SD) card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 3 through the external storage interface 220 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0090] Internal memory 221 can be used to store computer executable program code, which includes computer instructions. Processor 3 executes various functional applications and data processing of electronic device 100 by running the computer instructions stored in internal memory 221. In addition, internal memory 221 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS) 2, etc.

[0091] The memory involved in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0092] Electronic device 100 can implement audio functions such as music playback and recording through audio module 270, speaker 270A, receiver 270B, microphone 270C, headphone jack 270D, and application processor 3.

[0093] Buttons 290 include power buttons, volume buttons, etc. Buttons 290 can be mechanical buttons or touch buttons. Electronic device 100 can receive button inputs and generate key signal inputs related to user settings and function control of electronic device 100. Motor 291 can generate vibration alerts. Motor 291 can be used for incoming call vibration alerts or for touch vibration feedback. Indicator 292 can be an indicator light, used to indicate charging status, battery level changes, or to indicate messages, missed calls, notifications, etc. SIM card interface 295 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 295 to achieve contact and separation with electronic device 100. Electronic device 100 can support one or N SIM card interfaces, where N is a positive integer greater than 1. SIM card interface 295 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. In some embodiments, the electronic device 100 employs an embedded SIM (eSIM) card, which can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

[0094] The electronic device 100 can implement shooting functions through an ISP, a camera 293, a video codec, a GPU, a display screen 294, and an application processor 3. The ISP is used to process data fed back by the camera 293. In some embodiments, the ISP can be set in the camera 293. The camera 293 is used to capture still images or videos. In some embodiments, the electronic device 100 may include one or N cameras 293, where N is a positive integer greater than 1.

[0095] Electronic device 100 can implement display functions through a GPU, a display screen 294, and an application processor 3. The GPU is a microprocessor 3 for image processing, connected to the display screen 294 and the application processor 3. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. The processor 3 may include one or more GPUs, which execute computer instructions to generate or modify display information.

[0096] The power management module 240 is used to receive charging input from a charger. The charger can be a wireless charger, such as a wireless charging dock, or other electronic device 100 with reverse wireless charging capability. The power management module 240 can receive wireless charging input via the wireless charging coil 242 of the electronic device. The charger can also be a wired charger; for example, the power management module 240 can receive charging input from a wired charger via a USB interface 230. The power management module 240 is also referred to as a charging chip.

[0097] The power management module 240 can charge the battery 241 and also supply power to the electronic device 100. The power management module 240 receives input from the battery 241 and supplies power to the processor 3, internal memory 221, external memory interface 220, display screen 294, camera 293, and wireless communication module 260 on the main control board. The power management module 240 can also be used to monitor parameters such as battery 241 capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 240 may also be located within the processor 3.

[0098] The wireless communication function of the electronic device 100 can be realized through antenna 251, antenna 261, mobile communication module 250, wireless communication module 260, modem processor 3, etc.

[0099] Mobile communication module 250 can provide solutions for wireless communication applications, including 2G / 3G / 4G / 5G, applied to electronic device 100. Wireless communication module 260 can provide solutions for wireless communication applications, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies, applied to electronic device 100.

[0100] In related technologies, exemplary examples are shown in the appendix. Figure 2 As shown, in extremely cold conditions where the ambient temperature is below -25 degrees Celsius, when using electronic devices such as mobile phones 100, the UFS 2 storage in electronic devices 100 is also in an environment with an ambient temperature below -25 degrees Celsius. Since the operating temperature of UFS 2 is usually above -25 degrees Celsius, when UFS 2 is in an environment with a temperature below -25 degrees Celsius, the temperature of UFS 2 is lower than its operating temperature, which can lead to problems such as data corruption in UFS 2. For example, UFS 2 may experience bad blocks, freeze, or response timeouts. UFS 2 failures will cause the electronic device to shut down. Since electronic devices 100 need to use the data stored in UFS 2 to power on or restart, these failures will cause UFS 2 to malfunction, making it impossible for electronic devices 100 to use the data stored in UFS 2. Therefore, this will lead to problems such as electronic devices 100 being unable to power on or restart.

[0101] Therefore, this application provides a general-purpose flash memory UFS 2 temperature control circuit. Based on the UFS 2 temperature control circuit provided in this application embodiment, the UFS can be heated when the ambient temperature is lower than its operating temperature, thereby reducing UFS failures and enabling electronic devices to successfully power on or restart.

[0102] The UFS temperature control circuit provided in this application embodiment can be UFS 2 in electronic device 100.

[0103] For example, see attached Figure 3 As shown, the UFS temperature control circuit 1 includes a UFS 2, a processor 3, and a temperature sensor 4.

[0104] In one possible implementation, as shown in the appendix Figure 3 As shown, the UFS temperature control circuit 1 may also include a power management chip 5, a double data rate (DDR) synchronous dynamic random access memory (DDR) 6, and peripheral circuits 7, etc. This application embodiment does not limit the components of the UFS temperature control circuit 1.

[0105] In one possible implementation, as shown in the appendix Figure 3 As shown, there can be multiple temperature sensors 4, such as three. This application embodiment does not limit the number of temperature sensors 4.

[0106] In this embodiment, the temperature sensor 4 is disposed around the UFS 2 to detect the temperature of the UFS 2. In the UFS temperature control circuit 1, the peripheral circuit 7 is a circuit structure other than the UFS 2, processor 3, temperature sensor 4, power management chip 5, double data rate synchronous dynamic random access memory (DDR) 6, etc.

[0107] For example, see attached Figure 4 As shown, in the UFS temperature control circuit 1, the processor 3 is used to perform the following steps S401-S406 for heating:

[0108] Step S401: Processor 3 obtains the first indication information of UFS 2 and obtains the temperature of UFS 2 through temperature sensor 4.

[0109] The first indication information is used to characterize whether the number of error corrections for the data stored in UFS 2 is greater than the error correction count threshold. In this embodiment, the processor 3 can obtain the first indication information by reading the High Error Correction Code (HECC) value inside UFS 2. When the number of error corrections inside UFS 2 is greater than the error correction count threshold, UFS 2 sets HECC to valid, for example, HECC is 1 to indicate validity; when the number of error corrections inside UFS 2 is less than or equal to the error correction count threshold, UFS 2 sets HECC to invalid, for example, HECC is 0 to indicate invalid. The error correction count threshold can be set according to actual needs. For example, it can be obtained by statistically analyzing multiple error correction counts of UFS 2 under low temperature conditions, such as the average or median of multiple error correction counts when multiple UFS 2 instances are affected by low temperature conditions; it can also be set based on empirical values.

[0110] Step S402: Processor 3 determines whether the temperature of UFS 2 is less than the first temperature threshold.

[0111] In one possible implementation, the first temperature threshold can be the operating temperature of UFS 2, or it can be slightly lower or slightly higher than the operating temperature of UFS 2. This application does not limit the value of the first temperature threshold. Generally, when the ambient temperature drops below the operating temperature of UFS 2, the temperature of UFS 2 itself will be higher than the ambient temperature due to heat generated during operation. Considering a safety margin, the first temperature threshold is usually set to the operating temperature of UFS 2.

[0112] Determining whether the temperature of UFS 2 is less than the first temperature threshold is a necessary condition for processor 3 to perform heating. If the temperature of UFS 2 is less than the first temperature threshold, step S403 is executed for further determination; if the temperature of UFS 2 is greater than or equal to the first temperature threshold, the process returns to step S401, obtains the first indication information of UFS 2 again, and obtains the temperature of UFS 2 through temperature sensor 4.

[0113] Step S403: Processor 3 determines whether the number of error corrections for the data stored in UFS 2 is greater than the error correction threshold.

[0114] Since the subsequent temperature-raising method executed by processor 3 is based on the reading and writing of a portion of the devices in UFS 2, such as SRAM and flash memory, it consumes the performance of these devices, thereby consuming the performance of UFS 2. Therefore, after considering both temperature and the number of error correction cycles for UFS 2 stored data, processor 3 executes the temperature-raising method for UFS 2 to ensure the accuracy of the execution.

[0115] If the temperature of UFS 2 is below the first temperature threshold, the performance of UFS 2 is not necessarily affected. However, when the number of error corrections exceeds the error correction count threshold, it indicates that the number of error corrections on the data within UFS 2 has significantly increased, and the low temperature in the environment has begun to negatively impact the performance of UFS 2. Therefore, it is necessary to raise the temperature of UFS 2 in a timely manner to prevent further failures. Thus, in addition to judging the low temperature, it is also necessary to further determine whether the number of error corrections on the stored data in UFS 2 exceeds the error correction count threshold. This ensures that the temperature rise method is only executed when the performance of UFS 2 is negatively affected, reducing the false positive rate in judging the impact of low temperature on UFS 2 performance and improving the accuracy of judging the impact of low temperature on UFS 2 performance. If the number of error corrections on the stored data exceeds the error correction count threshold, step S404 is executed; if the number of error corrections on the stored data is less than or equal to the error correction count threshold, the subsequent step S407 is executed.

[0116] Step S404: Processor 3 controls the target module of UFS 2 to run and heat up.

[0117] If the temperature of UFS 2 is lower than the first temperature threshold and the number of error corrections for the data stored in UFS 2 is greater than the number of error corrections threshold, it indicates that the performance of UFS 2 has been negatively affected. At this time, a heating method needs to be executed, and the processor 3 controls the target module of UFS 2 to run for heating.

[0118] Step S405: After the first preset time, the processor 3 determines whether the temperature of UFS 2 is greater than the second temperature threshold.

[0119] The second temperature threshold is greater than the first temperature threshold. The first temperature threshold is the temperature threshold before the UFS 2 is heated, representing the starting temperature threshold, and is typically close to the UFS 2's operating temperature. The second temperature threshold is the temperature threshold after the UFS 2 is heated, representing the ending temperature threshold, and is greater than the UFS 2's operating temperature. Therefore, the second temperature threshold is greater than the first temperature threshold.

[0120] The second temperature threshold can be set according to actual needs. For example, it can be obtained by statistically analyzing multiple temperature values ​​of UFS 2, such as the minimum operating temperature of multiple UFS 2 devices; or it can be set based on empirical values.

[0121] The first preset time can be set according to actual needs. For example, it can be obtained by statistically analyzing multiple time differences during the heating process of UFS 2 from the start to the stop of heating, such as the average or median of multiple time differences when multiple UFS 2 devices start heating and stop heating; it can also be set based on empirical values, such as 116s.

[0122] Determining whether the temperature of UFS 2 is greater than the second temperature threshold is to determine whether the temperature of UFS 2 has reached the temperature condition for stopping heating. After heating for the first preset time, it is necessary to determine whether the temperature of UFS 2 is greater than the second temperature threshold. If the temperature of UFS 2 is greater than the second temperature threshold, step S406 is executed; if the temperature of UFS 2 is less than or equal to the second temperature threshold, step S404 is executed again to heat UFS 2 again until the temperature of UFS 2 is greater than the second temperature threshold.

[0123] Step S406: Processor 3 controls the target module to stop running to stop the temperature rise.

[0124] This step ensures that the temperature of UFS 2 after heating does not affect its performance, while also saving power consumption.

[0125] Steps S401-S406 described above are for implementing a temperature-raising method when the performance of UFS 2 is affected by low temperatures. The two temperature-raising criteria mentioned above are used to ensure that the temperature-raising method is executed only when the performance of UFS 2 is negatively impacted. This reduces the risk of UFS 2 failures, allows the electronic device 100 to successfully power on or restart, and also saves power consumption.

[0126] The working principle of the UFS temperature control circuit 1 is as follows:

[0127] Processor 3 obtains a first indication of whether the number of error corrections for the stored data in UFS 2 exceeds the error correction count threshold, and acquires the temperature of UFS 2 via temperature sensor 4. This information is used to determine whether to increase the temperature of UFS 2 based on the error correction count and temperature. If the temperature of UFS 2 is below the first temperature threshold and the number of error corrections for the stored data in UFS 2 exceeds the error correction count threshold, the target module of UFS 2 is controlled to increase its temperature. This temperature increase is performed when HECC is enabled and the temperature of UFS 2 is below the first temperature threshold. After the target module has been heated for a first preset time, if the temperature of UFS 2 exceeds a second temperature threshold, the target module is stopped to halt the heating process.

[0128] The UFS temperature control circuit 1 provided in this application embodiment can heat up the UFS 2 when HECC is enabled and the temperature is below a first temperature threshold. Therefore, it improves the problem of data corruption in the UFS 2 when the ambient temperature is below its operating temperature, which can lead to the shutdown of the electronic device 100 and prevent the device from powering on or restarting. This reduces UFS 2 malfunctions and allows the electronic device 100 to power on or restart successfully. It can also stop heating after a period of time when the temperature exceeds a second temperature threshold, thereby saving power consumption.

[0129] In this embodiment, meeting the temperature rise condition also requires consideration of factors such as the number of read / write operations of the processor 33 on the UFS 2, the battery charge, the battery mode, and whether the second CPU core processes data from the processor 3. The following embodiments of this application use these factors as examples to specifically describe the UFS temperature control circuit 1 of this application.

[0130] For example, see attached Figure 4 As shown, in the UFS temperature control circuit 1, the processor 3 is also used to execute the following steps S407-S410 to determine the temperature rise:

[0131] Step S407: Processor 3 determines whether the number of read and write operations performed by processor 3 on UFS 2 is greater than the read and write operation threshold.

[0132] This step is executed only in step S403 if the number of error corrections for the stored data is less than or equal to the error correction threshold. The read / write count threshold can be set according to actual needs. For example, it can be obtained by counting multiple read / write counts when the processor 3 reads and writes to UFS 2, such as the minimum value among multiple read / write counts when the processor 3 reads and writes to UFS 2 and occupies UFS 2; it can also be set based on empirical values.

[0133] Since the heating method in this embodiment consumes some device performance in UFS 2, such as SRAM and flash memory, to ensure user experience and prevent the devices in the heating method from occupying the bandwidth of processor 3 and UFS 2 during heating, considering the above factors, the heating method that consumes UFS 2 performance is not performed when processor 3 is occupying UFS 2. Determining whether the number of read / write operations of processor 3 to UFS 2 is greater than the read / write operation threshold is to determine whether processor 3 is occupying UFS 2. When the number of read / write operations of processor 3 to UFS 2 is greater than the read / write operation threshold, it indicates that processor 3 is occupying UFS 2. At this time, the heating method related to processor 3 in UFS 2 is not performed, and other heating methods can be performed. Therefore, proceed to the next step of judgment, and execute step S410. When the number of read / write operations of processor 3 to UFS 2 is less than or equal to the read / write operation threshold, it indicates that processor 3 is not occupying UFS 2, and UFS 2 can be heated. Proceed to the next step of judgment, and execute step S408.

[0134] Step S408: Processor 3 determines whether the battery 241 has a charge level greater than the charge threshold.

[0135] The power threshold can be set according to actual needs. For example, it can be obtained by counting multiple power values ​​of battery 241, such as counting the maximum value of multiple power values ​​of multiple batteries 241 when the UFS 2 temperature rises; or it can be set according to empirical values, such as 10%.

[0136] Because the heating method in this embodiment may rapidly deplete the battery 241's power, when the UFS 2 is in normal operation (e.g., without HECC) or the processor 3 is performing extensive data processing on the UFS 2, executing the UFS 2 heating method when the battery 241 is low will cause the battery 241 to drain rapidly. It may even cause the electronic device 100 to shut down prematurely due to power shortage, thus prematurely ending the ongoing UFS 2 heating method without raising the UFS 2's temperature. This not only affects the performance of the UFS 2 but also the user experience. Therefore, the UFS 2 heating method is not executed when the battery 241's power is too low.

[0137] When the charge level of battery 241 is greater than the charge threshold, it indicates that the charge level of battery 241 can support the temperature rise of UFS 2. Therefore, proceed to the next step and execute step S409. When the charge level of battery 241 is less than or equal to the charge threshold, it indicates that the charge level of battery 241 is insufficient to support the temperature rise of UFS 2. Therefore, return to step S401, obtain the first indication information of UFS 2 again, and obtain the temperature of UFS 2 through temperature sensor 4.

[0138] Step S409: Processor 3 determines whether battery 241 is in super power saving mode.

[0139] Since battery 241 is in ultra-low power mode, it indicates that the user does not want to consume battery 241's power. Executing the UFS 2 heating method at this time would cause battery 241 to drain rapidly, contradicting the user's intention to minimize power consumption in ultra-low power mode and negatively impacting user experience. Therefore, when battery 241 is in ultra-low power mode, the UFS 2 heating method is not executed, improving the user experience.

[0140] When battery 241 is in ultra-low power mode, the UFS 2 heating method is not executed, and the process returns to step S401 to obtain the first indication information of UFS 2 again and acquire the temperature of UFS 2 through temperature sensor 4. When battery 241 is not in ultra-low power mode, the UFS 2 heating method is executed, and step S404 is executed.

[0141] Step S410: UFS 2 disables the second CPU core from processing data from processor 3.

[0142] UFS 2 includes a second CPU core used for data transfer with processor 3. This step, S407, is executed only if the number of read / write operations performed by processor 3 on UFS 2 exceeds a threshold. If the number of read / write operations performed by processor 3 on UFS 2 exceeds the threshold, it indicates that processor 3 is consuming UFS 2 bandwidth. If the second CPU core is still controlled to process data from processor 3 to increase its temperature, this will consume bandwidth between processor 3 and UFS 2. Therefore, UFS 2 must prevent the second CPU core from processing data from processor 3 and avoid the temperature-increasing methods related to bandwidth consumption between processor 3 and UFS 2; other temperature-increasing methods can be used. Therefore, when operations related to processor 3 are prohibited in UFS 2—that is, when UFS 2 prohibits the second CPU core from processing data from processor 3—other temperature-increasing methods for UFS 2 are executed, and step S404 is executed, which can improve the user experience.

[0143] The steps S407-S410 described above are the UFS 2 heating method executed by the processor 3 after considering factors such as the number of read and write operations of the processor 3 to the UFS 2, the battery power, the battery mode, and whether the second CPU core processes the data from the processor 3.

[0144] Steps S401-S410 described above are the UFS 2 heating method executed by processor 3 after considering all factors such as temperature, the number of error correction cycles for UFS stored data, the number of read / write cycles of processor 3 to UFS 2, battery power, battery mode, and whether the second CPU core processes data from processor 3. Steps S401-S410 that meet the heating conditions include the following three cases:

[0145] 1) When the temperature of UFS 2 is less than the first temperature threshold and the number of error corrections for the data stored in UFS 2 is greater than the number of error corrections threshold, the processor 3 controls the target module of UFS 2 to run and increase the temperature.

[0146] 2) When the temperature of UFS 2 is less than the first temperature threshold and the number of error corrections of the data stored in UFS 2 is less than or equal to the error correction number threshold, the second indication information of UFS 2 is obtained; the second indication information is used to characterize whether the number of reads and writes of UFS 2 by the processor 3 is greater than the read and write number threshold; when the number of reads and writes of UFS 2 by the processor 3 is less than or equal to the read and write number threshold, the battery power is obtained; when the battery power is greater than the power threshold and the battery is not in the super power saving mode, the processor 3 controls the target module of UFS 2 to run and heat up.

[0147] 3) When the temperature of UFS 2 is less than the first temperature threshold and the number of error corrections of the data stored in UFS 2 is less than or equal to the error correction number threshold, the second indication information of UFS 2 is obtained; the second indication information is used to characterize whether the number of reads and writes of UFS 2 by processor 3 is greater than the read and write number threshold; when the number of reads and writes of UFS 2 by processor 3 is greater than the read and write number threshold, and UFS 2 prohibits the second CPU core from processing the data from processor 3, processor 3 controls the target module of UFS 2 to run and increase the temperature.

[0148] In this embodiment, the above-mentioned temperature rise judgment conditions are used to implement the temperature rise method while ensuring that the performance of UFS 2 is not negatively affected, and also taking into account the user experience. In this way, UFS 2 failures can be reduced, enabling the electronic device 100 to successfully power on or restart, while also improving the user experience.

[0149] In the following embodiments of this application, taking UFS 2 as an example that meets the above heating conditions, the UFS temperature control circuit 1 of this application will be specifically described.

[0150] Since the structure of UFS 2 dictates the heating method, it is essential to understand its structure before heating it. In the embodiments of this application, exemplarily, as shown in the attached diagram... Figure 5As shown, UFS 2 includes a first CPU core, a second CPU core, static random access memory (SRAM), flash memory, and a bus.

[0151] The first CPU core is used to manage the read and write operations of SRAM and flash memory. For example, the first CPU core reads and writes data to SRAM; the first CPU core reads and writes data to flash memory.

[0152] The second CPU core is used for data transfer with processor 3. Therefore, the second CPU core acts as the link between UFS 2 and processor 3 for data exchange. After receiving data from processor 3 onto the bus, the second CPU core processes the data, such as decoding the data, processing high-priority data commands, and correcting errors in the transmitted data signals. After processing the data from processor 3, the second CPU core sends the processed data to SRAM via the bus. Data transfer between the second CPU core and processor 3 is conducted through the signal transmission layer. The signal transmission layer includes an upper physical signal layer and a lower physical signal layer. The upper physical signal layer has a lower transmission speed, while the lower physical signal layer has a higher transmission speed. Data transfer between the second CPU core and processor 3 occurs at the lower physical signal layer, thus enabling high-speed data interaction between them.

[0153] SRAM is used to temporarily store the data received from the second CPU core. As an intermediate device, SRAM also provides access to the first CPU core, offering faster data access speeds.

[0154] Flash memory is a non-volatile memory that retains data after power loss until it is written with new data or erased. In one possible implementation, the flash memory can be NOR flash or NAND flash; this application embodiment does not limit the type of flash memory. After the first CPU core accesses data in SRAM via the bus, it sends the data to the flash memory via the bus and reads and writes data to the flash memory based on the data. The flash memory includes multiple storage blocks, such as storage block 0, storage block 1... storage block N, where N is a positive integer, N>1. A storage block is the smallest unit of storage information in the flash memory that can be erased and written. In one possible implementation, a storage block may include initial bad blocks and also running bad blocks; this application embodiment does not limit the composition of the storage blocks. Initial bad blocks refer to storage blocks that are already damaged when the UFS 2 is manufactured, while running bad blocks refer to bad storage blocks generated during normal operation after the UFS 2 is manufactured. The number of erase / write cycles of a storage block reflects its lifespan, and the number of erase / write cycles for each storage block is limited.

[0155] Furthermore, the functions of each device in the UFS 2 in this embodiment can be implemented in the UFS 2 software. The UFS 2 software system can adopt a layered architecture. The layered architecture divides the UFS 2 software into several layers, each with a clear role and division of labor. The layers communicate with each other via a bus.

[0156] As an example, the software architecture is shown in the appendix. Figure 5 As shown, it is divided into two layers: the host controller layer (HCL) and the flash controller layer (HCL).

[0157] The host control layer is the layer where data interaction occurs between UFS 2 and processor 3. It is primarily responsible for managing communication, data transmission, scheduling, and error correction between processor 3 and UFS 2. For example, it decodes data transmitted by processor 3, processes high-priority data commands, and corrects errors in transmitted data signals. Within the host control layer, the second CPU core processes the data from processor 3.

[0158] The flash memory control layer is responsible for managing flash memory read and write operations, including programming, erasing, and garbage collection of flash memory data. Within the flash memory control layer, the first CPU core handles flash memory read and write data.

[0159] Based on the structure of UFS 2 described above, in the embodiments of this application, exemplarily, as shown in the appendix... Figure 5 As shown, in the UFS temperature control circuit 1, the processor 3 uses three methods to heat up the UFS 2: A) putting the UFS 2 in SRAM idling mode; B) putting the UFS 2 in HCL full-speed mode; C) putting the UFS 2 in FCL full-speed mode. Here, SRAM idling mode refers to the UFS 2 being in a mode where the first CPU core reads and writes data to the SRAM; HCL full-speed mode refers to the UFS 2 being in a mode where the second CPU core processes data from the processor 3; and FCL full-speed mode refers to the UFS 2 being in a mode where the first CPU core reads and writes data to the flash memory.

[0160] A. Heating method: In SRAM idling mode, processor 3 controls the first CPU core to read and write data to SRAM. In other words, processor 3 controls SRAM to idle to generate heat. This mode does not occupy the bandwidth between processor 3 and UFS 2, and does not consume the lifespan of flash memory. With this heating method, both the first CPU core and SRAM generate heat, resulting in low heating efficiency.

[0161] B. Heating Method: In HCL full-speed mode, at the HCL layer, processor 3 controls the second CPU core to process data from processor 3. That is, at the HCL layer, processor 3 controls the second CPU core to process the data transmitted from processor 3 to UFS 2 through the I / O data port to generate heat. This mode only processes data from processor 3 at the HCL layer to generate heat, and does not perform subsequent storage, that is, it does not temporarily store in SRAM or flash memory. Therefore, it does not consume the lifespan of flash memory. This heating method only generates heat from the second CPU core, and the heating efficiency is moderate.

[0162] C. Heating method: In FCL full-speed mode, at the FCL layer, processor 3 controls the first CPU core to read and write data to the flash memory. In other words, at the FCL layer, processor 3 controls the first CPU core to read and write data to the flash memory to generate heat. This mode controls the first CPU core to read and write data to the flash memory at the FCL layer to generate heat, which consumes some of the lifespan of the flash memory. In this heating method, both the first CPU core and the flash memory generate heat, and the heating efficiency is relatively high.

[0163] The following embodiments of this application use three heating methods (A, B, and C) as examples to specifically describe the UFS temperature control circuit 1 of this application.

[0164] After processor 3 controls the UFS 2 to heat up, it is also necessary to determine when to stop the heating. For example, see attached... Figure 6 As shown, in the UFS temperature control circuit 1, the processor 3 is used to execute the following steps S601-S616 to determine whether to stop heating:

[0165] Step S601: Processor 3 controls UFS 2 to execute heating method A.

[0166] This step is executed when it is determined that the temperature rise condition is met, i.e., the UFS 2 needs to be heated. First, processor 3 controls UFS 2 to execute the low-efficiency heating method A, which involves controlling the first CPU core to read and write data to the SRAM and controlling the SRAM to idle to achieve heating. Since the performance of UFS 2 has already been affected by the low temperature, a small heating of UFS 2 can avoid the impact of the low temperature on its performance. A large heating of UFS 2 would waste power and also affect its performance. Therefore, UFS 2 is first controlled to undergo a small heating, i.e., heating method A is executed. Since conditions 1), 2), and 3) all meet the temperature rise condition, heating method A can be executed in all of them. Specifically, in conditions 1), 2), and 3), the first CPU core is controlled to read and write data to the SRAM to heat it.

[0167] Step S602: Processor 3 controls the UFS 2 to heat up for the first preset time.

[0168] After processor 3 controls UFS 2 to execute heating method A, the first preset time is maintained to ensure the heating duration. When processor 3 controls UFS 2 to heat up, it must consider both the effectiveness of the heating (ensuring UFS 2's performance is unaffected by temperature and reducing the risk of low temperatures) and the duration of the heating (that excessive heating time will negatively impact UFS 2's performance and user experience). Maintaining the heating for the first preset time effectively solves these problems.

[0169] Step S603: Processor 3 determines whether the temperature of UFS 2 is greater than the second temperature threshold.

[0170] During the initial preset heating period, processor 3 determines whether the temperature of UFS 2 exceeds a second temperature threshold to determine the stopping temperature for heating. Processor 3 cannot continuously control the heating of UFS 2, as this would affect its performance and user experience. Therefore, when the temperature of UFS 2 exceeds the second temperature threshold, step S604 is executed to stop heating; when the temperature of UFS 2 is less than or equal to the second temperature threshold, step S605 is executed to control UFS 2 to continue heating.

[0171] Step S604: Processor 3 determines that UFS 2 has stopped heating.

[0172] When the temperature of UFS 2 is greater than the second temperature threshold, it indicates that the performance of UFS 2 is no longer affected by temperature. Therefore, heating can be stopped, thereby reducing power consumption. In steps S401-S410 as described above, heating steps S601-S604 are executed for both cases 1) and 2) that meet the heating conditions.

[0173] Step S605: Processor 3 determines whether UFS 2 has HCL full-speed mode disabled.

[0174] According to steps S401-S410 described above, in case 3) where the heating condition is met, it is necessary to consider whether UFS 2 is in HCL full-speed mode disabled. Because case 3) occurs when processor 3 is already using UFS 2, if UFS 2 is still in HCL full-speed mode for heating, the heating will consume processor 3's processing power. Therefore, case 3) requires UFS 2 to disable HCL full-speed mode, i.e., not using heating method B to heat UFS 2; that is, skipping heating method B. If UFS 2 disables HCL full-speed mode, it indicates that UFS 2 is in case 3) where the heating condition is met. Heating method B is skipped, step S606 is not executed, and step S609 is executed. If UFS 2 does not disable HCL full-speed mode, it indicates that UFS 2 is in cases 1) and 2) where the heating condition is met. Heating method B is still executed, and step S606 is executed.

[0175] Step S606: Processor 3 controls UFS 2 to also execute the B heating method.

[0176] This step, performed when UFS 2 does not disable HCL full-speed mode, indicates that UFS 2 is in conditions 1) and 2) that meet the temperature rise conditions. Processor 3 controls UFS 2 to also execute temperature rise method B, whereby processor 3 controls the second CPU core to process data from processor 3 to achieve temperature rise. Specifically, in conditions 1) and 2), after controlling the first CPU core to perform SRAM read / write data temperature rise for a first preset time, and if the UFS temperature is less than or equal to a second temperature threshold, the second CPU core is also controlled to process data from processor 3 to achieve temperature rise.

[0177] Step S607: Processor 3 controls the UFS 2 to heat up for the first preset time.

[0178] Similarly, after processor 3 controls UFS 2 to execute the B heating method, it continues for a first preset time to ensure the heating duration. This ensures that the performance of UFS 2 is not affected by temperature, reduces the risk of low temperature in UFS 2, and avoids excessive heating time from affecting the performance of UFS 2 and impacting the user experience.

[0179] Step S608: Processor 3 determines whether the temperature of UFS 2 is greater than the second temperature threshold.

[0180] Similarly, during the B heating method's heating duration of the first preset time, processor 3 determines whether the temperature of UFS 2 is greater than the second temperature threshold in order to determine the stopping temperature for heating. Processor 3 cannot control the heating of UFS 2 indefinitely, as this would affect the performance of UFS 2 and the user experience. Therefore, when the temperature of UFS 2 is greater than the second temperature threshold, step S604 is executed to stop heating; when the temperature of UFS 2 is less than or equal to the second temperature threshold, step S609 is executed to control UFS 2 to continue heating.

[0181] Step S609: Processor 3 controls UFS 2 to also execute the C heating method.

[0182] This step is performed both with and without HCL full-speed mode disabled in UFS 2.

[0183] When UFS 2 does not disable HCL full-speed mode, i.e., when UFS 2 is in conditions 1) and 2) that meet the heating conditions, processor 3 controls UFS 2 to execute heating method A. After heating method A for a first preset time, if the temperature of UFS 2 is less than or equal to the second temperature threshold, processor 3 controls UFS 2 to also execute heating method B. After heating method B for a first preset time, if the temperature of UFS 2 is less than or equal to the second temperature threshold, processor 3 controls UFS 2 to also execute heating method C of step S609. Specifically, in conditions 1) and 2), after controlling the first CPU core to heat up SRAM read / write data for a first preset time, and if the temperature of UFS is less than or equal to the second temperature threshold, processor 3 also controls the second CPU core to process data from processor 3 to heat up the UFS. After controlling the second CPU core to process data from processor 3 to heat up the UFS for a first preset time, and if the temperature of UFS is less than or equal to the second temperature threshold, processor 3 also controls the first CPU core to heat up flash memory read / write data.

[0184] When UFS 2 disables HCL full-speed mode, i.e., when UFS 2 is in the third case that meets the heating conditions, processor 3 controls UFS 2 to execute heating method A. After heating for a first preset time using heating method A, if the temperature of UFS 2 is less than or equal to the second temperature threshold, heating method B is skipped. Processor 3 also controls UFS 2 to execute heating method C in step S609. Specifically, in the third case, after controlling the first CPU core to heat up the SRAM read / write data for a first preset time, and if the temperature of UFS is less than or equal to the second temperature threshold, the first CPU core is also controlled to heat up the flash memory read / write data.

[0185] Step S610: Processor 3 controls UFS 2 to search for the target block among multiple storage blocks.

[0186] In this context, the target block refers to the memory block among multiple memory blocks that is subject to erase / write operations. Because the processor 3 controls the UFS 2 to perform the C-heating method, the processor 3 controls the first CPU core to read and write data to the flash memory. Since the flash memory comprises multiple memory blocks, the first CPU core needs to locate the target block among these blocks for erase / write operations, thus generating heat. Therefore, UFS 2 scans the flash memory for suitable areas to erase / write to find the target block for this purpose.

[0187] Step S611: Processor 3 determines whether the memory block includes an initial bad block.

[0188] Since the initial bad block refers to a storage block that was already damaged at the time of manufacture of UFS 2, erasing or writing to the initial bad block will not consume the lifespan of the normal storage block, and therefore will not consume the lifespan of UFS 2. If the storage block includes the initial bad block, then the initial bad block is the target block, and step S614 is executed. The processor 3 controls the UFS 2 to heat up through the erase / write operation on the target block; that is, the processor 3 controls the UFS 2 to heat up through the erase / write operation on the initial bad block. If the storage block does not include the initial bad block, step S612 is executed for the next step of judgment.

[0189] Step S612: Processor 3 determines whether the memory block includes a bad block.

[0190] Since running bad blocks refer to bad storage blocks generated during normal operation after the UFS 2 leaves the factory, when there are no initial bad blocks, running bad blocks can be found as replacements for the initial bad blocks for erasing and rewriting. Similarly, erasing and rewriting running bad blocks will not consume the lifespan of normal storage blocks, and therefore will not consume the lifespan of the UFS 2. When the storage block includes running bad blocks, the running bad blocks are the target blocks, and step S614 is executed. The processor 3 controls the UFS 2 to heat up through the erasing and rewriting operation of the target block. That is, the processor 3 controls the UFS 2 to heat up through the erasing and rewriting operation of the running bad blocks. When the storage block does not include either the initial bad blocks or running bad blocks, the next step S613 is executed.

[0191] Step S613: Processor 3 designates the memory block with the fewest erase / write cycles as the target block.

[0192] If the storage block does not include initial bad blocks or running bad blocks, the storage block with the fewest erase / write cycles is designated as the target block. This is because the higher the erase / write cycle of a storage block, the shorter its lifespan. If a storage block with a high number of erase / write cycles is erased, its lifespan will be quickly exhausted. Since the number of storage blocks is fixed, the lifespan of UFS 2 will also decrease when at least one storage block reaches the end of its lifespan. Therefore, selecting the storage block with the fewest erase / write cycles as the target block for erasing / writing will reduce the consumption of storage block lifespan, thereby reducing the consumption of UFS 2 lifespan. Next, proceed to the next step, S614.

[0193] Step S614: Processor 3 controls UFS2 to heat up by erasing and writing the target block.

[0194] If the storage block includes an initial bad block, the initial bad block is the target block, and processor 3 controls UFS2 to heat up by performing erase and write operations on the initial bad block. If the storage block does not include an initial bad block but includes a running bad block, the running bad block is the target block, and processor 3 controls UFS2 to heat up by performing erase and write operations on the running bad block. If the storage block does not include either an initial bad block or a running bad block, the storage block with the fewest erase and write operations is designated as the target block, and processor 3 controls UFS2 to heat up by performing erase and write operations on the storage block with the fewest erase and write operations. Next, step S615 is executed.

[0195] Step S615: Processor 3 controls the UFS 2 to heat up for the first preset time.

[0196] Similarly, after the processor 3 controls the UFS 2 to heat up through the erase and write operations on the target block, it continues for a first preset time to ensure the heating duration. This ensures that the performance of UFS 2 is not affected by temperature, reduces the risk of low temperature in UFS 2, and avoids excessive heating time from affecting the performance of UFS 2 and the user experience.

[0197] Step S616: Processor 3 determines whether the temperature of UFS 2 is greater than the second temperature threshold.

[0198] Similarly, when processor 3 controls UFS 2 to heat up through erase and write operations on the target block for a first preset time, processor 3 determines whether the temperature of UFS 2 exceeds a second temperature threshold in order to determine the temperature at which to stop the heating. Processor 3 cannot control the heating of UFS 2 indefinitely, as this would affect the performance of UFS 2 and the user experience. Therefore, when the temperature of UFS 2 exceeds the second temperature threshold, step S604 is executed to stop the heating.

[0199] In one possible implementation, when the temperature of UFS 2 is less than or equal to the second temperature threshold, step S615 can be executed to control UFS 2 to continue heating for a first preset time until the temperature of UFS 2 is greater than the second temperature threshold. Alternatively, step S610 can be executed to control UFS 2 to continue searching for the target block among multiple storage blocks, thereby performing an erase / write operation on the target block to heat up until the temperature of UFS 2 is greater than the second temperature threshold. The embodiments of this application do not limit the method of continuing to heat up in the C heating method.

[0200] This application also provides a UFS temperature control method, which is the same as the temperature rise judgment method and temperature rise method executed by the processor 3 in the UFS temperature control circuit, and will not be described again here.

[0201] This application also provides an electronic device that may include the UFS temperature control circuit described above.

[0202] The UFS temperature control circuit, temperature control method, and electronic device provided in this application embodiment can raise the temperature of the UFS when the ambient temperature of the UFS is lower than its operating temperature, thereby reducing UFS failures and enabling the electronic device to be successfully powered on or restarted.

[0203] It is understood that, in order to achieve the above functions, the electronic device includes hardware and / or software modules that perform the respective functions. Based on the algorithm steps of the examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application. This embodiment can divide the electronic device into functional modules according to the above method examples. For example, each function can be divided into separate functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0204] This application also provides an electronic device that may include one or more processors and a memory.

[0205] The memory is coupled to the processor, and is used to store instructions that can be executed by one or more of the processors. For example, the memory and the processor can be coupled together via a bus.

[0206] The memory stores computer program code. This computer program code includes computer instructions, which, when executed by the processor, cause the electronic device to perform the UFS temperature control method described in this application.

[0207] The processor can be a processor or controller, such as a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with this disclosure. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0208] The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. These buses can be categorized as address buses, data buses, control buses, etc.

[0209] This application also provides a computer-readable storage medium storing computer program code. When the processor executes the computer program code, the electronic device executes the relevant method steps in the above method embodiments.

[0210] This application also provides a computer program product that, when run on a computer, causes the computer to execute the relevant method steps described in the above method embodiments.

[0211] The electronic devices, computer storage media, or computer program products provided in this application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0212] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0213] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0214] The units described above as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The functions of the integrated unit can be implemented in hardware or as software functional units.

[0215] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the contributing parts, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0216] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A temperature control circuit for a universal flash memory (UFS), characterized in that, The UFS temperature control circuit includes a processor, UFS, and a temperature sensor; The processor acquires first indication information of the UFS and obtains the temperature of the UFS through the temperature sensor; the first indication information is used to characterize whether the number of error corrections for the data stored in the UFS is greater than the error correction number threshold. The processor is used to control the target module of the UFS to run and increase the temperature when the temperature of the UFS is less than a first temperature threshold and the number of error corrections of the UFS stored data is greater than the number of error corrections threshold.

2. The UFS temperature control circuit according to claim 1, characterized in that, The UFS includes a first central processing unit (CPU) core, and the target module includes SRAM. The first CPU core is used to manage the read and write operations of the SRAM. Controlling the operation of the target module of the UFS to increase its temperature includes: The first CPU core is controlled to heat up the SRAM when reading and writing data.

3. The UFS temperature control circuit according to claim 2, characterized in that, The UFS also includes a second central processing unit (CPU) core, which is used for data transmission with the processor; the method of controlling the target module of the UFS to operate and heat up also includes: After controlling the first CPU core to heat up the SRAM for a first preset time while reading and writing data, and if the temperature of the UFS is less than or equal to a second temperature threshold, the second CPU core is also controlled to process the data from the processor to heat up.

4. The UFS temperature control circuit according to claim 3, characterized in that, The target module further includes flash memory, and the first CPU core is also used to manage the reading and writing of the flash memory; the control of the UFS target module to operate and heat up also includes: After controlling the second CPU core to process the data of the UFS and increase the temperature for a first preset time, and if the temperature of the UFS is less than or equal to the second temperature threshold, the first CPU core is also controlled to increase the temperature of the flash memory for reading and writing data.

5. The UFS temperature control circuit according to claim 1, characterized in that, The UFS includes a second central processing unit (CPU) core, which is used for data transmission with the processor; the processor is also used for: When the temperature of the UFS is less than a first temperature threshold and the number of error corrections for the data stored in the UFS is less than or equal to the number of error corrections threshold, the second indication information of the UFS is obtained; the second indication information is used to characterize whether the number of reads and writes to the UFS by the processor is greater than the number of reads and writes threshold. If the number of read / write operations performed by the processor on the UFS is less than or equal to the read / write operation threshold, the battery power level is obtained; if the battery power level is greater than the power threshold and the battery is not in super power saving mode, the target module of the UFS is controlled to run and heat up.

6. The UFS temperature control circuit according to claim 5, characterized in that, The UFS also includes a first central processing unit (CPU) core, and the target module includes SRAM. The first CPU core is used to manage the read and write operations of the SRAM. Controlling the operation of the target module of the UFS to increase its temperature includes: The first CPU core is controlled to heat up the SRAM when reading and writing data.

7. The UFS temperature control circuit according to claim 6, characterized in that, The method of controlling the target module of the UFS to operate and heat up also includes: After controlling the first CPU core to heat up the SRAM for a first preset time while reading and writing data, and if the temperature of the UFS is less than or equal to a second temperature threshold, the second CPU core is also controlled to process the data from the processor to heat up.

8. The UFS temperature control circuit according to claim 7, characterized in that, The target module also includes flash memory, and the first CPU core is further used to manage the reading and writing of the flash memory; controlling the operation of the UFS target module to increase its temperature includes: After controlling the second CPU core to process the data of the UFS and increase the temperature for a first preset time, and if the temperature of the UFS is less than or equal to the second temperature threshold, the first CPU core is also controlled to increase the temperature of the flash memory for reading and writing data.

9. The UFS temperature control circuit according to claim 1, characterized in that, The UFS includes a second central processing unit (CPU) core, which is used for data transmission with the processor; the processor is also used for: When the temperature of the UFS is less than a first temperature threshold and the number of error corrections for the data stored in the UFS is less than or equal to the number of error corrections threshold, the second indication information of the UFS is obtained; the second indication information is used to characterize whether the number of reads and writes to the UFS by the processor is greater than the number of reads and writes threshold. When the number of read / write operations performed by the processor on the UFS exceeds a threshold, and the UFS prohibits the second CPU core from processing data from the processor, the target module of the UFS is controlled to run and its temperature is increased.

10. The UFS temperature control circuit according to claim 9, characterized in that, The UFS also includes a first central processing unit (CPU) core, and the target module includes SRAM. The first CPU core is used to manage the read and write operations of the SRAM. Controlling the operation of the target module of the UFS to increase its temperature includes: The first CPU core is controlled to heat up the SRAM when reading and writing data.

11. The UFS temperature control circuit according to claim 10, characterized in that, The target module also includes flash memory, and the first CPU core is further used to manage the reading and writing of the flash memory; controlling the operation of the UFS target module to increase its temperature includes: After controlling the first CPU core to heat up the SRAM read / write data for a first preset time, and if the temperature of the UFS is less than or equal to a second temperature threshold, the first CPU core is also controlled to heat up the flash memory read / write data.

12. The UFS temperature control circuit according to claim 4, 8, or 11, characterized in that, The UFS also includes multiple storage blocks, and the processor is further configured to: After the first CPU core is controlled to heat up the flash memory for reading and writing data, a target block is obtained from the plurality of storage blocks, and the UFS is controlled to heat up the target block through erase and write operations.

13. The UFS temperature control circuit according to claim 12, characterized in that, The plurality of storage blocks include initial bad blocks, and the control of the UFS to heat up the target blocks through erase and write operations includes: The UFS is controlled to heat up by erasing and writing the initial bad blocks.

14. The UFS temperature control circuit according to claim 13, characterized in that, The plurality of storage blocks include running bad blocks but exclude the initial bad blocks, and controlling the UFS to heat up through the erase and write operations of the target blocks includes: The UFS is controlled to heat up by erasing and writing the bad blocks.

15. The UFS temperature control circuit according to claim 14, characterized in that, The plurality of storage blocks do not include the bad blocks and do not include the initialization blocks. Controlling the UFS to heat up the target blocks through erase / write operations includes: The UFS is controlled to heat up the storage block with the fewest erase / write operations among the plurality of storage blocks.

16. The UFS temperature control circuit according to any one of claims 1-15, characterized in that, The processor is also used for: After the target module has been heated for a first preset time, if the temperature of the UFS is greater than a second temperature threshold, the target module is stopped to stop heating; wherein the second temperature threshold is greater than the first temperature threshold.

17. A method for temperature control of a universal flash memory (UFS), characterized in that, For temperature control of general-purpose flash memory (UFS), wherein a temperature sensor is disposed around the UFS, the method includes: The first indication information of the UFS is obtained, and the temperature of the UFS is obtained through the temperature sensor; the first indication information is used to characterize whether the number of error corrections for the data stored in the UFS is greater than the error correction number threshold. If the temperature of the UFS is lower than a first temperature threshold and the number of error corrections for the UFS stored data is greater than the number of error corrections threshold, the target module of the UFS is controlled to run and increase its temperature.

18. The UFS temperature control method according to claim 17, characterized in that, The UFS includes a first central processing unit (CPU) core, and the target module includes SRAM. The first CPU core is used to manage the read and write operations of the SRAM. Controlling the operation of the target module of the UFS to increase its temperature includes: The first CPU core is controlled to heat up the SRAM when reading and writing data.

19. The UFS temperature control method according to claim 18, characterized in that, The UFS also includes a second central processing unit (CPU) core, which is used for data transmission with the processor; the method of controlling the target module of the UFS to operate and heat up also includes: After controlling the first CPU core to heat up the SRAM for a first preset time while reading and writing data, and if the temperature of the UFS is less than or equal to a second temperature threshold, the second CPU core is also controlled to process the data from the processor to heat up.

20. The UFS temperature control method according to claim 19, characterized in that, The target module also includes flash memory, and the first CPU core is further used to manage the reading and writing of the flash memory; controlling the operation of the UFS target module to increase its temperature includes: After controlling the second CPU core to process the data of the UFS and increase the temperature for a first preset time, and if the temperature of the UFS is less than or equal to the second temperature threshold, the first CPU core is also controlled to increase the temperature of the flash memory for reading and writing data.

21. The UFS temperature control method according to claim 17, characterized in that, The UFS includes a second central processing unit (CPU) core, which is used for data transmission with the processor; the method further includes: When the temperature of the UFS is less than a first temperature threshold and the number of error corrections for the data stored in the UFS is less than or equal to the number of error corrections threshold, the second indication information of the UFS is obtained; the second indication information is used to characterize whether the number of reads and writes to the UFS by the processor is greater than the number of reads and writes threshold. If the number of read / write operations performed by the processor on the UFS is less than or equal to the read / write operation threshold, the battery power level is obtained; if the battery power level is greater than the power threshold and the battery is not in super power saving mode, the target module of the UFS is controlled to run and heat up.

22. The UFS temperature control method according to claim 21, characterized in that, The UFS also includes a first central processing unit (CPU) core, and the target module includes SRAM. The first CPU core is used to manage the read and write operations of the SRAM. Controlling the operation of the target module of the UFS to increase its temperature includes: The first CPU core is controlled to heat up the SRAM when reading and writing data.

23. The UFS temperature control method according to claim 22, characterized in that, The method of controlling the target module of the UFS to operate and heat up also includes: After controlling the first CPU core to heat up the SRAM for a first preset time while reading and writing data, and if the temperature of the UFS is less than or equal to a second temperature threshold, the second CPU core is also controlled to process the data from the processor to heat up.

24. The UFS temperature control method according to claim 23, characterized in that, The target module also includes flash memory, and the first CPU core is further used to manage the reading and writing of the flash memory; controlling the operation of the UFS target module to increase its temperature includes: After controlling the second CPU core to process the data of the UFS and increase the temperature for a first preset time, and if the temperature of the UFS is less than or equal to the second temperature threshold, the first CPU core is also controlled to increase the temperature of the flash memory for reading and writing data.

25. The UFS temperature control method according to claim 17, characterized in that, The UFS includes a second central processing unit (CPU) core, which is used for data transmission with the processor; the method further includes: When the temperature of the UFS is less than a first temperature threshold and the number of error corrections for the data stored in the UFS is less than or equal to the number of error corrections threshold, the second indication information of the UFS is obtained; the second indication information is used to characterize whether the number of reads and writes to the UFS by the processor is greater than the number of reads and writes threshold. When the number of read / write operations performed by the processor on the UFS exceeds a threshold, and the UFS prohibits the second CPU core from processing data from the processor, the target module of the UFS is controlled to run and its temperature is increased.

26. The UFS temperature control method according to claim 25, characterized in that, The UFS also includes a first central processing unit (CPU) core, and the target module includes SRAM. The first CPU core is used to manage the read and write operations of the SRAM. Controlling the operation of the target module of the UFS to increase its temperature includes: The first CPU core is controlled to heat up the SRAM when reading and writing data.

27. The UFS temperature control method according to claim 26, characterized in that, The target module also includes flash memory, and the first CPU core is further used to manage the reading and writing of the flash memory; controlling the operation of the UFS target module to increase its temperature includes: After controlling the first CPU core to heat up the SRAM read / write data for a first preset time, and if the temperature of the UFS is less than or equal to a second temperature threshold, the first CPU core is also controlled to heat up the flash memory read / write data.

28. The UFS temperature control method according to claim 20, 24, or 27, characterized in that, The UFS also includes multiple storage blocks, and the processor is further configured to: After the first CPU core is controlled to heat up the flash memory for reading and writing data, a target block is obtained from the plurality of storage blocks, and the UFS is controlled to heat up the target block through erase and write operations.

29. The UFS temperature control method according to claim 28, characterized in that, The plurality of storage blocks include initial bad blocks, and the control of the UFS to heat up the target blocks through erase and write operations includes: The UFS is controlled to heat up by erasing and writing the initial bad blocks.

30. The UFS temperature control method according to claim 29, characterized in that, The plurality of storage blocks include running bad blocks but exclude the initial bad blocks, and controlling the UFS to heat up through the erase and write operations of the target blocks includes: The UFS is controlled to heat up by erasing and writing the bad blocks.

31. The UFS temperature control method according to claim 30, characterized in that, The plurality of storage blocks do not include the bad blocks and do not include the initialization blocks. Controlling the UFS to heat up the target blocks through erase / write operations includes: The UFS is controlled to heat up the storage block with the fewest erase / write operations among the plurality of storage blocks.

32. The UFS temperature control method according to any one of claims 17-31, characterized in that, The method further includes: After the target module has been heated for a first preset time, if the temperature of the UFS is greater than a second temperature threshold, the target module is stopped to stop heating; wherein the second temperature threshold is greater than the first temperature threshold.

33. An electronic device, characterized in that, Includes the UFS temperature control circuit as described in any one of claims 1-16.

34. An electronic device, characterized in that, The device includes a UFS and one or more processors, the UFS being used to store instructions executable by the one or more processors, the UFS storing computer program code including computer instructions, which, when executed by the processor, cause the electronic device to perform the UFS temperature control method as described in any one of claims 17-32.

35. A computer-readable storage medium, characterized in that, Includes computer instructions that, when executed on the electronic device, cause the electronic device to perform the UFS temperature control method as described in any one of claims 17-32.

36. A computer program product, characterized in that, When the computer program product is run on an electronic device, it causes the electronic device to perform the UFS temperature control method as described in any one of claims 17-32.

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