Ebaps device based on axially asymmetric two-stage amorphous silicon microchannel plate

Abstract

This application discloses an EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate, comprising: an AVG, a photocathode, an EBCMOS pixel array, an axially asymmetric dual-segment amorphous silicon microchannel plate, and an EBCMOS sensor; the axially asymmetric dual-segment amorphous silicon microchannel plate is disposed between the photocathode and the EBCMOS pixel array; the axially asymmetric dual-segment amorphous silicon microchannel plate is bonded to the EBCMOS pixel array; and the axially asymmetric dual-segment amorphous silicon microchannel plate and the EBCMOS sensor are bonded together. This EBAPS device enables electrons to undergo electron multiplication in a directional manner before entering the silicon target, allowing the multiplied electrons to enter the EBCMOS sensor in a directional manner. Simultaneously, the number of multiplied electrons is greatly increased, and crosstalk between electrons and pixels is isolated, thus improving imaging quality.

Description

Technical Field

[0001] This application relates to the field of low-light imaging device technology, and in particular to an EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate. Background Technology

[0002] The basic structure of existing EBAPS (Electron Bombarded Active Pixel Sensor) devices includes a photocathode, a vacuum drift region, and an EBCMOS pixel array. Signal amplification relies entirely on electron multiplication within the silicon target on the pixel surface. Under extremely low illumination conditions (ambient illuminance less than or equal to 0.001 lux), the equivalent charge generated by this type of device, even after multiplication, cannot significantly exceed the EBCMOS readout noise floor, resulting in a noticeable degradation in signal-to-noise ratio under sub-photon statistical conditions.

[0003] Meanwhile, since there is usually a free drift region of hundreds of micrometers between the photocathode and the EBCMOS in existing EBAPS devices, electrons are prone to significant angular scattering and lateral diffusion during long-distance drift under a high bias electric field, resulting in inter-pixel crosstalk and a decrease in the modulation transfer function, thus failing to obtain a high-resolution image.

[0004] Therefore, existing EBAPS devices suffer from problems such as insufficient intrinsic gain, high multiplication noise, and severe inter-pixel crosstalk when used in ultra-low illumination, which greatly limits their application in night vision, astronomical low-light detection, and other fields.

[0005] The information disclosed in the background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] This application addresses the aforementioned technical problems by providing an EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate. The resulting device can achieve efficient electron multiplication and acceleration while slowing down the movement speed of electrons impacting pixels, effectively improving imaging clarity in reduced illumination environments and preventing crosstalk.

[0007] This application provides an EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate, including: AVG, photocathode, EBCMOS pixel array, axially asymmetric dual-segment amorphous silicon microchannel plate, and EBCMOS; An axially asymmetric dual-segment amorphous silicon microchannel plate is disposed between the photocathode and the EBCMOS pixel array; the axially asymmetric dual-segment amorphous silicon microchannel plate is bonded to the EBCMOS pixel array. Axially asymmetric dual-segment amorphous silicon microchannel plate, EBCMOS bonding; The axially asymmetric dual-segment amorphous silicon microchannel plate includes: etching multiple amorphous silicon single holes; The outlet end of the amorphous silicon single aperture is positioned directly opposite each pixel on the EBCMOS pixel array; After electrons generated by the photocathode enter each amorphous silicon micropore, the high-energy electric field distribution in the amorphous silicon micropore first accelerates the electron multiplication. Then, the electrons are buffered by the relatively slow-down energy electric field to move to each pixel, ensuring multiplication while avoiding crosstalk caused by excessive movement speed.

[0008] Preferably, the axially asymmetric dual-segment amorphous silicon microchannel plate comprises, sequentially bonded along the electron transport direction: a first electrode layer, a first segment AMCP, a second electrode layer, a second segment AMCP, and a third electrode layer; An electric field E1 is formed by the potential difference between the first electrode layer and the second electrode layer, which controls the accelerated and multiplied motion of electrons entering this channel. An electric field E2 is formed by the potential difference between the second and third electrode layers, which controls the buffering speed and multiplication of electrons entering this channel.

[0009] Preferably, the amorphous silicon single pore comprises: a first microchannel, a second microchannel, and a third microchannel; the inner wall of the amorphous silicon wall at the first end of the second microchannel continues the contraction structure of the first microchannel; the inner wall of the amorphous silicon wall at the second end of the second microchannel continues the expansion structure of the third microchannel; a second electrode layer is disposed at the point of minimum diameter of the second microchannel; the second microchannel is divided into two halves at the point of minimum diameter. The first microchannel segment and half of it are within the electric field E1; the other half of the second microchannel segment and the third microchannel segment are within the electric field E2, where E1>E2, and the ratio of E1 / E2 is controlled between 2 and 5. Preferably, L1=L2>L 轴 The axial length L1 of the first microchannel; the length L2 of the third microchannel; and the axial length L of the second microchannel are also specified. 轴 ; Preferably, L1 is 80–120 μm; L2 is 80–120 μm; L 轴 The axial length is 0.7–1.4 μm; E1 is 8–15 kV / mm; E2 is 2–6 kV / mm.

[0010] Preferably, the diameter of the inlet end of the first microchannel is larger than the diameter of the constriction end; the diameter of the outlet end of the third microchannel is larger than the diameter of the constriction end.

[0011] Preferably, the diameter of the inlet end of the first microchannel is d1; the diameter of the outlet end of the third microchannel is d2; and the diameter at the central axis of the second microchannel is d3, where d1 > d3. <d2; Preferably, d1 is 6–8 μm, d3 is 3.5–4.5 μm, and d2 is 5–7 μm.

[0012] Preferably, the cone angle of the contraction end of the first microchannel is α1, the cone angle of the contraction end of the third microchannel is α2, and α1>α2; Preferably, α1 is 3°~5°, α2 is 1°~2°, and α1>α2.

[0013] Preferably, it includes: a silicon oxide layer; the silicon oxide layer is disposed between the axially asymmetric dual-segment amorphous silicon microchannel plate and the EBCMOS pixel array; Preferably, the first electrode layer, the second electrode layer, and the third electrode layer are all chromium or titanium metal thin films, and the thickness of the first electrode layer, the second electrode layer, and the third electrode layer is 200~500nm.

[0014] Preferably, the preparation method includes the following steps: Step S1: A top first electrode layer is deposited on the polished silicon substrate using DC magnetron sputtering. A first AMCP segment is grown on the bottom surface of the first electrode layer using PECVD. Micro-hole mask preparation and deep reactive ion etching are performed on the first AMCP segment to form a tilted amorphous silicon etched through-hole structure with a cone angle α1. A chromium metal thin film is deposited on the bottom surface of the first AMCP segment using magnetron sputtering as the second electrode layer. A second AMCP segment is grown on the bottom surface of the second electrode layer using PECVD. Micro-hole mask preparation and deep reactive ion etching are performed within the second AMCP segment to form a tilted amorphous silicon etched through-hole structure with a cone angle α2. A chromium metal thin film is deposited on the bottom surface of the second AMCP segment using magnetron sputtering as the third electrode layer. Step S2: A micro-hole array pattern is formed on the first electrode layer using photolithography to precisely align the opening position of the first electrode layer with the subsequent microchannel array. A high-energy-dominant Bosch deep reactive ion etching process is used to vertically etch the tapered vias, connecting and forming the first microchannel and half of the second microchannel. A second electrode layer is formed by sputter deposition at the bottom of the first AMCP. In the second AMCP, a right-angle amorphous silicon tapered via is etched using a high-energy-dominant Bosch etching process, connecting and forming the third microchannel and the other half of the second microchannel. The second AMCP is bonded to the bottom surface of the second electrode layer to obtain the overall structure of a multi-electrode dual-segment amorphous silicon microchannel plate: top electrode—first AMCP—middle electrode—second AMCP—bottom electrode. The resulting first electrode layer, first through-hole structure, second electrode layer, second through-hole structure, and third electrode layer are configured as a first microchannel, a second microchannel, and a third microchannel. Step S3: The overall structure of the multi-electrode dual-segment amorphous silicon microchannel plate is precisely aligned with the EBCMOS pixels, so that the axis of each amorphous silicon single hole of the microchannel corresponds one-to-one with the center of each pixel, and then bonded to obtain the EBAPS device.

[0015] Preferably, the DC magnetron sputtering deposition conditions for the first electrode layer are a sputtering power of 200-300W, an argon flow rate of 30-50sccm, and a chamber pressure controlled at 3-5mTorr, so that the thickness of the obtained metal film is 200-500nm. Preferably, step S1 further includes: to reduce the interfacial contact resistance between the metal and the subsequent amorphous silicon layer, depositing an n-type microcrystalline silicon transition layer with a thickness of 20-50 nm on the surface of the first electrode layer by PECVD, with the deposition temperature controlled at 250-300°C, and the reaction gas being a mixture of SiH4, PH3 and H2, wherein the volume fraction of PH3 is 0.5%-1%; The bonding in step S3 includes: Step S31: Perform pre-bonding at room temperature; Step S32: Annealing is performed at 150-250℃ for 2-4 hours to generate a stable Si-O-Si covalent bond structure through interfacial hydroxyl dehydration condensation reaction, thereby achieving low-temperature, high-strength direct bonding between the amorphous silicon microchannel plate and the EBCMOS.

[0016] The beneficial effects that this application can produce include: 1) The EBAPS device based on axially asymmetric dual-segment amorphous silicon microchannel plate provided in this application reconstructs the EBAPS electron multiplication, electron movement, and electron injection process at the physical structure level of the device. A high-gain dual-segment amorphous silicon microchannel multiplication structure is introduced between the photocathode and the EBCMOS, and it is bonded to the EBCMOS surface at a micrometer-level close-fit distance to construct an EBAPS structure with microchannel multiplication-close-fit injection structure. This allows electrons to complete electron multiplication in a directional manner before entering the silicon target, and allows the multiplied electrons to enter the EBCMOS in a directional manner. At the same time, the number of multiplied electrons is greatly increased, the crosstalk problem between electrons and pixels is isolated, and the imaging quality is improved.

[0017] 2) The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate provided in this application achieves a higher initial velocity for electrons in the first microchannel 211 by controlling L1 and L2, as well as electric fields E1 and E2, and buffering the velocity in the third microchannel 213. In the first microchannel 211, the large cone angle α1 causes the channel entrance to rapidly contract, and combined with the high accelerating electric field strength, the primary electrons emitted by the photocathode acquire high kinetic energy within a short distance and rapidly complete multiple multiplications. In the second microchannel segment, by reducing the cone angle α2 and lowering the electric field strength, the electron velocity is buffered during the transmission process near the pixel side, thereby reducing energy dissipation when electrons collide with the EBCMOS pixel surface and energy loss from collisions between electrons. Attached Figure Description

[0018] Figure 1 A schematic front cross-sectional view of an EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate in at least one embodiment provided in this application. Figure 2 A schematic diagram of the front cross-section of an amorphous silicon microchannel plate in at least one embodiment provided in this application; Figure 3 A schematic diagram of a microchannel single-pore structure in at least one embodiment provided in this application; Figure 4 A schematic diagram of the process flow in at least one embodiment provided in this application; Figure 5 The following are provided for this application: a) a structural diagram of the simulation device model in Embodiment 1; b) an existing MCP model; and c) an MCP model obtained in this embodiment. Figure 6 This application provides the Vaughan multiplication model used in the simulation of Example 1; Figure 7 The following simulation results of the electron multiplication trajectory obtained in Example 1 are provided for this application: a) MCP model of the existing structure; b) MCP model obtained in this example. Legend: AVG1, photocathode 2, first AMCP segment 3, second AMCP segment 4, EBCMOS pixel array 5, pixel 51, EBCMOS 6, first electrode layer 11, second electrode layer 12, third electrode layer 13, amorphous silicon single hole 21, amorphous silicon wall 25, first amorphous silicon substrate 22, second amorphous silicon substrate 23, silicon oxide layer 24, first microchannel 211, second microchannel 212, third microchannel 213. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] Technical means not detailed in this application and not used to solve the technical problems of this application are all set according to common general knowledge in the field, and multiple common general knowledge setting methods can be implemented.

[0022] See Figures 1-4 The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate provided in this application includes, from top to bottom, an AVG1, a photocathode layer 2, an axially asymmetric dual-segment microchannel plate assembly made of amorphous silicon, an EBCMOS 6, and an EBCMOS pixel array 5. The EBCMOS pixel array 5 includes multiple pixels.

[0023] The dual-segment microchannel plate assembly includes two segments bonded sequentially along the electron transport direction: a first segment AMCP3 and a second segment AMCP4, with a second electrode layer 12 disposed between them. A first electrode layer 11 is disposed on the end face of the first segment AMCP3 near the photocathode 2 to form an independently controllable dual-segment electric field structure. In the microchannel electric field design, an electric field E1 is formed by a potential difference between the first electrode layer 11 and the second electrode layer 12, and an electric field E2 is formed by a potential difference between the second electrode layer 12 and the third electrode layer 13.

[0024] The first AMCP3 segment, under the action of the first electric field E1, is used to strongly accelerate the primary electrons entering the channel, increasing the collision probability of electrons in the micro-control, resulting in a large number of multiplied electrons. The second AMCP4 segment has a third electrode layer 13 disposed on the end face near the EBCMOS pixel array 5, forming an independently controllable dual-segment electric field structure. Under the action of the second electric field E2, the second AMCP4 segment is used to buffer and stabilize the high-speed electrons entering the second AMCP4 segment after multiplication, forming an asymmetric electric field distribution along the axial direction inside the device, with a stronger front and weaker rear, achieving precise control of the electron dynamic process. This design allows electrons to obtain different kinetic energies as they move along the electric field direction, resulting in strong acceleration of electrons in the E1 electric field, increasing the collision probability of electrons in the micro-control, and generating a large number of multiplied electrons. Under the action of the electric field E2, it buffers and stabilizes the high-speed electrons while maintaining a certain velocity at the electron's end. The first microchannel 211 and half of the second microchannel 212 are in the electric field E1; the other half of the second microchannel 212 and the third microchannel 213 are in the electric field E2, where E1>E2 and the ratio of E1 / E2 is controlled between 2 and 5.

[0025] Multiple amorphous silicon single holes 21 are arranged in an array on the amorphous silicon microchannel plate, connecting the first AMCP3 and the second AMCP4. The exit end of the amorphous silicon single hole 21 is positioned directly opposite each pixel 51 on the EBCMOS pixel array 5.

[0026] like Figure 3 As shown, the amorphous silicon single-channel 21 includes a first microchannel 211, a second microchannel 212, and a third microchannel 213. An amorphous silicon wall 25 is disposed on the inner wall of the amorphous silicon single-channel 21 to form the first microchannel 211, the second microchannel 212, and the third microchannel 213. The two ends of the second microchannel 212 are connected to the first microchannel 211 and the third microchannel 213, respectively. The second microchannel 212 is a guide straight hole. The flared end of the first microchannel 211 faces the photocathode 2; the flared end of the third microchannel 213 faces the EBCMOS pixel array 5. The constricted ends of the first microchannel 211 and the third microchannel 213 are connected to the second microchannel 212, respectively. One side of the amorphous silicon single-channel 21 exhibits an asymmetrical tapering structure along the axial direction.

[0027] In one specific embodiment, the amorphous silicon single-hole structure 21 includes: a diameter d1 at the inlet of the first microchannel 211, a diameter d2 at the outlet of the third microchannel 213, and a diameter d3 at the central axis of the second microchannel 212, wherein d1 > d3. <d2。

[0028] In one specific embodiment, the cone angle at the constriction opening of the first microchannel 211 is α1, and the cone angle at the constriction opening of the third microchannel 213 is α2, where α1 > α2. By setting different taper angles at the openings of the first microchannel 211 and the third microchannel 213, different tapering angles can be formed. This allows the dimensions of various parts of the through-holes inside the channel plate to be adjusted according to imaging requirements during the axial movement of electrons, thereby obtaining the required acceleration and buffering motion. This enables accurate control of the electron movement speed and achieves better imaging results.

[0029] In one specific embodiment, the axial length of the first microchannel 211 is L1, the axial length of the third microchannel 213 is L2, and the axial length of the middle segment is L... 轴 L 轴 Including electrode thickness. By controlling L1 and L2, as well as electric fields E1 and E2, electrons acquire a higher initial velocity in the first microchannel 211 and are buffered in the third microchannel 213. In the first microchannel 211, the large cone angle α1 causes the channel entrance to rapidly contract, and combined with a high accelerating electric field strength, the primary electrons emitted by the photocathode acquire high kinetic energy in a short distance and rapidly complete multiple multiplications. In the second microchannel segment, by reducing the cone angle α2 and lowering the electric field strength, the electron velocity is buffered during the transmission process near the pixel side, thereby reducing the energy dispersion when electrons collide with the EBCMOS pixel surface and the energy loss from collisions between electrons.

[0030] The amorphous silicon walls 25 at both ends of the second microchannel 212 continue the expansion trend of the first microchannel 211 and the third microchannel 213, respectively, and form the minimum diameter d3 of the amorphous silicon single hole 21 at the second electrode layer 12. The second electrode layer 12 is located at the minimum aperture d3 of the microchannel in the axial direction. Its function is not only to divide the overall microchannel into two functional segments with different electric field strengths, but also to achieve electron control under the dual constraints of geometric structure and electric field structure.

[0031] In one specific embodiment, the amorphous silicon microchannel plate structure is as follows: Figure 2 The diagram shows a silicon oxide layer 24 (SiO2) disposed on the outer side of the third electrode layer 13 near the EBCMOS pixel array 5. x To achieve a closer fit between the microchannel board and the EBCMOS6, and to solve... Figure 2The third electrode layer 13 of the microchannel board may pose potential risks such as short circuits and voltage breakdown of pixels to the EBCMOS surface. In the design process, a silicon oxide isolation layer 24 is grown between the third electrode layer 13 at the end of the microchannel board and the EBCMOS pixel array 5, and a low-temperature hydrophilic direct bonding process is used to integrate the microchannel with the silicon oxide on the pixel surface. This effectively avoids leakage, short circuits and interface failure caused by direct contact between the bottom electrode of the microchannel board and the EBCMOS surface, and ensures reliable operation of the device under high voltage conditions.

[0032] In one specific embodiment, the cone angle α1 of the first microchannel 211 is 3°~5°, and the cone angle α2 of the third microchannel 213 is designed to be 1°~2°, with α1>α2; the inlet aperture d1 of the first microchannel 211 is 6~8μm, the aperture d3 of the second microchannel 212 is 3.5~4.5μm, and the outlet aperture d2 of the third microchannel 213 is 5~7μm. This configuration creates an asymmetric tapering structure in the axial direction of the microchannels.

[0033] In one specific embodiment, the first electrode layer 11, the second electrode layer 12, and the third electrode layer 13 are all chromium or titanium metal thin films with a thickness of 200~500nm.

[0034] In one specific embodiment, L1=L2>L 轴 The axial length L1 of the first microchannel (211); the length L2 of the third microchannel (213); and the axial length L of the second microchannel (212) are as follows: 轴 .

[0035] In one specific embodiment, the axial length L1 of the first microchannel 211 is 80–120 μm, and its internal electric field E1 is 8–15 kV / mm; the length L2 of the third microchannel 213 is 80–120 μm, and its internal electric field E2 is 2–6 kV / mm; the length L1 of the second microchannel 212 is... 轴 The axial length is 0.7–1.4 μm.

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments, but this does not limit the present invention in any way. Any modifications or improvements made based on the teachings of the present invention shall fall within the protection scope of the present invention.

[0037] Unless otherwise specified, all materials and instruments used in the following embodiments were obtained through commercial channels; and all detection methods used are existing methods unless otherwise specified.

[0038] (1) Amorphous silicon thin film growth steps The amorphous silicon thin films used in the first AMCP3 and the second AMCP4 sections were grown on the surface of the metal electrodes using plasma-enhanced chemical vapor deposition (PECVD). Before deposition, the substrate was ultrasonically cleaned for 10 minutes each with acetone, anhydrous ethanol, and deionized water, and then dried with nitrogen. Afterward, it was placed in the reaction chamber and subjected to plasma pretreatment with hydrogen gas at 100–150 W RF power for 3–5 minutes to remove surface adsorbed impurities and improve interfacial activity.

[0039] During amorphous silicon deposition, the substrate temperature was controlled at 280–320℃, the reaction chamber pressure was maintained at 0.8–1.2 Torr, and the reaction gas was a mixture of SiH4 and H2, with a SiH4 flow rate of 20–30 sccm and an H2 flow rate of 120–180 sccm. The RF power was controlled at 50–80 W. Under these conditions, the deposition rate remained stable at 0.8–1.2 μm / min. By controlling the deposition time, the amorphous silicon film thickness of both the first AMCP3 and the second AMCP4 sections reached the range of 80–120 μm, thus meeting the structural requirements for subsequent deep reactive ion etching to form high aspect ratio microchannels.

[0040] To improve the bulk resistivity and multiplication stability of amorphous silicon thin films, no dopant gas is introduced during the deposition process, resulting in intrinsic or slightly p-type characteristics, with the bulk resistivity controlled at 1×10⁻⁶. 9 ~5×10 9 Within the Ω·cm range. After deposition, the amorphous silicon thin film is subjected to vacuum annealing at 200℃ for 30 min to reduce the internal stress of the film and improve the film density, providing a stable material basis for subsequent microporous mask preparation and deep etching processes.

[0041] (2) The top and middle of the microchannel are achieved using an electrode deposition process. The deposition of the first electrode layer 11 and the second electrode layer 12 is strictly alternated with the amorphous silicon growth and microchannel etching processes. First, a top metal first electrode layer 11 is deposited on the polished silicon substrate using DC magnetron sputtering. The electrode material is chromium or titanium, the sputtering power is 200–300 W, the argon flow rate is 30–50 sccm, and the chamber pressure is controlled at 3–5 mTorr, resulting in a metal film thickness of 200–500 nm. To reduce the interfacial contact resistance between the metal and the subsequent amorphous silicon layer, an n-type microcrystalline silicon transition layer with a thickness of 20–50 nm is deposited on the surface of the metal first electrode layer 11 using PECVD. The deposition temperature is controlled at 250–300 °C, and the reaction gas is a mixture of SiH4, PH3, and H2, with a PH3 volume fraction of 0.5%–1%.

[0042] After the deposition of the top first electrode layer 11 and the transition layer, a first amorphous silicon thin film is grown on its surface using PECVD as the first AMCP3 segment, with process parameters consistent with the aforementioned amorphous silicon thin film growth steps. Subsequently, micro-hole mask preparation and deep reactive ion etching are performed on the first AMCP3 segment. This etching is an angled amorphous silicon etching, forming the first microchannel 211 with a cone angle α1 (3°~5°). After the etching of the first AMCP3 segment is completed and the polymer residue in the holes is removed by plasma cleaning, an n-type microcrystalline silicon transition layer with a thickness of 20~50nm is deposited again on the bottom surface of the first AMCP3 segment using PECVD. Then, a chromium metal thin film is deposited as the intermediate second electrode layer 12 using magnetron sputtering, with sputtering power, gas flow rate, and film thickness parameters the same as the top electrode, so that the thickness of the intermediate electrode is controlled at 200~500nm.

[0043] Simultaneously, a second amorphous silicon thin film is grown on the bottom surface of the second electrode layer 12 using PECVD technology as the second AMCP4 segment. The process parameters are consistent with the aforementioned amorphous silicon thin film growth steps. Subsequently, tilted amorphous silicon etching is performed to form a cone angle α2 (1°~2°). Then, the third electrode layer 13 is deposited at the bottom of the second AMCP4 segment using the aforementioned electrode deposition method. Through the above process, a multi-electrode segmented control structure is formed in the axial direction of the microchannel, providing a stable process foundation for subsequent bottom electrode deposition and device bonding.

[0044] (3) Realization of amorphous silicon microchannel plates and electrode etching processes First, after depositing the top metal electrode and the n-type microcrystalline silicon transition layer, a 6–8 μm thick positive photoresist is spin-coated onto its surface, followed by pre-baking at 90°C and hard baking at 150°C. Then, a micro-hole array pattern with a pore diameter of 6–8 μm and a spacing of 8–10 μm is formed on the top electrode layer using photolithography. Reactive ion etching of the chromium metal top electrode is performed using a Cl2 / Ar gas system at a radio frequency power of 180–250 W and a chamber pressure of 5–10 mTorr to ensure precise alignment of the top electrode opening with the subsequent microchannel array.

[0045] After etching the first electrode layer 11, an amorphous silicon thin film with a thickness of 80–120 μm was deposited on the etched via surface, and a microvia mask was fabricated. Subsequently, a high-energy-dominant Bosch deep reactive ion etching process was used for vertical etching of the tapered vias. During the etching stage, the SF6 flow rate was 140–160 sccm, the RF power was 480–550 W, and the cavity pressure was 18–22 mTorr; during the passivation stage, the C4F8 flow rate was 60–80 sccm, the RF power was 300–350 W, and the cavity pressure was 22–28 mTorr. The AMCP1 etching depth is 80-120 μm through approximately 600-800 etching / passivation cycles. Right-angle non-silicon etching is performed between the first microchannel 211 and the second microchannel 212 to form a tapered structure with a cone angle α1 of 3°-5°. This causes the aperture of half of the first microchannel 211 and the second microchannel 212 to naturally shrink from 6-8 μm at the inlet end to 3.5-4.5 μm at the outlet.

[0046] After the first AMCP3 etching is completed and cleaned by a combination of oxygen and argon plasma, a 20–50 nm n-type microcrystalline silicon transition layer is sputtered and deposited at its bottom. Subsequently, a 200–500 nm thick chromium metal film is sputtered and deposited to form the second electrode layer 12 at the bottom of the first AMCP3 section, i.e., the intermediate electrode layer, with an effective axial length L. 轴 The micrometer size should be controlled within the range of 0.7–1.4 μm. 轴 The length of the second microchannel 212 includes the total length of the amorphous silicon material and the second electrode layer 12.

[0047] The second AMCP4 microvia is etched using a high-energy-dominant Bosch etching process to create right-angle non-silicon tapered vias. During the etching stage, the SF6 flow rate is 90–110 sccm and the RF power is 300–350 W. During the passivation stage, the C4F8 flow rate is 90–110 sccm, which significantly enhances the sidewall protection during the etching process. This results in a gradually changing channel structure with a cone angle α2 of 1°–2° from the second microchannel 212 to the third microchannel 213. This allows the channel aperture to smoothly expand from 3.5–4.5 μm to an outlet diameter of 5–7 μm, which is the other half of the second microchannel 212 and the structure of the third microchannel 213.

[0048] Finally, after the second AMCP4 segment is etched, a chromium or titanium metal film with a thickness of 200-500 nm is sputtered and deposited at its bottom to form the third electrode layer 13 at the bottom of the second AMCP4 segment, thus completing the overall structure of the multi-electrode dual-segment amorphous silicon microchannel plate consisting of the top electrode, the first AMCP3 segment, the middle electrode, the second AMCP4 segment, and the bottom electrode. The micropores on the side of the second electrode layer 12 of the first AMCP3 segment are aligned with the right-angle micropores of the second AMCP4 segment and then aligned and bonded to form a complete amorphous silicon microchannel plate.

[0049] (4) Silicon dioxide growth and via etching on the surface of EBCMOS pixels After fabricating the multi-electrode dual-segment amorphous silicon microchannel plate structure, a silicon oxide layer 24 was constructed on the surface of the EBCMOS pixel to prevent short circuits caused by direct contact between the bottom electrode of the microchannel plate and the pixel metal interconnect layer. The electron beam was also spatially buffered and modulated before electron injection. The silicon oxide layer 24 was grown using plasma-enhanced chemical vapor deposition (PECVD), with the deposition temperature controlled at 250–300 °C and the reaction chamber pressure maintained at 0.8–1.2 Torr. The reaction gas was a mixture of SiH4 and N2O, with a SiH4 flow rate of 20–30 sccm and an N2O flow rate of 150–200 sccm, resulting in a SiO2 film thickness of 0.8–1.5 μm.

[0050] After the silicon oxide layer 24 is deposited, a 2–3 μm thick positive photoresist is spin-coated onto its surface and soft-baked at 90°C. Subsequently, exposure and development are performed using a mask corresponding to each EBCMOS pixel array, forming a via window at the center of each pixel. The sample is placed in a reactive ion etching (RIE) apparatus, where a CHF3 and O2 mixture is used for anisotropic etching of the silicon dioxide. The CHF3 flow rate is 35–45 sccm, the O2 flow rate is 3–6 sccm, the RF power is controlled at 180–250 W, and the chamber pressure is 30–45 mTorr. By precisely controlling the etching time, the silicon oxide layer 24 is completely etched through until the underlying pixel electrode metal surface is exposed.

[0051] Near the end of the etching process, the radio frequency power is gradually reduced to avoid over-etching and damaging the pixel metal layer. After etching, an oxygen plasma ashing process is used to remove residual photoresist, and nitrogen gas is used to purge and clean the inner wall of the via, providing clean and stable interface conditions for the subsequent low-temperature direct bonding of the amorphous silicon microchannel board and EBCMOS.

[0052] (5) Alignment and bonding of the dual-segment microchannel plate with the EBCMOS pixel surface After etching the silicon oxide vias, oxygen plasma activation treatment was performed on the surface of the AMCP bottom electrode and the silicon oxide surface of the EBCMOS, forming high-density hydroxyl groups. Subsequently, the AMCP and EBCMOS were precisely aligned in a clean environment, ensuring that the 21-axis of the microchannel amorphous silicon single hole corresponded one-to-one with the pixel center, and pre-bonding was performed at room temperature. Afterwards, annealing was carried out at 150–250℃ for 2–4 hours, generating a stable Si–O–Si covalent bond structure through the interfacial hydroxyl dehydration condensation reaction, achieving low-temperature, high-strength direct bonding between the amorphous silicon microchannel plate and the EBCMOS. This yielded the EBAPS device.

[0053] The obtained devices were subjected to performance simulation testing: 1. The structure of the simulation device model is as follows: Figure 5 As shown, Figure 5 'a' represents the existing MCP model. Figure 5 b is the MCP model obtained in this embodiment, with the same structural parameters as in this embodiment. Simulation initial conditions: initial emission of 5 electrons, applied accelerating voltage of -500V, Vaughan multiplication model ( Figure 6 ).

[0054] The simulation results of the electronic motion trajectory are as follows Figure 7 As shown, Figure 7 In an existing EBAPS device, the electron multiplication factor in the traditional MCP model is approximately 166 electrons (4.15 eV); in the MCP model of the device obtained in this embodiment, the electron multiplication factor is approximately 522 electrons (4.6 eV). The comparison shows that the structural gain effect provided by this application is approximately three times that of the traditional structure, and the electron multiplication provides directional and controllable motion, effectively improving imaging clarity in ambient illuminance less than or equal to 0.0001 lux, while avoiding image blurring caused by electron crosstalk.

[0055] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate, characterized in that, include: AVG (1), photocathode (2), EBCMOS pixel array (5), axially asymmetric dual-segment amorphous silicon microchannel plate, EBCMOS (6); An axially asymmetric dual-segment amorphous silicon microchannel plate is disposed between the photocathode (2) and the EBCMOS pixel array (5); the axially asymmetric dual-segment amorphous silicon microchannel plate is bonded to the EBCMOS pixel array (5); Axially asymmetric dual-segment amorphous silicon microchannel plate, EBCMOS (6) bonding; The axially asymmetric dual-segment amorphous silicon microchannel plate includes: a plurality of amorphous silicon single holes (21) arranged in an array; The exit end of the amorphous silicon single hole (21) is positioned directly opposite each pixel (51) on the EBCMOS pixel array (5); After the photocathode (2) generates electrons that enter each amorphous silicon single hole (21), they are accelerated by the asymmetric electric field in the amorphous silicon single hole (21), and then moved to each pixel (51) in a direction and buffered manner, so as to ensure the multiplication while avoiding crosstalk caused by excessive movement speed.

2. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to claim 1, characterized in that, The axially asymmetric dual-segment amorphous silicon microchannel plate comprises the following layers bonded sequentially along the electron transport direction: a first electrode layer (11), a first segment AMCP (3), a second electrode layer (12), a second segment AMCP (4), and a third electrode layer (13). An electric field E1 is formed by the potential difference between the first electrode layer (11) and the second electrode layer (12), which controls the accelerated motion of electrons entering this channel. An electric field E2 is formed by the potential difference between the second electrode layer (12) and the third electrode layer (13), which controls the buffering motion of electrons entering this channel.

3. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to claim 2, characterized in that, The amorphous silicon single-hole (21) includes: a first microchannel (211), a second microchannel (212), and a third microchannel (213); the inner wall of the amorphous silicon wall (25) at the first end of the second microchannel (212) continues the contraction structure of the first microchannel (211); the inner wall of the amorphous silicon wall (25) at the second end of the second microchannel (212) continues the expansion structure of the third microchannel (213); the second electrode layer (12) is disposed at the minimum diameter of the second microchannel (212); the second microchannel (212) is divided into two halves at the minimum diameter. The first microchannel (211) and half of it are in the electric field E1; the other half of the second microchannel (212) and the third microchannel (213) are in the electric field E2, E1>E2, and the ratio of E1 / E2 is controlled between 2 and 5. Preferably, L1=L2>L 轴 The axial length L1 of the first microchannel (211); the length L2 of the third microchannel (213); and the axial length L of the second microchannel (212) are as follows: 轴 ; Preferably, L1 is 80–120 μm; L2 is 80–120 μm; L 轴 The axial length is 0.7–1.4 μm; E1 is 8–15 kV / mm; E2 is 2–6 kV / mm.

4. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to claim 1, characterized in that, The inlet diameter of the first microchannel (211) is larger than the constriction diameter; the outlet diameter of the third microchannel (213) is larger than the constriction diameter.

5. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to claim 4, characterized in that, The diameter of the inlet end of the first microchannel (211) is d1; the diameter of the outlet end of the third microchannel (213) is d2; the diameter at the central axis of the second microchannel (212) is d3, where d1>d3. <d2; Preferably, d1 is 6–8 μm, d3 is 3.5–4.5 μm, and d2 is 5–7 μm.

6. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to claim 1, characterized in that, The cone angle of the contraction end of the first microchannel (211) is α1, and the cone angle of the contraction end of the third microchannel (213) is α2, and α1>α2; Preferably, α1 is 3°~5°, α2 is 1°~2°, and α1>α2.

7. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to claim 2, characterized in that, include: Silicon oxide layer (24); A silicon oxide layer (24) is disposed between the axially asymmetric dual-segment amorphous silicon microchannel plate and the EBCMOS pixel array (5). Preferably, the first electrode layer (11), the second electrode layer (12), and the third electrode layer (13) are all chromium or titanium metal thin films, and the thickness of the first electrode layer (11), the second electrode layer (12), and the third electrode layer (13) is 200~500nm.

8. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to any one of claims 1 to 6, characterized in that, The preparation method includes the following steps: Step S1: A top first electrode layer (11) is deposited on the polished silicon substrate using DC magnetron sputtering. A first AMCP (3) segment is grown on the bottom surface of the first electrode layer (11) using PECVD. Micro-hole mask preparation and deep reactive ion etching are performed on the first AMCP (3) segment to form a tilted amorphous silicon etched first-segment via structure with a cone angle α1. A chromium metal thin film is deposited on the bottom surface of the first AMCP (3) segment as a second electrode layer (12). A second AMCP (4) segment is grown on the bottom surface of the second electrode layer (12) using PECVD. Micro-hole mask preparation and deep reactive ion etching are performed in the second AMCP (4) segment to form a tilted amorphous silicon etched second-segment via structure with a cone angle α2. A chromium metal thin film is deposited on the bottom surface of the second AMCP (4) segment as a third electrode layer (13). Step S2: A micro-hole array pattern is formed on the first electrode layer (11) using photolithography, so that the opening position of the first electrode layer (11) is precisely aligned with the subsequent microchannel array. The vertical etching of the tapered via is performed using a high-energy dominant Bosch deep reactive ion etching process, connecting and forming half of the first microchannel (211) and the second microchannel (212). The second electrode layer (12) is formed by sputter deposition at the bottom of the first AMCP (3). The right-angle amorphous silicon tapered via is etched in the second AMCP (4) using a high-energy dominant Bosch etching process, connecting and forming the other half of the third microchannel (213) and the second microchannel (212). The second AMCP (4) is bonded to the bottom surface of the second electrode layer (12) to obtain the overall structure of the multi-electrode dual-segment amorphous silicon microchannel plate: top electrode - first AMCP (3) - middle electrode - second AMCP (4) - bottom electrode. The first electrode layer (11), the first through-hole structure, the second electrode layer (12), the second through-hole structure, and the third electrode layer (13) form a first microchannel (211), a second microchannel (212), and a third microchannel (213). Step S3: The overall structure of the multi-electrode dual-segment amorphous silicon microchannel plate is precisely aligned with the EBCMOS (6), so that the axis of each amorphous silicon single hole (21) of the microchannel corresponds one-to-one with the center of each pixel, and then bonded to obtain the EBAPS device.

9. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to claim 8, characterized in that, The DC magnetron sputtering deposition conditions for the first electrode layer (11) are sputtering power of 200-300W, argon flow rate of 30-50sccm, and chamber pressure controlled at 3-5mTorr, so that the thickness of the resulting metal film is 200-500nm.

10. The EBAPS device based on an axially asymmetric dual-segment amorphous silicon microchannel plate according to claim 8, characterized in that, Step S1 also includes: in order to reduce the interfacial contact resistance between the metal and the subsequent amorphous silicon layer, an n-type microcrystalline silicon transition layer with a thickness of 20-50 nm is deposited on the surface of the first electrode layer (11) by PECVD, the deposition temperature is controlled at 250-300℃, and the reaction gas is a mixture of SiH4, PH3 and H2, wherein the volume fraction of PH3 is 0.5%-1%; The bonding in step S3 includes: Step S31: Perform pre-bonding at room temperature; Step S32: Annealing is performed at 150-250℃ for 2-4 hours to generate a stable Si-O-Si covalent bond structure through interfacial hydroxyl dehydration condensation reaction, thereby achieving low-temperature, high-strength direct bonding between the amorphous silicon microchannel plate and the EBCMOS.

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