A low-storage decoding method, apparatus, electronic device, and storage medium based on damped posterior propagation of dual binary Turbo codes.

Abstract

This application provides a low-storage decoding method, apparatus, electronic device, and storage medium for dual-binary Turbo codes based on damped posterior propagation, belonging to the field of channel data decoding technology. The method includes: receiving an external information channel output sequence and calculating the channel log-likelihood ratio based on the external information channel output sequence; assigning the channel log-likelihood ratio as an initial posterior log-likelihood ratio; iteratively performing decoding operations based on the initial posterior log-likelihood ratio, a first decoder, and a second decoder until the maximum number of iterations is reached to obtain a target posterior log-likelihood ratio; performing symbol and decision operations on the target posterior log-likelihood ratio, and outputting a decoded bit sequence. This application can reduce the storage space occupied during the decoding process.

Description

Technical Field

[0001] This application belongs to the field of channel data decoding technology, and more specifically, relates to a low-storage decoding method, apparatus, electronic device, and storage medium based on damped a posteriori propagation of dual binary Turbo codes. Background Technology

[0002] The development of channel coding technology focuses on improving the reliability and noise immunity of data transmission, especially in the high-noise, multipath interference environment faced by power line communication (PLC) systems. Dual binary Turbo codes (DBTCs), as an advanced error-correcting code, have been applied in IEEE 1901 and ITU-T G.hn standards. Their core principle is iterative decoding through two component encoders and an interleaver, providing performance close to the Shannon limit.

[0003] However, the existing DBTC decoder has a bottleneck in terms of storage: it needs to explicitly store the three extrinsic information values ​​for each symbol, resulting in a total memory requirement of 7N (N is the number of encoded symbols / frame length; for double binary, one symbol corresponds to two bits), and the extrinsic information occupies a large amount of memory.

[0004] Therefore, a low-storage decoding method is needed. Summary of the Invention

[0005] The purpose of this application is to provide a low-storage decoding method, apparatus, electronic device, and storage medium for dual binary Turbo codes based on damped a posteriori propagation, so as to reduce the storage space occupied during the decoding process.

[0006] A first aspect of this application provides a low-memory decoding method for dual-binary Turbo codes based on damped a posteriori propagation, comprising: Receive the output sequence of the external information channel and calculate the channel log-likelihood ratio based on the output sequence of the external information channel; The channel log-likelihood ratio is assigned the initial posterior log-likelihood ratio; Based on the initial posterior log-likelihood ratio, the first decoder and the second decoder are iteratively executed to perform the decoding operation until the maximum number of iterations is reached, and the target posterior log-likelihood ratio is obtained. Perform symbol and decision operations on the target posterior log-likelihood ratio and output the decoded bit sequence.

[0007] In one embodiment, the decoding operation is iteratively performed based on the initial posterior log-likelihood ratio, the first decoder, and the second decoder until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio, including: During each iteration, the first decoder performs the following operations: Perform a deinterleaving operation on the historical posterior log-likelihood ratio output by the second decoder in the previous iteration to obtain the first input information after deinterleaving; Determine the first undamped posterior log-likelihood ratio based on the first input information; The updated posterior information is obtained based on the first input information and the undamped first posterior log-likelihood ratio. During each iteration, the second decoder performs the following operations: An interleaving operation is performed on the updated posterior information output by the first decoder to obtain the second input information; Determine the undamped second posterior log-likelihood ratio based on the second input information; The posterior log-likelihood ratio after this iteration is obtained based on the second input information and the undamped second posterior log-likelihood ratio. The above operation is repeated until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio. In the first round of iteration, the first decoder performs a deinterleaving operation based on the initial posterior log-likelihood ratio.

[0008] In one embodiment, calculating the channel log-likelihood ratio based on the channel output sequence includes: Determine the first soft information, the second soft information, and the information bit pairs in the channel output sequence; The channel log-likelihood ratio is calculated based on the first soft information, the second soft information, and the information bit pairs.

[0009] In one embodiment, calculating the channel log-likelihood ratio based on the external information channel output sequence includes: Determine the first soft information, the second soft information, and the information bit pairs in the output sequence of the external information channel; The channel log-likelihood ratio is calculated based on the first soft information, the second soft information, and the information bit pairs.

[0010] In one embodiment, a deinterleaving operation is performed on the historical posterior log-likelihood ratio output by the second decoder in the previous iteration to obtain the deinterleaved first input information, including: The historical posterior log-likelihood ratio output by the second decoder in the previous iteration is recombined by the deinterleaver to obtain the first input information after deinterleaving.

[0011] In one embodiment, determining the undamped first posterior log-likelihood ratio based on the first input information includes: Based on the first branch metric formula, forward recursive calculation and backward recursive calculation are performed on the first input information and the first check bit soft information to obtain the undamped first posterior log-likelihood ratio. The first check bit soft information is obtained based on the first soft information.

[0012] In one embodiment, an interleaving operation is performed on the updated posterior information output by the first decoder to obtain second input information, including: The updated post-hoc information output by the first decoder is reassembled by an interleaver to obtain the second input information.

[0013] In one embodiment, determining the undamped second posterior log-likelihood ratio based on the second input information includes: The second input information and the second check bit soft information are calculated based on the second branch metric formula to obtain the undamped second posterior log-likelihood ratio; The second check bit soft information is obtained based on the second soft information.

[0014] A second aspect of this application provides a low-memory decoding device for dual-binary Turbo codes based on damped a posteriori propagation, comprising: The channel log-likelihood ratio calculation module is used to receive the output sequence of the external information channel and calculate the channel log-likelihood ratio based on the output sequence of the external information channel. The assignment module is used to assign the channel log-likelihood ratio to the initial posterior log-likelihood ratio; The decoding module is used to iteratively perform decoding operations based on the first decoder and the second decoder until the maximum number of iterations is reached, and obtain the target posterior log-likelihood ratio. The output module is used to perform symbol and decision on the target posterior log-likelihood ratio and output the decoded bit sequence.

[0015] In one embodiment, the decoding module, specifically configured to perform the following operations during each iteration: Perform a deinterleaving operation on the historical posterior log-likelihood ratio output by the second decoder in the previous iteration to obtain the first input information after deinterleaving; Determine the first undamped posterior log-likelihood ratio based on the first input information; The updated posterior information is obtained based on the first input information and the undamped first posterior log-likelihood ratio. During each iteration, the second decoder performs the following operations: An interleaving operation is performed on the updated posterior information output by the first decoder to obtain the second input information; Determine the undamped second posterior log-likelihood ratio based on the second input information; The posterior log-likelihood ratio after this iteration is obtained based on the second input information and the undamped second posterior log-likelihood ratio. The above operation is repeated until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio. In the first round of iteration, the first decoder performs a deinterleaving operation based on the initial posterior log-likelihood ratio.

[0016] In one embodiment, the channel log-likelihood ratio calculation module is specifically used for: Determine the first soft information, the second soft information, and the information bit pairs in the output sequence of the external information channel; The channel log-likelihood ratio is calculated based on the first soft information, the second soft information, and the information bit pairs.

[0017] In one embodiment, the decoding module is specifically used for: The historical posterior log-likelihood ratio output by the second decoder in the previous iteration is recombined by the deinterleaver to obtain the first input information after deinterleaving.

[0018] In one embodiment, the decoding module is specifically used for: Based on the first branch metric formula, forward recursive calculation and backward recursive calculation are performed on the first input information and the first check bit soft information to obtain the undamped first posterior log-likelihood ratio. The first check bit soft information is obtained based on the first soft information.

[0019] In one embodiment, the decoding module is specifically used for: The updated post-hoc information output by the first decoder is reassembled by an interleaver to obtain the second input information.

[0020] In one embodiment, the decoding module is specifically used for: The second input information and the second check bit soft information are calculated based on the second branch metric formula to obtain the undamped second posterior log-likelihood ratio; The second check bit soft information is obtained based on the second soft information.

[0021] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the steps of the above-described low-memory decoding method for dual binary Turbo codes based on damped a posteriori propagation.

[0022] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described low-storage decoding method for dual binary Turbo codes based on damped a posteriori propagation.

[0023] A fifth aspect of this application provides a computer program product, including a computer program or computer executable instructions, wherein when the computer program or computer executable instructions are executed by a processor, the steps of the above-described low-memory decoding method for dual binary Turbo codes based on damped a posteriori propagation are implemented.

[0024] The beneficial effects of the low-storage decoding method, apparatus, electronic device, and storage medium based on damped posterior propagation of dual binary Turbo codes provided in this application are as follows: This application's embodiments transform traditional extrinsic information storage into the direct propagation of the posterior log-likelihood ratio, reducing the storage space required for independent extrinsic information and thus reducing the storage space occupied during decoding. Secondly, while reducing memory requirements, this application's embodiments, based on the core principle of dual-binary Turbo codes, calculate the channel log-likelihood ratio by receiving the extrinsic information channel output sequence, and use this as the initial posterior log-likelihood ratio. The first and second decoders iteratively execute the decoding operation until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio. Finally, the symbols and decisions are performed to output the decoded bit sequence, providing reliable data transmission error correction capabilities and ensuring the accuracy and stability of data transmission. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A flowchart illustrating a low-memory decoding method for dual binary Turbo codes based on damped posterior propagation, provided as an embodiment of this application; Figure 2 A system architecture diagram of a low-memory decoding system for dual binary Turbo codes based on damped a posteriori propagation provided in an embodiment of this application; Figure 3 A structural block diagram of a low-memory decoding device for dual binary Turbo codes based on damped a posteriori propagation provided in an embodiment of this application; Figure 4 This is a schematic block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0027] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.

[0029] Please refer to Figure 1 , Figure 1 The flowchart of a low-memory decoding method for dual binary Turbo codes based on damped a posteriori propagation provided in an embodiment of this application can be executed by an electronic device. The method may include: S101-S104.

[0030] S101: Receive the output sequence of the external information channel and calculate the channel log-likelihood ratio based on the output sequence of the external information channel.

[0031] In this embodiment, calculating the channel log-likelihood ratio based on the external information channel output sequence includes: Determine the first soft information, the second soft information, and the information bit pairs in the output sequence of the external information channel; The channel log-likelihood ratio is calculated based on the first soft information, the second soft information, and the information bit pairs.

[0032] In this embodiment, the channel log-likelihood ratio can be calculated based on the following formula: ,in, Time index representing symbol sequence ( N represents the last moment; Indicates time The received soft information (channel observations) corresponding to the system bits are the aforementioned first soft information and second soft information, respectively; Indicates time The transmitted information bit pairs correspond to the symbols Bit mapping, . The channel reliability factor is defined as follows: ,in This represents the average symbol energy of the signal. This represents the one-sided power spectral density of additive white Gaussian noise. The formula calculates the power spectral density of the transmitted symbol given the received signal. Relative to the transmitted symbol The channel log-likelihood ratio.

[0033] S102: Assign the channel log-likelihood ratio to the initial posterior log-likelihood ratio.

[0034] In this embodiment, since no prior information or extrinsic information has been generated in the initial stage of iteration (both are set to zero), according to the decomposition principle of the log-likelihood ratio, the channel log-likelihood ratio calculated by the above formula is directly assigned to the initial posterior log-likelihood ratio. In other words: This is because in the initial stage of iteration, both prior information and extrinsic information are zero, so the posterior information can be obtained directly numerically through the channel observation formula mentioned above.

[0035] S103: Based on the initial posterior log-likelihood ratio, the first decoder and the second decoder are iteratively executed to perform decoding operations until the maximum number of iterations is reached, and the target posterior log-likelihood ratio is obtained.

[0036] In this embodiment, reference Figure 2 Decoder 1 (the first decoder) and Decoder 2 (the second decoder) are the two core computational modules for Turbo code decoding, corresponding to the two component encoders of the dual-binary Turbo code (both are recursive systematic convolutional codes, RSC). They have symmetrical structures but different functions. After initializing the received sequence, they exchange information through an interleaver and a deinterleaver (deinterleaver) to finally obtain the decision sequence. The decoding process is not a one-time computation but a multi-round cyclic optimization. The two decoders process the data alternately, with each round based on the optimization results of the previous round, further improving the accuracy of the posterior log-likelihood ratio (LLR).

[0037] In this embodiment, the target posterior log-likelihood ratio is the final probability judgment index output after the maximum number of iterations, which can be used as input for subsequent decisions. In this embodiment, the maximum number of iterations can be 6.

[0038] S104: Perform symbol and decision on the target posterior log-likelihood ratio and output the decoded bit sequence.

[0039] In this embodiment, for a symbol of a double binary Turbo code, the true value of the symbol is determined based on the value of the target posterior LLR, and the decoded bit sequence is the final output original data form.

[0040] As can be seen from the above, the embodiments of this application transform traditional extrinsic information storage into the direct propagation of the posterior log-likelihood ratio, reducing the storage space of independent extrinsic information and thus reducing the storage space occupied during the decoding process. Secondly, while reducing memory requirements, the embodiments of this application, based on the core principle of dual binary Turbo codes, calculate the channel log-likelihood ratio by receiving the extrinsic information channel output sequence, and use this as the initial posterior log-likelihood ratio. The first decoder and the second decoder iteratively perform the decoding operation until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio. Finally, the symbols and decisions are performed to output the decoded bit sequence, providing reliable data transmission error correction capabilities and ensuring the accuracy and stability of data transmission.

[0041] In one embodiment of this application, a decoding operation is iteratively performed based on an initial posterior log-likelihood ratio, a first decoder, and a second decoder until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio, including: During each iteration, the first decoder performs the following operations: Perform a deinterleaving operation on the historical posterior log-likelihood ratio output by the second decoder in the previous iteration to obtain the first input information after deinterleaving; Determine the first undamped posterior log-likelihood ratio based on the first input information; The updated posterior information is obtained based on the first input information and the undamped first posterior log-likelihood ratio. During each iteration, the second decoder performs the following operations: An interleaving operation is performed on the updated posterior information output by the first decoder to obtain the second input information; Determine the undamped second posterior log-likelihood ratio based on the second input information; The posterior log-likelihood ratio after this iteration is obtained based on the second input information and the undamped second posterior log-likelihood ratio. The above operation is repeated until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio. In the first round of iteration, the first decoder performs a deinterleaving operation based on the initial posterior log-likelihood ratio.

[0042] In one embodiment, a deinterleaving operation is performed on the historical posterior log-likelihood ratio output by the second decoder in the previous iteration to obtain the deinterleaved first input information, including: The historical posterior log-likelihood ratio output by the second decoder in the previous iteration is recombined by the deinterleaver to obtain the first input information after deinterleaving.

[0043] In this embodiment, the first decoder uses the posterior log-likelihood ratio output by the second decoder in the previous iteration. via deinterleaver Reassembly, as the prior input information of the first decoder (This information is the posterior information output by the second decoder in the previous iteration): .

[0044] In one embodiment, determining the undamped first posterior log-likelihood ratio based on the first input information includes: Based on the first branch metric formula, forward recursive calculation and backward recursive calculation are performed on the first input information and the first check bit soft information to obtain the undamped first posterior log-likelihood ratio. The first check bit soft information is obtained based on the first soft information.

[0045] In this embodiment, the first branch metric formula can be a modified branch metric formula. In this embodiment, the deinterleaved input information is used. It is directly absorbed into the branch metric as prior information. In the calculation: ; in, Symbolic time index; For a moment The first check bit soft information; This is the check bit value (0 or 1) corresponding to the state transition. Combining forward and backward recursive calculations, the undamped first posterior log-likelihood ratio is obtained. .

[0046] In one embodiment, the updated posterior information is obtained based on the first input information and the undamped first posterior log-likelihood ratio, which can be achieved based on the following formula: ,in, To update posterior information, the damping factor .

[0047] In one embodiment, an interleaving operation is performed on the updated posterior information output by the first decoder to obtain second input information, including: The updated post-hoc information output by the first decoder is reassembled by an interleaver to obtain the second input information.

[0048] In this embodiment, it can be implemented in the following way: Update the posterior information output by the first decoder Through the interleaver Reassembly, as prior input information for the second decoder , .

[0049] In one embodiment, determining the undamped second posterior log-likelihood ratio based on the second input information includes: The second input information and the second check bit soft information are calculated based on the second branch metric formula to obtain the undamped second posterior log-likelihood ratio; The second check bit soft information is obtained based on the second soft information.

[0050] In this embodiment, a second branch metric formula, modified symmetrically to the first branch metric formula, is used, combined with a second check bit. Perform the calculation: The undamped second a posteriori LLR was calculated. .

[0051] In one embodiment, the posterior log-likelihood ratio after this iteration, based on the second input information and the undamped second posterior log-likelihood ratio, can be obtained using the following formula: .

[0052] In one embodiment, performing symbol and decision operations on the target posterior log-likelihood ratio and outputting a decoded bit sequence can be achieved based on the following formula: .

[0053] In one embodiment of this application, compared with the prior art, the embodiment of this application eliminates the traditional external information storage and transforms it into a posterior log-likelihood ratio. Direct propagation enables embedded transmission of external information, and the Turbo interleaver ensures information orthogonality through statistical independence. Besides a dedicated external information storage area, only the following two core storage partitions are retained: Partition A: Posterior probability storage area (Posterior RAM) with a capacity of 3N. Stores the continuously updated posterior log-likelihood ratio vector during iterative decoding. (Each symbol contains 3 LLR values). This region is multiplexed through timing control in the iterative computation of the first and second decoders, replacing the external information RAM and information bit RAM in the traditional scheme.

[0054] Partition B: Parity RAM (Parity Information Storage Area) Capacity: 2N. Stores fixed amounts of received parity bit channel soft information. and (Each symbol corresponds to 2 parity bits).

[0055] Total storage requirements: Partition A (3N) + Partition B (2N) = 5N. Compared to a traditional dual-binary Turbo decoder (which typically requires 7N of storage resources), this embodiment achieves approximately 29% storage resource savings.

[0056] Corresponding to the damped posterior propagation-based low-memory decoding method for dual binary Turbo codes in the above embodiment, Figure 2 This is a structural block diagram of a low-memory decoding device for dual-binary Turbo codes based on damped a posteriori propagation, provided as an embodiment of this application. For ease of explanation, only the parts relevant to the embodiment of this application are shown. References Figure 3 The low-storage decoding device 20 based on damped a posteriori propagation dual binary Turbo code includes: a channel log-likelihood ratio calculation module 21, an assignment module 22, a decoding module 23, and an output module 24.

[0057] Among them, the channel log-likelihood ratio calculation module 21 is used to receive the external information channel output sequence and calculate the channel log-likelihood ratio based on the external information channel output sequence; Assignment module 22 is used to assign the channel log-likelihood ratio to the initial posterior log-likelihood ratio; Decoding module 23 is used to iteratively perform decoding operations based on the first decoder and the second decoder until the maximum number of iterations is reached, and obtain the target posterior log-likelihood ratio; Output module 24 is used to perform symbol and decision on the target posterior log-likelihood ratio and output the decoded bit sequence.

[0058] In one embodiment, the decoding module 23 is specifically configured to perform the following operations during each iteration: Perform a deinterleaving operation on the historical posterior log-likelihood ratio output by the second decoder in the previous iteration to obtain the first input information after deinterleaving; Determine the first undamped posterior log-likelihood ratio based on the first input information; The updated posterior information is obtained based on the first input information and the undamped first posterior log-likelihood ratio. During each iteration, the second decoder performs the following operations: An interleaving operation is performed on the updated posterior information output by the first decoder to obtain the second input information; Determine the undamped second posterior log-likelihood ratio based on the second input information; The posterior log-likelihood ratio after this iteration is obtained based on the second input information and the undamped second posterior log-likelihood ratio. The above operation is repeated until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio. In the first round of iteration, the first decoder performs a deinterleaving operation based on the initial posterior log-likelihood ratio.

[0059] In one embodiment, the channel log-likelihood ratio calculation module 21 is specifically used for: Determine the first soft information, the second soft information, and the information bit pairs in the output sequence of the external information channel; The channel log-likelihood ratio is calculated based on the first soft information, the second soft information, and the information bit pairs.

[0060] In one embodiment, the decoding module 23 is specifically used for: The historical posterior log-likelihood ratio output by the second decoder in the previous iteration is recombined by the deinterleaver to obtain the first input information after deinterleaving.

[0061] In one embodiment, the decoding module 23 is specifically used for: Based on the first branch metric formula, forward recursive calculation and backward recursive calculation are performed on the first input information and the first check bit soft information to obtain the undamped first posterior log-likelihood ratio. The first check bit soft information is obtained based on the first soft information.

[0062] In one embodiment, the decoding module 23 is specifically used for: The updated post-hoc information output by the first decoder is reassembled by an interleaver to obtain the second input information.

[0063] In one embodiment, the decoding module 23 is specifically used for: The second input information and the second check bit soft information are calculated based on the second branch metric formula to obtain the undamped second posterior log-likelihood ratio; The second check bit soft information is obtained based on the second soft information.

[0064] See Figure 4 , Figure 4 This is a schematic block diagram of an electronic device provided according to an embodiment of this application. Figure 4 The electronic device 300 in this embodiment may include one or more processors 301, one or more input devices 302, one or more output devices 303, and one or more memories 304. The processors 301, input devices 302, output devices 303, and memories 304 communicate with each other via a communication bus 305. The memories 304 store computer programs, including program instructions. The processors 301 execute the program instructions stored in the memories 304. Specifically, the processors 301 are configured to invoke the program instructions to perform the functions of each module 4 in the aforementioned device embodiments, for example... Figure 3 The functions of the channel log-likelihood ratio calculation module 21, assignment module 22, decoding module 23, and output module 24 are described.

[0065] It should be understood that, in the embodiments of this application, the processor 301 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0066] Input device 302 may include a touchpad, a fingerprint sensor (for collecting the user's fingerprint information and fingerprint orientation information), a microphone, etc., and output device 303 may include a display (LCD, etc.), a speaker, etc.

[0067] The memory 304 may include read-only memory and random access memory, and provides instructions and data to the processor 301. A portion of the memory 304 may also include non-volatile random access memory. For example, the memory 304 may also store device type information.

[0068] In specific implementations, the processor 301, input device 302, and output device 303 described in the embodiments of this application can execute the implementation method described in the low-storage decoding method of dual binary Turbo codes based on damped a posteriori propagation provided in the embodiments of this application, or they can execute the implementation method of the electronic device described in the embodiments of this application, which will not be repeated here.

[0069] In another embodiment of this application, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program, which includes program instructions. When executed by a processor, the program instructions implement all or part of the processes in the methods described above. Alternatively, the computer program can instruct related hardware to complete the process. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include any entity or device capable of carrying computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0070] The computer-readable storage medium can be an internal storage unit of the electronic device in any of the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium can also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device. Furthermore, the computer-readable storage medium can include both internal and external storage units of the electronic device. The computer-readable storage medium is used to store computer programs and other programs and data required by the electronic device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0071] This application provides a computer program product, which includes computer-executable instructions or a computer program. The computer-executable instructions or the computer program are stored in a computer-readable storage medium. The processor of an electronic device reads the computer-executable instructions from the computer-readable storage medium and executes the computer-executable instructions, causing the electronic device to execute the low-storage decoding method of dual binary Turbo codes based on damped a posteriori propagation described in this application embodiment.

[0072] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0073] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the electronic devices and units described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0074] In the several embodiments provided in this application, it should be understood that the disclosed electronic devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces or units, or they may be electrical, mechanical, or other forms of connection.

[0075] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of this application, depending on actual needs.

[0076] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0077] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A low-memory decoding method for dual-binary Turbo codes based on damped a posteriori propagation, characterized in that, include: Receive the output sequence of the external information channel and calculate the channel log-likelihood ratio based on the output sequence of the external information channel; The channel log-likelihood ratio is assigned the initial posterior log-likelihood ratio; Based on the initial posterior log-likelihood ratio, the first decoder and the second decoder are iteratively executed to perform decoding operations until the maximum number of iterations is reached, and the target posterior log-likelihood ratio is obtained. Perform symbol and decision operations on the target posterior log-likelihood ratio and output the decoded bit sequence.

2. The low-memory decoding method for dual-binary Turbo codes based on damped a posteriori propagation as described in claim 1, characterized in that, The step of iteratively performing decoding operations based on the initial posterior log-likelihood ratio, the first decoder, and the second decoder until the maximum number of iterations is reached, to obtain the target posterior log-likelihood ratio, includes: During each iteration, the first decoder performs the following operations: Perform a deinterleaving operation on the historical posterior log-likelihood ratio output by the second decoder during the previous iteration to obtain the first input information after deinterleaving; Determine the first undamped posterior log-likelihood ratio based on the first input information; The updated posterior information is obtained based on the first input information and the undamped first posterior log-likelihood ratio. During each iteration, the second decoder performs the following operations: An interleaving operation is performed on the updated posterior information output by the first decoder to obtain the second input information; Determine the undamped second posterior log-likelihood ratio based on the second input information; The posterior log-likelihood ratio after this round of iteration is obtained based on the second input information and the undamped second posterior log-likelihood ratio. The above operation is repeated until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio. In the first iteration, the first decoder performs the deinterleaving operation based on the initial posterior log-likelihood ratio.

3. The low-memory decoding method for dual-binary Turbo codes based on damped a posteriori propagation as described in claim 2, characterized in that, The calculation of the channel log-likelihood ratio based on the external information channel output sequence includes: Determine the first soft information, the second soft information, and the information bit pair in the output sequence of the external information channel; The channel log-likelihood ratio is calculated based on the first soft information, the second soft information, and the information bit pairs.

4. The low-memory decoding method for dual-binary Turbo codes based on damped a posteriori propagation as described in claim 2, characterized in that, The step of performing a deinterleaving operation on the historical posterior log-likelihood ratio output by the second decoder in the previous iteration to obtain the first input information after deinterleaving includes: The historical posterior log-likelihood ratio output by the second decoder in the previous iteration is recombined by the deinterleaver to obtain the first input information after deinterleaving.

5. The low-memory decoding method for dual-binary Turbo codes based on damped a posteriori propagation as described in claim 3, characterized in that, Determining the undamped first posterior log-likelihood ratio based on the first input information includes: Based on the first branch metric formula, forward recursive calculation and backward recursive calculation are performed on the first input information and the first check bit soft information to obtain the undamped first posterior log-likelihood ratio. The first check bit soft information is obtained based on the first soft information.

6. The low-memory decoding method for dual-binary Turbo codes based on damped a posteriori propagation as described in claim 2, characterized in that, The step of performing an interleaving operation on the updated posterior information output by the first decoder to obtain the second input information includes: The updated post-hoc information output by the first decoder is reassembled by an interleaver to obtain the second input information.

7. The low-memory decoding method for dual binary Turbo codes based on damped a posteriori propagation as described in claim 3, characterized in that, Determining the undamped second posterior log-likelihood ratio based on the second input information includes: The second input information and the second check bit soft information are calculated based on the second branch metric formula to obtain the undamped second posterior log-likelihood ratio; The second check bit soft information is obtained based on the second soft information.

8. A low-memory decoding device based on damped a posteriori propagation dual binary Turbo codes, characterized in that, include: The channel log-likelihood ratio calculation module is used to receive the external information channel output sequence and calculate the channel log-likelihood ratio based on the external information channel output sequence. The assignment module is used to assign the channel log-likelihood ratio to the initial posterior log-likelihood ratio; The decoding module is used to iteratively perform decoding operations based on the first decoder and the second decoder until the maximum number of iterations is reached, so as to obtain the target posterior log-likelihood ratio. The output module is used to perform symbol and decision on the target posterior log-likelihood ratio and output the decoded bit sequence.

9. The low-memory decoding device for dual binary Turbo codes based on damped a posteriori propagation as described in claim 8, characterized in that, The decoding module is specifically used so that, during each iteration, the first decoder performs the following operations: Perform a deinterleaving operation on the historical posterior log-likelihood ratio output by the second decoder during the previous iteration to obtain the first input information after deinterleaving; Determine the first undamped posterior log-likelihood ratio based on the first input information; The updated posterior information is obtained based on the first input information and the undamped first posterior log-likelihood ratio. During each iteration, the second decoder performs the following operations: An interleaving operation is performed on the updated posterior information output by the first decoder to obtain the second input information; Determine the undamped second posterior log-likelihood ratio based on the second input information; The posterior log-likelihood ratio after this round of iteration is obtained based on the second input information and the undamped second posterior log-likelihood ratio. The above operation is repeated until the maximum number of iterations is reached to obtain the target posterior log-likelihood ratio. In the first iteration, the first decoder performs the deinterleaving operation based on the initial posterior log-likelihood ratio.

10. The low-memory decoding device for dual binary Turbo codes based on damped a posteriori propagation as described in claim 9, characterized in that, The channel log-likelihood ratio calculation module is specifically used for: Determine the first soft information, the second soft information, and the information bit pair in the channel output sequence; The channel log-likelihood ratio is calculated based on the first soft information, the second soft information, and the information bit pairs.

11. The low-memory decoding device for dual binary Turbo codes based on damped a posteriori propagation as described in claim 9, characterized in that, The decoding module is specifically used for: The historical posterior log-likelihood ratio output by the second decoder in the previous iteration is recombined by the deinterleaver to obtain the first input information after deinterleaving.

12. The low-memory decoding device for dual binary Turbo codes based on damped a posteriori propagation as described in claim 10, characterized in that, The decoding module is specifically used for: Based on the first branch metric formula, forward recursive calculation and backward recursive calculation are performed on the first input information and the first check bit soft information to obtain the undamped first posterior log-likelihood ratio. The first check bit soft information is obtained based on the first soft information.

13. The low-memory decoding device for dual binary Turbo codes based on damped a posteriori propagation as described in claim 9, characterized in that, The decoding module is specifically used for: The updated post-hoc information output by the first decoder is reassembled by an interleaver to obtain the second input information.

14. The low-memory decoding device for dual binary Turbo codes based on damped a posteriori propagation as described in claim 10, characterized in that, The decoding module is specifically used for: The second input information and the second check bit soft information are calculated based on the second branch metric formula to obtain the undamped second posterior log-likelihood ratio; The second check bit soft information is obtained based on the second soft information.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

16. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

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