A communication gateway, signal demodulation method, and communication system

Abstract

This invention provides a communication gateway, a signal demodulation method, and a communication system. The communication gateway includes: a first communication module comprising a first microprocessor, used for demodulating analog input signals from field devices and transmitting the demodulated analog input signals to a main control module, and for modulating digital output signals and transmitting the modulated digital output signals to corresponding field devices; the main control module includes a second microprocessor, used for transmitting the demodulated analog input signals to a field switch via the second communication module, and for transmitting digital output signals to corresponding first communication modules; the main control module is connected to at least one first communication module, and each first communication module is connected to multiple field devices; this invention uses a first microprocessor to implement signal demodulation and signal modulation, replacing dedicated modulation and demodulation chips, increasing the types and total number of signals accessed by field devices, and reducing hardware costs.

Description

Technical Field

[0001] This invention relates to the field of industrial communication technology, and in particular to a communication gateway, a signal demodulation method, and a communication system. Background Technology

[0002] As Ethernet continues to achieve success across a wide range of fields, from enterprise networks to factory networks, control networks, and finally field networks, it continues to extend into the production field. Based on IEEE (Institute of Electrical and Electronics Engineers) and IEC (International Electrotechnical Commission) standards, relevant organizations have specifically developed the Ethernet-APL (Ethernet with an Advanced Physical Layer) standard for process automation. This provides two-wire Ethernet connections extending to the field, primarily used to connect field devices, such as sensors and actuators, to control networks. APL gateways with Ethernet-APL interfaces support Ethernet / IP (Industrial Ethernet), HART-IP (HART based on IP), OPC-UA (Open Platform Communications Unified Architecture), PROFINET (Process Fieldbus Ethernet), or any other higher-level automation protocols based on Ethernet. When Ethernet-APL is combined with HART-IP, an IP-based version of HART (Highway Addressable Remote Transducer), HART remains one of the main application protocols in new process automation technologies.

[0003] Field devices corresponding to APL refer to field devices with Ethernet-APL interfaces. HART-IP field devices are divided into three categories: wired HART, wireless HART, and Ethernet-APL devices. New Ethernet-APL devices can be directly connected to the corresponding APL field switch. Wireless HART devices can also be connected to and powered by the corresponding APL field switch through a wireless HART gateway; this is considered a new construction project. Replacing wired HART devices with new Ethernet-APL devices is too costly. However, in retrofit projects that connect a large number of wired HART devices in industrial fields to the Ethernet-APL network via Ethernet-APL gateways, the original wired HART-enabled field devices remain usable. The HART gateway in this technology is based on a microprocessor (CPU), a dedicated HART modem chip, and other circuit modules. It supports simultaneous connection of multiple HART devices, polling and scanning of multiple HART devices with different IDs on a single loop, and simultaneous parallel scanning of all HART channels. Therefore, each channel requires its own HART modem chip. After the HART modem acquires the communication data from the field devices, it outputs it to the CPU via a serial port. The CPU then outputs communication data in a specified format through a hardware module based on the Ethernet-APL physical layer. The more channels a HART gateway can connect to, the more HART modem chips are needed. However, these chips are expensive, making them unsuitable for large-scale wired HART connections. Summary of the Invention

[0004] This invention provides a communication gateway, a signal demodulation method, and a communication system to solve the technical problem that the aforementioned gateway is inconvenient to communicate with a large number of field devices.

[0005] The present invention provides a communication gateway, comprising: a first communication module, a main control module, and a second communication module; the first communication module includes a first microprocessor, configured to demodulate analog input signals from field devices and transmit the demodulated analog input signals to the main control module, and to modulate digital output signals and transmit the modulated digital output signals to corresponding field devices; the main control module includes a second microprocessor, configured to transmit the demodulated analog input signals through the second communication module to a field switch, and to transmit the digital output signals to the corresponding first communication module, wherein the digital output signals are generated by the second microprocessor or received from the second communication module; the main control module is connected to at least one first communication module, and each first communication module is connected to multiple field devices.

[0006] In one embodiment of the present invention, the first microprocessor includes: an analog-to-digital sampling unit, configured to digitally sample the analog signal to be sampled in the current sampling period to obtain a current sampling signal, wherein the analog signal to be sampled is obtained based on the analog input signal; a mixing unit, configured to provide two local oscillator signals and mix the current sampling signal with each of the local oscillator signals respectively to obtain a mixed real part signal and a mixed imaginary part signal, wherein the two local oscillator signals are orthogonal signals; a filtering unit, configured to filter out high-frequency components in the mixed real part signal and the mixed imaginary part signal to obtain a filtered real part signal and a filtered imaginary part signal in the current sampling period; and a demodulation determination unit, configured to cross-multiply the filtered real part signal and the filtered imaginary part signal in the current sampling period with the filtered real part signal and the filtered imaginary part signal in the previous sampling period to obtain two multiplication results, and determine the demodulated analog input signal based on the difference between the two multiplication results.

[0007] In one embodiment of the present invention, the first communication module further includes: a channel circuit for conditioning the analog input signal and conditioning the modulated digital output signal, wherein the analog signal to be sampled is the conditioned analog input signal, and there are multiple channel circuits, each of which is connected to at least one field device; a multiplexer switch for outputting the modulated digital output signal to the corresponding channel circuit; and the channel circuits are respectively connected to the multiplexer switch and the corresponding field device.

[0008] In one embodiment of the present invention, the channel circuit includes: a reference circuit for providing a reference voltage to boost the analog input signal to the voltage range corresponding to analog-to-digital sampling; an input conditioning circuit for filtering the analog input signal and superimposing the reference voltage to obtain a conditioned analog input signal, the input conditioning circuit including a bandpass filter circuit; and an output conditioning circuit including a capacitive coupling circuit and a passive filter circuit. The input conditioning circuit is connected to the field device, the reference circuit, and the analog-to-digital conversion interface in the first microprocessor, respectively. The output conditioning circuit is connected to the field device and the multiplexer, respectively. The multiplexer is also connected to the digital-to-analog conversion interface in the first microprocessor.

[0009] In one embodiment of the present invention, the first microprocessor and the second microprocessor transmit and receive serial data through a pair of pins, the serial data including the digital output signal and the analog input signal; a first pin for requesting transmission and a second pin for carrier detection output are configured between the first microprocessor and the second microprocessor, the first pin and the second pin being based on the pin functions corresponding to the modem chip.

[0010] This invention provides a signal demodulation method applied to a communication gateway. The communication gateway includes a first microprocessor. The signal demodulation method executed by the first microprocessor includes: acquiring a current sampling signal for the current sampling period, the current sampling signal being obtained by digital sampling of an analog signal to be sampled; providing two local oscillator signals and mixing the current sampling signal with each of the local oscillator signals to obtain a mixed real part signal and a mixed imaginary part signal, the two local oscillator signals being orthogonal signals; filtering out high-frequency components from the mixed real part signal and the mixed imaginary part signal to obtain a filtered real part signal and a filtered imaginary part signal for the current sampling period; cross-multiplying the filtered real part signal and the filtered imaginary part signal for the current sampling period with the filtered real part signal and the filtered imaginary part signal for the previous sampling period to obtain two multiplication results; determining a serial port signal based on the difference between the two multiplication results and outputting it.

[0011] In one embodiment of the present invention, before obtaining the current sampled signal of the current sampling period, the method further includes: determining the interrupt frequency of signal demodulation based on the digital sampling frequency, and setting a preset interrupt flag bit according to the interrupt frequency and the sub-process call frequency; if the value of the preset interrupt flag bit is a first flag value, then executing the local oscillator signal generation sub-process and the mixing sub-process; if the value of the preset interrupt flag bit is a second flag value, then executing the filtering sub-process, the demodulation determination sub-process and the serial port signal output sub-process.

[0012] In one embodiment of the present invention, after obtaining the current sampled signal of the current sampling period, the method further includes: storing the current sampled value in the current sampled signal into a filter loop array, wherein the filter loop array is used to cyclically store the current sampled value and multiple historical sampled values; performing mean filtering on the current sampled value based on a preset normalization factor, a preset offset, and the filter loop array to obtain a filtered sampled value, wherein the preset normalization factor is determined based on the array length of the filter loop array and a scaling ratio used to characterize the amplitude between analog and digital signals, and the preset offset is based on the filter loop array. The array length of the group and the correction factor used to characterize the zero-crossing offset between the analog signal and the digital signal are determined; the filtered sample value is output as the current sample value, or the filtered sample value is output as the current sample value, and the filtered sample value is detected to generate a corresponding prompt signal; wherein, the detection of the filtered sample value includes: performing amplitude fault detection on the filtered sample value according to a preset first amplitude threshold and a preset second amplitude threshold; and / or, performing symbol integrity detection on the filtered sample value based on a preset start threshold and a preset end threshold of the digital signal.

[0013] In one embodiment of the present invention, filtering out high-frequency components from the real and imaginary parts of the mixing signal to obtain the filtered real and imaginary parts of the current sampling period includes: alternately storing the real and imaginary sampled values ​​of the mixing signal and the mixing imaginary sampled values ​​of the mixing signal into a buffer array, and updating the current index corresponding to the sampled value to be stored; performing convolution operation from the current index of the buffer array until the end of the buffer array, wherein the convolution operation includes convolving the corresponding real sampled value of the mixing signal with preset filter coefficients and accumulating it to the real accumulator, and... The corresponding mixing imaginary part sample value is convolved with the preset filter coefficients and accumulated to the imaginary part accumulator; the convolution operation starts from the beginning of the buffer array and continues until the current index of the buffer array; if there is no floating-point unit, the real part accumulator and the imaginary part accumulator are scaled by fixed-point numbers to obtain the filtered real part sample value in the filtered real part signal and the filtered imaginary part sample value in the filtered imaginary part signal of the current sampling period; if there is a floating-point unit, the value of the real part accumulator is determined as the filtered real part sample value, and the value of the imaginary part accumulator is determined as the filtered imaginary part sample value.

[0014] The present invention provides a communication system, the communication system including a communication gateway as described in any of the above embodiments; or, a first microprocessor in the communication gateway for executing a signal demodulation method as described in any of the above embodiments.

[0015] The beneficial effects of the present invention are as follows: The communication gateway, signal demodulation method and communication system proposed in the present invention realize signal demodulation and signal modulation through the first microprocessor in the first communication module, which replaces the dedicated modulation and demodulation chip, increases the types and total number of signals accessed by field devices and reduces hardware costs. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram:

[0018] Figure 1 A schematic diagram of an exemplary system architecture provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of an exemplary system architecture provided in another embodiment of the present invention; Figure 3This is a schematic diagram of the system architecture of an Ethernet-APL gateway for HART instruments provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of the architecture of a first communication board provided in one embodiment of the present invention; Figure 5 This is a schematic diagram of the coherent demodulation process provided in one embodiment of the present invention; Figure 6 This is a flowchart illustrating a signal demodulation method provided in one embodiment of the present invention; Figure 7 This is a flowchart illustrating a coherent demodulation algorithm provided in one embodiment of the present invention; Figure 8 A flowchart illustrating the sampling data processing sub-process provided in one embodiment of the present invention; Figure 9 This is a flowchart illustrating a filtering sub-process provided in one embodiment of the present invention; Figure 10(a) is a schematic diagram of the carrier start detection result provided in an embodiment of the present invention; Figure 10(b) is a schematic diagram of carrier attenuation detection results provided in an embodiment of the present invention; Figure 10(c) is a schematic diagram of the carrier detection start result provided in an embodiment of the present invention; Figure 10(d) is a schematic diagram of the carrier detection end result provided in one embodiment of the present invention. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0020] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0022] Please see Figure 1 , Figure 1 This is a schematic diagram of an exemplary system architecture provided in an embodiment of the present invention. Figure 1 As shown, the communication architecture corresponding to the Ethernet-APL (Ethernet with an Advanced Physical Layer) protocol includes APL-compatible field devices, field switches, power switches, and the control system. The power switches can connect to the control system, such as controllers, engineering workstations, and equipment management systems, via industrial Ethernet. Multiple field switches can be connected to the power switches, thus converting Ethernet-APL to industrial Ethernet. Field switches can provide multiple ports for connecting field devices; for example, up to 50 ports. APL-compatible field devices refer to field devices with Ethernet-APL interfaces, supporting Ethernet / IP (Industrial Ethernet), HART-IP (HART based on IP), OPC-UA (Open Platform Communications Unified Architecture), PROFINET (Process Fieldbus Ethernet), or any other higher-level automation protocol based on Ethernet. HART (Highway Addressable Remote Transducer) is an open communication protocol for addressable high-speed channels of remote sensors. HART-IP field devices are divided into three categories: wired HART devices, wireless HART devices, and Ethernet-APL devices. Ethernet-APL devices can be directly connected to the field switch, while wireless HART devices need to be connected to the field switch through a wireless HART gateway. A large number of wired HART devices need to be connected to the field switch through an Ethernet-APL gateway. The communication gateway provided by this invention can be applied to Ethernet-APL gateways, thereby expanding the signal types and total number of connected field devices.

[0023] In one embodiment of the present invention, please refer to Figure 2 , Figure 2 This is a schematic diagram of an exemplary system architecture provided in another embodiment of the present invention. Figure 2 As shown, the system architecture includes field devices 210, a communication gateway 220, and a field switch 230. The communication gateway 220 includes a first communication module 221, a main control module 222, and a second communication module 223. The first communication module 221 includes a first microprocessor for demodulating the analog input signal from the field device 210 and transmitting the demodulated analog input signal to the main control module, as well as modulating the digital output signal and transmitting the modulated digital output signal to the corresponding field device. The main control module 222 includes a second microprocessor for transmitting the demodulated analog input signal to the field switch via the second communication module, and transmitting the digital output signal to the corresponding first communication module. The digital output signal is generated by the second microprocessor or received from the second communication module. The main control module is connected to at least one first communication module, and each first communication module is connected to multiple field devices.

[0024] In one embodiment of the present invention, the communication gateway further includes a power supply module for supplying power to the first communication module, the main control module, and the second communication module.

[0025] In one embodiment of the present invention, all the first communication modules, power supply modules, and second communication modules are designed as independent boards, connected to the main control board via slots. In this case, the first communication module is the first communication board, the power supply module is the power supply board, the second communication module is the second communication board, and the main control module is the main control board.

[0026] In one embodiment of the present invention, independent boards, such as the first communication board, the second communication board, the main control board, etc., are no different from circuit modules, such as the first communication module, the second communication module, the main control module, etc., except for pluggability, in terms of circuit function.

[0027] In one embodiment of the present invention, the first communication board is a HART communication board, the second communication board is an Ethernet-APL communication board, and the field device is a HART instrument.

[0028] In one embodiment of the present invention, the Ethernet-APL communication board uses the Ethernet-APL physical layer chip as its core and communicates with the second microprocessor (CPU) of the main control board through the MAC (Media Access Control Address) interface. It is responsible for transmitting the HART instrument data collected by the CPU of the main control board to the field switch through a cable such as 10BASE-T1L (10 Mbps single-pair twisted pair).

[0029] In one embodiment of the present invention, the digital output signal is obtained by the field switch forwarding the signal from the control system to the second communication module, or by the control signal generated by the main control module.

[0030] In one embodiment of the present invention, the first microprocessor and the second microprocessor transmit and receive serial data through a pair of pins. The serial data includes a digital output signal and a demodulated analog input signal. A first pin for requesting transmission and a second pin for carrier detection output are configured between the first microprocessor and the second microprocessor. The first pin and the second pin are functional pins corresponding to the modem chip.

[0031] In one embodiment of the present invention, the CPU of the main control board includes 12 pins for communicating with the first communication board. The pins are divided into 3 groups. The two pins in each group are the serial data transmission interface (Transmit, Tx) and the reception interface (Receive, Rx), respectively. The other two pins correspond to the RTS (Request to Send) pin and the OCD (Carrier Detect) output pin of the standard HART modem chip, thereby interacting with each first communication board to collect data from the field device. At this time, each main control board can insert up to 3 first communication boards.

[0032] In one embodiment of the present invention, if the CPU chip of the main control board has a built-in MAC kernel, it can be connected to the physical layer chip of the second communication board through the MAC interface, and the data of the field device collected can be encapsulated in HART IP format and transmitted to the field switch.

[0033] In one embodiment of the present invention, please refer to Figure 3 , Figure 3 This is a schematic diagram of the system architecture of an Ethernet-APL gateway for HART instruments provided in one embodiment of the present invention. Figure 3 As shown, within the Ethernet-APL gateway, the main control board communicates with the HART communication board via GPIO (General-Purpose Input / Output) and with the Ethernet-APL communication board via the MAC interface; the three HART communication boards can communicate with four-wire field devices (two power lines and two signal lines) or two-wire field instruments (signals superimposed on the power lines); the power board is connected to the main control board, and the Ethernet-APL communication board communicates with the field switch via 10BASE-T1L.

[0034] In one embodiment of the present invention, the first communication module further includes: a channel circuit for conditioning an analog input signal and conditioning a modulated digital output signal, wherein the analog signal to be sampled is a conditioned analog input signal, and there are multiple channel circuits, each channel circuit being connected to at least one field device; a multiplexer switch for outputting the modulated digital output signal to the corresponding channel circuit; and the channel circuits being connected to the multiplexer switch and the corresponding field device, respectively.

[0035] In one embodiment of the present invention, during the signal demodulation process, after the analog input signal is conditioned by the channel circuit, it is acquired by the ADC (Analog-to-Digital Converter) inside the first microprocessor (CPU) of the first communication board, calculated by the software signal demodulation algorithm, and the result is sent to the CPU of the main control board through OCD and RX.

[0036] In one embodiment of the present invention, during signal modulation, the CPU of the main control board sends the digital output signal to be modulated and transmitted to the CPU of the first channel board via RTS and TX. After software modulation algorithm, the modulated result is output through DAC and output conditioning circuit. Furthermore, because multiple channel circuits share a single DAC channel, the CPU of the first communication board needs to control the multiplexer switch to determine which DAC channel outputs to the corresponding channel circuit.

[0037] In one embodiment of the present invention, the channel circuit includes: a reference circuit for providing a reference voltage to boost the analog input signal to the voltage range corresponding to analog-to-digital sampling; an input conditioning circuit for filtering the analog input signal and superimposing the reference voltage to obtain a conditioned analog input signal, the input conditioning circuit including a bandpass filter circuit; and an output conditioning circuit including a capacitive coupling circuit and a passive filter circuit. The input conditioning circuit is connected to the field device, the reference circuit, and the analog-to-digital conversion interface in the first microprocessor, respectively. The output conditioning circuit is connected to the field device and a multiplexer switch, and the multiplexer switch is also connected to the digital-to-analog conversion interface in the first microprocessor.

[0038] In one embodiment of the present invention, the CPU chip of the first communication board is selected to have three 12-bit ADC channels and two 12-bit DAC channels (Digital-to-Analog Converter). The three ADC channels can be sampled synchronously and independently, responsible for receiving the analog input signals corresponding to the field devices, while only one DAC channel, in conjunction with a multiplexer, is used to transmit the digital output signals. Therefore, each first communication board has three channel circuits. For four-wire field devices, it supports polling and scanning of multiple field devices with different IDs on each channel, where only one device has a 4-20mA signal; for two-wire field devices, each channel can only connect to one field device.

[0039] In one embodiment of the present invention, the reference circuit can provide a relatively stable reference voltage, such as 1.2V (volts), for analog input signals, such as HART signals, thereby boosting the analog input signals (such as -0.5V to 0.5V) to a voltage range (such as 0.1V to 1.1V) that is convenient for internal ADC sampling. Since it is not used for precise measurement, the requirements for accuracy and other performance are not high. Considering low power consumption and low cost, the core of the reference circuit can be a parallel voltage reference chip.

[0040] In one embodiment of the present invention, the frequency of HART communication is relatively low and not sensitive to noise. The input conditioning circuit can be a bandpass filter circuit composed of passive components. The bandpass filter circuit is composed of a low-pass filter with a cutoff frequency of 10615Hz and a high-pass filter with a cutoff frequency of 884.6Hz cascaded to filter the analog input signal. The DC voltage bias obtained after voltage division of the reference voltage is superimposed on the filtered signal and used as the input of the internal ADC for sampling, which is the conditioned analog input signal.

[0041] In one embodiment of the present invention, since the modulated digital output signal is directly output by the DAC, the amplitude of the signal can be precisely controlled, the noise is low and the waveform is relatively ideal. Therefore, the output conditioning circuit is simple and can be directly coupled into the loop by a capacitor, and then directly output through a passive filter circuit composed of RC (resistors and capacitors).

[0042] In one embodiment of the present invention, the first microprocessor includes: an analog-to-digital sampling unit, configured to digitally sample the analog signal to be sampled in the current sampling period to obtain a current sampling signal, wherein the analog signal to be sampled is obtained based on an analog input signal; a mixing unit, configured to provide two local oscillator signals and mix the current sampling signal with each local oscillator signal to obtain a mixed real part signal and a mixed imaginary part signal, wherein the two local oscillator signals are orthogonal signals; a filtering unit, configured to filter out high-frequency components in the mixed real part signal and the mixed imaginary part signal to obtain a filtered real part signal and a filtered imaginary part signal in the current sampling period; and a demodulation determination unit, configured to cross-multiply the filtered real part signal and the filtered imaginary part signal in the current sampling period with the filtered real part signal and the filtered imaginary part signal in the previous sampling period to obtain two multiplication results, and determine the demodulated analog input signal based on the difference between the two multiplication results.

[0043] In one embodiment of the present invention, in order to reduce communication latency, the demodulation algorithm needs to use coherent demodulation. Although the CPU of the first communication board has a built-in hardware serial port, the hardware serial port driver sends and receives data in the form of data frames and cannot control every bit of the data stream. Therefore, the demodulated analog input signal is sent to the CPU of the main control board through the GPIO pin in conjunction with the software program.

[0044] In one embodiment of the present invention, please refer to Figure 4 , Figure 4 This is a schematic diagram of the architecture of a first communication board provided in one embodiment of the present invention. Figure 4 As shown, each first communication board includes three channel circuits. Each channel circuit, such as HART channel 1, consists of a reference circuit, an input conditioning circuit, and an output conditioning circuit. The input conditioning circuit of each channel circuit is connected to the corresponding ADC interface; for example, the first input conditioning circuit is connected to the ADC1 interface, and the second input conditioning circuit is connected to the ADC2 interface. The output conditioning circuit of each channel circuit is connected to a multiplexer switch. The multiplexer switch is connected to the DAC interface of the CPU. The CPU in the first communication board and the CPU of the main control board transmit the demodulated analog input signal through OCD and RX, and transmit the digital output signal through RTS and TX.

[0045] In one embodiment of the present invention, a low-cost communication gateway for a large number of field devices is provided. As a general-purpose device, the microprocessor, after years of development, integrates analog peripherals such as ADCs and DACs, and, together with timers and GPIOs, can realize a complete minimum system, improving the cost-effectiveness of the communication gateway.

[0046] In one embodiment of the present invention, two common modulation methods for digital output signals are frequency selection and direct digital synthesis (DDS). Frequency selection involves a switching switch (implemented using a timer in software modulation) controlling two independent oscillators (implemented by changing the setting of another timer in software modulation) under the control of the baseband signal to generate carrier signals of different frequencies, controlled by the baseband signal. DDS uses a fixed-frequency precision clock source as a reference. The reference clock frequency is divided downwards by a specified scaling factor in a binary phase accumulator. The truncated output of the phase accumulator serves as the sine (or cosine) lookup table address, mapping the phase information to a sine amplitude. Because DDS uses only one timer, this invention chooses DDS to modulate the signal to save resources.

[0047] Among related technologies, the most commonly used software demodulation algorithm is the zero-crossing detection method, which is simple to implement but has a large latency. This invention utilizes coherent demodulation to demodulate analog input signals.

[0048] In one embodiment of the present invention, please refer to Figure 5 , Figure 5 This is a schematic diagram of a coherent demodulation process provided in one embodiment of the present invention. Figure 5 As shown, coherent demodulation uses two signals (LO1, LO2) with the same frequency and orthogonal phase as the local oscillator (LO). The analog input signal and the LO signal are mixed by a multiplier to generate a mixed signal. The output of the multiplier consists of two parts: a low-frequency signal, the difference between the original signal frequency and the local oscillator frequency (i.e., the baseband signal), and a high-frequency signal, the sum of their frequencies (i.e., the high-frequency component). To shift the signal frequency range to a suitable low-frequency range for processing, this invention selects the LO signal frequency as an intermediate frequency (IF) signal, such as 1700 Hz. After the mixed signal passes through a low-pass filter (LPF), the parameters of the two LPFs are the same, retaining only the baseband signal. The rate of change of the phase difference between two adjacent sampling points characterizes the change in the analog input signal. To avoid directly calculating the arctangent function, this invention uses an adder to calculate the difference term of the two signals to recover the original signal.

[0049] Please see Figure 6 , Figure 6 This is a flowchart illustrating a signal demodulation method provided in one embodiment of the present invention. Figure 6 As shown, in an exemplary embodiment, the signal demodulation method includes at least steps S610 to S640, and is applied to a communication gateway. The communication gateway includes a first microprocessor, and the signal demodulation method executed by the first microprocessor is described in detail below: Step S610: Obtain the current sampling signal of the current sampling period. The current sampling signal is obtained by digitally sampling the analog signal to be sampled.

[0050] In one embodiment of the present invention, before obtaining the current sampled signal of the current sampling period, the method further includes: determining the interrupt frequency of signal demodulation based on the digital sampling frequency, and setting a preset interrupt flag bit according to the interrupt frequency and the sub-process call frequency; if the value of the preset interrupt flag bit is a first flag value, then the local oscillator signal generation sub-process and the mixing sub-process are executed; if the value of the preset interrupt flag bit is a second flag value, then the filtering sub-process, the demodulation determination sub-process and the serial port signal output sub-process are executed.

[0051] In one embodiment of the present invention, the calling method of each sub-process within each interrupt cycle is set based on the interrupt frequency and the sub-process calling frequency.

[0052] In one embodiment of the present invention, the signal demodulation process of the present invention includes a sampling data processing sub-process, a local oscillator signal generation sub-process, a mixing sub-process, a filtering sub-process, a demodulation determination sub-process, and a serial port signal output sub-process.

[0053] In one embodiment of the present invention, a sampling data processing sub-process is used to perform moving average filtering on the current sampled signal. A local oscillator signal generation sub-process is used to provide two local oscillator signals. A mixing sub-process is used to mix the current sampled signal with each of the local oscillator signals respectively. A filtering sub-process filters out high-frequency components from the real and imaginary parts of the mixed signal. A demodulation determination sub-process is used to cross-multiply the filtered real and imaginary parts of the current sampling period with the filtered real and imaginary parts of the previous sampling period to obtain two multiplication results, and determine the serial port signal based on the difference between the two multiplication results. A serial port signal output sub-process is used to output the serial port signal to the second microprocessor of the main control board.

[0054] In one embodiment of the present invention, the interrupt frequency of signal demodulation is the same as the frequency of the sampling data processing sub-process, such as 19.2 kHz (kilohertz), and the call frequency of other sub-processes is the same, which is half of the interrupt frequency, such as 9.6 kHz. In order to shorten the computational load of each interrupt cycle and match the call cycle of each sub-process, the entire signal demodulation algorithm is executed in two calls, and the signal demodulation is divided into two parts by a preset interrupt flag (rx_cycle_counter) to meet the requirements.

[0055] In one embodiment of the present invention, the first flag value and the second flag value are bitwise inverses of each other, such as the first flag value being 0xaa (10101010) and the second flag value being 0x55 (01010101).

[0056] In one embodiment of the present invention, please refer to Figure 7 , Figure 7 This is a flowchart illustrating a coherent demodulation algorithm provided in one embodiment of the present invention. Figure 7 As shown, within each interrupt cycle, the coherent demodulation algorithm is called; sampled data processing: mean filtering is performed on the current sampled signal; rx_cycle_counter: obtain the value of the preset interrupt flag; Case 0xaa: if the value of the preset interrupt flag is 0xaa, then the local oscillator signal generation sub-process and the mixing sub-process are entered sequentially, and the sub-process is broken; if the value of the preset interrupt flag is 0x55, then the sub-process is entered sequentially and the sub-process is broken; if neither the preset interrupt flag is 0xaa nor 0x55, then the default situation is entered for fault handling.

[0057] In one embodiment of the present invention, after obtaining the current sampling signal of the current sampling period, the method further includes: storing the current sampling value in the current sampling signal into a filter loop array, wherein the filter loop array is used to cyclically store the current sampling value and multiple historical sampling values; performing mean filtering on the current sampling value based on a preset normalization factor, a preset offset, and the filter loop array to obtain a filtered sampling value, wherein the preset normalization factor is determined based on the array length of the filter loop array and a scaling ratio used to characterize the amplitude between the analog signal and the digital signal, and the preset offset is determined based on the array length of the filter loop array and a correction factor used to characterize the zero-crossing offset between the analog signal and the digital signal; outputting the filtered sampling value as the current sampling value, or, outputting the filtered sampling value as the current sampling value, and detecting the filtered sampling value to generate a corresponding prompt signal; wherein, detecting the filtered sampling value includes: performing amplitude fault detection on the filtered sampling value according to a preset first amplitude threshold and a preset second amplitude threshold; and / or, performing symbol integrity detection on the filtered sampling value based on a preset start threshold and a preset end threshold of the digital signal.

[0058] In one embodiment of the present invention, in order to increase the accuracy of signal demodulation, the current sampled value is subjected to moving mean filtering before demodulation.

[0059] In one embodiment of the present invention, the current sampled value obtained after ADC sampling is stored in the filter loop array (Filter_param).

[0060] In one embodiment of the present invention, the filter window length is determined based on the array length of the filter loop array. For example, if the array length is 4, then the filter window length is 4.

[0061] In one embodiment of the present invention, a scaling factor on the amplitude and a correction factor on the zero-crossing offset are determined based on the amplitudes of the digital signal and the analog signal. For example, the scaling factor is 1.5 and the offset factor is 650. In this case, the preset normalization factor, i.e., the divisor of the filter, is 6 = 1.5 × 4; the preset offset is 2600 = 650 × 4. For example, if the ADC acquires a sine wave input signal with an amplitude of 0.3V and an offset of 0.75V, the digital value after mean filtering will be between 18 and 238. At this time, the baud rate of the serial port signal exactly meets the HART specification requirements, and bit synchronization is no longer required.

[0062] In one embodiment of the present invention, an initial total sample value is obtained based on an initial sample value and the sum of multiple historical sample values; an actual total sample value is determined based on the difference between the initial total sample value and a preset offset; and a filtered sample value is determined based on the quotient of the actual total sample value and a preset normalization factor. In one embodiment of the present invention, amplitude fault detection is performed on the filtered sampled value according to a preset first amplitude threshold and a preset second amplitude threshold, including: if the filtered sampled value is greater than the preset first amplitude threshold, or the filtered sampled value is less than the preset second amplitude threshold, then a fault detection flag is accumulated to generate a fault indication signal; if the filtered sampled value is less than or equal to the preset first amplitude threshold and the filtered sampled value is greater than or equal to the preset second amplitude threshold, then the fault detection flag is cleared.

[0063] In one embodiment of the present invention, a first amplitude threshold is preset to characterize the maximum signal amplitude, and a second amplitude threshold is preset to characterize the DC bias.

[0064] In one embodiment of the present invention, a fault detection flag (ADCFault) is set in the sampling data processing sub-process. Because the sine wave signal sampled by the ADC should always have a fixed amplitude DC bias under normal circumstances, if the filtered sample value output after mean filtering is less than 0, the fault detection flag starts to accumulate; if the filtered sample value output after mean filtering is greater than 255, the input signal amplitude exceeds the limit, and the fault detection flag starts to accumulate.

[0065] In one embodiment of the present invention, a symbol integrity detection is performed on the filtered sampled value based on a preset start threshold and a preset end threshold of the digital signal, including: the digital signal is a sinusoidal signal; if the filtered sampled value is greater than the preset start threshold of the sinusoidal signal and less than the preset end threshold of the sinusoidal signal, then a sampling count flag is incremented to generate a complete symbol prompt signal; if the filtered sampled value is less than or equal to the preset start threshold of the sinusoidal signal, or the filtered sampled value is greater than or equal to the preset end threshold of the sinusoidal signal, then the sampling count flag is cleared; if the value of the sampling count flag is greater than the preset end determination threshold, then the value of the sampling count flag is updated to the preset end determination threshold.

[0066] In one embodiment of the present invention, in order to provide the OCD signal in a timely and accurate manner, the output of the mean filter, the Test variable, that is, the filtered sample value, is also used to determine the start and end of the sine wave signal. For example, the digital values ​​98 and 158 correspond to the amplitude of the sine wave signal ±25mV, that is, timing starts when it is greater than 25mV or less than -25mV. Since the call frequency of the entire signal demodulation is 19.2kHz, the preset end judgment threshold can be set to 22, which can ensure that during the demodulation process, when the sine wave signal ends, the serial port output can completely output the last symbol.

[0067] In one embodiment of the present invention, amplitude fault detection is performed on the filtered sampled value according to a preset first amplitude threshold and a preset second amplitude threshold, including: if the filtered sampled value is greater than the preset first amplitude threshold, or the filtered sampled value is less than the preset second amplitude threshold, then a fault detection flag is incremented to generate a fault indication signal; if the filtered sampled value is less than or equal to the preset first amplitude threshold and the filtered sampled value is greater than or equal to the preset second amplitude threshold, then the fault detection flag is cleared; if the filtered sampled value is greater than a preset start threshold of the sine wave signal and the filtered sampled value is less than a preset end threshold of the sine wave signal, then an increment is added. The sampling count flag is used to generate a complete symbol prompt signal. If the filtered sample value is less than or equal to the preset start threshold of the sine wave signal, or greater than or equal to the preset end threshold of the sine wave signal, the sampling count flag is cleared and the filtered sample value is returned as the current sample value. If the value of the sampling count flag is greater than the preset end threshold, the value of the sampling count flag is updated to the preset end threshold and the filtered sample value is returned as the current sample value. If the value of the sampling count flag is less than or equal to the preset end threshold, the filtered sample value is returned as the current sample value.

[0068] In one embodiment of the present invention, please refer to Figure 8 , Figure 8 A schematic flowchart of a sampling data processing sub-process provided in one embodiment of the present invention is shown. Figure 8As shown, when a new ADC sample value, i.e., the current sample value, is acquired, the oldest historical sample value in the filter loop array is removed, and the historical sample values ​​are shifted sequentially backward before storing the current sample value, achieving a first-in-first-out (FIFO) sampling value. The filtered sample value is calculated as: (current sample value + sum of multiple historical sample values ​​- preset offset) / preset normalization factor. If the filtered sample value is greater than 255 or less than 0, the fault detection flag (ADCFault) is incremented. If the filtered sample value is less than or equal to 255 and greater than or equal to 0, the fault detection flag (ADCFault) is cleared. If the filtered sample value is greater than 98 and less than 158, the sampling count flag (Testcnt) is incremented. If the filtered sample value is less than or equal to 98 or greater than or equal to 158, the sampling count flag (Testcnt) is cleared, and the filtered sample value is returned. If the sampling count flag is greater than 22, it is set to 22, and the filtered sample value is returned. If the sampling count flag is less than 22, the filtered sample value is returned.

[0069] Step S620: Provide two local oscillator signals, and mix the current sampled signal with each local oscillator signal to obtain the mixed real part signal and the mixed imaginary part signal. The two local oscillator signals are orthogonal signals.

[0070] In one embodiment of the present invention, the two local oscillator signals have the same frequency and amplitude, and a phase difference of π / 2. The frequency can be 1.7 kHz.

[0071] In one embodiment of the present invention, the mixing subprocess multiplies the current sampled signal returned by the sampling data processing subprocess with the local oscillator signal, and the output is also divided into two paths, one of which is the real part signal and the other is the imaginary part signal.

[0072] Step S630: Filter out the high-frequency components in the real and imaginary parts of the mixing signal to obtain the filtered real and imaginary parts of the current sampling period.

[0073] In one embodiment of the present invention, the filtering subprocess removes the high-frequency components after mixing, retains only the low-frequency components, and passes them to the demodulation determination subprocess.

[0074] In one embodiment of the present invention, filtering is performed using an LPF.

[0075] In one embodiment of the present invention, LPFs are divided into two types: FIR (Finite Impulse Response) and IIR (Infinite Impulse Response). The most significant characteristic of an FIR filter is that the system response is a finite-length sequence, and its output signal is essentially the convolution of the input signal and the parameter matrix, i.e., a combination of adders and multipliers with tapped delays, making it simple to implement. The present invention uses FIR, such as a sixth-order fully serial FIR, where the filter coefficients are quantized into signed 8-bit numbers. For example, the preset filter coefficients (fircoe) = [18, 54, 109, 127, 109, 54, 18].

[0076] In one embodiment of the present invention, filtering out high-frequency components from the real and imaginary parts of the mixing signal to obtain the filtered real and imaginary parts of the current sampling period includes: alternately storing the real and imaginary sampled values ​​of the mixing signal into a buffer array and updating the current index corresponding to the sampled value to be stored; performing a convolution operation starting from the current index of the buffer array until the end of the buffer array, wherein the convolution operation includes convolving the corresponding real sampled value of the mixing signal with preset filter coefficients and accumulating it to the real accumulator, and... The corresponding imaginary part sampled value of the mixer is convolved with the preset filter coefficients and accumulated to the imaginary part accumulator; the convolution operation starts from the beginning of the buffer array and continues until the current index of the buffer array; if there is no floating-point operation unit, the real part accumulator and the imaginary part accumulator are scaled by fixed-point numbers to obtain the filtered real part sampled value in the filtered real part signal and the filtered imaginary part sampled value in the filtered imaginary part signal of the current sampling period; if there is a floating-point operation unit, the value of the real part accumulator is determined as the filtered real part sampled value, and the value of the imaginary part accumulator is determined as the filtered imaginary part sampled value.

[0077] In one embodiment of the present invention, filtering out high-frequency components in the real and imaginary parts of the mixing signal to obtain the filtered real and imaginary parts of the current sampling period includes: obtaining the current index corresponding to the sampled value to be stored in the buffer array and assigning the current index to a local variable; alternately storing the real and imaginary sampled values ​​of the mixing signal into the buffer array based on the current index and accumulating the local variable; if the accumulated local variable is greater than or equal to the array length of the buffer array, then clearing the local variable; if the accumulated local variable is less than the array length of the buffer array, or if a local variable is cleared, then assigning the accumulated local variable or the cleared local variable to the current index, clearing the real accumulator and the imaginary accumulator, making the first temporary pointer point to the sampled value corresponding to the new current index assignment, making the second temporary pointer point to the preset filter coefficient, and assigning the new current index to the convolution indicator variable; if the convolution indicator variable is less than The length of the buffer array is then determined by performing convolution operations from the new current index and updating the convolution indicator variable. The convolution operation includes convolving the real part sample value of the mixer corresponding to the first temporary pointer with the preset filter coefficient corresponding to the second temporary pointer and accumulating it to the real part accumulator; convolving the imaginary part sample value of the mixer corresponding to the first temporary pointer with the preset filter coefficient corresponding to the second temporary pointer and accumulating it to the imaginary part accumulator. If the convolution indicator variable is greater than or equal to the length of the buffer array, or the accumulated convolution indicator variable is greater than or equal to the length of the buffer array, the convolution indicator variable or the accumulated convolution indicator variable is cleared to zero, and the first temporary pointer is set to the beginning position of the buffer array to perform convolution operations from the beginning position of the buffer array until the convolution operation before the new current index is completed. If all convolution operations are completed, the real part accumulator and the imaginary part accumulator are shifted right by eight bits and then right by one bit.

[0078] In one embodiment of the present invention, please refer to Figure 9 , Figure 9 This is a flowchart illustrating a filtering sub-process provided in one embodiment of the present invention. Figure 9 As shown, two identical FIR filters are required. The filtering sub-process manages the input sample values ​​through a circular queue and performs multiplication-accumulation operations and fixed-point scaling. The filtering sub-process includes sample value input and buffer maintenance, and two-stage convolution operation. Specifically, in the sample value input and buffer maintenance, it is responsible for receiving new sample values ​​and updating the pointer, ensuring that data exists in the circular array in a "first-in, first-out" manner. The specific steps include: parameter input: receiving the real part pointer (... Re), virtual pointer ( Im) and the current index (sampleIndex) of the buffer circular array (Samples) where the sampled value is to be stored. Re stores the real part of the signal. Im stores the imaginary part of the signal, and sampleIndex is the index of the two input signal arrays. Local variable initialization: assign sampleIndex to the local variable (idx). Store sampled values: store the real part sampled value Re of the mixing input into Samples[idx], then increment idx; store the imaginary part sampled value Im of the mixing input into Samples[idx], then increment idx again. Even indices in Samples store the real part of the mixing signal, and odd indices store the imaginary part of the mixing signal. Loop boundary check: check if idx has reached the upper limit of the buffer loop array, such as 14. If so, set idx to 0 to achieve loop coverage; otherwise, skip the reset. Update index and clear accumulator: write the updated idx back to sampleIndex, and simultaneously clear both accumulators, the real part accumulator (accRe) and the imaginary part accumulator (accIm), to prepare for subsequent calculations. By splitting the calculation into two sub-loops, the time-consuming modulo operation "i % 14" is avoided during the calculation process. Because the buffer is circular, the computation is split into two parts. The first stage of the convolution operation processes the data from the "current index" to the "end of the buffer": pointer positioning: setting the first temporary pointer ( p) points to Samples[idx], which is the oldest data or the starting position in the buffer; coefficient alignment: makes the second temporary pointer ( `coeff` points to the filter coefficient table (`fircoeff`). `idx` is assigned to the convolution indicator variable (`i`). If the condition `i < 14` is true, the convolution operation is performed: `accRe +=` p ( (++coeff) multiplies the real part sampled values ​​of the mixer with the coefficients and accumulates them to the real part accumulator, i.e., real part convolution operation. (++coeff) moves the second temporary pointer to the next filter coefficient; accIm += p ( (coeff) is used for the convolution operation to process the imaginary part sampling values of the mixing frequency. i is incremented by 2 to jump to the next pair of complex sampling points. When i reaches 14, the loop is exited, and the pointer variable p corresponding to the first temporary pointer is redirected to the starting address of Samples, so as to prepare for processing the first half of the data. The second-stage convolution process processes the data from "buffer start" to "before the current index" to complete the full convolution operation. The second loop (i < idx) repeats the same convolution operation logic as the first stage. Through these two loops, the program traverses the window with a length of 14 completely without judging the subscript overflow inside the loop, improving the execution efficiency. Since the CPU of the first communication board does not have a floating-point operation unit (FloatPoint Unit, FPU), in order to speed up the operation, the FIR parameters are quantized into 8-bit signed fixed-point numbers. Therefore, the real part accumulator accRe and the imaginary part accumulator accIm are first shifted 8 bits to the right and then 1 bit to the right for normalization processing (-128 to 127) to achieve fixed-point number scaling. Finally, the calculated real part result and imaginary part result are returned through the real part pointer Re and the imaginary part pointer Im.

[0079] In an embodiment of the present invention, after the ADC sampling values are subjected to moving average filtering, DC component removal, and normalization, they become a sine wave of digital quantities from -127 to 127.

[0080] Step S640: Cross-multiply the filtered real part signal and the filtered imaginary part signal of the current sampling period with the filtered real part signal and the filtered imaginary part signal of the previous sampling period to obtain two multiplication results, determine the serial port signal based on the gap between the two multiplication results, and output it.

[0081] In an embodiment of the present invention, cross-multiplying the filtered real part signal and the filtered imaginary part signal of the current sampling period with the filtered real part signal and the filtered imaginary part signal of the previous sampling period to obtain two multiplication results includes: multiplying the filtered real part signal of the current sampling period with the filtered imaginary part signal of the previous sampling period to obtain the first multiplication result; multiplying the filtered imaginary part signal of the current sampling period with the filtered real part signal of the previous sampling period to obtain the second multiplication result.

[0082] In an embodiment of the present invention, the serial port signal is obtained according to the difference term between the two multiplication results.

[0083] In an embodiment of the present invention, if the difference term is greater than zero, it is determined that the serial port signal is a high-level signal; if the difference term is less than zero, it is determined that the serial port signal is a low-level signal.

[0084] In an embodiment of the present invention, the serial port signal is the demodulated analog input signal.

[0085] In one embodiment of the present invention, the present invention replaces the HART modem chip with a microprocessor and implements HART signal reception based on a coherent demodulation algorithm, thereby designing a low-latency Ethernet-APL gateway for wired HART instruments at the lowest possible cost. Please refer to Figures 10(a) to 10(d). Figure 10(a) is a schematic diagram of the carrier start detection result provided in one embodiment of the present invention, Figure 10(b) is a schematic diagram of the carrier attenuation detection result provided in one embodiment of the present invention, Figure 10(c) is a schematic diagram of the carrier detection start result provided in one embodiment of the present invention, and Figure 10(d) is a schematic diagram of the carrier detection end result provided in one embodiment of the present invention. As shown in Figures 10(a) to 10(d), the carrier signal, i.e., the analog input signal, is displayed on the oscilloscope in cursor tracking mode (Cursor... The carrier signal and OCD signal are observed through channel 1 (C1), and the OCD signal is observed through channel 2 (C2) or channel 3 (C3). The observation time Δt is the time difference of the carrier signal between the two dashed lines, and y1 and y2 are the amplitudes of the carrier signal at the intersection of the dashed lines, respectively. In Figure 10(a), the carrier start time is 1.117 ms, which conforms to the HART specification. If it is less than 5 symbol times, it is 4.2 ms. In Figure 10(b), the carrier decay time is 90.66 μs. The carrier detection start time is 2.693ms, which meets the specification requirement of less than 6 symbol times, such as 5.0ms. Based on the observation conditions corresponding to Figure 10(b), the carrier stop time can also be measured as 29.34μs (not shown in the figure), which meets the specification requirement of less than 3 symbol times, such as 2.5ms. In Figure 10(c), the carrier detection start time is 2.693ms, which meets the specification requirement of less than 6 symbol times, such as 5.0ms. In Figure 10(d), the carrier detection end time is 776μs, which meets the specification requirement of less than 6 symbol times, such as 5.0ms.

[0086] Embodiments of the present invention also provide a communication system, the communication system including a communication gateway as provided in the various embodiments described above; or, a first microprocessor in the communication gateway for executing a signal demodulation method as provided in the various embodiments described above.

[0087] In the above embodiments, unless otherwise specified, the use of ordinal numbers such as "first" and "second" to describe common objects only indicates that they refer to different instances of the same object, rather than indicating that the objects being described must be in a given order, whether temporally, spatially, sequentially, or in any other way.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A communication gateway, characterized in that, The communication gateway includes: a first communication module, a main control module, and a second communication module; The first communication module includes a first microprocessor, used to demodulate the analog input signal of the field device and transmit the demodulated analog input signal to the main control module, and to modulate the digital output signal and transmit the modulated digital output signal to the corresponding field device; The main control module includes a second microprocessor, used to transmit the demodulated analog input signal to the field switch through the second communication module, and to transmit the digital output signal to the corresponding first communication module. The digital output signal is generated based on the second microprocessor or received from the second communication module. The main control module is connected to at least one first communication module, and each first communication module is connected to multiple field devices.

2. The communication gateway according to claim 1, characterized in that, The first microprocessor includes: The analog-to-digital sampling unit is used to digitally sample the analog signal to be sampled in the current sampling period to obtain the current sampled signal, wherein the analog signal to be sampled is obtained based on the analog input signal; A mixing unit is used to provide two local oscillator signals and mix the current sampled signal with each of the local oscillator signals to obtain a mixed real part signal and a mixed imaginary part signal, wherein the two local oscillator signals are orthogonal signals; A filtering unit is used to filter out high-frequency components in the real part signal and the imaginary part signal of the mixing, so as to obtain the filtered real part signal and the filtered imaginary part signal of the current sampling period. The demodulation determination unit is used to cross-multiply the filtered real part signal and the filtered imaginary part signal of the current sampling period with the filtered real part signal and the filtered imaginary part signal of the previous sampling period to obtain two multiplication results, and determine the demodulated analog input signal based on the difference between the two multiplication results.

3. The communication gateway according to claim 2, characterized in that, The first communication module further includes: The channel circuit is used to condition the analog input signal and the conditioned digital output signal. The analog signal to be sampled is the conditioned analog input signal. There are multiple channel circuits, and each channel circuit is connected to at least one field device. A multiplexer switch is used to output the modulated digital output signal to the corresponding channel circuit. The channel circuits are respectively connected to the multiplexer switch and the corresponding field devices.

4. The communication gateway according to claim 3, characterized in that, The channel circuit includes: A reference circuit is used to provide a reference voltage to boost the analog input signal to the voltage range corresponding to analog-to-digital sampling. An input conditioning circuit is used to filter the analog input signal and superimpose the reference voltage to obtain a conditioned analog input signal. The input conditioning circuit includes a bandpass filter circuit. The output conditioning circuit includes a capacitive coupling circuit and a passive filter circuit; The input conditioning circuit is connected to the field device, the reference circuit, and the analog-to-digital conversion interface in the first microprocessor, respectively. The output conditioning circuit is connected to the field device and the multiplexer, respectively. The multiplexer is also connected to the digital-to-analog conversion interface in the first microprocessor.

5. The communication gateway according to any one of claims 1-4, characterized in that, The first microprocessor and the second microprocessor communicate with each other via a pair of pins to transmit and receive serial data, which includes the digital output signal and the demodulated analog input signal. A first pin for request transmission and a second pin for carrier detection output are configured between the first microprocessor and the second microprocessor. The first pin and the second pin are obtained based on the pin functions of the corresponding modem chip.

6. A signal demodulation method, characterized in that, Applied to a communication gateway, the communication gateway includes a first microprocessor, and the signal demodulation method executed by the first microprocessor includes: Obtain the current sampling signal for the current sampling period, wherein the current sampling signal is obtained by digitally sampling the analog signal to be sampled; Two local oscillator signals are provided, and the current sampled signal is mixed with each of the local oscillator signals to obtain a mixed real part signal and a mixed imaginary part signal. The two local oscillator signals are orthogonal signals. High-frequency components are filtered out from the real and imaginary parts of the mixed signal to obtain the filtered real and imaginary parts of the current sampling period; The filtered real part and filtered imaginary part of the current sampling period are cross-multiplied with the filtered real part and filtered imaginary part of the previous sampling period to obtain two multiplication results. The serial port signal is determined based on the difference between the two multiplication results and then output.

7. The signal demodulation method according to claim 6, characterized in that, Before obtaining the current sampled signal for the current sampling period, the following steps are also included: The interrupt frequency for signal demodulation is determined based on the digital sampling frequency, and a preset interrupt flag is set according to the interrupt frequency and the sub-process call frequency. If the value of the preset interrupt flag is the first flag value, then the local oscillator signal generation sub-process and the mixing sub-process are executed. If the value of the preset interrupt flag is the second flag value, then the filtering sub-process, demodulation determination sub-process, and serial port signal output sub-process are executed.

8. The signal demodulation method according to any one of claims 6-7, characterized in that, After obtaining the current sampled signal for the current sampling period, the process also includes: The current sampled value in the current sampled signal is stored in a filter loop array, which is used to cyclically store the current sampled value and multiple historical sampled values. The current sampled value is mean-filtered based on a preset normalization factor, a preset offset, and the filter loop array to obtain a filtered sampled value. The preset normalization factor is determined based on the array length of the filter loop array and a scaling factor used to characterize the amplitude between the analog signal and the digital signal. The preset offset is determined based on the array length of the filter loop array and a correction factor used to characterize the zero-crossing offset between the analog signal and the digital signal. The filtered sampled value is output as the current sampled value, or the filtered sampled value is output as the current sampled value, and the filtered sampled value is detected to generate a corresponding prompt signal; The detection of the filtered sampled values ​​includes: Based on a preset first amplitude threshold and a preset second amplitude threshold, amplitude fault detection is performed on the filtered sampled values; and / or, Based on preset start and preset end thresholds of the digital signal, the filtered sample values ​​are subjected to symbol integrity detection.

9. The signal demodulation method according to any one of claims 6-7, characterized in that, Filtering out high-frequency components from the real and imaginary parts of the mixed signal to obtain the filtered real and imaginary parts of the current sampling period includes: The real part sample value of the mixed signal and the imaginary part sample value of the mixed signal are alternately stored into the buffer array, and the current index corresponding to the sample value to be stored is updated. The convolution operation starts from the current index of the buffer array and continues until the end of the buffer array. The convolution operation includes convolving the corresponding real part sample value of the mixer with the preset filter coefficients and accumulating it to the real part accumulator, and convolving the corresponding imaginary part sample value of the mixer with the preset filter coefficients and accumulating it to the imaginary part accumulator. The convolution operation begins at the beginning of the buffer array and continues until the current index of the buffer array. If there is no floating-point unit, the real part accumulator and the imaginary part accumulator are scaled by fixed-point numbers to obtain the filtered real part sampled value in the filtered real part signal of the current sampling period and the filtered imaginary part sampled value in the filtered imaginary part signal. If a floating-point unit exists, the value of the real part accumulator is determined as the filtered real part sample value, and the value of the imaginary part accumulator is determined as the filtered imaginary part sample value.

10. A communication system, characterized in that, The communication system includes a communication gateway as described in any one of claims 1-5; Alternatively, a first microprocessor in a communication gateway is configured to perform the signal demodulation method as described in any one of claims 6-9.

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