A BMS address allocation system and method

Abstract

This invention relates to the field of battery address allocation, and particularly to a BMS address allocation system and method. It includes an address allocation drive input circuit, an address allocation drive output circuit, and an address allocation status feedback circuit. The address allocation drive input circuit is connected to a second MCU; the address allocation drive output circuit is connected to the address allocation drive input circuit; the address allocation status feedback circuit is connected to the address allocation drive input circuit; the address allocation drive output circuit is connected to a first MCU; and the address allocation status feedback circuit is also connected to the first MCU. This system enables automatic address allocation for batteries and simultaneously identifies the master / slave status of the batteries, facilitating battery pack connection. It can accurately identify abnormalities caused by wiring harness contact during assembly, significantly reducing installation costs, improving installation efficiency, lowering installation difficulty, and enhancing the competitiveness and stability of address acquisition in BMS products.

Description

Technical Field

[0001] This invention relates to the field of battery address allocation, and in particular to a BMS address allocation system and method. Background Technology

[0002] With the widespread application of energy storage systems in scenarios such as power frequency regulation, peak shaving and valley filling, home energy storage, and backup power, the application scope of energy storage systems is constantly expanding. Currently, energy storage systems are mainly divided into high-voltage energy storage systems formed by multiple modules connected in series and low-voltage energy storage systems formed by multiple modules connected in parallel. An energy storage system consists of multiple battery modules, which need to transmit and report battery information. Different battery modules are identified by their addresses. In some application scenarios, more battery modules need to be connected in parallel to increase battery module capacity, and high-speed CAN communication is required between battery modules to transmit and report battery module information. If address assignment for each battery module is done manually during battery deployment and installation, the product installation is inflexible, requires a large investment of human resources, demands a certain level of expertise from installers, and has high assembly and maintenance costs. Summary of the Invention

[0003] The purpose of this invention is to solve the aforementioned problems by designing a current-mode driven transmitting circuit. To achieve the above objective, this invention provides the following solution: A BMS address allocation system includes an address allocation driver input circuit, an address allocation driver output circuit, and an address allocation status feedback circuit. The address allocation driver input circuit is connected to the second MCU; The address allocation driver output circuit is connected to the address allocation driver input circuit; The address allocation status feedback circuit is connected to the address allocation drive input circuit; The address allocation drive output circuit is connected to the first MCU; the address allocation status feedback circuit is connected to the first MCU.

[0004] As a further improvement to this technical solution, the first MCU and the second MCU are connected to a communication bus to receive the assigned address.

[0005] As a further improvement to this technical solution, each battery to be assigned an address is connected to a BMS, which includes an MCU, an address allocation drive input circuit, an address allocation drive output circuit, and an address allocation status feedback circuit.

[0006] As a further improvement to this technical solution, the address allocation drive input circuit is composed of an optocoupler U35, a resistor R324, a resistor R284, and a diode D13. The first input port DI1 of the address allocation drive input circuit is connected to the anode of the LED of the optocoupler U35; the second input port DI2 of the address allocation drive input circuit is connected to the cathode of the LED of the optocoupler U35. The DC power supply VDD is connected to one end of resistor R324, and the other end of resistor R324 is connected to the anode of diode D13. The cathode of diode D13 is connected to the positive terminal of the photoelectric sensor of optocoupler U35. One end of resistor R284 is connected to the anode of diode D13, and the other end of resistor R284 is connected to the output terminal DI_DET of the address allocation drive input circuit. The negative terminal of the photoelectric sensor of optocoupler U35 is grounded. The output terminal DI_DET of the address allocation driver input circuit is connected to the second MCU.

[0007] As a further improvement to this technical solution, the address allocation drive output circuit is composed of resistors R175 and R176 and optocoupler U21; the anode of the LED of optocoupler U21 is connected to the DC power supply VDD, and the cathode of the LED of optocoupler U21 is connected to the output terminal DO_CTR of the address allocation drive output circuit. The positive terminal of the photoelectric sensor of optocoupler U21 is connected to the power supply VDD, and the negative terminal of the photoelectric sensor of optocoupler U21 is connected to resistor R176. The other end of resistor R176 is connected to the output terminal DO1 of the address allocation drive output circuit. The output terminal DO_CTR of the address allocation driver output circuit is connected to the first MCU, and the output terminal DO1 of the address allocation driver output circuit is connected to the address allocation driver input circuit.

[0008] As a further improvement to this technical solution, the address allocation status feedback circuit is composed of resistors R177, R180, R181 and optocoupler U22. The power supply VDD is connected to one end of resistor R177, and the other end of resistor R177 is connected to the positive terminal of the photoelectric sensor of the optocoupler U22; the output terminal DO_DET of the address allocation status feedback circuit is connected to one end of resistor R180, and the other end of resistor R180 is connected to the positive terminal of the photoelectric sensor of the optocoupler U22; the negative terminal of the photoelectric sensor of the optocoupler U22 is grounded. The output terminal DO2 of the address allocation status feedback circuit is connected to one end of resistor R181, the other end of resistor R181 is connected to the anode of the LED of optocoupler U22, and the cathode of the LED of optocoupler U22 is grounded. The output terminal DO_DET of the address allocation status feedback circuit is connected to the first MCU, and the output terminal DO2 of the address allocation status feedback circuit is connected to the address allocation drive input circuit.

[0009] A BMS address allocation method includes the following steps: S1. Start the battery; The S2 and BMS MCU settings include the address allocation drive input circuit, address allocation drive output circuit, and address allocation status feedback circuit port signals; the master and slave devices are determined, and the last slave device is identified. S3. Set the host address to 0x00; S4. The host changes the output level of the address allocation driver output circuit DO_CTR and broadcasts the address; S5 and BMS obtain the broadcast address and reply to the host to complete the address acquisition; S6, Host stop broadcast address; S7. Repeat S4 to S6; S8. The master receives the last reply from the slave and closes the address allocation.

[0010] As a further improvement to this technical solution, the address of the (n+1)th battery is the address of the nth battery plus 1.

[0011] As a further improvement to this technical solution, the master and slave devices are determined, and the specific method for determining the last slave device is as follows: the BMS with the DI_DET port at a high level is the master device; the BMS with the DO_DET port at a high level is the last slave device. Attached Figure Description

[0012] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Figure 1 This is a schematic diagram of the structure of a BMS address allocation system according to the present invention; Figure 2 This is a schematic diagram of the address allocation drive input circuit structure of a BMS address allocation system according to the present invention; Figure 3 This is a schematic diagram of the address allocation drive output circuit structure of a BMS address allocation system according to the present invention; Figure 4 This is a schematic diagram of the address allocation status feedback circuit structure of a BMS address allocation system according to the present invention; Figure 5 This is a flowchart illustrating a BMS address allocation method according to the present invention. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0014] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” and “described” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0015] The present invention will now be described in detail with reference to the accompanying drawings. Example 1

[0016] like Figure 1 The figure shows a schematic diagram of a BMS address allocation system.

[0017] A battery module includes the battery's BMS system and the battery itself. The BMS system BMSi of battery module i is connected to battery i through an AFE module circuit. BMSi includes an AFE module circuit, a controller MCUi module, a communication module, an address allocation drive input circuit, an address allocation drive output circuit, and an address allocation status feedback circuit.

[0018] The DO_CTR port of the address allocation drive output circuit of MCUi module and battery module i is connected. The DO1 port of this address allocation drive output circuit is connected to the DI1 port of the address allocation drive input circuit of battery module i+1. The DI2 port of the address allocation drive input circuit of battery module i+1 is connected to the DO2 port of the address allocation status feedback circuit of battery module i. The DO_DET port of the address allocation status feedback circuit of battery module i is connected to the MCUi module of battery module n. The DI_DET port of the address allocation drive input circuit of battery module i is connected to MCUi. The DI1 port of the address allocation drive input circuit of battery module i is connected to the DO1 port of the address allocation drive output circuit of battery module i-1. The DI2 port of the address allocation drive input circuit of battery module i is connected to the DO2 port of the address allocation status feedback circuit of battery module i-1. The DI_DET port of the address allocation drive input circuit of battery module i+1 is connected to MCUi+1. The host is connected to the address allocation drive input circuit of battery module 1.

[0019] Each battery pack's MCU module is connected to the communication bus via its own communication module. The host computer interacts with each battery pack through the communication bus, which is an RS485 and CAN bus. The host computer broadcasts addresses to be assigned via the communication bus, and the battery pack to be assigned an address receives it and then replies to the host via the same communication bus. Example 2

[0020] like Figure 2 As shown, this is a schematic diagram of the address allocation drive input circuit structure of a BMS address allocation system.

[0021] The address allocation drive input circuit for battery module i+1 consists of optocoupler U35, resistor R324, resistor R284, and diode D13. The first input port DI1 of the address allocation drive input circuit is connected to the anode of the LED of optocoupler U35; the second input port DI2 of the address allocation drive input circuit is connected to the cathode of the LED of optocoupler U35.

[0022] The DC power supply VDD is connected to one end of resistor R324, and the other end of resistor R324 is connected to the anode of diode D13. The cathode of diode D13 is connected to the positive terminal of the photosensor in optocoupler U35. One end of resistor R284 is connected to the anode of diode D13, i.e., one end of resistor R284 is connected between the anode of diode D13 and resistor R324. The other end of resistor R284 is connected to the output terminal DI_DET of the address allocation drive input circuit. The negative terminal of the photosensor in optocoupler U35 is grounded.

[0023] The first input port DI1 of the address allocation driver input circuit is connected to the output port DO1 of the address allocation driver output circuit of battery module i. The second input port DI2 of the address allocation driver input circuit is connected to the output port DO2 of the address allocation status feedback circuit of battery module i. The output terminal DI_DET of the address allocation driver input circuit is connected to MCUi+1 of battery module i+1.

[0024] When there is a forward voltage difference between the anode and cathode of the LED in optocoupler U35, optocoupler U35 is turned on, and a current is generated from the positive to the negative terminal on the photoelectric sensor side of optocoupler U35. Otherwise, optocoupler U35 is turned off, and there is no current on the photoelectric sensor side of optocoupler U35. When there is no voltage difference between the first input port DI1 and the second input port DI2 of the address allocation drive input circuit, optocoupler U35 is turned off. At this time, since the cathode of diode D13 is at a high level, diode D13 is turned off, there is no current in resistor R324, and the output terminal DI_DET of the address allocation drive input circuit is at a high level. When there is a voltage difference between the first input port DI1 and the second input port DI2 of the address allocation drive input circuit, optocoupler U35 is turned on. The cathode of diode D13 is grounded through the photoelectric sensor of optocoupler U35, diode D13 is turned on, and the DC power supply VDD forms a loop through resistor R324, diode D13, and ground. No current flows through resistor R284, and DI_DET is at a low level. Example 3

[0025] like Figure 3 As shown, this is a schematic diagram of the address allocation drive output circuit structure of a BMS address allocation system.

[0026] The address allocation driver output circuit consists of resistors R175 and R176 and optocoupler U21; the anode of the LED of optocoupler U21 is connected to the DC power supply VDD, and the cathode of the LED of optocoupler U21 is connected to the output terminal DO_CTR of the address allocation driver output circuit. The positive terminal of the photoelectric sensor of optocoupler U21 is connected to the power supply VDD, and the negative terminal of the photoelectric sensor of optocoupler U21 is connected to resistor R176. The other end of resistor R176 is connected to the output terminal DO1 of the address allocation drive output circuit. The output terminal DO_CTR of the address allocation driver output circuit is connected to the MCUi of battery module i, and the output terminal DO1 of the address allocation driver output circuit is connected to the first input port DI1 of the address allocation driver input circuit of battery module i+1.

[0027] When the output terminal DO_CTR of the address allocation driver output circuit is low, the LED of optocoupler U21 is turned on, and the photoelectric sensor of optocoupler U21 is also turned on. If the output terminal DO1 of the address allocation driver output circuit is low at this time, the power supply VDD forms a path through the photoelectric sensor of optocoupler U21 to the output terminal DO1 of the address allocation driver output circuit, and current flows through resistor R176. Example 4

[0028] like Figure 4 The figure shows a schematic diagram of the address allocation status feedback circuit structure of a BMS address allocation system.

[0029] The address allocation status feedback circuit consists of resistors R177, R180, and R181, and optocoupler U22. The power supply VDD is connected to one end of resistor R177, and the other end of resistor R177 is connected to the positive terminal of the photoelectric sensor of optocoupler U22; the output terminal DO_DET of the address allocation status feedback circuit is connected to one end of resistor R180, and the other end of resistor R180 is connected to the positive terminal of the photoelectric sensor of optocoupler U22; the negative terminal of the photoelectric sensor of optocoupler U22 is grounded. The output terminal DO2 of the address allocation status feedback circuit is connected to one end of resistor R181, and the other end of resistor R181 is connected to the anode of the LED of optocoupler U22. The cathode of the LED of optocoupler U22 is grounded. The output terminal DO_DET of the address allocation status feedback circuit is connected to the MCUi of battery module i, and the output terminal DO2 of the address allocation status feedback circuit is connected to the second input port DI2 of the address allocation drive input circuit of battery module i+1.

[0030] When the output terminal DO2 of the address allocation status feedback circuit is low, the LED of optocoupler U22 is not conducting, the photoelectric sensor of optocoupler U22 is in the off state, no current flows through resistors R177 and R180, and the output terminal DO_DET of the address allocation status feedback circuit is high. When the output terminal DO2 of the address allocation status feedback circuit is high, the photoelectric sensor of optocoupler U22 is conducting, and the power supply VDD forms a path through resistor R177, the photoelectric sensor of optocoupler U22, and ground, and the output terminal DO_DET of the address allocation status feedback circuit is low. Example 5

[0031] like Figure 5 The diagram shows a flowchart of a BMS address allocation method.

[0032] After battery startup, the DO_CTR of the MCU control address allocation drive output circuit of all battery BMS is low. The 3.3V power supply of the previous battery pack is connected to the LED of optocoupler U21 through resistor R175. The low DO_CTR causes the LED of optocoupler U21 to light up, and the photoelectric sensor of optocoupler U21 is turned on. The 5V isolation voltage passes through the photoelectric sensor of optocoupler U21, and then through the current-limiting resistor R176 to the address allocation drive input circuit of the next battery pack connected to it. The optocoupler U35 of the address allocation drive input circuit of the next battery pack is turned on, and feeds back to the address allocation status feedback circuit of the previous battery pack through the DI2 port and the DO2 port of the previous battery pack, turning on the optocoupler U22 of the address allocation status feedback circuit of the previous battery pack. The high-level signal of DO_DET of the previous battery pack turns low due to the conduction of optocoupler U22. DI_DET turns low due to the conduction of optocoupler U35.

[0033] Because the DI1 and DI2 ports of the first battery pack are floating, the optocoupler U35 of the first battery pack is not conducting, so the DI_DET of the first battery pack is high. Because the optocoupler U22 of the last battery pack is not conducting, the DO_DET of the last battery pack is set to high. The MCU of the first battery pack identifies itself as the master battery pack by its DI_DET port being high, the MCUs of the other battery packs identify themselves as slave battery packs by their DI_DET ports being low, and the MCU of the last slave battery pack identifies itself as the last slave battery pack by its DO_DET port being high. The port states of the master battery pack and each slave battery pack at this time are shown in the table below:

[0034] After the system confirms the master battery pack and slave battery pack, the MCU of the master battery pack defines its own address as 0x00 and begins to allocate addresses to the slave battery pack.

[0035] The MCU of the master battery pack sets its own address allocation drive output circuit DO_CTR to a high level, and simultaneously broadcasts address 0x01 to all batteries via the communication bus. The address signal receiving circuit DI_DET of the slave battery pack, which is directly connected to the master DO1 and DO2 ports, goes high. The MCU of the slave battery pack acquires the bus broadcast address 0x01. At the same time, the slave battery pack detects its own DO_DET signal. If the signal is low, it replies to the master battery pack via the bus that it has completed address acquisition and will continue address allocation. If the signal is high, it replies to the master battery pack via the bus that it has completed address acquisition and stopped address allocation.

[0036] After receiving a reply from slave battery group 0x01, the master battery group sets its DO_CTR low and broadcasts address 0x02 to all batteries via the bus. Slave battery 0x01, upon receiving a low DI_DET signal, sets its own address allocation driver output circuit's DO_CTR high. The address signal receiving circuit of the slave battery group directly connected to slave battery 0x01's DO1 and DO2 outputs a high DI_DET signal. The MCU of this slave battery group acquires the address 0x02 broadcast on the communication bus and replies to the master via the bus. This process continues until address allocation is completed for all battery groups. After the last battery obtains an address, its DO_DET port goes high, and the MCU of this battery group replies to the master battery group via the bus, indicating that address acquisition is complete and address allocation has stopped.

[0037] The BMS continuously monitors DO_DET and DI_DET. When a new battery is connected after the Nth battery (the N+1th battery), the DO_DET of the Nth battery changes from high to low. The Nth battery replies to the host via the bus with the new battery connection information and its own address. Upon receiving this information, the host broadcasts an address allocation command again. The Nth battery, upon receiving the address allocation command, sets the DO_CTR of its address allocation driver output circuit to high. The DI_DET of the slave address signal receiving circuit of the new battery, which is directly connected to slave DO1 and DO2 at 0x0n, outputs high. This battery automatically acquires the address 0x0n+1 broadcast by the communication bus and feeds back the address acquisition status and whether to continue address allocation via the bus. The DO_DET port of the new (N+1th) battery itself is detected as high. The MCU of this battery pack replies to the host via the bus with information indicating that the battery pack has completed address acquisition and stopped address allocation. In summary, the BMS address allocation system and method proposed in this invention achieve automatic address allocation for batteries and simultaneously identify the master and slave status of batteries, facilitating battery pack connection. This solution integrates parallel operation status monitoring, enabling intelligent real-time identification of the connection and removal of parallel batteries, accurately identifying anomalies caused by wiring harness contact during assembly, significantly reducing installation costs, improving installation efficiency, lowering installation difficulty, and enhancing the competitiveness of BMS products and the stability of address acquisition.

Claims

1. A BMS address allocation system, characterized in that, Includes address allocation drive input circuit, address allocation drive output circuit, and address allocation status feedback circuit; The address allocation driver input circuit is connected to the second MCU; The address allocation driver output circuit is connected to the address allocation driver input circuit; The address allocation status feedback circuit is connected to the address allocation drive input circuit; The address allocation drive output circuit is connected to the first MCU; the address allocation status feedback circuit is connected to the first MCU.

2. The BMS address allocation system according to claim 1, characterized in that, The first MCU and the second MCU are connected to the communication bus and are used to receive the assigned address.

3. The BMS address allocation system according to claim 1, characterized in that, Each battery to be assigned an address is connected to a BMS, which includes an MCU, an address allocation drive input circuit, an address allocation drive output circuit, and an address allocation status feedback circuit.

4. A BMS address allocation system according to claim 1, characterized in that, The address allocation drive input circuit consists of an optocoupler U35, a resistor R324, a resistor R284, and a diode D13. The first input port DI1 of the address allocation drive input circuit is connected to the anode of the LED of the optocoupler U35; the second input port DI2 of the address allocation drive input circuit is connected to the cathode of the LED of the optocoupler U35. The DC power supply VDD is connected to one end of resistor R324, and the other end of resistor R324 is connected to the anode of diode D13. The cathode of diode D13 is connected to the positive terminal of the photoelectric sensor of optocoupler U35. One end of resistor R284 is connected to the anode of diode D13, and the other end of resistor R284 is connected to the output terminal DI_DET of the address allocation drive input circuit. The negative terminal of the photoelectric sensor of optocoupler U35 is grounded. The output terminal DI_DET of the address allocation driver input circuit is connected to the second MCU.

5. A BMS address allocation system according to claim 1, characterized in that, The address allocation drive output circuit consists of resistors R175 and R176 and an optocoupler U21; the anode of the LED of the optocoupler U21 is connected to the DC power supply VDD, and the cathode of the LED of the optocoupler U21 is connected to the output terminal DO_CTR of the address allocation drive output circuit. The positive terminal of the photoelectric sensor of optocoupler U21 is connected to the power supply VDD, and the negative terminal of the photoelectric sensor of optocoupler U21 is connected to resistor R176. The other end of resistor R176 is connected to the output terminal DO1 of the address allocation drive output circuit. The output terminal DO_CTR of the address allocation driver output circuit is connected to the first MCU, and the output terminal DO1 of the address allocation driver output circuit is connected to the address allocation driver input circuit.

6. A BMS address allocation system according to claim 1, characterized in that, The address allocation status feedback circuit consists of resistors R177, R180, and R181, and optocoupler U22. The power supply VDD is connected to one end of resistor R177, and the other end of resistor R177 is connected to the positive terminal of the photoelectric sensor of the optocoupler U22; the output terminal DO_DET of the address allocation status feedback circuit is connected to one end of resistor R180, and the other end of resistor R180 is connected to the positive terminal of the photoelectric sensor of the optocoupler U22; the negative terminal of the photoelectric sensor of the optocoupler U22 is grounded. The output terminal DO2 of the address allocation status feedback circuit is connected to one end of resistor R181, the other end of resistor R181 is connected to the anode of the LED of optocoupler U22, and the cathode of the LED of optocoupler U22 is grounded. The output terminal DO_DET of the address allocation status feedback circuit is connected to the first MCU, and the output terminal DO2 of the address allocation status feedback circuit is connected to the address allocation drive input circuit.

7. A BMS address allocation method, comprising allocating BMS addresses using the BMS address allocation system as described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1. Start the battery; The S2 and BMS MCU settings include the address allocation drive input circuit, address allocation drive output circuit, and address allocation status feedback circuit port signals; the master and slave devices are determined, and the last slave device is identified. S3. Set the host address to 0x00; S4. The host changes the output level of the address allocation driver output circuit DO_CTR and broadcasts the address; S5 and BMS obtain the broadcast address and reply to the host to complete the address acquisition; S6, Host stop broadcast address; S7. Repeat S4 to S6; S8. The master receives the last reply from the slave and closes the address allocation.

8. A BMS address allocation method according to claim 7, characterized in that, The address of the (n+1)th battery is the address of the nth battery plus 1.

9. A BMS address allocation method according to claim 7, characterized in that, The specific method for determining the master and slave devices, and the last slave device, is as follows: the BMS with the DI_DET port high is the master; the BMS with the DO_DET port high is the last slave.

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