Enhanced polar heterostructure and transistor, method of manufacture

Abstract

This invention discloses a heterostructure with enhanced polarization, a transistor, and a manufacturing method, relating to the field of semiconductor technology. It improves the structural reliability of the manufactured heterostructure by protecting its surface with a silicon oxide passivation layer and creates a high two-dimensional electron gas concentration at the interface of the heterostructure, thereby enhancing the performance of semiconductor devices including the heterostructure. The manufacturing method of the heterostructure includes: forming a stack on a substrate; the stack includes a first semiconductor layer and a second semiconductor layer sequentially stacked along the thickness direction of the substrate; the interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas. Next, a silicon nitride passivation layer is formed on the second semiconductor layer. Then, the silicon nitride passivation layer is removed using an oxidizing acid solution, and a silicon oxide passivation layer is formed in situ on the second semiconductor layer; the heterostructure includes the stack and the silicon oxide passivation layer. The manufacturing method of the transistor includes the above-described method for manufacturing the heterostructure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a heterostructure and transistor with enhanced polarization, and a method for manufacturing them. Background Technology

[0002] Gallium nitride-based heterostructures possess a two-dimensional electron gas at the interface. These two-dimensional electron gases exhibit extremely high mobility along the planar direction (especially at lower temperatures and when lattice vibrations are reduced), hence they are also called high-mobility two-dimensional electron gases. High-performance ultra-high frequency, ultra-high speed field-effect transistors—HEMTs (also known as MODFETs)—operate by utilizing this high-mobility two-dimensional electron gas in the modulated doped heterojunction potential well (channel).

[0003] However, the two-dimensional electron gas concentration of heterostructures formed by existing manufacturing methods is low, which is not conducive to improving the working performance of semiconductor devices including such heterostructures. Summary of the Invention

[0004] The purpose of this invention is to provide an enhanced polarization heterostructure and transistor, and a manufacturing method thereof, so as to improve the structural reliability of the manufactured enhanced polarization heterostructure by protecting the surface of the enhanced polarization heterostructure through a silicon oxide passivation layer, while making the interface of the enhanced polarization heterostructure have a high two-dimensional electron gas concentration, which is beneficial to improving the working performance of semiconductor devices including the enhanced polarization heterostructure.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for manufacturing an enhanced polarization heterostructure, the method comprising: firstly, forming a stack on a substrate; the stack comprising a first semiconductor layer and a second semiconductor layer sequentially stacked along the thickness direction of the substrate; a two-dimensional electron gas being present at the interface between the first semiconductor layer and the second semiconductor layer; nextly, forming a silicon nitride passivation layer on the second semiconductor layer; and nextly, removing the silicon nitride passivation layer using an oxidizing acid solution and forming a silicon oxide passivation layer in situ on the second semiconductor layer; the enhanced polarization heterostructure comprises the stack and the silicon oxide passivation layer.

[0006] Using the above technical solution, the manufacturing method provided by the present invention uses an oxidizing acid solution to remove the silicon nitride passivation layer first formed on the second semiconductor layer, and then forms a silicon oxide passivation layer in situ on the second semiconductor layer. In other words, the present invention replaces the silicon nitride passivation layer on the second semiconductor layer with a silicon oxide passivation layer in its original position using an oxidizing acid solution. Because the Si-O bonds in the silicon oxide passivation layer are more polar than the Si-N bonds in the silicon nitride passivation layer, replacing the silicon oxide passivation layer on the second semiconductor layer is more conducive to improving the polarization intensity of the stack. Furthermore, it can solve the technical problems in the prior art where oxygen cannot be introduced into the metal-organic chemical vapor deposition (MOCVD) equipment, and the high growth temperature of the silicon oxide layer easily causes oxygen atoms to enter the second semiconductor layer, resulting in instability of the second semiconductor material. As a result, silicon oxide passivation layers cannot be directly grown on the surface of the second semiconductor layer, so existing stacks use silicon nitride passivation layers. The additional channel formed between the silicon nitride passivation layer and the stack has a depletion and scattering effect on the main channel of the stack, resulting in poor performance of the heterostructure. It is beneficial to improve the two-dimensional electron gas concentration and electron mobility at the interface between the first semiconductor layer and the second semiconductor layer in the enhanced polarization heterostructure formed by the manufacturing method provided by the present invention, thereby improving the working performance of semiconductor devices including enhanced polarization heterostructures.

[0007] In one example, the stack comprises a gallium nitride-based stack. Furthermore, the first semiconductor layer is a gallium nitride layer, and the second semiconductor layer comprises an aluminum gallium nitride layer.

[0008] In one example, an in-situ epitaxial method is used to form a silicon nitride passivation layer on the second semiconductor layer.

[0009] In one example, the thickness of the silicon nitride passivation layer is greater than or equal to 1 nm and less than or equal to 100 nm.

[0010] In one example, the thickness of the silicon oxide passivation layer is greater than or equal to 1 nm and less than or equal to 10 nm.

[0011] In one example, the oxidizing acid solution includes at least one of nitric acid solution, phosphoric acid solution, and hydrofluoric acid solution.

[0012] In one example, the concentration of the oxidizing acid solution is greater than or equal to 1:10 and less than or equal to 1:1.

[0013] In one example, the temperature of the oxidizing acid solution is greater than or equal to room temperature and less than or equal to 200°C.

[0014] In one example, the process of removing the silicon nitride passivation layer with an oxidizing acid solution and forming a silicon oxide passivation layer in situ on the second semiconductor layer takes a time greater than or equal to 10 seconds and less than or equal to 10 minutes.

[0015] In a second aspect, the present invention provides a method for manufacturing a transistor, which includes the manufacturing method provided by the first aspect and its various implementations described above.

[0016] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0017] Thirdly, the present invention provides a heterostructure with enhanced polarization, which is manufactured using the manufacturing method provided in the first aspect and its various implementations.

[0018] The beneficial effects of the third aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0019] Fourthly, the present invention provides a transistor manufactured using the manufacturing method provided in the second aspect and various implementations thereof.

[0020] The beneficial effects of the fourth aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 This is a schematic diagram of the polarization of a gallium nitride-based heterostructure.

[0023] Figure 2 This is a schematic diagram of the energy band structure of a gallium nitride-based heterostructure.

[0024] Figure 3 A flowchart illustrating a method for manufacturing a heterostructure with enhanced polarization provided in an embodiment of the present invention;

[0025] Figure 4 A longitudinal cross-sectional view of the enhanced polarization heterostructure formed by the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 1 ;

[0026] Figure 5 A longitudinal cross-sectional view of the enhanced polarization heterostructure formed by the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 2 ;

[0027] Figure 6A longitudinal cross-sectional view of the enhanced polarization heterostructure formed by the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 3 ;

[0028] Figure 7 A longitudinal cross-sectional view of the enhanced polarization heterostructure formed by the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 4 ;

[0029] Figure 8 TEM comparison image of the enhanced polarization heterostructure (part b) formed by the manufacturing method provided in the embodiment of the present invention and the heterostructure (part a) in the prior art.

[0030] Reference numerals: 11 is a stacked layer, 12 is the first semiconductor layer, 13 is the second semiconductor layer, 14 is the silicon nitride passivation layer, and 15 is the silicon oxide passivation layer. Detailed Implementation

[0031] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0032] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0033] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0036] Heterogeneous structures refer to structures or systems composed of different materials. These materials possess different physical, chemical, or electronic properties. Heterogeneous structures can take the form of composite materials, heterogeneous thin films, multilayer structures, or heterogeneous nanostructures. The formation of heterogeneous structures typically involves interfaces between different materials, which play a crucial role in the material's properties and behavior. By forming interfaces between different materials, heterogeneous structures can achieve specific functions and properties, such as enhanced mechanical strength, improved photoelectric conversion efficiency, and enhanced magnetism. The design and fabrication of heterogeneous structures require precise control over the interfaces between different materials to achieve the desired functions and properties.

[0037] Specifically, for heterostructures formed by certain polarization materials, such as gallium nitride / aluminum gallium nitride, or aluminum nitride, indium aluminum nitride, scandium aluminum nitride, etc., a two-dimensional electron gas is formed between the two different polarization material layers in the heterostructure. Taking the AlGaN / GaN heterostructure as an example: Figure 1As shown, in the AlGaN / GaN heterostructure, the GaN layer is much thicker than the AlGaN layer. Therefore, the GaN layer is completely relaxed, exhibiting only spontaneous polarization along the c-axis [000-1]. The AlGaN layer is thinner, and the lattice constant of AlGaN is greater than that of GaN. This lattice mismatch causes tensile stress in the AlGaN layer, resulting in piezoelectric and spontaneous polarization pointing towards the [000-1] direction. Since both polarization intensities are negative, positive polarization charges are generated at their respective lower interfaces, and negative polarization charges at their upper interfaces. Because the spontaneous and piezoelectric polarization intensities of AlGaN are stronger than those of GaN, the total polarization intensity of AlGaN cancels out the spontaneous polarization intensity of GaN. The net positive polarization charge remaining at the heterostructure interface after charge cancellation can be calculated from the difference in polarization intensities between AlGaN and GaN. According to the principle of charge balance, negatively charged electrons with the same charge density as the positively polarized electrons will be induced at the interface of the heterostructure.

[0038] like Figure 2 As shown, AlGaN and GaN materials have different band gaps; AlGaN has a larger band gap than GaN, and there is a band step difference at the bottom of their conduction bands. Simultaneously, positive polarization charges exist at their interface. The band step difference, combined with the large amount of positive charge at the interface, causes the energy band at the bottom of the conduction band to bend, forming a two-dimensional potential well at the heterostructure interface. This two-dimensional potential well confines polarization-induced electrons within it. These electrons can only move in two dimensions along the plane of the heterostructure interface within the potential well, hence the term "two-dimensional electron gas."

[0039] In practical applications, the concentration of two-dimensional electron gas at the heterostructure interface is related to the polarization intensity of the AlGaN / GaN heterostructure. Specifically, the higher the polarization intensity, the higher the concentration of two-dimensional electron gas. Once the heterostructure has grown, the concentration of two-dimensional electron gas and electron mobility at the interface are fixed and difficult to adjust. If a structure with higher two-dimensional electron gas and electron mobility is required, it must be achieved by changing the Al composition and the thickness of each layer, which increases both cost and difficulty.

[0040] In addition, to protect the surface of the heterostructure from contamination or oxidation during transportation, a silicon nitride passivation layer is present on the heterostructure to improve its structural reliability. However, the silicon nitride passivation layer forms an additional channel with the barrier layer of polar materials such as AlGaN, and the carrier concentration of this additional channel can reach 10-1. 13 cm -2 The magnitude of the effect depletes and scatters the main channel, leading to a decrease in the two-dimensional electron gas concentration and electron mobility in the main channel, resulting in a decline in the performance of semiconductor devices, including those with heterostructures.

[0041] To address the aforementioned technical problems, embodiments of the present invention provide an enhanced polarization heterostructure, a transistor, and a manufacturing method. Specifically, in the manufacturing method of the enhanced polarization heterostructure provided by the present invention, an oxidizing acid solution is used to remove the silicon nitride passivation layer previously formed on the second semiconductor layer, and a silicon oxide passivation layer is formed in situ on the second semiconductor layer. This increases the two-dimensional electron gas concentration and electron mobility at the interface between the first and second semiconductor layers in the enhanced polarization heterostructure, thereby improving the operating performance of semiconductor devices including the enhanced polarization heterostructure.

[0042] Firstly, such as Figure 3 As shown, this embodiment of the invention provides a method for manufacturing a heterostructure with enhanced polarization. The following will describe a method based on... Figures 4 to 7 The cross-sectional view shown illustrates the manufacturing process. Specifically, the method for manufacturing this enhanced polarization heterostructure includes the following steps:

[0043] First, such as Figure 4 As shown, a stack 11 is formed on a substrate; the stack 11 includes a first semiconductor layer 12 and a second semiconductor layer 13 sequentially stacked along the thickness direction of the substrate; a two-dimensional electron gas is present at the interface between the first semiconductor layer 12 and the second semiconductor layer 13.

[0044] Specifically, the manufacturing method provided in this embodiment of the invention does not specifically limit the structure and material of the substrate, or the structure and material of the stack, as long as the interface between the first semiconductor layer and the second semiconductor layer included in the stack has a two-dimensional electron gas.

[0045] For example, the substrate material may include at least one of SiC, GaN, sapphire, and diamond.

[0046] For example, the materials of the first semiconductor layer and the second semiconductor layer include at least two different types of polarization materials.

[0047] For example, the aforementioned stack may include a gallium nitride-based stack. Furthermore, the first semiconductor layer may be a gallium nitride layer, and the second semiconductor layer may include a gallium aluminum nitride layer. With this configuration, the GaN-based material exhibits higher electron mobility, saturated electron velocity, and breakdown electric field, which can further improve the two-dimensional electron gas concentration and carrier mobility at the interface of the fabricated enhanced polarization heterostructure.

[0048] Of course, the first semiconductor layer and the second semiconductor layer of the stack can also include other types of polarization materials such as AlN, InAlN or ScAlN.

[0049] The thicknesses of the first and second semiconductor layers in the stack can be set according to actual needs and are not specifically limited here. Furthermore, in the actual manufacturing process, epitaxial growth and other processes can be used to form the aforementioned stack.

[0050] Next, as Figure 5 As shown, a silicon nitride passivation layer 14 is formed on the second semiconductor layer 13.

[0051] In actual manufacturing processes, in-situ epitaxy can be used to form a silicon nitride passivation layer on the second semiconductor layer. This prevents the stack from being damaged by impacts or scratches during handling and transfer, and also prevents the stack from reacting with air or other external elements during transfer, thus improving the quality of the stack. Of course, other methods can also be used to form the silicon nitride passivation layer.

[0052] As for the thickness of the silicon nitride passivation layer, it can be determined based on the thickness of the subsequently formed silicon oxide passivation layer and actual needs; no specific limit is made here.

[0053] For example, the thickness of the silicon nitride passivation layer can be greater than or equal to 1 nm and less than or equal to 100 nm. For instance, the thickness of the silicon nitride passivation layer can be 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, etc. In this case, the thickness of the silicon nitride passivation layer within the above range helps prevent the subsequent silicon oxide passivation layer formed based on the silicon element in the silicon nitride passivation layer from being too thin, ensuring that the silicon oxide passivation layer has a high passivation effect and protective function for the stack, further improving the structural reliability and electrical performance of the manufactured reinforced polarization heterostructure. In addition, it can also prevent excessive material consumption and excessively long manufacturing time due to excessively thick silicon nitride passivation layers, which helps control the manufacturing cost of reinforced polarization heterostructures while also improving the manufacturing efficiency.

[0054] Next, as Figure 6 and Figure 7 As shown, an oxidizing acid solution is used to remove the silicon nitride passivation layer, and a silicon oxide passivation layer 15 is formed in situ on the second semiconductor layer 13; the heterostructure for enhanced polarization includes a stack 11 and a silicon oxide passivation layer 15.

[0055] Specifically, the type, concentration, temperature, and treatment time of the oxidizing acid solution can be set according to the thickness of the silicon nitride passivation layer and the silicon oxide passivation layer, as well as the actual needs. Any solution can remove the silicon nitride passivation layer and form the silicon oxide passivation layer.

[0056] For example, an oxidizing acid solution may include at least one of nitric acid solution, phosphoric acid solution, and hydrofluoric acid solution. For instance, an oxidizing acid solution may consist only of nitric acid solution, phosphoric acid solution, or hydrofluoric acid solution.

[0057] The concentration, temperature, and treatment time of the oxidizing acid solution can be determined based on the type of oxidizing acid solution and the thickness of the silicon nitride passivation layer and the silicon oxide passivation layer.

[0058] For example, the concentration of the oxidizing acid solution can be greater than or equal to 1:10 and less than or equal to 1:1. For instance, the concentration of the oxidizing acid solution can be greater than or equal to 1:10, 1:9, 1:8, 1:7, 1:6, 1:5, 1:4, 1:3, 1:2, or 1:1, etc. This setting prevents excessively long processing times due to too low an oxidizing acid solution concentration, thus improving the manufacturing efficiency of the enhanced polarization heterostructure. It also prevents residual silicon nitride from affecting the electrical properties of the enhanced polarization heterostructure if the oxidizing acid solution does not completely remove the silicon nitride passivation layer within the same processing time, ensuring that the manufactured enhanced polarization heterostructure has a high two-dimensional electron gas concentration and electron mobility. Furthermore, it prevents excessively high manufacturing costs due to too high an oxidizing acid solution concentration.

[0059] For example, the temperature of the oxidizing acid solution can be greater than or equal to room temperature (25°C) and less than or equal to 200°C. For instance, the temperature of the oxidizing acid solution can be greater than or equal to 25°C, 30°C, 50°C, 80°C, 100°C, 120°C, 150°C, 180°C, or 200°C. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect described above when the concentration of the oxidizing acid solution can be greater than or equal to 1:10 and less than or equal to 1:1, and will not be repeated here.

[0060] For example, the processing time for removing the silicon nitride passivation layer with an oxidizing acid solution and forming a silicon oxide passivation layer in situ on the second semiconductor layer can be greater than or equal to 10 seconds and less than or equal to 10 minutes. For instance, the processing time can be 10 seconds, 20 seconds, 30 seconds, 1 minute, 2 minutes, 4 minutes, 6 minutes, 8 minutes, or 10 minutes, etc. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect described above where the concentration of the oxidizing acid solution can be greater than or equal to 1:10 and less than or equal to 1:1, and will not be repeated here.

[0061] For example, when the oxidizing acid solution is a phosphoric acid solution, the volume ratio of phosphoric acid to water in the oxidizing acid solution can be 1:3. The temperature of the oxidizing acid solution can be 100℃. The treatment time can be 1 minute.

[0062] The thickness of the formed silicon oxide passivation layer can be set according to the thickness of the silicon nitride passivation layer and actual needs, and no specific limit is made here.

[0063] For example, the thickness of the silicon oxide passivation layer can be greater than or equal to 1 nm and less than or equal to 10 nm. For instance, the thickness of the silicon oxide passivation layer can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. This setting prevents the passivation and protection effects of the silicon oxide passivation layer from being too weak due to a small thickness, ensuring that the silicon oxide passivation layer has a high passivation effect and protection effect on the stack, further improving the structural reliability and electrical performance of the manufactured reinforced polarization heterostructure. In addition, it can also prevent excessive material consumption and excessively long manufacturing time due to an excessively thick silicon oxide passivation layer, which helps control the manufacturing cost of the reinforced polarization heterostructure while also improving the manufacturing efficiency.

[0064] As can be seen from the above, such as Figures 4 to 8 As shown, the manufacturing method provided in this embodiment of the invention uses an oxidizing acid solution to remove the silicon nitride passivation layer 14 previously formed on the second semiconductor layer 13, and then forms a silicon oxide passivation layer 15 in situ on the second semiconductor layer 13. In other words, this embodiment of the invention replaces the original position of the silicon nitride passivation layer 14 on the second semiconductor layer 13 with a silicon oxide passivation layer 15 using an oxidizing acid solution. Because the Si-O bonds in the silicon oxide passivation layer 15 are more polar than the Si-N bonds in the silicon nitride passivation layer 14, replacing the second semiconductor layer with a silicon oxide passivation layer 15 is more beneficial for improving the polarization intensity of the stack 11. Furthermore, it can solve the technical problems in the prior art where oxygen cannot be introduced into the metal-organic chemical vapor deposition (MOCVD) equipment, and the high growth temperature of the silicon oxide layer easily causes oxygen atoms to enter the second semiconductor layer, resulting in instability of the second semiconductor material. As a result, the silicon oxide passivation layer 15 cannot be directly grown on the surface of the stack 11, so the existing stack 11 uses a silicon nitride passivation layer 14. The additional channel formed between the silicon nitride passivation layer 14 and the stack 11 has a depletion and scattering effect on the main channel of the stack 11, resulting in poor performance of the heterostructure. It is beneficial to improve the two-dimensional electron gas concentration and electron mobility at the interface of the first semiconductor layer 12 and the second semiconductor layer 13 in the enhanced polarization heterostructure formed by the manufacturing method provided in the embodiments of the present invention, thereby improving the working performance of semiconductor devices including enhanced polarization heterostructures.

[0065] Secondly, the present invention also provides an embodiment and a comparative example to illustrate the performance differences between the enhanced polarization heterostructure formed by the manufacturing method provided by the present invention and existing heterostructures:

[0066] Example

[0067] The manufacturing method provided in this embodiment first forms a stack on a substrate; the stack includes a gallium nitride (GaN) layer and a gallium aluminum nitride (GaN) layer sequentially stacked along the thickness direction of the substrate. The GaN layer has a thickness of 120 nm, and the GaN layer has a thickness of 21 nm. Next, a silicon nitride (SiN) passivation layer with a thickness of 2 nm is formed on the GaN layer. Then, the SiN passivation layer is removed using a hot phosphoric acid solution, and a silicon oxide passivation layer with a thickness of 4 nm is formed in situ on the GaN layer. The heterostructure for enhanced polarization includes the stack and the silicon oxide passivation layer.

[0068] Comparative Example

[0069] The manufacturing method provided in the comparative example first forms a stack on a substrate; the stack includes a gallium nitride (GaN) layer and a gallium aluminum nitride (GaN) layer sequentially stacked along the thickness direction of the substrate. The GaN layer has a thickness of 120 nm, and the GaN layer has a thickness of 21 nm. Next, a silicon nitride (SiN) passivation layer with a thickness of 2 nm is formed on the SiN layer. The heterostructure includes the stack and the SiN passivation layer.

[0070] Table 1. Test parameters of heterostructures formed by the manufacturing methods provided in the embodiments and comparative examples.

[0071]

[0072] As can be seen from the data in Table 1, the electron mobility of the enhanced polarization heterostructure after wet treatment with hot H3PO4 solution provided in the embodiment is improved, indicating that the scattering of electrons in the main channel by the additional sub-channel is reduced; at the same time, the concentration of two-dimensional electron gas increases, and the polarization intensity of the heterostructure increases.

[0073] Secondly, embodiments of the present invention provide a method for manufacturing a transistor, which includes the manufacturing method provided by the first aspect and its various implementations described above.

[0074] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0075] Thirdly, embodiments of the present invention provide an enhanced polarization heterostructure, which is manufactured using the manufacturing method provided in the first aspect and its various implementations.

[0076] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0077] Fourthly, embodiments of the present invention provide a transistor manufactured using the manufacturing method provided in the second aspect and its various implementations described above.

[0078] The beneficial effects of the fourth aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0079] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0080] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for manufacturing a heterostructure with enhanced polarization, characterized in that, include: A stack is formed on the substrate; The stack includes a first semiconductor layer and a second semiconductor layer sequentially stacked along the thickness direction of the substrate; A two-dimensional electron gas exists at the interface between the first semiconductor layer and the second semiconductor layer; A silicon nitride passivation layer is formed on the second semiconductor layer; The silicon nitride passivation layer is removed using an oxidizing acid solution, and a silicon oxide passivation layer is formed in situ on the second semiconductor layer; The enhanced polarization heterostructure includes the stack and the silicon oxide passivation layer.

2. The method for manufacturing a heterostructure with enhanced polarization according to claim 1, characterized in that, The stacked layer includes a gallium nitride-based stacked layer; the first semiconductor layer is a gallium nitride layer, and the second semiconductor layer includes a gallium nitride aluminum layer.

3. The method for manufacturing a heterostructure with enhanced polarization according to claim 1, characterized in that, The silicon nitride passivation layer is formed on the second semiconductor layer using an in-situ epitaxial method.

4. The method for manufacturing a heterostructure with enhanced polarization according to claim 1, characterized in that, The thickness of the silicon nitride passivation layer is greater than or equal to 1 nm and less than or equal to 100 nm; And / or, the thickness of the silicon oxide passivation layer is greater than or equal to 1 nm and less than or equal to 10 nm.

5. The method for manufacturing a heterostructure with enhanced polarization according to claim 1, characterized in that, The oxidizing acid solution includes at least one of nitric acid solution, phosphoric acid solution, and hydrofluoric acid solution.

6. The method for manufacturing a heterostructure with enhanced polarization according to claim 1, characterized in that, The concentration of the oxidizing acid solution is greater than or equal to 1:10 and less than or equal to 1:1; The temperature of the oxidizing acid solution is greater than or equal to room temperature and less than or equal to 200°C.

7. The method for manufacturing a heterostructure with enhanced polarization according to any one of claims 1 to 6, characterized in that, The process of removing the silicon nitride passivation layer with an oxidizing acid solution and forming a silicon oxide passivation layer in situ on the second semiconductor layer takes a time greater than or equal to 10 seconds and less than or equal to 10 minutes.

8. A method for manufacturing a transistor, characterized in that, The method for manufacturing a heterostructure with enhanced polarization as described in any one of claims 1 to 7.

9. A heterostructure for enhanced polarization, characterized in that, The enhanced polarization heterostructure is formed using the manufacturing method described in any one of claims 1 to 7.

10. A transistor, characterized in that, The transistor is manufactured using the manufacturing method described in claim 8.

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