Semiconductor device based on heterojunction polarization principle and preparation method thereof
By using a method of preparing the gate metal after ohmic contact annealing, combined with the use of hard masks and sidewall dielectric layers, the problems of high-temperature annealing affecting gate performance and insufficient photolithography precision in P-gate GaN HEMTs are solved, achieving high-precision small-size gate shrinkage and improving device reliability and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUBEI JIUFENGSHAN LAB
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-02
AI Technical Summary
In the prior art, the gate structure of P-gate GaN high mobility field-effect transistors (P-gate GaN HEMTs) is usually located before the ohmic contact in the manufacturing process. This causes high-temperature annealing to have an adverse effect on the static/dynamic performance and reliability of the P-gate structure. In addition, the photolithography process is not precise enough, making it difficult to fabricate small-sized structures.
A fabrication method based on the heterojunction polarization principle is adopted. The gate metal is fabricated after ohmic contact annealing. By using a combination of hard mask and sidewall dielectric layer, the gate metal and p-GaN mesa are self-aligned and high-precision small-size shrinkage is achieved, avoiding damage to the Schottky junction caused by high-temperature annealing. Chemical mechanical polishing and wet etching are used to ensure process accuracy.
It improves the long-term reliability and lifespan of the device under high temperature and high electric field conditions, solves the problems of insufficient precision in photolithography process and fabrication of small-size structures, and enhances the device's voltage withstand capability and conductivity.
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Figure CN122138430A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, specifically to a method for fabricating a semiconductor device based on the heterojunction polarization principle and the semiconductor device itself. Background Technology
[0002] Compound power semiconductor devices, due to their wide bandgap and other material properties, can achieve higher Baring figure of merit and exhibit better power performance. However, the material properties, epitaxial structure, and processing performance of compound semiconductor materials greatly limit their device fabrication process, requiring a comprehensive consideration of the complex constraints between device structure design requirements, subtractive processing, and process thermal budget.
[0003] The gate of a P-gate GaN high mobility field-effect transistor (P-gate GaN HEMT) is a typical example of the mutual constraints and trade-offs among various factors: In the P-GaN / AlGaN / GaN heterojunction structure, P-GaN is located on the top layer to realize the enhancement gate structure, and generally the p-GaN below the gate is retained to control the gate energy band (such as the drain-side injection structure, which also retains the p-GaN next to the drain ohm for hole injection); the device drift region is etched to remove P-GaN, leaving only the AlGaN / GaN heterojunction, and ohmic contacts are fabricated on the AlGaN barrier layer exposed by the etching.
[0004] Therefore, in P-gate GaN HEMTs, the gate structure is typically placed before the ohmic contact during the fabrication process. However, this process sequence inevitably results in the P-type gate structure needing to undergo high-temperature annealing during ohmic contact formation. This adversely affects the static / dynamic performance and reliability of the metal / P-GaN Schottky junction in the P-type gate and also limits the process window for ohmic contact annealing. Summary of the Invention
[0005] Based on the above description, the present invention provides a semiconductor device based on the heterojunction polarization principle and its fabrication method, which aims to achieve alignment of the gate metal and the p-GaN mesa while realizing the back gate process, and ensure that there is no ion damage at the gate metal / p-GaN interface.
[0006] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: This invention provides a method for fabricating a semiconductor device based on the heterojunction polarization principle, comprising: S10. Provide a substrate layer, and sequentially form a buffer layer, a channel layer, a barrier layer and a p-GaN epitaxial layer on the substrate layer. After cleaning, form a hard mask on the surface of the p-GaN epitaxial layer. S20. After patterning the hard mask, the p-GaN epitaxial layer is etched to passivate the device surface and form a passivation layer. S30. Etch the passivation layer and barrier layer on the device surface to expose the channel layer and form an ohmic contact hole; S40. Deposit ohmic contact metal at the ohmic contact hole and anneal to form an ohmic contact; S50. Deposit a dielectric layer on the device surface; S60. Perform chemical mechanical polishing on the device to remove the passivation layer and dielectric layer above the hard mask, exposing the hard mask; S70. Etch the hard mask to deposit gate metal on the p-GaN epitaxial layer to obtain a semiconductor device.
[0007] Furthermore, step S20 includes: S21. After patterning the hard mask, a sidewall dielectric layer is formed on the device surface, the sidewall dielectric layer is etched, and the sidewall dielectric layer on the side of the hard mask is retained. S22. Etch the p-GaN epitaxial layer to passivate the device surface and form a passivation layer.
[0008] Furthermore, step S22 includes: S22. After etching the p-GaN epitaxial layer, the sidewall dielectric layer is etched to passivate the device surface and form a passivation layer.
[0009] Furthermore, the channel layer is made of GaN, and the barrier layer is made of AlGaN.
[0010] Furthermore, the hard mask is made of silicon nitride, and its thickness is 0.1 μm to 1 μm.
[0011] Furthermore, the passivation layer is made of silicon dioxide, and the thickness of the passivation layer is 50 nm to 200 nm; The dielectric layer is made of silicon dioxide, and its thickness is 50 nm to 200 nm.
[0012] Furthermore, in step S40, the material of the ohmic contact metal includes at least one of titanium, aluminum, and titanium nitride; The thickness of the ohmic contact metal is 10 nm to 150 nm.
[0013] Furthermore, in step S40, the annealing temperature is 500℃~600℃, and the annealing time is 8 min~15 min.
[0014] Furthermore, in step S70, when etching the hard mask, an 86 vol%~88 vol% phosphoric acid solution is used, and the etching is performed at 150℃~170℃.
[0015] The present invention also provides a semiconductor device based on the heterojunction polarization principle, which is prepared by the semiconductor device preparation method based on the heterojunction polarization principle described above.
[0016] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: 1. A novel process for fabricating gate metal after annealing the ohmic contact of a device is achieved through the design and combination of specific process methods, process structures, and process flows.
[0017] 2. Through process structure design, self-alignment of two structures can be achieved by separately fabricating p-GaN abutments and gate metal (with patterning of the corresponding device structures performed in two separate photolithography steps), and the process capability to fabricate high-precision, small-size gate shrinkage structures is also available. This solves the problems of insufficient process precision and inability to fabricate small-size structures when fabricating P-type gate structures using photolithography in the "back-gate process".
[0018] 3. By combining the process structure and process method, the p-GaN mesa surface does not need to be exposed by ion etching during the fabrication of the gate Schottky contact, thus avoiding ion bombardment damage and over-etching introduced into the p-GaN surface during dielectric windowing. Attached Figure Description
[0019] Figure 1 This is a schematic diagram illustrating the fabrication process of an enhanced GaN HEMT unit cell with a P-type gate structure in the prior art. Figure 2 This is a schematic diagram of the gateless shrinkage unit cell structure of an enhanced GaN HEMT with a P-type gate structure in the prior art. Figure 3 This is a schematic diagram of the structure of an enhanced GaN HEMT with a gate shrinkage unit cell in the prior art, featuring a P-type gate structure. Figure 4 This is a schematic diagram of the fabrication process of an enhanced GaN HEMT cell with a P-type gate structure after gate Schottky metal deposition in the prior art. Figure 5 This is a schematic diagram of the structure of an enhanced GaN HEMT unit cell with a P-type gate structure after gate Schottky metal deposition in the prior art. Figure 6 This is a schematic flowchart of an embodiment of the semiconductor device fabrication method based on the heterojunction polarization principle provided by the present invention. Figure 7 This is a schematic flowchart of another embodiment of the semiconductor device fabrication method based on the heterojunction polarization principle provided by the present invention; Figure 8 To be according to Figure 7 A schematic diagram of the structure of the semiconductor device prepared by the method shown. Figure 9 This is a schematic flowchart of another embodiment of the semiconductor device fabrication method based on the heterojunction polarization principle provided by the present invention; Figure 10 To be according to Figure 9 A schematic diagram of the structure of the semiconductor device prepared by the method shown. Detailed Implementation
[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0022] Compound power semiconductor devices, due to their wide bandgap and other material properties, can achieve higher Baring figure of merit and exhibit better power performance. However, the material properties, epitaxial structure, and processing performance of compound semiconductor materials greatly limit their device fabrication process, requiring a comprehensive consideration of the complex constraints between device structure design requirements, subtractive processing, and process thermal budget.
[0023] The gate of a P-gate GaN high mobility field-effect transistor (P-gate GaN HEMT) is a typical example of the mutual constraints and trade-offs among various factors: In the P-GaN / AlGaN / GaN heterojunction structure, P-GaN is located on the top layer to realize the enhancement gate structure, and generally the p-GaN below the gate is retained to control the gate energy band (such as the drain-side injection structure, which also retains the p-GaN next to the drain ohm for hole injection); the device drift region is etched to remove P-GaN, leaving only the AlGaN / GaN heterojunction, and ohmic contacts are fabricated on the AlGaN barrier layer exposed by the etching.
[0024] Therefore, in P-gate GaN HEMTs, the gate structure is usually placed before the ohmic contact in the manufacturing process. However, this process sequence inevitably results in the P-type gate structure needing to undergo high-temperature annealing during ohmic contact formation, which adversely affects the static / dynamic performance and reliability of the metal / P-GaN Schottky junction in the P-type gate and also limits the process window for ohmic contact annealing.
[0025] Currently, commercially available gallium nitride (GaN-on-Si) enhancement-mode (E-mode) power devices are categorized by voltage ratings, including 650 V, 200 V, 100 V, and 45 V. Different process dimensions are required for each voltage rating to accommodate varying device structural dimensions (such as gate width, drift region length, and ohmic width), achieving a balance between voltage withstand capability and conduction capability. Mainstream E-mode GaN HEMTs primarily employ a P-type GaN gate, with gate control achieved by controlling the 2DEG beneath the AlGaN / GaN heterojunction below the TiN / p-GaN Schottky junction using the gate potential. Therefore, the electrical properties of the TiN / p-GaN Schottky junction are crucial for the device's dynamic / static characteristics and reliability. To ensure the electrical properties of the TiN / p-GaN Schottky junction at the process level, the p-GaN surface must be free from ion damage caused by etching, resist removal, or other processes before depositing the TiN gate metal. Figure 1 As shown, TiN is often deposited immediately after the initial GaN-on-Si epitaxial wafer has been cleaned, so the Schottky junction of the gate is the first to be fabricated among all device structures.
[0026] See Figure 1 In GaN HEMTs, the gate-first process places the deposition of the TiN / p-GaN Schottky junction and the fabrication of the P-type gate before other structures in the unit cell, including the ohmic contact. However, the formation of the ohmic contact requires annealing at a certain temperature to allow the metal to react with the GaN surface and form a high concentration of N-type doping at the gold-semiconductor interface to improve the carrier transport capacity of the interface. Taking the commonly used gold-free ohmic process in GaN manufacturing as an example, high-temperature annealing for 5 to 10 minutes is required to allow the Ti at the bottom of the Ti / Al / TiN multilayer metal to react with GaN to form TiN and nitrogen vacancies in GaN. The nitrogen vacancies in GaN act as donor states, reducing the barrier height and width at the gold-semiconductor interface. However, the ohmic annealing process also affects the performance of the TiN / p-GaN Schottky junction in the already formed P-type gate. Annealing at 500°C, compared to 300°C, results in higher gate leakage current, thus affecting device performance and reliability. Therefore, the temperature of gold-free ohmic annealing is often controlled at 550℃, which is not the optimal process parameter for gold-free ohmic annealing.
[0027] To ensure the reliability of the device gate under high gate-drain off-state electric fields, the gate structure needs to confine the gate metal to the edge of the p-GaN abutment in the p-gate, and ensure strict alignment of the "metal-p-GaN abutment," or the gate metal needs to be recessed a certain distance towards the center of the p-GaN abutment along the source / drain direction of the device to form a gate retraction (e.g., Figure 2 and Figure 3(As shown). Taking a 650 V enhancement-mode GaN HEMT as an example, the gate width is typically 1.5~2 μm, and the gate retraction on one side is typically 0.05 μm~0.2 μm; for a 100 V enhancement-mode GaN HEMT, due to its smaller structural size, the gate width is typically 0.3~0.5 μm, making gate retraction more difficult to fabricate. This structure makes it difficult to fabricate TiN gate metal on the p-GaN stage after etching, because the overlay accuracy of the corresponding process cannot meet the structural size requirements of gate retraction. In conventional processes, the gate metal is deposited before other device structures are formed. Therefore, gate metal patterning needs to be completed before the p-GaN stage is formed, and continuous etching of "TiN metal + p-GaN stage" is performed using the etching mask in the gate metal patterning step to complete the P-type gate fabrication. At the same time, during the P-type gate fabrication process, gate retraction is achieved through processes such as "sidewall self-alignment" or "metal side etching" to ensure gate reliability. Therefore, the alignment requirements between the gate metal and the p-GaN mesa in conventional processes make it difficult to fabricate the p-GaN mesa and the gate metal separately in two photolithography steps.
[0028] like Figure 4 As shown, simply depositing the TiN gate metal after the formation of the ohmic contact can indeed avoid the impact of ohmic annealing on the performance of the TiN / p-GaN Schottky junction, but it will bring the following problems: I. For example Figure 2 and Figure 3 As shown, the P-type gate structure requires ensuring that the gate metal forms a Schottky contact only on the top of the P-type mesa. If using... Figure 4 The process of "post-Gate Schottky metal deposition" in the Chinese process becomes "etching of the p-GaN stage, followed by fabrication of the ohmic contact, and finally deposition of the gate metal." Since the ohmic contact process is inserted between the p-GaN stage and the gate metal, the patterning of the p-GaN stage and the gate dielectric opening needs to be completed separately through two photolithography processes, thus requiring overlay of the two photolithography processes. Due to the critical dimension (CD) and overlay accuracy (OVL) of the photolithographic pattern, the alignment of the gate dielectric opening with the p-GaN stage is difficult to guarantee: if the two dimensions are similar, the gate dielectric opening may exceed the p-GaN stage due to photolithographic errors, causing the gate metal to form a gold-semiconductor contact outside the p-GaN stage, resulting in enhanced local electric field and increased gate leakage; if the gate metal width is reduced to increase the photolithographic error tolerance, the Schottky contact area will be too small, leading to insufficient gate control capability.
[0029] II. Mainstream P-gate GaN HEMT device designs require a gate retraction structure between the TiN / p-GaN Schottky contact formed by the gate metal and the edge of the p-GaN abutment to reduce gate leakage current and extend gate lifetime. This places extremely high demands on the etching of the p-GaN abutment and the gate dielectric via. Currently, P-gate GaN HEMTs are mostly based on 6- or 8-inch silicon-based GaN epitaxial wafers. 650 V and 100 V devices are mostly lithographically produced using I-line lithography, with a minimum CD of around 0.5 μm and an OVL of 0.1~0.15 μm, making it difficult to fabricate a gate retraction of 0.05 μm. This problem increases the process difficulty of the "post-gate Schottky metal deposition" process, reduces device yield, and adversely affects production efficiency.
[0030] III. Figure 5 As shown, the post-Schottky metal deposition process for the gate requires etching openings in the dielectric layer up to the p-GaN abutment surface during the fabrication of the P-type gate structure. However, the plasma etching process involves a physical bombardment mechanism, which can cause etching damage and over-etching on the p-GaN surface. This affects the electric field distribution within the gate p-GaN and the Schottky contact performance, negatively impacting device performance and reliability. Furthermore, the limitations of etch cutoff (CD) and open-velocity (OVL) also impose stringent requirements on the gate dielectric etching openings, necessitating strict control over the sidewall angles during etching and ensuring the CD of the etched pattern.
[0031] In summary, the gate-first process cannot avoid the high temperature effect of ohmic contact annealing on the P-type gate in P-gate GaN HEMT; however, simply placing the gate metal fabrication after the formation of the ohmic contact will bring about problems in device fabrication and reliability.
[0032] Therefore, a specialized process technology is needed to implement the post-gate process in P-gate GaN HEMT fabrication. This technology should have the following characteristics: 1. The process precision between the gate Schottky metal and the p-GaN mesa needs to meet the structural requirements of metal alignment and gate retraction; 2. The process of exposing the p-GaN semiconductor surface during Schottky junction fabrication should not introduce etching damage or over-etching problems on the semiconductor surface. This technology utilizes a specific process flow to form a structure with specific process characteristics (referring to a temporary structure formed during the process, which will participate in the fabrication of the final structure in subsequent processes) to adjust the fabrication sequence of the gate and ohmic contact structure, avoiding the gate degradation problem caused by the traditional "gate-first" process in subsequent processes at high temperatures.
[0033] In view of this, see Figure 6 This invention provides a method for fabricating a semiconductor device based on the heterojunction polarization principle, comprising: S10. Provide a substrate layer, and sequentially form a buffer layer, a channel layer, a barrier layer and a p-GaN epitaxial layer on the substrate layer. After cleaning, form a hard mask on the surface of the p-GaN epitaxial layer. S20. After patterning the hard mask, the p-GaN epitaxial layer is etched to passivate the device surface and form a passivation layer. S30. Etch the passivation layer and barrier layer on the device surface to expose the channel layer and form an ohmic contact hole; S40. Deposit ohmic contact metal at the ohmic contact hole and anneal to form an ohmic contact; S50. Deposit a dielectric layer on the device surface; S60. Perform chemical mechanical polishing on the device to remove the passivation layer and dielectric layer above the hard mask, exposing the hard mask; S70. Etch the hard mask to deposit gate metal on the p-GaN epitaxial layer to obtain a semiconductor device.
[0034] In the technical solution of this invention, a hard mask is introduced and patterned through etching to define the p-GaN mesa region. In subsequent steps, chemical mechanical polishing (CMP) is used to remove excess dielectric layers and expose the hard mask. Finally, the hard mask is etched to define the gate region, eliminating the dependence of the p-GaN mesa and gate metal on independent photolithographic overlay precision. By preferentially annealing in step S40 and then depositing the gate metal in S70, the Schottky junction is ensured to completely avoid the high-temperature annealing process. Therefore, the band structure of the gate metal-p-GaN interface is not thermally damaged, significantly reducing gate leakage current and improving the long-term reliability and lifetime of the device under high temperature and high electric field conditions.
[0035] The technical solution of this invention achieves a novel process for preparing gate metal after annealing the ohmic contact of a device through the design and combination of specific process methods, process structure and process flow.
[0036] Meanwhile, through process structure design, self-alignment of the two structures can be achieved under the premise of separately fabricating p-GaN stage and gate metal (patterning of the corresponding device structure in two-step photolithography), and it has the process capability to fabricate high-precision, small-size gate shrinkage structures, solving the problem of insufficient process accuracy and inability to fabricate small-size structures when fabricating P-type gate structures in the "back gate process".
[0037] Furthermore, by combining process structure and process methods, this solution eliminates the need for ion etching to expose the p-GaN mesa surface during the fabrication of the gate Schottky contact, thus avoiding ion bombardment damage and over-etching on the p-GaN surface during dielectric windowing.
[0038] For further details, please refer to [link / reference]. Figure 7 and Figure 8 Step S20 includes: S21. After patterning the hard mask, a sidewall dielectric layer is formed on the device surface, the sidewall dielectric layer is etched, and the sidewall dielectric layer on the side of the hard mask is retained. S22. Etch the p-GaN epitaxial layer to passivate the device surface and form a passivation layer.
[0039] In the technical solution of this invention, by forming and retaining a sidewall dielectric layer on the side of the hard mask, the lateral dimension is controlled by the thickness of the deposited thin film. When the hard mask is etched in a subsequent step, the retained sidewall dielectric layer will block part of the edge of the hard mask, so that the area finally exposed for depositing the gate metal is smaller than the hard mask area defined by the original photolithography. This mechanism naturally forms the inward shrinkage of the gate metal relative to the p-GaN mesa, i.e., gate retraction. This solution can precisely control the amount of gate retraction and solves the problem that the gate metal exceeds the p-GaN mesa due to photolithography overlay errors, causing edge electric field concentration and increased leakage current.
[0040] For further details, please refer to [link / reference]. Figure 9 and Figure 10 Step S22 includes: S22. After etching the p-GaN epitaxial layer, the sidewall dielectric layer is etched to passivate the device surface and form a passivation layer.
[0041] In the technical solution of the present invention, after forming the p-GaN stage, the sidewall dielectric layer on the side of the hard mask is etched away so that in subsequent steps, the high-quality integrally formed passivation layer can replace the physical isolation function of the original sidewall dielectric layer, effectively blocking the leakage path at the gate edge and significantly improving the device's withstand voltage and long-term stability.
[0042] Furthermore, the channel layer is made of GaN, and the barrier layer is made of AlGaN.
[0043] In the technical solution of this invention, a material combination of GaN / AlGaN / p-GaN is used to provide a conductive channel with high mobility and low loss. Furthermore, the p-GaN layer achieves safe normally closed characteristics and excellent gate control capability. Combined with the unique fabrication process of this invention, the advantages of this material system are maximized, thereby fabricating a next-generation power semiconductor device with high withstand voltage, low on-resistance and high reliability.
[0044] It should be noted that the process parameters of the channel layer, the barrier layer and the p-GaN epitaxial layer can be adjusted according to the needs of the device, and are not limited here.
[0045] Furthermore, the hard mask is made of silicon nitride, and its thickness is 0.1 μm to 1 μm.
[0046] In the technical solution of this invention, silicon nitride with a thickness of 0.1 μm to 1 μm is used as a hard mask to prevent high-energy ions during the etching process from penetrating the mask and damaging the underlying p-GaN active region, thus ensuring the integrity of the semiconductor material below the gate. Specifically, in some embodiments of this invention, the thickness of the hard mask is 0.5 μm.
[0047] Furthermore, the passivation layer is made of silicon dioxide, and the thickness of the passivation layer is 50 nm to 200 nm; The dielectric layer is made of silicon dioxide, and its thickness is 50 nm to 200 nm.
[0048] In the technical solution of this invention, silicon dioxide is used as both the passivation layer and the dielectric layer. The material consistency perfectly adapts to the CMP planarization process, and the appropriate thickness balances insulation performance, stress control, and step coverage. Specifically, in some embodiments of this invention, the thickness of both the passivation layer and the dielectric layer is 100 nm. Within this thickness range, the internal stress of SiO2 is low and controllable, preventing excessive mechanical stress on the underlying fragile p-GaN mesas or sidewall structures, thus preventing pattern collapse or lattice damage and ensuring the geometric integrity of the gate shrinkage structure.
[0049] Furthermore, in step S40, the material of the ohmic contact metal includes at least one of titanium, aluminum, and titanium nitride; The thickness of the ohmic contact metal is 10 nm to 150 nm.
[0050] In the technical solution of this invention, the above-mentioned material is used as the ohmic contact metal to ensure low contact resistance and high current capability, and to adapt to the requirements of high-temperature annealing reaction kinetics and subsequent CMP planarization process; while ensuring the quality of ohmic contact, excessive thermal budget and surface morphology deterioration are avoided, laying a solid physical foundation for the subsequent preparation of high-quality P-type gate Schottky junctions in a thermally damage-free environment.
[0051] Furthermore, in step S40, the annealing temperature is 500℃~600℃, and the annealing time is 8 min~15 min.
[0052] In the technical solution of this invention, by adjusting the annealing parameters and utilizing the time window before the gate is fabricated, a powerful annealing strategy that traditional processes cannot withstand is implemented. Sufficient annealing helps repair surface damage caused by etching, reduces interface state density, and solves the long-standing problem of the mutual constraint between "ohmic contact resistance" and "gate reliability" in GaN HEMTs. This enables the device to simultaneously possess industry-leading low on-resistance and excellent gate insulation performance, significantly improving the overall performance of the power device. Specifically, in some embodiments of this invention, the annealing temperature is 550°C, and the annealing time is 10 min.
[0053] Furthermore, in step S70, when etching the hard mask, an 86 vol%~88 vol% phosphoric acid solution is used, and the etching is performed at 150℃~170℃.
[0054] In the technical solution of this invention, the high selectivity and lack of physical bombardment characteristics of wet etching are utilized to precisely remove the SiN hard mask while exposing a high-quality p-GaN surface without any damage. Specifically, in some embodiments of this invention, the etching temperature is 160°C.
[0055] The present invention also provides a semiconductor device based on the heterojunction polarization principle, which is prepared by the semiconductor device preparation method based on the heterojunction polarization principle described above.
[0056] Since this semiconductor device based on the heterojunction polarization principle adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.
[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
[0058] In summary, the technical solution of this application has the following beneficial technical effects: 1. A novel process for fabricating gate metal after annealing the ohmic contact of a device is achieved through the design and combination of specific process methods, process structures, and process flows.
[0059] 2. Through process structure design, self-alignment of two structures can be achieved by separately fabricating p-GaN abutments and gate metal (with patterning of the corresponding device structures performed in two separate photolithography steps), and the process capability to fabricate high-precision, small-size gate shrinkage structures is also available. This solves the problems of insufficient process precision and inability to fabricate small-size structures when fabricating P-type gate structures using photolithography in the "back-gate process".
[0060] 3. By combining the process structure and process method, the p-GaN mesa surface does not need to be exposed by ion etching during the fabrication of the gate Schottky contact, thus avoiding ion bombardment damage and over-etching introduced into the p-GaN surface during dielectric windowing.
Claims
1. A method for fabricating a semiconductor device based on the heterojunction polarization principle, characterized in that, include: S10. Provide a substrate layer, and sequentially form a buffer layer, a channel layer, a barrier layer and a p-GaN epitaxial layer on the substrate layer. After cleaning, form a hard mask on the surface of the p-GaN epitaxial layer. S20. After patterning the hard mask, the p-GaN epitaxial layer is etched to passivate the device surface and form a passivation layer. S30. Etch the passivation layer and barrier layer on the device surface to expose the channel layer and form an ohmic contact hole; S40. Deposit ohmic contact metal at the ohmic contact hole and anneal to form an ohmic contact; S50. Deposit a dielectric layer on the device surface; S60. Perform chemical mechanical polishing on the device to remove the passivation layer and dielectric layer above the hard mask, exposing the hard mask; S70. Etch the hard mask to deposit gate metal on the p-GaN epitaxial layer to obtain a semiconductor device.
2. The semiconductor device fabrication method based on the heterojunction polarization principle according to claim 1, characterized in that, Step S20 includes: S21. After patterning the hard mask, a sidewall dielectric layer is formed on the device surface, the sidewall dielectric layer is etched, and the sidewall dielectric layer on the side of the hard mask is retained. S22. Etch the p-GaN epitaxial layer to passivate the device surface and form a passivation layer.
3. The semiconductor device fabrication method based on the heterojunction polarization principle according to claim 2, characterized in that, Step S22 includes: S22. After etching the p-GaN epitaxial layer, the sidewall dielectric layer is etched to passivate the device surface and form a passivation layer.
4. The method for fabricating a semiconductor device based on the heterojunction polarization principle according to claim 1, characterized in that, The channel layer is made of GaN, and the barrier layer is made of AlGaN.
5. The method for fabricating a semiconductor device based on the heterojunction polarization principle according to claim 1, characterized in that, The hard mask is made of silicon nitride and has a thickness of 0.1 μm to 1 μm.
6. The method for fabricating a semiconductor device based on the heterojunction polarization principle according to claim 1, characterized in that, The passivation layer is made of silicon dioxide, and its thickness is 50 nm to 200 nm. The dielectric layer is made of silicon dioxide, and its thickness is 50 nm to 200 nm.
7. The method for fabricating a semiconductor device based on the heterojunction polarization principle according to claim 1, characterized in that, In step S40, the material of the ohmic contact metal includes at least one of titanium, aluminum, and titanium nitride; The thickness of the ohmic contact metal is 10 nm to 150 nm.
8. The method for fabricating a semiconductor device based on the heterojunction polarization principle according to claim 1, characterized in that, In step S40, the annealing temperature is 500℃~600℃ and the annealing time is 8 min~15 min.
9. The method for fabricating a semiconductor device based on the heterojunction polarization principle according to claim 1, characterized in that, In step S70, when etching the hard mask, an 86 vol%~88 vol% phosphoric acid solution is used, and the etching is performed at 150℃~170℃.
10. A semiconductor device based on the heterojunction polarization principle, characterized in that, The semiconductor device was prepared according to the method for fabricating a semiconductor device based on the heterojunction polarization principle as described in any one of claims 1 to 9.