Image sensor, pixel structure and method of manufacturing the same

Abstract

This invention provides an image sensor, a pixel structure, and a method for manufacturing the same. The pixel structure includes a photoelectric conversion region disposed in a semiconductor substrate and a conductive plate disposed above it. The conductive plate covers a first region of the photoelectric conversion region and induces a hole accumulation layer on its surface by receiving a bias signal, achieving electrical pinning. A doped pinning layer is disposed in a second region outside the projection range of the conductive plate, achieving physical pinning, wherein the doping concentration of the surface doping profile of the first region is lower than that of the second region. Through the synergistic effect of electric field modulation and doping modulation, a stable potential distribution is formed on the surface of the photoelectric conversion region, effectively suppressing dark current. Because high-concentration doping is avoided in the first region, the impact of doping compensation on the potential well is reduced, thereby maintaining a large charge storage space even under pixel miniaturization conditions, improving the full-well capacity and the dynamic range and signal-to-noise ratio of the image sensor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an image sensor, pixel structure, and manufacturing method thereof. Background Technology

[0002] In complementary metal-oxide-semiconductor (CMOS) image sensors, photodiodes (PDs) are used to convert incident light into charge signals. To suppress dark currents generated on the surface of the photodiode, a pinned photodiode (PPD) structure is typically employed. In this structure, a doped region is formed on the surface of the photodiode by ion implantation into the silicon surface of the photoelectric conversion region.

[0003] As pixel size shrinks, the size of the photoelectric conversion area gradually decreases, and the proportion of the surface area in the overall structure increases, making the influence of surface-related properties on device performance more significant.

[0004] Therefore, how to maintain good device performance while shrinking device size is a common issue in the industry.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] In view of the problems in the prior art, the purpose of this invention is to provide an image sensor, a pixel structure and a method for manufacturing the same, to overcome the difficulties of the prior art and to solve the technical problem that the reduction in the size of image sensor devices affects device performance in related technologies.

[0007] The first aspect of this disclosure provides a pixel structure, which includes: The photoelectric conversion region is disposed in the semiconductor substrate; A conductive plate is disposed on a dielectric layer above a semiconductor substrate and covers a first region of the photoelectric conversion region. The conductive plate is configured to receive a bias signal to induce the formation of a hole accumulation layer on the surface of the first region. A doped pinning layer is formed in the second region of the photoelectric conversion region, the second region being located outside the projection range of the conductive plate on the semiconductor substrate, wherein the doped pinning layer is formed by ion implantation of the second region using the conductive plate as a mask; The doping concentration of the surface doping profile in the first region is lower than that in the surface doping profile in the second region.

[0008] Optionally, the second region at least partially surrounds the first region to form the periphery of the photoelectric conversion zone.

[0009] Optionally, the edge of the conductive plate and the edge of the doped pinned layer have an overlapping region in a direction perpendicular to the semiconductor substrate, the overlapping region being formed by the lateral diffusion of dopants in the semiconductor substrate.

[0010] Optionally, the conductive plate is an N-type doped polycrystalline silicon plate.

[0011] Optionally, the doped pinning layer is a P-type doped layer.

[0012] Optionally, it also includes: a transmission gate disposed on one side of the photoelectric conversion region, wherein the conductive plate and the transmission gate are formed of the same material layer and have a physical gap.

[0013] Optionally, the conductive plate has an asymmetrical polygonal profile, and at least one side of the polygon is arranged parallel to the edge of the transmission gate.

[0014] A second aspect of this disclosure provides an image sensor that includes the pixel structure of any of the above embodiments.

[0015] A third aspect of this disclosure provides a method for manufacturing a pixel structure, comprising: A semiconductor substrate is provided, and a photoelectric conversion region is formed in the semiconductor substrate; A conductive plate is formed on a dielectric layer above the photoelectric conversion region, and the conductive plate covers the first region of the photoelectric conversion region; Using a conductive plate as a mask, ion implantation is performed into the second region of the photoelectric conversion region to form a doped pinning layer, so that the doping concentration of the surface doping profile of the first region is lower than that of the surface doping profile of the second region. The second region is located outside the projection range of the conductive plate on the semiconductor substrate. The conductive plate is configured to receive a bias signal to induce the formation of a hole accumulation layer on the surface of a first region.

[0016] Optionally, a conductive plate is formed on a dielectric layer above the photoelectric conversion region, including: A gate dielectric layer is formed above the photoelectric conversion region as a dielectric layer; A polycrystalline silicon material layer is deposited on the gate dielectric layer and then N-type doped. A polycrystalline silicon material layer is patterned and etched to form a conductive plate and a transmission gate adjacent to the conductive plate.

[0017] Optionally, the method for manufacturing the pixel structure further includes: When patterning the polysilicon material layer, an avoidance structure is etched on the side of the conductive plate adjacent to the transmission gate so that the conductive plate presents an asymmetrical polygonal outline, and at least one side of the polygon is parallel to the edge of the transmission gate.

[0018] The image sensor, pixel structure, and manufacturing method thereof proposed in this disclosure have the following advantages: In this pixel structure, in the first region of the photoelectric conversion area, a hole accumulation layer is induced to form on the semiconductor surface by applying a bias signal through a conductive plate disposed above it. This hole accumulation layer modulates the carrier distribution at the interface through the action of an electric field, achieving electrical pinning of the surface potential. By adjusting the bias voltage amplitude, the degree of hole accumulation can be continuously adjusted, thereby achieving adjustable control of the surface potential state without changing the device structure or manufacturing process.

[0019] In the second region of the photoelectric conversion region, a doped pinning layer is formed by ion implantation to provide physical passivation based on the doping distribution. The first and second regions are disposed adjacent to each other on the surface, and the doping concentration of the surface doping profile of the first region is lower than that of the surface doping profile of the second region, thereby forming a control structure with lateral differences on the surface of the photoelectric conversion region.

[0020] In the structure disclosed herein, since no high concentration of doping is introduced into the first region, its surface potential is determined by the applied bias voltage, thereby reducing or avoiding the influence of doping compensation on the potential well, and enabling the photoelectric conversion region to maintain a large effective charge storage space.

[0021] Meanwhile, the second region still provides stable surface passivation capability through the doped pinning layer, while the first region achieves electrical passivation of interface defects through the hole accumulation layer. The two mechanisms work synergistically in space to form a continuous potential distribution on the surface of the photoelectric conversion region, thereby reducing the adverse effects on charge storage capability while ensuring dark current suppression capability.

[0022] Based on the above structure, a stable and adjustable potential distribution can be formed on the surface of the photoelectric conversion region during pixel operation, effectively suppressing the generation of thermally generated carriers caused by interface defects and improving interface recombination behavior, thereby reducing dark current and white spot defects. At the same time, by reducing the intrusion of high-concentration doping into the potential well, a high full-well capacity can still be maintained even with a smaller pixel size, which is beneficial for improving dynamic range and signal-to-noise ratio.

[0023] Furthermore, by replacing some of the physical doping with an electric field-induced hole accumulation layer, the sensitivity to doping dosage, diffusion, and thermal process fluctuations can be reduced, thereby improving the consistency of device performance and process stability.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0026] Figure 1 This is a cross-sectional schematic diagram of a pixel structure provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of the layout of a conductive plate and a transmission gate provided for an embodiment of this disclosure; Figure 3 A schematic diagram of another conductive plate and transmission gate layout provided in an embodiment of this disclosure; Figure 4 A flowchart illustrating a method for manufacturing a pixel structure according to an embodiment of this disclosure; Figure 5 This is a cross-sectional schematic diagram of the pixel structure after the photoelectric conversion region has been formed during the manufacturing process of the pixel structure according to an embodiment of the present disclosure; Figure 6 This is a cross-sectional schematic diagram of the pixel structure after the conductive plate and the second region are formed during the manufacturing process of the pixel structure provided in this embodiment of the disclosure. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0029] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0030] In image sensors of related technologies, a pinning layer is typically formed on the surface of the photoelectric conversion region to modulate the surface state. This pinning layer is generally formed by doping the surface of the photoelectric conversion region, creating a region with a relatively high doping concentration on the surface.

[0031] In some implementations, the pinning layers are continuously distributed along the surface of the photoelectric conversion region, thereby forming a relatively uniform doped structure in the lateral direction.

[0032] In this type of structure, since the pinning layer is typically doped with a dopant of the opposite conductivity type to the photoelectric conversion region, its formation process may affect the doping and potential distribution within the photoelectric conversion region. For example, in the case of an N-type photoelectric conversion region, a P-type doped pinning layer may participate in the formation of the potential distribution in the adjacent region and affect the charge storage region.

[0033] Meanwhile, during the formation process, doping may diffuse longitudinally or laterally, causing the surface doped region to extend into the photoelectric conversion region, thereby changing the local potential distribution characteristics of the photoelectric conversion region.

[0034] As pixel size decreases, the influence of the aforementioned doping distribution on the potential structure inside the photoelectric conversion region is further enhanced, resulting in a certain coupling relationship between surface state regulation and charge storage characteristics.

[0035] Therefore, how to reduce the impact of surface doping on the potential distribution inside the photoelectric conversion region while achieving surface state control of the photoelectric conversion region, and how to achieve differentiated control of different regions, has become a technical problem that needs to be considered.

[0036] This disclosure provides a pixel structure that introduces different surface modulation methods in different regions of the photoelectric conversion region by constructing a spatially differentiated structural configuration on the surface of the photoelectric conversion region. Specifically, in some regions, the electric field formed by the conductive structure and its bias modulates the surface carrier distribution, while in other regions, the structure formed by doping influences the surface potential distribution, thereby forming a modulation structure with lateral differences on the surface of the photoelectric conversion region.

[0037] Figure 1 A pixel structure provided for embodiments of this disclosure, such as Figure 1 As shown, the pixel structure includes a photoelectric conversion region 1, a conductive plate 2, and a doped pinning layer 3.

[0038] The photoelectric conversion region 1 is disposed in the semiconductor substrate 10 and is used to receive incident light and generate a corresponding charge signal. The photoelectric conversion region 1 can be a doped region disposed in the semiconductor substrate 10, such as an N-type doped region, and a potential well for storing photogenerated charge carriers is formed inside it.

[0039] The conductive plate 2 is disposed on the dielectric layer 4 above the semiconductor substrate 10, and the conductive plate 2 is isolated from the semiconductor substrate 10 by the dielectric layer 4. The conductive plate 2 covers the first region 11 of the photoelectric conversion region 1, and the first region 11 is located within the projection range of the conductive plate 2 on the semiconductor substrate 10.

[0040] In some embodiments, the conductive plate 2 covers most of the photoelectric conversion region 1, making the first region 11 larger in area than the second region 12.

[0041] The conductive plate 2 is configured to be electrically connected to an external bias circuit to receive a bias signal. Under the action of the bias signal, an electric field is generated on the surface of the first region 11 through the dielectric layer 4, which modulates the carrier distribution in the first region 11, thereby forming a hole accumulation layer on the surface of the first region 11. The hole accumulation layer is located near the interface of the semiconductor substrate 10 close to the dielectric layer 4.

[0042] In some embodiments, the conductive plate 2 is electrically connected to an external bias circuit to receive a bias signal. Under the bias voltage, an electric field is formed on the surface of the first region 11 through the dielectric layer 4, thereby modulating the carrier distribution in the region and forming a hole accumulation layer near the interface. By adjusting the bias voltage amplitude, the carrier density of the hole accumulation layer can be changed, thereby achieving continuous control of the surface potential of the first region 11.

[0043] A doped pinning layer 3 is formed in a second region 12 of the photoelectric conversion region 1, which is located outside the projection range of the conductive plate 2 onto the semiconductor substrate 10. The doped pinning layer 3 can be formed by an ion implantation process, for example, by implanting P-type impurities onto the surface of the semiconductor substrate 10 to form a region with a relatively high doping concentration.

[0044] In terms of spatial distribution, the first region 11 and the second region 12 are arranged adjacent to each other on the surface of the photoelectric conversion region 1. The doping concentration of the surface doping profile of the first region 11 is lower than that of the surface doping profile of the second region 12.

[0045] In some embodiments, due to the high doping concentration of the surface doping profile of the second region 12, dopants may diffuse into the interior of the photoelectric conversion region 1, resulting in a reduction in charge storage space and a doping compensation effect, thereby significantly reducing the full-well capacity (FWC). The doping compensation effect manifests as the cancellation of N-type doping in the photoelectric conversion region by P-type impurities, thereby changing the original potential well distribution and reducing the charge storage capacity.

[0046] Compared to the doping distribution in the second region 12, in the embodiments of this disclosure, since the first region 11 does not form a doped pinning layer 3, the doping concentration of the surface doping profile of the first region 11 remains at a low level, thereby weakening or avoiding the doping compensation effect caused by doping.

[0047] Therefore, the potential distribution of the photoelectric conversion region 1 in the first region 11 is mainly controlled by the applied electric field, rather than determined by the built-in potential formed by the high concentration of doping.

[0048] In the above structure, the difference in doping distribution between the first region 11 and the second region 12 results in different potential regulation mechanisms on the surface of the photoelectric conversion region 1 in the lateral direction. Specifically, the surface potential of the first region 11 is mainly regulated by the electrical bias applied by the conductive plate 2, while the surface potential of the second region 12 is mainly determined by the doped pinning layer 3.

[0049] Based on the above structure, in the first region 11, the hole accumulation layer formed by the bias signal applied by the conductive plate 2 can adjust the carrier distribution on the surface of the semiconductor substrate 10 and functionally achieve a surface carrier regulation effect similar to that of the doped pinning layer 3, thereby realizing the regulation of the surface potential.

[0050] In the second region 12, the doping distribution formed by the doped pinning layer 3 affects the surface potential distribution. As a result, a surface state regulation structure with the synergistic effect of multiple regions is formed on the surface of the photoelectric conversion region 1.

[0051] During pixel operation, the above structure forms a stable potential distribution on the surface of photoelectric conversion region 1, thereby regulating its band structure, suppressing the generation of thermally excited charge carriers at the interface, and regulating the recombination behavior of the interface charge carriers.

[0052] Based on this, since the doping concentration of the first region 11 is low, the influence of surface doping on the internal potential distribution can be reduced, so that a large effective charge storage space can still be maintained and the full well capacity can be improved even when the pixel size is reduced.

[0053] In embodiments of this disclosure, the semiconductor substrate 10 may be a single-crystal silicon substrate, such as a P-type silicon substrate or an N-type silicon substrate, or it may be a semiconductor layer formed by an epitaxial structure, but is not limited thereto.

[0054] The photoelectric conversion region 1 can be realized by forming a region with a predetermined doping type and doping concentration distribution in the semiconductor substrate 10.

[0055] For example, in one alternative embodiment, the photoelectric conversion region 1 is an N-type doped region disposed in a P-type semiconductor substrate, thereby forming a potential well structure therein for storing photogenerated electrons. The N-type doped region can be formed by processes such as ion implantation, epitaxial growth, or diffusion, and its doping concentration and depth distribution can be designed according to the pixel size and charge storage requirements.

[0056] Structurally, the photoelectric conversion region 1 may include a shallow region 1a near the surface of the semiconductor substrate 10 and a body region 1b extending into the semiconductor substrate 10. The body region 1b may include a charge collection region 1b1 located below the shallow region 1a and a photosensitive depletion region 1b2 located below the charge collection region 1b1. The shallow region 1a constitutes the interface region between the photoelectric conversion region 1 and the upper dielectric layer 4, and the physical properties of this interface region are key factors determining the surface carrier generation and recombination behavior.

[0057] In the structure disclosed herein, the shallow region 1a of the photoelectric conversion region 1 is divided into a first region 11 and a second region 12 in the horizontal direction, and the different regions differ in doping distribution and potential control method.

[0058] During operation, incident photons are absorbed within photoelectric conversion region 1, generating electron-hole pairs. Electrons are collected and stored within the potential well of photoelectric conversion region 1. The doping distribution of photoelectric conversion region 1 determines its internal potential distribution, thus affecting the collection efficiency and storage capacity of photogenerated electrons.

[0059] In addition, by maintaining a low doping concentration in the first region 11, the potential compression of the charge collection region 1b1 and the photosensitive depletion region 1b2 by the surface doping is reduced, thereby improving the full-well capacity of the pixel.

[0060] The doping distribution and surface potential state near the surface of the photoelectric conversion region 1 jointly determine the carrier distribution at the interface. In the first region 11, due to the relatively low doping concentration of the surface doping profile, its surface potential is mainly controlled by the electrical bias applied by the upper conductive plate 2. In the second region 12, due to the formation of the doped pinning layer 3, its doping distribution affects the surface potential distribution. Thus, the photoelectric conversion region 1 forms a potential distribution characteristic that is spatially related in the surface direction.

[0061] Based on the above structure, while maintaining the photoelectric conversion region 1’s function of collecting and storing photogenerated carriers, the carrier distribution on its surface region can be controlled by different mechanisms, thereby taking into account both surface characteristics and charge storage characteristics to a certain extent.

[0062] In embodiments of this disclosure, the conductive plate 2 is disposed on the dielectric layer 4 above the semiconductor substrate 10 and covers the first region 11 of the photoelectric conversion region 1.

[0063] The dielectric layer 4 can serve as a gate dielectric layer, used to form electrical isolation and establish an electric field coupling relationship between the conductive plate 2 and the semiconductor substrate 10. The projection range of the conductive plate 2 on the semiconductor substrate 10 defines the spatial location of the first region 11.

[0064] The conductive plate 2 is configured to receive a bias signal. In some embodiments, the bias signal is a negative DC bias, the amplitude of which is configured to cause the surface of the semiconductor substrate 10 in the first region 11 to be in a hole accumulation state, so that the surface carrier distribution is dominated by holes.

[0065] Furthermore, the amount of charge per unit area in the hole accumulation layer can reach an order of magnitude comparable to the amount of carriers introduced by the doped pinning layer 3, thereby distinguishing the first region 11 from the second region 12 in terms of the surface potential establishment mechanism.

[0066] Within a certain range, as the bias voltage amplitude changes, the carrier distribution state on the surface of the first region 11 changes accordingly.

[0067] The hole accumulation layer is a high-concentration hole distribution region formed on the surface of the semiconductor substrate 10, where the carrier concentration is higher than that of the bulk region 1b. It is located near the interface between the semiconductor substrate 10 and the dielectric layer 4, and is related to the geometry of the conductive plate 2 and the applied bias voltage.

[0068] In terms of materials, the conductive plate 2 can be formed of polycrystalline silicon. In some embodiments, the conductive plate 2 is an N-type doped polycrystalline silicon plate, and its doping type is consistent with other gate structures in the device to adapt to process integration requirements.

[0069] Alternatively, the conductive plate 2 can also be formed of other conductive materials, such as a metal layer or a composite conductive layer, but is not limited thereto.

[0070] In terms of layer structure, the pixel structure may further include an interlayer dielectric layer and interconnect structures located in the interlayer dielectric layer (not shown in the figure). The interlayer dielectric layer is used to achieve electrical isolation between the conductive plate and the interconnect structures. The interconnect structures can be used to connect the conductive plate 2 to an external bias circuit.

[0071] The thickness of the dielectric layer 4 is less than that of the interlayer dielectric layer, which enables the conductive plate 2 and the surface of the semiconductor substrate 10 to have a strong electric field coupling capability. This allows for the rapid establishment of a hole accumulation layer with a small bias voltage amplitude, while reducing the interference of the upper interconnect structure on the surface potential.

[0072] In terms of spatial relationship, the edge of the conductive plate 2 overlaps with the edge of the doped pinning layer 3 in planar projection. Specifically, due to the lateral diffusion of dopant ions in the semiconductor substrate 10, the doped pinning layer 3 extends from the second region 12 downwards from the conductive plate 2, thereby forming a transition overlap region of a predetermined width below the edge of the conductive plate 2. Within this overlap region, the built-in potential generated by physical doping and the induced electric field generated by the conductive plate 2 work together to form a continuous and smooth potential transition on the surface of the photoelectric conversion region 1 between the first region 11 and the second region 12.

[0073] In some embodiments, the doped pinning layer 3 is a boron-doped P-type layer with a relatively high doping concentration in the second region 12. Boron doping can be achieved during formation by ion implantation combined with thermal processing, thereby forming a doped region of predetermined depth and lateral distribution on the surface of the semiconductor substrate 10.

[0074] Based on the above structure, in the first region 11, a hole accumulation layer formed by bias voltage participates in the surface carrier regulation. The hole accumulation layer is the enrichment of majority carriers induced by the bias voltage signal at the interface. Functionally, it is equivalent to a P-type pinning layer formed by physical doping, which is used to shield interface state defects.

[0075] In the second region 12, surface potential modulation is achieved through the doping distribution of the pinned layer 3. In the edge region of the conductive plate 2, due to the presence of the overlapping region, the two modulation mechanisms form a continuous transition in space, thereby forming a continuous surface state distribution on the surface of the photoelectric conversion region 1.

[0076] During operation, the bias voltage received by the conductive plate 2 can be a constant bias voltage, the amplitude of which can be set according to the device design to adjust the carrier distribution state on the surface of the first region 11. The size, shape, and coverage relationship between the conductive plate 2 and the photoelectric conversion region 1 can be adjusted according to the pixel size and layout design, for example, in the form of a rectangle, polygon, or other shapes, thereby defining the range of the first region 11.

[0077] With the above settings, the conductive plate 2 introduces a surface control method related to spatial position without changing the overall structure of the photoelectric conversion region 1, so that the photoelectric conversion region 1 has different surface carrier control mechanisms in different regions.

[0078] In embodiments of this disclosure, the second region 12 is located outside the projection range of the conductive plate 2 on the semiconductor substrate 10, thereby spatially distinguishing it from the first region 11 covered by the conductive plate 2.

[0079] The doped pinning layer 3 can be formed by ion implantation on the surface of the semiconductor substrate 10, for example by implanting P-type impurities to form a surface region with a high doping concentration in the second region 12. The doped pinning layer 3 can be located in a shallow region close to the surface of the semiconductor substrate 10 and has a certain doping depth in the vertical direction, the lateral extent of which is defined by the layout of the implanted region.

[0080] In terms of spatial distribution, the second region 12 can at least partially surround the first region 11 and be distributed along the boundary of the photoelectric conversion region 1, thereby forming a peripheral region structure. Through this surrounding arrangement, the second region 12 can be distributed along the boundary of the photoelectric conversion region 1 and arranged around the first region 11 covered by the conductive plate 2.

[0081] Regarding the doping distribution, the doping concentration of the surface doping profile of the first region 11 is lower than that of the surface doping profile of the second region 12. The first region 11 can be maintained at the background doping level or a low doping concentration, while the second region 12 has a relatively high doping concentration on its surface due to the formation of the doped pinning layer 3, thereby forming a doping distribution feature that varies laterally on the surface of the photoelectric conversion region 1.

[0082] In some embodiments, at the edge of the conductive plate 2, the edge of the doped pinning layer 3 may extend downwards from the conductive plate 2, thereby forming a partially overlapping area on the planar projection.

[0083] The overlapping region can be formed by the lateral diffusion of dopants in the semiconductor substrate 10. That is, during the formation of the doped pinning layer 3, the dopants diffuse from the second region 12 toward the first region 11, so that the local area below the edge of the conductive plate 2 is simultaneously affected by the doping distribution and electric field modulation.

[0084] Within this overlapping region, the electric field modulation introduced by the doped pinning layer 3 and the conductive plate 2 is spatially superimposed, resulting in a transitional carrier distribution in this region. Consequently, a continuously changing surface state distribution is formed between the first region 11 and the second region 12, rather than an abrupt boundary.

[0085] Thus, a composite control mechanism consisting of doping control and electric field control is formed on the surface of photoelectric conversion region 1.

[0086] In embodiments of this disclosure, combined with Figure 1 and Figure 2 As shown, the pixel structure also includes a transfer gate 5 disposed on one side of the photoelectric conversion region 1. The transfer gate 5 is used to be turned on in a controlled manner during pixel operation to control the transfer of charge accumulated in the photoelectric conversion region 1 to subsequent nodes (such as the floating diffusion region 6). The transfer gate 5 is disposed at the edge of the photoelectric conversion region 1 and forms a charge transport channel with the photoelectric conversion region 1 on the surface of the semiconductor substrate 10 that is regulated by the gate voltage.

[0087] The conductive plate 2 and the transmission gate 5 can be formed from the same material layer, for example, simultaneously formed in the same polysilicon layer through a patterning process, thereby achieving integration without adding additional process steps.

[0088] In terms of spatial layout, a physical gap is provided between the conductive plate 2 and the transmission gate 5, meaning that the two are separated from each other and do not directly contact each other in the layout. The size of this physical gap can be limited by the minimum design rule of the specific process node. By setting this physical gap, the conductive plate 2 and the transmission gate 5 are electrically isolated, thereby ensuring that the bias signal received by the conductive plate 2 and the pulse switching signal received by the transmission gate 5 do not interfere with each other, avoiding negative impacts on charge transfer efficiency.

[0089] In some implementations, combined Figure 2 and Figure 3 As shown, in order to accommodate the complex internal layout of pixels, the conductive plate 2 can present an asymmetrical polygonal outline to adapt to the spatial arrangement of the photoelectric conversion area 1 and the transmission gate 5. The length and angle of each side of this polygonal outline are precisely designed according to the effective photosensitive area of ​​the photoelectric conversion area 1 and the geometric position of the transmission gate 5.

[0090] By adopting an asymmetrical polygonal contour, the conductive plate 2 can maximize the coverage of the first region 11 to achieve surface passivation while flexibly avoiding the transmission gate 5 and other pixel components (such as reset tubes, source followers, etc.), thereby optimizing the relative positional relationship between the photoelectric conversion region 1 and its surrounding functional units.

[0091] Optionally, in the polygonal profile, at least one edge of the conductive plate 2 is arranged parallel to the edge of the transmission gate 5. Within this gap region, the electric field generated by the conductive plate 2 and the potential distribution near the transmission gate 5 exhibit a consistent spatial variation trend, which is beneficial for forming a smooth potential transition between the photoelectric conversion region 1 and the transmission gate 5, thereby improving the charge transfer efficiency.

[0092] In practical applications, the outline shape of the conductive plate 2 and its relative position to the transmission gate 5 can be adjusted according to the pixel size, the layout of the photoelectric conversion area 1, and the process design rules. For example, in some embodiments, the conductive plate 2 can be set as an approximately straight edge structure on the side near the transmission gate 5 and parallel to the edge of the transmission gate 5, thereby forming a regular gap area; while on the side away from the transmission gate 5, other boundary shapes can be adopted to adapt to the peripheral structure of the photoelectric conversion area 1.

[0093] The above-described structure of the conductive plate 2 and the transfer gate 5 achieves spatial and functional decoupling while maintaining process compatibility: the conductive plate 2 is used to modulate the electric field on the surface of the photoelectric conversion region 1 (i.e., surface potential modulation structure), while the transfer gate 5 is used to control the charge transfer path. The two work together to improve surface potential modulation capability while also considering charge transfer performance, thereby improving the overall performance of the pixel.

[0094] This disclosure also provides an image sensor that includes the pixel structure of any of the above embodiments and can be formed based on CMOS technology.

[0095] An image sensor comprises multiple pixel structures arranged along the row and column directions to form a two-dimensional pixel array. Each pixel structure corresponds to a photosensitive unit used to acquire incident light signals.

[0096] Structurally, each pixel structure can share some peripheral circuits, such as row selection circuits, column readout circuits, and bias circuits. The bias circuit is used to provide bias signals to the conductive plates 2 in each pixel structure to achieve corresponding surface electric field modulation.

[0097] During operation, incident light irradiates the pixel array, and photoelectric conversion region 1 in each pixel structure generates photogenerated carriers and collects and stores them; under the action of control signal, the charge signal is transferred to the subsequent node through transmission gate 5, and processed by readout circuit to form image signal.

[0098] In image sensors, since each pixel structure adopts the structural configuration of any of the above embodiments, a surface potential distribution structure is formed at the pixel level by the synergistic effect of doping control and electric field control.

[0099] In some embodiments, the image sensor may further include an optical structure, such as a microlens array and a filter structure, disposed above the pixel array for focusing or spectrally selecting incident light; and a signal processing circuit disposed below or around the pixel array for amplifying, converting, or processing the readout electrical signals. However, the embodiments disclosed herein are not limited to specific peripheral structural forms.

[0100] With the above configuration, the image sensor can work collaboratively under a unified bias condition at the pixel array level, which helps to improve the stability and consistency of image acquisition.

[0101] This disclosure also provides a method for manufacturing a pixel structure, which can be used to manufacture... Figure 1 The pixel structure is shown. Additionally... Figure 1 The pixel structure shown can also be implemented through other processes, and the embodiments disclosed herein are not limited thereto.

[0102] like Figure 4 As shown, the manufacturing method of the pixel structure includes: Step 410: Provide a semiconductor substrate and form a photoelectric conversion region in the semiconductor substrate; Step 420: A conductive plate is formed on the dielectric layer above the photoelectric conversion region, and the conductive plate covers the first region of the photoelectric conversion region; Step 430: Using the conductive plate as a mask, ion implantation is performed into the second region of the photoelectric conversion region to form a doped pinning layer, so that the doping concentration of the surface doping profile of the first region is lower than that of the surface doping profile of the second region, and the second region is located outside the projection range of the conductive plate on the semiconductor substrate. The conductive plate is configured to receive a bias signal to induce the formation of a hole accumulation layer on the surface of a first region.

[0103] Through the above steps, the surface doping profile of the first region is kept lower than that of the second region, while the second region has a relatively high doping concentration due to the formation of a doped pinning layer, thus forming a region distribution with doping differences on the surface of the photoelectric conversion region.

[0104] Through the above process, a pixel structure with the above structural features can be obtained. In the obtained structure, the first region covered by the conductive plate and the second region where the doped pinning layer is located are spatially adjacent, and a transition region is formed at the edge of the conductive plate, thereby forming a continuous structural distribution on the surface of the photoelectric conversion region.

[0105] The manufacturing method of the pixel structure is described in detail below, using cross-sectional views of the pixel structure at each stage of the manufacturing process.

[0106] like Figure 5 As shown, a semiconductor substrate 10 is provided, and a photoelectric conversion region 1 is formed in the semiconductor substrate 10.

[0107] In this step, a semiconductor substrate 10, such as a single-crystal silicon substrate, can be provided.

[0108] In some embodiments, the semiconductor substrate 10 is a P-type doped substrate, and its doping concentration can be selected according to the design requirements of the pixel device. Alternatively, the semiconductor substrate 10 may also include an epitaxial layer structure, such as forming one or more epitaxial silicon layers on the substrate, to adjust the longitudinal potential distribution of the photoelectric conversion region.

[0109] In the semiconductor substrate 10, a photoelectric conversion region 1 can be formed by an ion implantation process. For example, N-type impurity ions can be implanted into the semiconductor substrate 10 to form an N-type doped region within a predetermined area, thereby constituting the photoelectric conversion region 1. Ion implantation can be performed using a single implantation or multiple energy implantation methods to form a doped profile with a predetermined depth distribution.

[0110] In some embodiments, an isolation structure 7, such as a shallow trench isolation (STI) structure, may be formed before forming the photoelectric conversion region 1 to define the boundaries of each pixel unit. The photoelectric conversion region 1 may be formed in the active region between adjacent isolation structures 7.

[0111] After ion implantation, the semiconductor substrate 10 can be thermally treated, such as by annealing, to activate doping and repair lattice damage generated during implantation. By adjusting the annealing temperature and time, the doping distribution and longitudinal diffusion range of the photoelectric conversion region 1 can be further controlled.

[0112] Structurally, the photoelectric conversion region 1 may include a shallow region 1a near the surface of the semiconductor substrate 10 and a bulk region 1b extending into the semiconductor substrate 10. The doping concentration and distribution of the shallow region 1a can be used to influence the potential characteristics near the surface, while the doping distribution of the bulk region 1b is used to form a charge storage region.

[0113] like Figure 6 As shown, a conductive plate 2 is formed on the dielectric layer 4 above the photoelectric conversion region 1, and the conductive plate 2 covers the first region 11 of the photoelectric conversion region 1.

[0114] In this step, a dielectric layer 4 may first be formed on the surface of the semiconductor substrate 10. In some embodiments, the dielectric layer 4 is a gate dielectric layer, such as a silicon oxide layer or a high dielectric constant material layer, used to provide electrical isolation and achieve electric field coupling between the conductive plate 2 and the surface of the semiconductor substrate 10.

[0115] The gate dielectric layer can be grown on the surface of the semiconductor substrate 10 to form a silicon oxide layer through a thermal oxidation process. Thermal oxidation can be carried out in oxygen or an oxygen-containing atmosphere, and an oxide layer of predetermined thickness can be obtained by controlling the temperature and time.

[0116] Alternatively, dielectric layer 4 can also be formed by chemical vapor deposition, such as depositing silicon dioxide, silicon nitride, or a high dielectric constant material layer, but is not limited thereto.

[0117] The thickness of dielectric layer 4 can be set according to device design requirements. For example, if it is necessary to enhance the electric field coupling between the conductive plate and the surface of the semiconductor substrate 10, a relatively thin dielectric layer 4 can be selected, while if it is necessary to improve insulation or reduce leakage current, its thickness can be appropriately increased.

[0118] After the gate dielectric layer is formed, a polycrystalline silicon material layer can be deposited on it. The polycrystalline silicon material layer can be formed using processes such as low-pressure chemical vapor deposition (LPCVD).

[0119] Subsequently, the polycrystalline silicon material layer can be doped, for example, with N-type doping, to form a conductive polycrystalline silicon layer. Doping can be achieved through in-situ doping or subsequent ion implantation combined with annealing.

[0120] After the polysilicon material layer is formed, it can be patterned using photolithography and etching processes to form the conductive plate 2 and the adjacent transmission gate 5. During this patterning process, the conductive plate 2 and the transmission gate 5 can be defined simultaneously by the same polysilicon layer, thus maintaining consistency in material and process sources.

[0121] In some embodiments, during the patterning etching of the polycrystalline silicon material layer, combined with Figure 2 and Figure 3 As shown, a clearance structure 25 can be formed on the side of the conductive plate 2 adjacent to the transmission gate 5. For example, by partially removing polysilicon material on this side, the conductive plate 2 is made to form a concave or truncated boundary in this direction, thereby giving the conductive plate 2 an asymmetrical polygonal profile. At least one side of the polygon can be arranged parallel to the edge of the transmission gate 5, thereby forming a gap region with a certain regularity between them as the clearance structure 25.

[0122] Through the patterning process described above, the conductive plate 2 covers the first region 11 of the photoelectric conversion region 1 on the layout. Its coverage area is used to define the spatial division between the first region 11 and the second region 12 during subsequent ion implantation. At the same time, a physical gap is formed between the conductive plate 2 and the transmission gate 5 to meet the process design rules and maintain electrical isolation between the two.

[0123] like Figure 1 As shown, using the conductive plate 2 as a mask, ion implantation is performed into the second region 12 of the photoelectric conversion region 1 to form a doped pinning layer 3.

[0124] In this embodiment, the conductive plate 2 is configured during its formation to define the spatial range for subsequent ion implantation, so that ion implantation selectively targets the second region 12. The ion implantation step is performed after the conductive plate 2 is formed, so as to utilize the conductive plate 2 to spatially define the ion implantation region.

[0125] Since the conductive plate 2 has a shielding effect on the implanted ions, the ion implantation mainly occurs outside the projection range of the conductive plate 2 on the semiconductor substrate 10, thereby forming a doped pinning layer 3 in the second region 12, while the first region 11 covered by the conductive plate 2 does not form a corresponding doped pinning layer.

[0126] In some embodiments, during the heat treatment process following ion implantation, the dopant diffuses in the semiconductor substrate 10, including longitudinal and lateral diffusion, thereby forming a transition region near the edge of the conductive plate 2.

[0127] Thus, a doped differential structure consisting of a first region 11 and a second region 12 is formed on the surface of the photoelectric conversion region 1. The first region 11 does not form a doped pinning layer during the manufacturing process, and its surface state is subsequently controlled by the bias voltage of the conductive plate.

[0128] In a practical implementation, ion implantation, such as implanting P-type impurity ions, can be performed on the semiconductor substrate 10 to form a region with a high doping concentration on the surface of the second region 12. The energy and dose of ion implantation can be set according to the device design so that the doped pinning layer 3 is mainly distributed in the shallow region near the surface of the semiconductor substrate 10 and forms a predetermined doping profile.

[0129] In some embodiments, the semiconductor substrate 10 may be heat-treated after ion implantation to activate doping and modulate the doping distribution.

[0130] During this process, the dopant can diffuse to a certain extent in the semiconductor substrate 10, including diffusion along the depth direction and lateral diffusion along the surface direction. Through this lateral diffusion, the dopant can extend downwards from the edge of the conductive plate 2, thereby forming a transition region of a certain width below the edge of the conductive plate 2.

[0131] Through the above-described ion implantation and subsequent processing, a doped pinning layer 3 is formed in the second region 12, resulting in a relatively high doping concentration on the surface doping profile of this region. In the first region 11 covered by the conductive plate 2, the doped pinning layer 3 is not formed on its surface due to being blocked by the conductive plate 2 during the implantation process, thus maintaining a relatively low doping concentration.

[0132] As a result, a regional structure with different doping distribution is formed on the surface of the photoelectric conversion region 1, so that the doping concentration of the surface doping profile of the first region 11 is lower than that of the surface doping profile of the second region 12.

[0133] In terms of spatial distribution, the second region 12 can be distributed around the first region 11, thereby forming a peripheral region structure on the surface of the photoelectric conversion region 1. At the boundary between the first region 11 and the second region 12, due to the transition region formed by lateral diffusion, the doping distribution between the two regions changes continuously.

[0134] This step allows for selective definition of the ion implantation region using the conductive plate 2 without the need for an additional independent mask, thereby forming a spatially differentiated doped structure on the surface of the photoelectric conversion region 1.

[0135] In some embodiments, after forming the doped pinning layer 3, an interlayer dielectric layer may be formed above the conductive plate 2. The interlayer dielectric layer can be formed by methods such as chemical vapor deposition to achieve electrical isolation between different conductive layers. Subsequently, contact holes can be formed in the interlayer dielectric layer to expose portions of the conductive plate or other conductive structures.

[0136] In some embodiments, after forming the contact holes, an interconnect structure (not shown in the figures) can be further formed. The interconnect structure can be formed by depositing and patterning a metallic material to achieve an electrical connection between the conductive plate and the bias circuit. This interconnect structure allows a predetermined bias signal to be provided to the conductive plate.

[0137] In some embodiments, after completing the above structure, a passivation layer or optical structure may be formed on top of the device. For example, a protective layer may be formed to cover the pixel structure, or optical elements such as microlenses or filter layers may be formed to improve the utilization efficiency of incident light. This disclosure does not limit the specific form of the optical structure.

[0138] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A pixel structure, characterized in that, include: The photoelectric conversion region is disposed in the semiconductor substrate; A conductive plate is disposed on a dielectric layer above the semiconductor substrate and covers a first region of the photoelectric conversion region. The conductive plate is configured to receive a bias signal to induce the formation of a hole accumulation layer on the surface of the first region. A doped pinning layer is formed in a second region of the photoelectric conversion region, the second region being located outside the projection range of the conductive plate on the semiconductor substrate, wherein the doped pinning layer is formed by ion implantation of the second region using the conductive plate as a mask; The doping concentration of the surface doping profile in the first region is lower than that in the surface doping profile in the second region.

2. The pixel structure according to claim 1, characterized in that, The second region at least partially surrounds the first region to form the peripheral region of the photoelectric conversion area.

3. The pixel structure according to claim 1, characterized in that, The edge of the conductive plate and the edge of the doped pinned layer have an overlapping region in a direction perpendicular to the semiconductor substrate, and the overlapping region is formed by the lateral diffusion of dopants in the semiconductor substrate.

4. The pixel structure according to claim 1, characterized in that, The conductive plate is an N-type doped polycrystalline silicon plate.

5. The pixel structure according to claim 1, characterized in that, The doped pinning layer is a P-type doped layer.

6. The pixel structure according to claim 1, characterized in that, Also includes: A transmission gate is provided on one side of the photoelectric conversion region, and the conductive plate and the transmission gate are formed of the same material layer and have a physical gap.

7. The pixel structure according to claim 6, characterized in that, The conductive plate has an asymmetrical polygonal outline, and at least one side of the polygon is arranged parallel to the edge of the transmission gate.

8. An image sensor, characterized in that, Includes the pixel structure according to any one of claims 1-7.

9. A method for manufacturing a pixel structure, characterized in that, include: A semiconductor substrate is provided, and a photoelectric conversion region is formed in the semiconductor substrate; A conductive plate is formed on a dielectric layer above the photoelectric conversion region, and the conductive plate covers a first region of the photoelectric conversion region; Using the conductive plate as a mask, ion implantation is performed into the second region of the photoelectric conversion region to form a doped pinning layer, so that the doping concentration of the surface doping profile of the first region is lower than that of the surface doping profile of the second region, and the second region is located outside the projection range of the conductive plate on the semiconductor substrate. The conductive plate is configured to receive a bias signal to induce the formation of a hole accumulation layer on the surface of the first region.

10. The method for manufacturing a pixel structure according to claim 9, characterized in that, The formation of a conductive plate on the dielectric layer above the photoelectric conversion region includes: A gate dielectric layer is formed above the photoelectric conversion region as the dielectric layer; A polycrystalline silicon material layer is deposited on the gate dielectric layer and then N-type doped. The polycrystalline silicon material layer is patterned and etched to form the conductive plate and the transmission gate adjacent to the conductive plate.

11. The method for manufacturing a pixel structure according to claim 10, characterized in that, Also includes: When patterning the polycrystalline silicon material layer, an avoidance structure is etched on the side of the conductive plate adjacent to the transmission gate, so that the conductive plate presents an asymmetrical polygonal outline, and at least one side of the polygon is parallel to the edge of the transmission gate.

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