A device structure of a silicon carbide umosfet
By introducing a P-type grounding component and a P-type trench bottom injection region into silicon carbide UMOSFET devices, the problems of difficult cell size reduction and insufficient surge reliability are solved, achieving smaller characteristic on-resistance and higher device reliability, making them suitable for high-voltage, high-temperature, and high-efficiency applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-03-31
- Publication Date
- 2026-07-10
AI Technical Summary
Existing silicon carbide UMOSFET devices suffer from problems such as difficulty in reducing cell size and insufficient surge reliability in high-voltage, high-temperature, and high-efficiency applications. In particular, the deep P-type electric field modulation layer has high requirements for depth and strong constraints on the characteristic on-resistance, gate-drain capacitance, and shielding efficiency.
In the silicon carbide UMOSFET device structure, a P-type grounding component and a P-type trench bottom injection region are introduced. The P-type grounding component is perpendicular to both sides and below the gate trench, and the P-type trench bottom injection region is located below the gate trench and in contact with the P-type electric field modulation layer. This adjusts the proportion of parasitic JFET region resistance, reduces cell size, and improves surge reliability.
This achieves a smaller cell size and a smaller characteristic on-resistance, while improving the surge reliability and gate-drain capacitance shielding efficiency of the device, thus achieving a high-efficiency trade-off.
Smart Images
Figure CN122373418A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a device structure of a silicon carbide UMOSFET. Background Technology
[0002] In the context of a generally positive outlook for the power electronics industry, power semiconductor devices, which play a decisive role in power electronics, have become a direct factor affecting the cost and efficiency of power electronic devices. Although silicon-based power devices are already quite mature, as power semiconductors gradually develop towards higher power, higher frequency, and lower power consumption, silicon (Si)-based devices, due to their inherent physical characteristics, are beginning to be difficult to apply to some high-voltage, high-temperature, high-efficiency, and high-power-density applications.
[0003] Silicon carbide (SiC) materials have gained widespread attention due to their superior physical properties, leading to the development of SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistor) technology. Compared to silicon-based devices, the high thermal conductivity and wide bandgap of silicon carbide materials determine its suitability for applications requiring high current density, high breakdown field strength, and high operating temperature. Compared to comparable SiMOSFETs, SiC MOSFETs exhibit lower on-resistance and switching losses, making them suitable for higher operating frequencies, while their high thermal conductivity significantly improves high-temperature stability.
[0004] like Figure 1 An existing UMOSFET (U-Groove Metal-Oxide-Semiconductor Field-Effect Transistor) device is provided. It uses a very deep P-type electric field modulation layer to push the electric field concentrated at the corner of the UMOSFET gate trench to the vicinity of the maximum depth of the P-type electric field modulation layer. In other words, it pushes the electric field concentration point from the interior of the oxide layer into the silicon carbide body, thereby realizing the application and promotion of UMOSFET devices. However, the extremely deep P-type electric field modulation layer requires ultra-high energy ion implantation to achieve this. The lateral diffusion of ion implantation is proportional to the energy, which wastes a lot of cell size from this perspective. In addition, the topology of the P-type electric field modulation layer connected in parallel to the upper surface of the device is also very wasteful of cell size.
[0005] In addition, the surge reliability of silicon carbide UMOSFETs is one of the reliability issues that hinders their widespread adoption. A deeper P-type electric field modulation layer and a lower current transport layer doping concentration can modulate the resistive component into the silicon carbide body, but ultimately at the cost of a larger characteristic on-resistance. Furthermore, the shielding efficiency of the gate-drain capacitance by the bottom injection region is inversely proportional to the grounding distance of the grounding component, and the grounding component will sacrifice some characteristic on-resistance. Therefore, the constraint relationship between the shielding efficiency of the gate-drain capacitance and the characteristic on-resistance is very strong. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides a silicon carbide UMOSFET device structure. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a silicon carbide UMOSFET device structure, the device structure comprising: N-type substrate; The N-type drift region is located on the upper surface of the N-type substrate; The P-type electric field modulation layer is located on the N-type drift regions at both ends of the device; The current transport layer is located on the N-type drift region and the P-type electric field modulation layer; The P-type channel region is located on the current transport layer; The N+ source region is located in the P-type channel region; The gate trench is located in the middle region of the device and extends through the N+ source region into the current transport layer. The P-type grounding component is perpendicular to the gate trench and located on both sides and below the gate trench, and is in contact with both the P-type electric field modulation layer and the N-type drift region. The gate dielectric layer is located on the inner wall of the gate trench; The gate electrode is located within the gate trench; The drain electrode is located on the lower surface of the N-type substrate.
[0007] In one embodiment of the present invention, viewed from a top view: the P-type grounding component is a strip structure perpendicular to the gate trench; the P-type grounding components are symmetrically distributed on both sides of the gate trench, and the P-type grounding components on both sides are in contact with the P-type electric field modulation layer and the N-type drift region, respectively.
[0008] In one embodiment of the present invention, the device structure further includes: The P-type trench bottom injection region is located below the gate trench and is in contact with the P-type electric field modulation layer at the gate trench.
[0009] In one embodiment of the present invention, viewed from a top view: the P-type grounding component is a strip structure perpendicular to the gate trench; the P-type grounding components are symmetrically distributed on both sides of the gate trench, and the P-type grounding components on both sides are in contact with the P-type electric field modulation layer, the N-type drift region, and the P-type trench bottom injection region, respectively.
[0010] In one embodiment of the present invention, viewed from a top view: the P-type grounding component is a dotted staggered distribution structure perpendicular to the gate trench; the P-type grounding components are asymmetrically distributed on both sides of the gate trench, and the P-type grounding components on both sides are in contact with the P-type electric field modulation layer, the N-type drift region, and the P-type trench bottom injection region at the corresponding gate trench, respectively.
[0011] In one embodiment of the present invention, the width of the P-type grounding component is the width of the entire device cell.
[0012] In one embodiment of the present invention, the doping concentration of the P-type grounding component is 5E19cm⁻¹. -3 ~1E17cm -3 .
[0013] In one embodiment of the present invention, the doping concentration of the P-type grounding component is the same as the doping concentration of the P-type trench bottom injection region.
[0014] In one embodiment of the present invention, the depth of the P-type trench bottom injection region below the gate trench is 0.2 μm to 1.0 μm; the width of the P-type trench bottom injection region is 0.2 to 1.1 times the width of the gate trench.
[0015] The beneficial effects of this invention are: The silicon carbide UMOSFET device structure proposed in this invention is a novel device structure designed to solve the problems of high depth requirements for the dual-sided deep P-type electric field modulation layer and the difficulty in further reducing the cell size. Specifically, this invention introduces P-type grounding components on both sides and below the gate trench. Compared with the traditional P-type grounding components located on both sides of the device, the width of the dual-sided deep P-type electric field modulation layer is reduced in the device cell size, thereby reducing the device cell size to achieve a smaller characteristic on-resistance. This invention also introduces a P-type trench bottom injection region below the gate trench. The P-type trench bottom injection region and the P-type electric field modulation layer modulate the resistance composition to improve surge reliability. Specifically, by appropriately increasing the resistance of the parasitic JFET region between the P-type trench bottom injection region and the P-type grounding component, the proportion of the parasitic JFET region resistance in the overall device resistance can be adjusted, so that the hot spot is located inside the parasitic JFET region, thereby improving surge reliability. Furthermore, the arrangement of point-like P-type grounding components reduces the occupation of the channel region by the P-type grounding components while maintaining the same grounding spacing of the P-type trench bottom injection region, increasing the area of the channel region and achieving a smaller characteristic on-resistance. The well-grounded P-type trench bottom injection region can shield part of the gate-drain capacitance, achieving a trade-off between characteristic on-resistance and capacitance shielding efficiency.
[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of a silicon carbide UMOSFET device structure provided in an embodiment of the present invention; Figure 2 This is provided by the embodiments of the present invention. Figure 1 The diagram shows a cross-sectional view of the device structure at section A. Figure 3 This is provided by the embodiments of the present invention. Figure 1 The diagram shows a cross-sectional view of the device structure at section B. Figure 4 This is a schematic diagram of another silicon carbide UMOSFET device structure provided in an embodiment of the present invention; Figure 5 This is provided by the embodiments of the present invention. Figure 4 The diagram shows a cross-sectional view of the device structure at section A. Figure 6 This is provided by the embodiments of the present invention. Figure 4 The diagram shows a cross-sectional view of the device structure at section B. Figure 7 This is a schematic diagram of another silicon carbide UMOSFET device structure provided in an embodiment of the present invention; Figure 8 This is provided by the embodiments of the present invention. Figure 7The diagram shows a cross-sectional view of the device structure at section A. Figure 9 This is provided by the embodiments of the present invention. Figure 7 The diagram shows a cross-sectional view of the device structure at section B. Figure 10 This is provided by the embodiments of the present invention. Figure 7 The diagram shows a cross-sectional view of the device structure at section C.
[0018] Explanation of reference numerals in the attached figures: 1- N-type substrate; 2- N-type drift region; 3- P-type electric field modulation layer; 4- Current transport layer; 5- P-type channel region; 6- N+ source region; 7- P-type grounding component; 8- P-type trench bottom injection region; 9- Gate dielectric layer; 10- Gate electrode; 11- Drain electrode. Detailed Implementation
[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0020] Please see Figure 1 This invention provides a silicon carbide UMOSFET device structure, which includes: N-type substrate 1; N-type drift region 2 is located on the upper surface of N-type substrate 1; The P-type electric field modulation layer 3 is located on the N-type drift region 2 at both ends of the device; Current transport layer 4 is located on N-type drift region 2 and P-type electric field modulation layer 3; P-type channel region 5 is located on current transport layer 4; N+ source region 6 is located in P-type channel region 5; The gate trench is located in the middle region of the device and extends through the N+ source region 6 into the current transport layer 4. The P-type grounding component 7 is perpendicular to the gate trench and located on both sides and below the gate trench, and is in contact with both the P-type electric field modulation layer 3 and the N-type drift region 2. Gate dielectric layer 9 is located on the inner wall of the gate trench; Gate electrode 10 is located within the gate trench; Drain electrode 11 is located on the lower surface of N-type substrate 1.
[0021] The embodiments of the present invention as viewed from a top view are as follows Figure 1 As shown: the P-type grounding component 7 is a strip structure perpendicular to the gate trench; the P-type grounding component 7 is symmetrically distributed on both sides of the gate trench, and the P-type grounding component 7 on both sides is in contact with the P-type electric field modulation layer 3 and the N-type drift region 2, respectively. Figure 2 , Figure 3 They respectively indicated Figure 1 The cross-sectional views at sections A and B provide a clearer view of the introduced P-type grounding component 7.
[0022] The silicon carbide UMOSFET device structure proposed in this embodiment of the invention further includes: a P-type trench bottom injection region 8, located below the gate trench, and in contact with the P-type electric field modulation layer 3 at the gate trench.
[0023] The embodiments of the present invention as viewed from a top view are as follows Figure 4 As shown: the P-type grounding component 7 is a strip structure perpendicular to the gate trench; the P-type grounding component 7 is symmetrically distributed on both sides of the gate trench, and the P-type grounding component 7 on both sides is in contact with the P-type electric field modulation layer 3, the N-type drift region 2, and the P-type trench bottom injection region 8, respectively. Figure 5 , Figure 6 They respectively indicated Figure 4 The cross-sectional view at sections A and B provides a clearer view of the introduced P-type grounding component 7 and the P-type trench bottom injection area 8.
[0024] The embodiments of the present invention as viewed from a top view are as follows Figure 7 As shown: the P-type grounding component 7 is a dotted staggered distribution structure perpendicular to the gate trench; the P-type grounding component 7 is asymmetrically distributed on both sides of the gate trench, and the P-type grounding component 7 on both sides is in contact with the P-type electric field modulation layer 3, the N-type drift region 2, and the P-type trench bottom injection region 8 at the corresponding gate trench. Figure 8 , Figure 9 , Figure 10 They respectively indicated Figure 7 The cross-sectional views at sections A, B, and C provide a clearer view of the introduced P-type grounding component 7 and the P-type trench bottom injection area 8.
[0025] In this embodiment of the invention, the N-type substrate 1 can be a SiC substrate.
[0026] In this embodiment of the invention, the N-type drift region 2 has a doping concentration of 1E15cm. -3 ~3E16cm -3 The doping ions can be impurity ions such as N (nitrogen) and P (phosphorus) that can form N-type semiconductors; their depth and doping concentration change with the device voltage level. For example, 1200V devices commonly use an N-type drift region with a doping concentration of 1E16cm-3 and an implantation depth of 10μm.
[0027] In this embodiment of the invention, the P-type electric field modulation layer 3 has a doping concentration of 5E19cm⁻¹. -3 ~1E17cm -3The doping ions can be impurity ions such as B (boron) and AL (aluminum) that can form a P-type semiconductor; the P-type electric field modulation layer 3 is used to alleviate the electric field concentration at the gate oxide layer; it is located above the N-type drift region 2, or can extend partially into the interior of the N-type drift region 2; its width can extend to the interior or exterior of the vertical extension line of the trench sidewall; as shown in the cross-sectional schematic diagram, the P-type electric field modulation layers 3 at both ends of the device are disconnected from each other (not connected) and are in contact with the P-type grounding component 7.
[0028] In this embodiment of the invention, the current transport layer 4 has a doping concentration of 2E16cm. -3 ~5E17cm -3 The doping ions can be impurity ions such as N (nitrogen) and P (phosphorus) that can form N-type semiconductors. The current transport layer 4 is used to alleviate excessive resistance increase and modulate the resistance composition. The maximum value of the resistance composition can be modulated between the two P-type electric field modulation layers 3 to enhance the surge reliability of the device.
[0029] In this embodiment of the invention, the P-type channel region 5 has a doping concentration of 1E17cm. -3 ~2E17cm -3 The doping ions can be impurity ions such as B (boron) and Al (aluminum) that can form P-type semiconductors.
[0030] In this embodiment of the invention, the N+ source region 6 has a doping concentration of 1E19cm. -3 ~5E20cm -3 The doping ions can be impurity ions such as N (nitrogen) and P (phosphorus) that can form N-type semiconductors; they form an ohmic contact with the source electrode.
[0031] The P-type grounding component 7 of this invention has a doping concentration of 5E19cm⁻¹. -3 ~1E17cm -3 The doping ions can be impurity ions such as B (boron) and AL (aluminum) that can form a P-type semiconductor; their depth extends into the P-type electric field modulation layer 3 or extends beyond the P-type electric field modulation layer 3 into the N-type drift region 2, and their width is the width of the entire device cell size, for example, it can be 0.2μm ~ 2.0μm. Figure 1 and Figure 3 In the top view of the device, the strips are arranged perpendicular to the gate trench. Figure 7 In the top view of the device, the P-type grounding component 7 is arranged in a staggered pattern perpendicular to the gate trench. The P-type grounding component 7 serves five functions: firstly, to connect the P-type channel region 5 to the surface / source electrode (not shown in the figure, but common knowledge); secondly, to form a P-type ohmic contact on the surface (connected to the source electrode); and thirdly, to connect the P-type electric field modulation layer 3 to the source electrode. Figure 3 and Figure 7 In addition, its function also includes connecting the P-type trench bottom injection region 8 to the source electrode. Figure 7 Its functions also include modulating characteristic on-resistance and various grounding effects.
[0032] In this embodiment of the invention, the P-type groove bottom injection zone 8 (only appears in...) Figure 3 or Figure 7 (in the middle), its doping concentration is the same as that of the P-type grounding component 7, for example, the doping concentration is 5E19cm. -3 ~1E17cm -3 The doping ions can be impurity ions such as boron (B) and aluminum (AL) that can form P-type semiconductors. The depth of the doped ions below the gate trench is 0.2 μm to 1.0 μm, and the width is 0.2 to 1.1 times the width of the gate trench. The P-type trench bottom injection region 8 is in contact with the P-type grounding component 7. The P-type trench bottom injection region 8 has three functions: First, it further modulates the electric field at the gate dielectric layer 9 (by modulating the electric field into the silicon carbide body, it alleviates the concentration of the electric field at the gate dielectric layer 9). Second, it modulates the resistance composition to improve the surge reliability of the device, that is, it appropriately increases the resistance of the parasitic JFET region between the P-type trench bottom injection region 8 and the P-type grounding component 7, that is, it adjusts the proportion of the parasitic JFET region resistance in the overall device resistance, so that the hot spot is located inside the parasitic JFET region, thereby improving surge reliability. Of course, the arrangement shown in the figure can also achieve the purpose of improving surge reliability by adjusting the spacing of the P-type electric field modulation layers 3 at both ends or the doping concentration of the current transport layer 4. Thirdly, the arrangement of point-type P-type grounding components 7 reduces the occupation of the channel area by the P-type grounding components 7 while ensuring the same grounding spacing of the P-type bottom injection area 8, increases the area of the channel area, realizes the characteristic conduction resistance, and the P-type bottom injection area 8 with good grounding effect can shield part of the gate leakage capacitance, realizing a compromise modulation between the shielding efficiency of the gate leakage capacitance.
[0033] In this embodiment of the invention, the gate dielectric layer 9 can be made of silicon dioxide or alumina and other dielectric materials; its thickness is 30nm~80nm.
[0034] In this embodiment of the invention, the gate electrode 10 can be made of polycrystalline silicon. The drain electrode 11 and the source electrode can be made of a Ti / Au metal stack.
[0035] To provide a more accurate and clear description of the device characteristics, and because the gate-source isolation dielectric and source electrode on the upper surface of the device are no different from those of conventional MOSFET devices, they are not shown.
[0036] In summary, the silicon carbide UMOSFET device structure proposed in this embodiment of the invention is a novel device structure designed to solve the problems of high depth requirements for the dual-sided deep P-type electric field modulation layer and the difficulty in further reducing the cell size. Specifically, this invention introduces P-type grounding components 7 on both sides and below the gate trench. Compared with the traditional P-type grounding components 7 located on both sides of the device, the width of the dual-sided deep P-type electric field modulation layer 3 is reduced in the device cell size, thereby reducing the device cell size to achieve a smaller characteristic on-resistance. The present invention also introduces a P-type trench bottom injection region 8 below the gate trench. The P-type trench bottom injection region 8 and the P-type electric field modulation layer 3 modulate the resistance composition to improve surge reliability. That is, by appropriately increasing the resistance of the parasitic JFET region between the P-type trench bottom injection region 8 and the P-type grounding component 7, the proportion of the parasitic JFET region resistance in the overall device resistance can be adjusted, so that the hot spot is located inside the parasitic JFET region, thereby improving surge reliability. Furthermore, the arrangement of the point-like P-type grounding components 7 reduces the occupation of the channel region by the P-type grounding components 7 while ensuring the same grounding spacing of the P-type trench bottom injection region 8, increasing the area of the channel region and achieving a smaller characteristic on-resistance. The P-type trench bottom injection region 8 with good grounding effect can shield part of the gate drain capacitance, achieving a trade-off between characteristic on-resistance and capacitance shielding efficiency.
[0037] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0038] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.
[0039] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A device structure for a silicon carbide UMOSFET, characterized in that, The device structure includes: N-type substrate; The N-type drift region is located on the upper surface of the N-type substrate; The P-type electric field modulation layer is located on the N-type drift regions at both ends of the device; The current transport layer is located on the N-type drift region and the P-type electric field modulation layer; The P-type channel region is located on the current transport layer; The N+ source region is located in the P-type channel region; The gate trench is located in the middle region of the device and extends through the N+ source region into the current transport layer. The P-type grounding component is perpendicular to the gate trench and located on both sides and below the gate trench, and is in contact with both the P-type electric field modulation layer and the N-type drift region. The gate dielectric layer is located on the inner wall of the gate trench; The gate electrode is located within the gate trench; The drain electrode is located on the lower surface of the N-type substrate.
2. The device structure of the silicon carbide UMOSFET according to claim 1, characterized in that, Viewed from above: The P-type grounding component is a strip structure perpendicular to the gate trench; the P-type grounding components are symmetrically distributed on both sides of the gate trench, and the P-type grounding components on both sides are in contact with the P-type electric field modulation layer and the N-type drift region, respectively.
3. The device structure of the silicon carbide UMOSFET according to claim 1, characterized in that, The device structure also includes: The P-type trench bottom injection region is located below the gate trench and is in contact with the P-type electric field modulation layer at the gate trench.
4. The device structure of the silicon carbide UMOSFET according to claim 3, characterized in that, Viewed from above: The P-type grounding component is a strip structure perpendicular to the gate trench; the P-type grounding components are symmetrically distributed on both sides of the gate trench, and the P-type grounding components on both sides are in contact with the P-type electric field modulation layer, the N-type drift region, and the P-type trench bottom injection region, respectively.
5. The device structure of the silicon carbide UMOSFET according to claim 3, characterized in that, From a top-down view: the P-type grounding components are a dotted, staggered distribution structure perpendicular to the gate trench; the P-type grounding components are asymmetrically distributed on both sides of the gate trench, and the P-type grounding components on both sides are in contact with the P-type electric field modulation layer, N-type drift region, and P-type trench bottom injection region at the corresponding gate trench, respectively.
6. The device structure of the silicon carbide UMOSFET according to claim 2, 4, or 5, characterized in that, The width of the P-type grounding component is equal to the width of the entire device cell.
7. The device structure of the silicon carbide UMOSFET according to claim 1, characterized in that, The doping concentration of the P-type grounding component is 5E19cm⁻¹. -3 ~1E17cm -3 .
8. The device structure of the silicon carbide UMOSFET according to claim 3, characterized in that, The doping concentration of the P-type grounding component is the same as the doping concentration of the P-type trench bottom injection region.
9. The device structure of the silicon carbide UMOSFET according to claim 3, characterized in that, The depth of the P-type trench bottom injection region below the gate trench is 0.2μm to 1.0μm; the width of the P-type trench bottom injection region is 0.2 to 1.1 times the width of the gate trench.