An LED chip structure based on a gallium oxide interlayer and its fabrication process

Abstract

This invention discloses an LED chip structure based on a gallium oxide interlayer and its fabrication process. The chip structure sequentially comprises a substrate, an AlN nucleation layer, a U-GaN buffer layer, an N-GaN layer, a superlattice stress relief layer, a multi-quantum-well active layer, a P-GaN layer, an ohmic contact layer, a β-Ga₂O₃ interlayer, and an indium tin oxide current diffusion layer. The β-Ga₂O₃ interlayer possesses high transmittance optical characteristics and is formed by annealing and oxidizing gallium nitride, followed by indium tin oxide deposition. This creates a heterojunction interface on the two contact surfaces, forming a triangular well and a two-dimensional electron gas, further enhancing lateral current diffusion. This invention enables performance and structural control of LED optoelectronic devices, reduces local current density, and improves the brightness, uniformity, lifespan, and stability of LED devices.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an LED chip structure based on a gallium oxide interlayer and its fabrication process. Background Technology

[0002] Although third-generation semiconductor materials, represented by gallium nitride (GaN), have driven significant progress in solid-state lighting technology, GaN-based light-emitting diodes (LEDs) still face several key technical bottlenecks in their application to integrated circuits, hindering their development in large-size, high-density displays. Specifically, (1) the high ohmic contact resistance of p-type GaN leads to increased device operating voltage and reduced efficiency; (2) uneven lateral current diffusion within the p-type layer causes local current congestion, affecting light emission uniformity and device lifespan; and (3) the light extraction efficiency is not ideal, and the absorption and reflection of light by traditional metal or transparent conductive electrodes causes severe photon loss.

[0003] To address these issues, the industry commonly uses indium tin oxide (ITO) as the current diffusion layer. However, ITO and GaN have similar band gaps (approximately 3.5 eV and 3.4 eV, respectively), resulting in limited band shift at their interface and making it difficult to form significant band bending. Consequently, it is impossible to generate a highly mobile two-dimensional electron gas to optimize current diffusion. Furthermore, the ohmic contact performance between ITO and p-GaN still needs improvement.

[0004] Gallium oxide (β-Ga₂O₃), as an emerging fourth-generation ultrawide bandgap semiconductor material, boasts a bandgap of approximately 4.9 eV, demonstrating excellent application prospects. On one hand, β-Ga₂O₃ achieves excellent ohmic contact characteristics when in contact with GaN, with a contact resistivity as low as 10⁻⁶. -4 Ω·cm 2 On the other hand, β-Ga2O3 exhibits extremely high optical transmittance in the visible light band, minimizing the absorption of emitted photons. More importantly, there is a significant conduction band shift between β-Ga2O3 and GaN. When they form a heterojunction, the strong band bending at the interface naturally creates a triangular potential well, effectively trapping electrons and forming a highly mobile two-dimensional electron gas, providing an efficient channel for the lateral diffusion of current. However, current technologies do not fully utilize this unique physical property of the β-Ga2O3 / GaN heterojunction. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an LED chip structure and its fabrication process based on a gallium oxide interlayer. By introducing a β-Ga2O3 interlayer, the problems of ohmic contact, current diffusion and light extraction efficiency of GaN-based LEDs in the background art are solved, thereby breaking through the technical barriers of large-size LED displays.

[0006] The technical solution adopted by the present invention to solve its technical problem is: to provide an LED chip structure based on a gallium oxide interlayer, wherein a substrate, an AlN nucleation layer, a U-GaN buffer layer, an N-GaN layer, a superlattice stress relief layer, a multi-quantum well active layer, a P-GaN layer, an ohmic contact layer, a β-Ga2O3 interlayer, and an indium tin oxide current diffusion layer are sequentially disposed therefrom.

[0007] A two-dimensional electron gas is formed at the heterojunction interface between the β-Ga2O3 intermediate layer and the ohmic contact layer for lateral diffusion of current; the β-Ga2O3 intermediate layer and the indium tin oxide current diffusion layer form a low-resistance path for longitudinal current transmission.

[0008] In a preferred embodiment of the present invention, the thickness of the AlN nucleation layer is no greater than 1000 nm.

[0009] In a preferred embodiment of the present invention, the thickness of the U-GaN buffer layer is 200 nm to 5000 nm; the thickness of the N-GaN layer is 200 to 5000 nm, and the doping concentration is 10. 17 ~10 20 cm -3 The thickness of the P-GaN layer is 20–500 nm, and the doping concentration is 10. 17 ~10 20 cm -3 The thickness of the ohmic contact layer is 20–500 nm, and the doping concentration is 10. 17 ~10 20 cm -3 .

[0010] In a preferred embodiment of the present invention, the superlattice stress relief layer is composed of alternating InGaN / GaN layers, with a maximum of 40 layers; wherein the thickness of a single InGaN layer and a single GaN layer is no greater than 100 nm, and the composition of the InGaN material is In x Ga 1-x N, 0 < x < 1.

[0011] In a preferred embodiment of the present invention, the multi-quantum-well active layer is composed of alternating InGaN / GaN layers, with a maximum of 40 layers; wherein the thickness of a single InGaN layer and a single GaN layer is no greater than 100 nm, and the composition of the InGaN material is In x Ga 1-x N, 0 < x < 1.

[0012] In a preferred embodiment of the present invention, the thickness of the β-Ga2O3 intermediate layer is no greater than 100 nm.

[0013] In a preferred embodiment of the present invention, the thickness of the indium tin oxide current diffusion layer is no greater than 500 nm.

[0014] In a preferred embodiment of the present invention, the substrate includes Al2O3, Si, GaN, and SiC.

[0015] This invention also provides a fabrication process for an LED chip structure based on a gallium oxide interlayer, comprising the following steps:

[0016] S1. Evaporate or sputter an AlN nucleation layer on the substrate surface;

[0017] S2. A U-GaN buffer layer is grown on the surface of the AlN nucleation layer;

[0018] S3. An N-GaN layer is grown at high temperature on the surface of the U-GaN buffer layer;

[0019] S4. Alternately grow InGaN / GaN on the N-GaN layer to form a superlattice structure and create a superlattice stress relief layer;

[0020] S5. A multi-quantum well structure is grown on the superlattice stress relief layer to form a multi-quantum well active layer composed of alternating InGaN well layers and GaN barrier layers.

[0021] S6. Grow a P-GaN layer on the multi-quantum-well active layer;

[0022] S7. Growing heavily doped P-GaN layers on the P-GaN layer. + -GaN, as an ohmic contact layer;

[0023] S8. Prepare a Ga2O3 thin film on the ohmic contact layer to form a β-Ga2O3 intermediate layer;

[0024] S9. An ITO thin film is deposited on the β-Ga2O3 intermediate layer as an indium tin oxide current diffusion layer.

[0025] In a preferred embodiment of the present invention, in step S8, a GaN layer with a preferred thickness of 20 nm is grown on the ohmic contact layer. After growth, it is oxidized in oxygen plasma at a pressure of 1.0 Torr, an oxygen flow rate of 12 sccm, a temperature of 150-200 °C, and an oxidation time of 30 minutes, so that the GaN surface layer is transformed into a β-Ga2O3 thin film with a thickness of about 10 nm.

[0026] Compared with the prior art, this technical solution has the following advantages:

[0027] 1. This invention fully utilizes the unique physical properties of the β-Ga2O3 / GaN heterojunction to achieve improved device performance based on efficient current diffusion of a two-dimensional electron gas. A significant conduction band shift exists between gallium oxide (~4.9 eV) and gallium nitride (~3.4 eV), and a triangular potential well is generated at the heterojunction interface formed by their contact due to band bending. Under the action of an applied electric field, electrons are confined within this potential well, forming a highly mobile two-dimensional electron gas. In contrast, schematic diagrams of the band structure with and without the gallium oxide interlayer are shown below. Figure 2 As shown, this two-dimensional electron gas possesses extremely high in-plane electron mobility, serving as a superconducting lateral current propagation channel. This allows current to diffuse rapidly and uniformly throughout the active region of the device, significantly suppressing current crowding effects. This not only improves current injection efficiency and reduces heat accumulation caused by local carrier saturation but also effectively enhances the device's luminous brightness and uniformity, preventing the formation of local hot spots, thereby improving the device's reliability and lifespan.

[0028] 2. This invention improves external quantum efficiency through the synergistic effect of low-resistivity ohmic contact and high light extraction efficiency; excellent ohmic contact can be formed between β-Ga2O3 and p-Ga2O3, with a contact resistivity as low as 10. -4 Ω·cm 2 The magnitude is comparable to that of traditional indium tin oxide (ITO) contacts (typically 10). -2 Ω·cm 2 The device exhibits significant advantages in terms of light transmittance (on the order of magnitude). Simultaneously, β-Ga₂O₃ possesses extremely high optical transmittance in the visible light band, successfully resolving the technical contradiction of metal electrodes exhibiting good conductivity but lacking light transmittance. This combination of high conductivity and high transmittance ensures efficient current injection while minimizing photon absorption losses by the electrodes, thereby significantly improving the device's light extraction efficiency. The synergistic optimization of ohmic contact and light extraction efficiency jointly contributes to a comprehensive improvement in the device's external quantum efficiency.

[0029] 3. The fabrication process of this invention has good compatibility and cost-effectiveness; the β-Ga2O3 thin film can be controlled and adjusted precisely by controlling parameters such as oxygen atmosphere, temperature, and pressure. This fabrication process is highly compatible with the existing manufacturing process of gallium nitride-based optoelectronic devices, requires no complex or expensive additional equipment, has simple steps, good repeatability, and good controllability and scalability, laying a solid foundation for large-scale industrial applications. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the epitaxial structure of an LED chip based on a β-Ga2O3 intermediate layer, as shown in the example.

[0031] Figure 2 (a) is the band structure diagram of the two-dimensional electron gas formed by β-Ga2O3 with ITO and gallium nitride in the embodiment, and (b) is the band structure diagram of the heterojunction interface of β-Ga2O3 and ITO in the embodiment.

[0032] Figure 3 The example shows the current conduction and light emission patterns of a gallium oxide intermediate layer.

[0033] Figure 4 This is a schematic diagram illustrating current diffusion using two-dimensional cavitation gas as an example. Detailed Implementation

[0034] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Example

[0036] This embodiment provides a fabrication process for an LED chip structure based on a gallium oxide interlayer, including the following steps:

[0037] (1) An AlN layer was grown on the substrate to form a nucleation layer. The growth temperature was 850 ℃, the pressure was 150 Torr, the precursor was trimethylaluminum (TMAl), and the molar flow rate was controlled at 15 μmol / min. High-purity ammonia (NH3) was used as the nitrogen source with a flow rate of 5 slm and the AlN thickness was 100 nm.

[0038] (2) A U-GaN layer was grown on AlN as a buffer layer. Using trimethylgallium (TMGa) and high-purity ammonia (NH3) as precursors, an undoped GaN layer with a thickness of 2 μm was grown in an H2 carrier gas atmosphere at a growth temperature of 1050 °C and a reaction chamber pressure of 100 Torr.

[0039] (3) An N-GaN layer was grown on U-GaN, using silane as the n-type dopant source. The growth temperature was 1020 ℃, the pressure was 100 Torr, the precursor was trimethylgallium (TMGa), and an appropriate amount of SiH4 was introduced to control the carrier concentration at 5E18 cm⁻¹. -3 The final growth thickness was 2.5 μm.

[0040] (4) A superlattice stress-relieving layer was grown on N-GaN. The structure consisted of 10 alternating InGaN / GaN layers. The growth temperature was 780 °C, the pressure was 200 Torr, the thickness of each InGaN layer was 10 nm, the thickness of each GaN layer was 10 nm, trimethylindium (TMIn) and trimethylgallium (TMGa) were used as group III sources, and high-purity N2 was used as the carrier gas. The total thickness was 200 nm.

[0041] (5) A multi-quantum-well active layer was grown on the stress-relief layer. The structure consisted of 12 alternating InGaN / GaN layers. The quantum well layer was grown at a temperature of 750 °C, the quantum barrier layer at a temperature of 850 °C, and the pressure was 200 Torr. The thickness of each InGaN quantum well was 3 nm, and the thickness of each GaN quantum barrier was 12 nm. Trimethylindium (TMIn) and trimethylgallium (TMGa) were used as group III sources, and high-purity N2 was used as the carrier gas. The total thickness was 180 nm.

[0042] (6) P-GaN was grown on multiple quantum wells using dicyclopentadienyl magnesium (Cp2Mg) as the p-type dopant source at a growth temperature of 930 °C and a pressure of 100 Torr. Trimethylgallium (TMGa) was used as the gallium source, and the hole concentration was made up to 5E17 cm⁻¹ by controlling the Cp2Mg flow rate. -3 The final growth thickness was 0.2 μm.

[0043] (7) An ohmic contact layer was grown on P-GaN using highly doped InGaN material and dicyclopentadienyl magnesium (Cp2Mg) as the p-type dopant source. The growth temperature was 800 °C and the pressure was 100 Torr. The hole concentration was increased to 1E19 cm by significantly increasing the Cp2Mg flux. -3 The final growth thickness is 20 nm.

[0044] (8) A 20 nm thick undoped GaN layer was grown on the ohmic contact layer using trimethylgallium (TMGa) as a precursor in a nitrogen atmosphere of 800 °C and 100 Torr. After growth, the GaN layer was oxidized in oxygen plasma at a pressure of 1.0 Torr and an oxygen flow rate of 12 sccm at a temperature of 150-200 °C for 30 minutes to transform the GaN surface layer into a β-Ga2O3 thin film with a thickness of about 10 nm.

[0045] (9) An ITO transparent conductive layer was deposited on the surface of the gallium oxide thin film by electron beam evaporation, using indium tin oxide (ITO) as the evaporation source, at a substrate temperature of 150 °C and a 5 × 10⁻⁶ Ω·cm evaporation rate. -3 ITO films were deposited under a vacuum of Pa, with the deposition rate controlled at 0.2 nm / s, resulting in a thickness of 150 nm. The films were then annealed in air at 500 °C for 30 minutes to optimize light transmittance and conductivity.

[0046] The LED chip structure based on a gallium oxide interlayer fabricated in this embodiment comprises, sequentially, a substrate, an AlN nucleation layer, a U-GaN buffer layer, an N-GaN layer, a superlattice stress relief layer, a multi-quantum-well active layer, a P-GaN layer, an ohmic contact layer, a gallium oxide interlayer, and an indium tin oxide current diffusion layer. A two-dimensional electron gas is formed at the heterojunction interface between the gallium oxide interlayer and the ohmic contact layer for lateral current diffusion; the gallium oxide interlayer and the indium tin oxide current diffusion layer form a low-resistance path for longitudinal current transport. Figures 2 to 4 In this embodiment, a heterojunction band structure is designed to form a two-dimensional electron gas and a two-dimensional hole gas to enhance the lateral migration of current and thus enhance the current diffusion, thereby improving the brightness, uniformity, heat dissipation, lifespan and stability of the LED.

[0047] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An LED chip structure based on a gallium oxide interlayer, characterized in that: The substrate is sequentially provided with an AlN nucleation layer, a U-GaN buffer layer, an N-GaN layer, a superlattice stress relief layer, a multi-quantum well active layer, a P-GaN layer, an ohmic contact layer, a β-Ga2O3 intermediate layer, and an indium tin oxide current diffusion layer. A two-dimensional electron gas is formed at the heterojunction interface between the β-Ga2O3 intermediate layer and the ohmic contact layer for lateral diffusion of current; the β-Ga2O3 intermediate layer and the indium tin oxide current diffusion layer form a low-resistance path for longitudinal current transmission.

2. The LED chip structure based on a gallium oxide interlayer according to claim 1, characterized in that: The thickness of the AlN nucleation layer is no greater than 1000 nm.

3. The LED chip structure based on a gallium oxide interlayer according to claim 1, characterized in that: The thickness of the U-GaN buffer layer is 200 nm to 5000 nm; the thickness of the N-GaN layer is 200 to 5000 nm, and the doping concentration is 10. 17 ~10 19 cm -3 The thickness of the P-GaN layer is 20–500 nm, and the doping concentration is 10. 18 ~10 19 cm -3 The thickness of the ohmic contact layer is 20–500 nm, and the doping concentration is 10. 19 ~10 20 cm -3 .

4. The LED chip structure based on a gallium oxide interlayer according to claim 1, characterized in that: The superlattice stress relief layer is composed of alternating InGaN / GaN layers, with a maximum of 40 layers; wherein the thickness of a single InGaN layer and a single GaN layer is no greater than 100 nm, and the composition of the InGaN material is In x Ga 1-x N, 0 < x < 1.

5. The LED chip structure based on a gallium oxide interlayer according to claim 1, characterized in that: The multi-quantum-well active layer is composed of alternating InGaN / GaN layers, with a maximum of 40 layers; wherein the thickness of a single InGaN layer and a single GaN layer is no greater than 100 nm, and the composition of the InGaN material is In x Ga 1-x N, 0 < x < 1.

6. The LED chip structure based on a gallium oxide interlayer according to claim 1, characterized in that: The thickness of the β-Ga2O3 intermediate layer is no greater than 100 nm.

7. The LED chip structure based on a gallium oxide interlayer according to claim 1, characterized in that: The thickness of the indium tin oxide current diffusion layer is no greater than 500 nm.

8. The LED chip structure based on a gallium oxide interlayer according to claim 1, characterized in that: The substrate includes Al2O3, Si, GaN, and SiC.

9. The fabrication process of an LED chip structure based on a gallium oxide interlayer as described in any one of claims 1 to 8, characterized in that: Includes the following steps: S1. Evaporate or sputter an AlN nucleation layer on the substrate surface; S2. A U-GaN buffer layer is grown on the surface of the AlN nucleation layer. S3. A layer of N-GaN is grown at high temperature on the surface of the U-GaN buffer layer. S4. Alternately grow InGaN / GaN on the N-GaN layer to form a superlattice structure and create a superlattice stress relief layer; S5. A multi-quantum well structure is grown on the superlattice stress relief layer to form a multi-quantum well active layer composed of alternating InGaN well layers and GaN barrier layers. S6. Grow a P-GaN layer on the multi-quantum-well active layer; S7. Growing heavily doped P-GaN layers on the P-GaN layer. + -GaN, as an ohmic contact layer; S8. Prepare a Ga2O3 thin film on the ohmic contact layer to form a β-Ga2O3 intermediate layer; S9. An ITO thin film is deposited on the β-Ga2O3 intermediate layer as an indium tin oxide current diffusion layer.

10. The fabrication process of an LED chip structure based on a gallium oxide interlayer according to claim 9, characterized in that: In step S8, using trimethylgallium as a precursor, a GaN layer is grown on the ohmic contact layer under a nitrogen atmosphere of 800 °C and 100 Torr. After growth, it is oxidized in oxygen plasma at a pressure of 1.0 Torr and an oxygen flow rate of 12 sccm, at a temperature of 150-200 °C, for 30 minutes, so that the GaN surface layer is transformed into a β-Ga2O3 film. The thickness of the β-Ga2O3 film is not greater than the thickness of the GaN.

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