Display panel and display device

Abstract

This application discloses a display panel and a display device, belonging to the field of display technology. The display panel includes a receiving substrate and multiple pad groups. The receiving substrate has a main body and an edge portion surrounding the main body. Multiple pad groups are disposed on the main body and the edge portion, and the pad groups are configured to bond light-emitting chips. The spacing between two adjacent pad groups on the main body is greater than the spacing between two adjacent pad groups on the edge portion. This application can improve the production yield of the display panel and enhance its display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In the related technology, the manufacturing process of a micro light-emitting diode (Micro LED) display panel requires mass transfer to bond multiple micro light-emitting diodes onto multiple pads on a receiving substrate.

[0003] However, due to the high temperature of the bonding environment and the different coefficients of thermal expansion of the materials of the receiving substrate, the pads, and the micro-LEDs, non-uniform thermal expansion deformation occurs during the heating stage. This causes positional shifts in the bonding between the micro-LEDs and the pads on the receiving substrate, typically at the micrometer and sub-micrometer levels. Since the pixel pitch of the micro-LEDs is extremely small (usually less than or equal to 50 micrometers), these positional shifts significantly affect the bonding. During heating, the thermal expansion at the edges of the receiving substrate is greater than that in the center, resulting in a relatively large bonding offset between the pads and the LEDs at the edges. This leads to defects such as color mixing, uneven brightness, short circuits, or open circuits in the LEDs at the edges of the bonded display panel, significantly reducing the production yield and affecting the display effect.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide a display panel and a display device that can improve the production yield of the display panel and improve the display effect of the display panel.

[0006] To solve the above problems, the technical solution of this application is as follows: In a first aspect, this application proposes a display panel, comprising: A receiving substrate has a main body and an edge portion disposed around the main body; and Multiple pad groups are disposed on the main body and the edge portion, and the pad groups are configured to bond light-emitting chips; The spacing between two adjacent pad groups on the main body is greater than the spacing between two adjacent pad groups on the edge.

[0007] In one embodiment of this application, the plurality of pad groups include a plurality of first pad groups and a plurality of second pad groups, wherein the plurality of first pad groups are disposed on the main body portion and the plurality of second pad groups are disposed on the edge portion; The ratio of the spacing between two adjacent first pad groups to the spacing between two adjacent second pad groups is greater than or equal to 1.01.

[0008] In one embodiment of this application, the difference between the spacing between two adjacent first pad groups and the spacing between two adjacent second pad groups is greater than or equal to 1 micrometer.

[0009] In one embodiment of this application, the ratio of the spacing between two adjacent first pad groups to the spacing between two adjacent second pad groups is less than or equal to 1.5.

[0010] In one embodiment of this application, the difference between the spacing between two adjacent first pad groups and the spacing between two adjacent second pad groups is less than or equal to 70 micrometers.

[0011] In one embodiment of this application, the spacing between two adjacent first pad groups is less than or equal to 200 micrometers; The spacing between two adjacent second pad groups is greater than or equal to 134 micrometers.

[0012] In one embodiment of this application, in a plan view of the display panel, the ratio of the area of ​​the main body to the area of ​​the receiving substrate is in the range of 0.4 to 0.8.

[0013] In one embodiment of this application, when the ambient temperature is a first temperature, the ratio of the distance between two adjacent first pad groups to the distance between two adjacent second pad groups is a first ratio. When the ambient temperature is the second temperature, the ratio of the spacing between two adjacent first pad groups to the spacing between two adjacent second pad groups is the second ratio value; Wherein, the first temperature is lower than the second temperature, and the first ratio is greater than the second ratio.

[0014] In one embodiment of this application, in a plan view of the display panel, When the ambient temperature is the first temperature, the ratio of the area of ​​the edge portion to the area of ​​the main body portion is the third ratio. When the ambient temperature is the second temperature, the ratio of the area of ​​the edge portion to the area of ​​the main body portion is the fourth ratio. The third ratio is greater than the fourth ratio.

[0015] In one embodiment of this application, the display panel further includes: Multiple first light-emitting chips, wherein the first light-emitting chips are bonded to the first pad group; Multiple second light-emitting chips are bonded to the second pad group; The distance between two adjacent first light-emitting chips is greater than the distance between two adjacent second light-emitting chips.

[0016] In one embodiment of this application, each first light-emitting chip includes two first electrodes, each first pad group includes two spaced-apart first sub-pads, the first electrodes are bonded to the first sub-pads, and the bonding offset between the first electrodes and the first sub-pads is less than or equal to 3 micrometers; and / or, Each of the second light-emitting chips includes two second electrodes, and each of the second pad groups includes two spaced-apart second sub-pads. The second electrodes are bonded to the second sub-pads, and the bonding offset between the second electrodes and the second sub-pads is less than or equal to 3 micrometers.

[0017] Secondly, this application proposes a display device, including a display panel, the display panel comprising: A receiving substrate has a main body and an edge portion disposed around the main body; and Multiple pad groups are disposed on the main body and the edge portion, and the pad groups are configured to bond light-emitting chips; The spacing between two adjacent pad groups on the main body is greater than the spacing between two adjacent pad groups on the edge.

[0018] Before bonding the multiple pad groups to the light-emitting chip in this application, at temperatures below the bonding environment, the spacing between two adjacent pad groups on the edge is smaller than the spacing between two adjacent pad groups on the main body. During bonding of the pad groups to the light-emitting chip, the receiving substrate with the pad groups needs to be placed in the bonding environment. Due to the increased ambient temperature and the greater thermal expansion of the edge than the receiving substrate, the spacing between two adjacent pad groups on the main body is approximately equal to the spacing between two adjacent pad groups on the edge in the bonding environment. This reduces the bonding offset between the pad groups on the edge and the light-emitting chip, improves the production yield of the display panel, and enhances the display effect. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0021] Figure 1 This is a schematic diagram of the receiving substrate, pads, and light-emitting chip in a room temperature environment related to this technology. Figure 2 This is a schematic diagram of the receiving substrate, pads, and light-emitting chip in the bonding environment of related technologies; Figure 3 This is a plan view of an embodiment of the receiving substrate of this application at a temperature below the bonding environment; Figure 4 This is a plan view of an embodiment of the receiving substrate of this application being in the temperature of the bonding environment; Figure 5 This is a flowchart of a method for manufacturing the display panel of this application; Figure 6 yes Figure 5 The diagram shown illustrates step S1 in the method for manufacturing the display panel of this application. Figure 7 yes Figure 5 The diagram shown illustrates step S2 in the method for manufacturing the display panel of this application. Figure 8 yes Figure 5 The diagram shown illustrates step S3 in the method for manufacturing the display panel of this application. Figure 9 yes Figure 5 The diagram shown illustrates step S4 in the method for manufacturing the display panel of this application. Figure 10 yes Figure 5 The diagram shown illustrates step S5 in the method for manufacturing the display panel of this application. Figure 11 This is a schematic diagram of an initial pad substrate and a light-emitting chip in a normal temperature environment; Figure 12 yes Figure 11 The diagram shows the initial pad substrate and the light-emitting chip after being heated from room temperature to the bonding environment. Figure 13 This is another schematic diagram of the initial pad substrate and light-emitting chip in a normal temperature environment; Figure 14 yes Figure 13 The diagram shows the initial pad substrate and the light-emitting chip after being heated from room temperature to the bonding environment. Figure 15 This is a schematic diagram of the receiving substrate, pads, and light-emitting chip in a normal temperature environment according to the fourth embodiment.

[0022] Explanation of reference numerals in the attached figures: 100. Display panel; 10. Receiving substrate; D1, First direction; P1, initial bonding position; P11, first initial bonding position; P12, second initial bonding position; P2, target bonding position; P21, first target bonding position; P22, second target bonding position; K, compensation data; K1, first compensation data; K2, second compensation data; M, thermally induced offset vector; M1, first thermally induced offset vector; M2, second thermally induced offset vector; 11. Main body; 12. Edges; 20. Pad group; 21. Initial pad group; 211. First initial pad group; 212. Second initial pad group; 22. First pad group; 23. Second pad group; 30. Light-emitting chip; 31. First light-emitting chip; 32. Second light-emitting chip; 40. Initial pad substrate; 50. Pad group; 51. First pad group; 52. Second pad group; 61. First light-emitting chip; 62. Second light-emitting chip. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0024] In the related technology, during the fabrication of a Micro LED display panel, multiple Micro LEDs need to be bonded to multiple pads 20a on a receiving substrate through mass transfer.

[0025] However, due to the high temperature of the bonding environment, the materials of the receiving substrate 10a, the pad 20a, and the micro-LED 30a have different coefficients of thermal expansion. Therefore, the micro-LED 30a, the receiving substrate 10a, and the pad 20a will undergo non-uniform thermal expansion deformation during the heating stage. This causes the bonding position between the micro-LED 30a and the pad 20a on the receiving substrate to shift due to thermal expansion deformation. This shift is typically at the micrometer and sub-micrometer level. However, the pixel pitch of the micro-LED is extremely small (usually less than or equal to 50 micrometers). The positional shift caused by thermal expansion deformation will greatly affect the bonding of the micro-LED, resulting in serious defects in the display panel such as color mixing, uneven brightness, short circuits, or open circuits. This significantly reduces the production yield of the display panel and affects the display effect.

[0026] Please see Figure 1 In related technologies, pads 20a are provided on the receiving substrate 10a, and the light-emitting chip 30a is transferred to the pads 20a of the receiving substrate 10a in a normal temperature environment, and the light-emitting chip 30a is aligned with the pads 20a.

[0027] Please see Figure 2 When the temperature is increased from room temperature to bonding environment, the light-emitting chip 30a, pad 20a and receiving substrate 10a undergo thermal expansion and deformation. Due to the difference in the coefficient of thermal expansion of the light-emitting chip 30a, pad 20a and receiving substrate 10a, the light-emitting chip 30a cannot be aligned with the pad 20a after heating. In severe cases, defects such as color mixing, uneven brightness, short circuit or open circuit will occur, which significantly reduces the production yield of display panel 100a.

[0028] This application discloses a display device, which can be a tablet computer, e-reader, electronic display screen, laptop computer, mobile phone, augmented reality (AR) / virtual reality (VR) device, media player, wearable device, digital camera, car navigation system, etc. The display device includes a display panel.

[0029] Please see Figure 3 This application proposes a display panel, which is a micro light-emitting diode display panel.

[0030] The display panel can be manufactured using the display panel manufacturing method described in this application.

[0031] The display panel includes a receiving substrate 10 and multiple pad groups 50.

[0032] The receiving substrate 10 has a main body portion 11 and an edge portion 12 disposed around the main body portion 11.

[0033] Multiple pad groups 50 are provided on the main body 11 and the edge portion 12. The pad groups 50 are configured to bond light-emitting chips.

[0034] Among them, the distance E1 between two adjacent pad groups 50 on the main body 11 is greater than the distance E2 between two adjacent pad groups 50 on the edge 12.

[0035] Please see Figure 3 In this embodiment, before the multiple pad groups 50 are bonded to the light-emitting chip, at a temperature lower than the bonding environment, the distance E2 between two adjacent pad groups 50 located on the edge portion 12 is smaller than the distance E1 between two adjacent pad groups 50 located on the main body portion 11. When bonding the pad groups 50 to the light-emitting chip, the receiving substrate 10 with the pad groups 50 needs to be placed in the bonding environment. Because the ambient temperature rises and the thermal expansion of the edge portion 12 is greater than that of the receiving substrate 10, please refer to... Figure 4 In the bonding environment, the spacing E3 between two adjacent pad groups 50 on the main body 11 is approximately equal to the spacing E4 between two adjacent pad groups 50 on the edge 12, thereby reducing the bonding offset between the pad groups 50 on the edge 12 and the light-emitting chip, improving the production yield of the display panel, and improving the display effect of the display panel.

[0036] Optionally, the plurality of pad groups 50 includes a plurality of first pad groups 51 and a plurality of second pad groups 52. The plurality of first pad groups 51 are disposed on the main body portion 11. The plurality of second pad groups 52 are disposed on the edge portion 12.

[0037] The ratio of the spacing E1 between two adjacent first pad groups 51 to the spacing E2 between two adjacent second pad groups 52 is greater than or equal to 1.01.

[0038] In this embodiment, the ratio of the spacing E1 between two adjacent first pad groups 51 to the spacing E2 between two adjacent second pad groups 52 can be 1.01, 1.02, 1.03, 1.04, 1.05, 1.06, 1.07, 1.08, 1.09, 1.10, 1.11, 1.12, 1.13, 1.14, 1.15, 1.16, 1.17, 1.18, 1.19, 1.20, 1 .21, 1.22, 1.23, 1.24, 1.25, 1.26, 1.27, 1.28, 1.29, 1.30, 1.31, 1.32, 1.33, 1.34, 1.35, 1.36, 1.37, 1.38, 1.39, 1.40, 1.41, 1.42, 1.43, 1.44, 1.45, 1.46, 1.47, 1.48, 1.49, 1.50, etc.

[0039] When the display panel is applied to small-sized display devices, such as electronic watches and micro screens, the ratio of the distance E1 between two adjacent first pad groups 51 to the distance E2 between two adjacent second pad groups 52 can be relatively small, thereby reducing the bonding offset between the second pad group 52 on the edge portion 12 and the second light-emitting chip 62, improving the production yield of the display panel, and improving the display effect of the display panel.

[0040] Optionally, the ratio of the spacing E1 between two adjacent first pad groups 51 to the spacing E2 between two adjacent second pad groups 52 is less than or equal to 1.5.

[0041] In this embodiment, when the display panel is applied to a large-size display device, such as a television, computer screen, or laptop screen, the ratio of the distance E1 between two adjacent first pad groups 51 to the distance E2 between two adjacent second pad groups 52 can be relatively large, thereby reducing the bonding offset between the second pad group 52 on the edge portion 12 and the second light-emitting chip 62, improving the production yield of the display panel, and improving the display effect of the display panel.

[0042] However, when the ratio of the distance E1 between two adjacent first pad groups 51 to the distance E2 between two adjacent second pad groups 52 is too large, a new problem arises: after bonding and returning to room temperature, the distance E1 between two adjacent first pad groups 51 is greater than the distance E2 between two adjacent second pad groups 52. At this time, the multiple first pad groups 51 on the main body 11 are sparsely arranged, while the multiple second pad groups 52 on the edge portion 12 are densely arranged. When the display panel is on, the edge portion 12 of the display panel is brighter, but the central portion is darker. To improve the brightness uniformity between the edge portion 12 and the central portion of the display panel, this embodiment limits the ratio of the distance E1 between two adjacent first pad groups 51 to the distance E2 between two adjacent second pad groups 52 to less than or equal to 1.5. This improves the overall brightness uniformity of the display panel and enhances the display effect.

[0043] Optionally, the ratio of the spacing E1 between two adjacent first pad groups 51 to the spacing E2 between two adjacent second pad groups 52 is in the range of 1.01 to 1.5.

[0044] Optionally, the difference between the spacing E1 between two adjacent first pad groups 51 and the spacing E2 between two adjacent second pad groups 52 is greater than or equal to 1 micrometer.

[0045] In this embodiment, the difference between the spacing E1 between two adjacent first pad groups 51 and the spacing E2 between two adjacent second pad groups 52 can be 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, 10 micrometers, 11 micrometers, 12 micrometers, 13 micrometers, 14 micrometers, 15 micrometers, 16 micrometers, 17 micrometers, 18 micrometers, 19 micrometers, 20 micrometers, 21 micrometers, 22 micrometers, 23 micrometers, 24 micrometers, 25 micrometers, 26 micrometers, 27 micrometers, 28 micrometers, 29 micrometers, 30 micrometers, or 31 micrometers. 32 micrometers, 33 micrometers, 34 micrometers, 35 micrometers, 36 micrometers, 37 micrometers, 38 micrometers, 39 micrometers, 40 micrometers, 41 micrometers, 42 micrometers, 43 micrometers, 44 micrometers, 45 micrometers, 46 micrometers, 47 micrometers, 48 ​​micrometers, 49 micrometers, 50 micrometers, 51 micrometers, 52 micrometers, 53 micrometers, 54 micrometers, 55 micrometers, 56 micrometers, 57 micrometers, 58 micrometers, 59 micrometers, 60 micrometers, 61 micrometers, 62 micrometers, 63 micrometers, 64 micrometers, 65 micrometers, 66 micrometers, 67 micrometers, 68 micrometers, 69 micrometers, 70 micrometers, etc.

[0046] When the display panel is applied to small-sized display devices, such as electronic watches and micro screens, the difference between the spacing E1 between two adjacent first pad groups 51 and the spacing E2 between two adjacent second pad groups 52 can be relatively small, thereby reducing the bonding offset between the second pad group 52 on the edge portion 12 and the second light-emitting chip 62, improving the production yield of the display panel, and improving the display effect of the display panel.

[0047] Optionally, the difference between the spacing E1 between two adjacent first pad groups 51 and the spacing E2 between two adjacent second pad groups 52 is less than or equal to 70 micrometers.

[0048] In this embodiment, when the display panel is applied to a large-size display device, such as a television, computer screen, or laptop screen, the difference between the spacing E1 between two adjacent first pad groups 51 and the spacing E2 between two adjacent second pad groups 52 can be relatively large, thereby reducing the bonding offset between the second pad group 52 on the edge portion 12 and the second light-emitting chip 62, improving the production yield of the display panel, and improving the display effect of the display panel.

[0049] However, when the difference between the spacing E1 between two adjacent first pad groups 51 and the spacing E2 between two adjacent second pad groups 52 is too large, a new problem arises: after bonding and returning to room temperature, the spacing E1 between two adjacent first pad groups 51 is greater than the spacing E2 between two adjacent second pad groups 52. At this time, the multiple first pad groups 51 on the main body 11 are sparsely arranged, while the multiple second pad groups 52 on the edge portion 12 are densely arranged. When the display panel is on, the edge portion 12 of the display panel is brighter, but the central portion is darker. To improve the brightness uniformity between the edge portion 12 and the central portion of the display panel, this embodiment limits the difference between the spacing E1 between two adjacent first pad groups 51 and the spacing E2 between two adjacent second pad groups 52 to less than or equal to 70 micrometers. This improves the overall brightness uniformity of the display panel and enhances the display effect.

[0050] Optionally, the spacing E1 between two adjacent first pad groups 51 is less than or equal to 200 micrometers.

[0051] In this embodiment, when the bonding process returns to room temperature, the distance E1 between two adjacent first pad groups 51 is greater than the distance E2 between two adjacent second pad groups 52. At this time, the multiple first pad groups 51 on the main body 11 are sparsely arranged, while the multiple second pad groups 52 on the edge portion 12 are densely arranged. When the display panel is on display, the edge portion 12 of the display panel appears brighter, while the central portion is darker. To improve the brightness uniformity between the edge portion 12 and the central portion of the display panel, this embodiment limits the distance E1 between two adjacent first pad groups 51 to less than or equal to 200 micrometers. This increases the density of the multiple first pad groups 51 on the main body 11, resulting in a relatively higher brightness at the location of the main body 11. This improves the overall brightness uniformity of the display panel and enhances the display effect.

[0052] Optionally, the spacing E1 between two adjacent first pad groups 51 is in the range of 135 micrometers to 200 micrometers.

[0053] In this embodiment, the spacing E1 between two adjacent first pad groups 51 can be 135 micrometers, 140 micrometers, 145 micrometers, 150 micrometers, 155 micrometers, 160 micrometers, 165 micrometers, 170 micrometers, 175 micrometers, 180 micrometers, 185 micrometers, 190 micrometers, 195 micrometers, 200 micrometers, etc.

[0054] Optionally, the spacing E2 between two adjacent second pad groups 52 is greater than or equal to 134 micrometers.

[0055] In this embodiment, when the bonding process returns to room temperature, the distance E1 between two adjacent first pad groups 51 is greater than the distance E2 between two adjacent second pad groups 52. At this time, the multiple first pad groups 51 on the main body 11 are sparsely arranged, while the multiple second pad groups 52 on the edge portion 12 are densely arranged. When the display panel is on, the edge portion 12 of the display panel appears brighter, while the central portion is darker. To improve the brightness uniformity between the edge portion 12 and the central portion of the display panel, this embodiment limits the distance E2 between two adjacent second pad groups 52 to greater than or equal to 134 micrometers. This reduces the density of the multiple second pad groups 52 on the edge portion 12, resulting in a relatively lower brightness at the edge portion 12, thereby improving the overall brightness uniformity of the display panel and enhancing the display effect.

[0056] Optionally, the spacing E2 between two adjacent second pad groups 52 is in the range of 134 micrometers to 199 micrometers.

[0057] In this embodiment, the spacing E2 between two adjacent second pad groups 52 can be 134 micrometers, 139 micrometers, 144 micrometers, 149 micrometers, 154 micrometers, 159 micrometers, 164 micrometers, 169 micrometers, 174 micrometers, 179 micrometers, 184 micrometers, 189 micrometers, 194 micrometers, 199 micrometers, etc.

[0058] Optionally, the display panel may also include a plurality of first light-emitting chips 61 and a plurality of second light-emitting chips 62.

[0059] The first light-emitting chip 61 is bonded to the first pad group 51. The second light-emitting chip 62 is bonded to the second pad group 52.

[0060] Among them, the distance E1 between two adjacent first light-emitting chips 61 is greater than the distance E2 between two adjacent second light-emitting chips 62.

[0061] In this embodiment, the light-emitting chip can be a miniature light-emitting diode or a sub-millimeter light-emitting diode.

[0062] Before bonding, multiple first light-emitting chips 61 and multiple second light-emitting chips 62 are disposed on a transfer plate. The transfer plate includes a central portion and 12 edge portions surrounding the central portion. The multiple first light-emitting chips 61 are disposed in the central portion of the transfer plate, and the multiple second light-emitting chips 62 are disposed in the 12 edge portions of the transfer plate.

[0063] Before bonding, on the transfer board, the distance E1 between two adjacent first light-emitting chips 61 is equal to the distance E2 between two adjacent second light-emitting chips 62.

[0064] During the bonding process, the receiving substrate 10 with pad groups 50 is placed in the bonding environment. Due to the increased ambient temperature and the greater thermal expansion of the edge portion 12 than that of the receiving substrate 10, the spacing E3 between two adjacent pad groups 50 on the main body portion 11 and the spacing E4 between two adjacent pad groups 50 on the edge portion 12 are approximately equal in the bonding environment. At this time, the transfer board is positioned opposite the receiving substrate 10. Each first light-emitting chip 61 can align with the first pad group 51, and each second light-emitting chip 62 can align with the second pad group 52. This reduces the bonding offset between the second light-emitting chip 62 and the second pad group 52, solving the problem of relatively large bonding offset between the pad groups 50 and the light-emitting chips on the edge portion 12 of the receiving substrate 10, improving the production yield of the display panel and enhancing the display effect.

[0065] Optionally, in a plan view of the display panel, the ratio of the area of ​​the main body 11 to the area of ​​the receiving substrate 10 is in the range of 0.4 to 0.8.

[0066] In this embodiment, the main body 11 is surrounded by the edge portion 12. The size of the main body 11 depends on the coefficient of thermal expansion of the material of the receiving substrate 10, the coefficient of thermal expansion of the pad material, the coefficient of thermal expansion of the micro light-emitting diode material, and the size and area of ​​the display panel.

[0067] When the coefficient of thermal expansion of the material of the receiving substrate 10 is relatively large, the thermal expansion of the portion of the receiving substrate 10 closer to the edge is relatively large. Therefore, the proportion of the main body 11 in the receiving substrate 10 can be relatively reduced, thereby increasing the area of ​​the edge portion 12 and reducing the offset between the pad group 50 on the edge portion 12 and the light-emitting chip.

[0068] When the area of ​​the receiving substrate 10 is relatively large, the brightness of the main body 11 will be lower than that of the edge portion 12 because the pad groups 50 on the edge portion 12 are more densely packed while the pad groups 50 on the main body 11 are more sparsely packed. This phenomenon is exacerbated when the area of ​​the edge portion 12 is relatively large, affecting the display effect. Therefore, when the area of ​​the receiving substrate 10 is relatively large, the proportion of the main body 11 in the receiving substrate 10 can be increased, thereby improving the uniformity of the overall brightness of the display panel and improving the display effect.

[0069] Optionally, the edge portion 12 includes a first edge sub-portion and a second edge sub-portion.

[0070] The first edge sub-part is disposed around the main body 11. The second edge sub-part is disposed around the first edge sub-part.

[0071] The spacing between two adjacent pad groups 50 on the main body 11 is greater than the spacing between two adjacent pad groups 50 on the first edge sub-part.

[0072] The spacing between two adjacent pad groups 50 on the first edge sub-part is greater than the spacing between two adjacent pad groups 50 on the second edge sub-part.

[0073] In the relatively large receiving substrate 10, the first edge sub-section is closer to the edge of the receiving substrate 10 than the second edge sub-section. Therefore, the thermal expansion of the first edge sub-section is greater than that of the second edge sub-section. Thus, this embodiment configures the spacing between two adjacent pad groups 50 on the first edge sub-section to be greater than the spacing between two adjacent pad groups 50 on the second edge sub-section. This reduces the bonding offset between the pad groups 50 on the first and second edge sub-sections and the light-emitting chip, improving the production yield of the display panel and enhancing its display effect.

[0074] Optionally, each first light-emitting chip 61 includes two first electrodes. Each first pad group 51 includes two spaced-apart first sub-pads. The first electrodes are bonded to the first sub-pads. The bonding offset between the first electrodes and the first sub-pads is less than or equal to 3 micrometers.

[0075] Each second light-emitting chip 62 includes two second electrodes. Each second pad group 52 includes two spaced-apart second sub-pads. The second electrodes are bonded to the second sub-pads. The bonding offset between the second electrodes and the second sub-pads is less than or equal to 3 micrometers.

[0076] It's important to understand that bond offset is a metric used to evaluate the degree of overlap between the electrode and the sub-pad. When the electrode and sub-pad are perfectly aligned, the bond offset is 0. When the edge of the electrode cannot align with the edge of the sub-pad, the distance between the electrode edge and the sub-pad edge is the bond offset.

[0077] In this embodiment, by differentiating the spacing E1 between two adjacent first pad groups 51 and the spacing E2 between two adjacent second pad groups 52, the bonding offset of the first pad group 51 and the second pad group 52 can be controlled within 3 micrometers after bonding is completed. This reduces the bonding offset between the pad group 50 on the edge portion 12 and the light-emitting chip, improves the production yield of the display panel, and enhances the display effect of the display panel.

[0078] Optionally, when the ambient temperature is a first temperature, the ratio of the spacing E1 between two adjacent first pad groups 51 to the spacing E2 between two adjacent second pad groups 52 is a first ratio.

[0079] When the ambient temperature is the second temperature, the ratio of the spacing E3 between two adjacent first pad groups 51 to the spacing E4 between two adjacent second pad groups 52 is the second ratio.

[0080] Among them, the first temperature is less than the second temperature, and the first ratio is greater than the second ratio. In this embodiment, since the thermal expansion of the edge portion 12 is greater than that of the main body portion 11, as the temperature rises, the increase in the distance between two adjacent second pad groups 52 is greater than the increase in the distance between two adjacent first pad groups 51. Therefore, the first ratio is greater than the second ratio.

[0081] This embodiment utilizes the phenomenon that the thermal expansion of the edge portion 12 is greater than that of the main body portion 11 to differentiate the spacing E1 between adjacent first pad groups 51 and the spacing E2 between adjacent second pad groups 52 at room temperature. This makes the spacing E3 between the first pad groups 51 and the spacing E4 between the second pad groups 52 nearly equal in the bonding environment, thereby reducing the bonding offset between the second pad group 52 and the second light-emitting chip 62, improving the production yield of the display panel, and improving the display effect of the display panel.

[0082] Optionally, in the plan view of the display panel, When the ambient temperature is the first temperature, the ratio of the area of ​​the edge portion 12 to the area of ​​the main body portion 11 is the third ratio.

[0083] When the ambient temperature is the second temperature, the ratio of the area of ​​the edge portion 12 to the area of ​​the main body portion 11 is the fourth ratio.

[0084] The third ratio is greater than the fourth ratio.

[0085] In this embodiment, since the coefficient of thermal expansion of the edge portion 12 is greater than that of the main body portion 11, the amount of thermal expansion of the edge portion 12 is greater than that of the main body portion 11 as the temperature rises. At room temperature, the spacing E2 between adjacent second pad groups 52 is set to be smaller than the spacing E1 between adjacent first pad groups 51. When the temperature rises to the bonding temperature, since the amount of thermal expansion of the edge portion 12 is greater than that of the main body portion 11, the increase in the spacing E4 between two adjacent second pad groups 52 is greater than the increase in the spacing E3 between two adjacent first pad groups 51. This makes the spacing E3 between the first pad groups 51 and the spacing E4 between the second pad groups 52 nearly equal in the bonding environment, thereby reducing the bonding offset between the second pad groups 52 and the second light-emitting chip 62, improving the production yield of the display panel, and improving the display effect of the display panel.

[0086] Please see Figure 5 To address the aforementioned problems, this application proposes a method for manufacturing a display panel 100, comprising the following steps: Step S1: Provide the receiving substrate 10.

[0087] Please see Figure 6In step S1, no pad group 20 is provided on the receiving substrate 10.

[0088] Step S2: Determine multiple initial bonding positions P1 on the receiving substrate 10 for bonding and alignment with multiple light-emitting chips 30 respectively.

[0089] Please see Figure 7 In step S2, a transfer substrate with multiple light-emitting chips 30 on one side can be positioned opposite to a receiving substrate 10, and the orthographic projection of the pins of each light-emitting chip 30 can be recorded on the receiving substrate 10. The orthographic projection of the pins of the light-emitting chip 30 is the initial bonding position P1.

[0090] Step S3: Based on the predetermined compensation data K and the initial bonding position P1, determine the target bonding position P2 of each light-emitting chip 30 on the receiving substrate 10.

[0091] Please see Figure 8 In step S3, based on the initial bonding position P1 of each light-emitting chip 30 and according to the compensation data K, the target bonding position P2 is determined. The target bonding position P2 is the actual position of the pad group 20 on the receiving substrate 10.

[0092] Step S4: Based on the target bonding position P2, fabricate pad groups 20 corresponding to each light-emitting chip 30 on the receiving substrate 10.

[0093] Please see Figure 9 In step S4, after the pad group 20 is fabricated on the target bonding position P2 of the receiving substrate 10, the receiving substrate 10 and the transfer substrate are set opposite each other in a normal temperature environment. The pins of the multiple light-emitting chips 30 are aligned with the initial bonding position P1, and the pins of the multiple light-emitting chips 30 are not aligned with the pad group 20.

[0094] Step S5: Transfer and bond each light-emitting chip 30 to the corresponding pad group 20 of the receiving substrate 10.

[0095] Please see Figure 10 In step S5, the temperature is raised from room temperature to bonding environment, and the light-emitting chip 30, pad group 20 and receiving substrate 10 undergo thermal expansion deformation. Due to the difference in the coefficient of thermal expansion of the light-emitting chip 30, pad group 20 and receiving substrate 10, the light-emitting chip 30 is offset from the initial bonding position P1 to the target bonding position P2 relative to the receiving substrate 10. At this time, the pins of the light-emitting chip 30 are aligned with the corresponding pad group 20.

[0096] In step S5, bonding agent can be applied to the pins of the light-emitting chip 30, or to the pad group 20, or to both the pins of the light-emitting chip 30 and the pad group 20. The bonding agent will melt when heated to the bonding environment, connecting the pins of the light-emitting chip 30 to the pad group 20 to achieve bonding.

[0097] The temperature can be increased from room temperature to the bonding environment by heating, specifically by placing the receiving substrate 10 on a heating plate. The heating plate generates heat, which is transferred to the receiving substrate 10 and the pad assembly 20, causing the bonding agent to melt. Laser heating can also be used, where a laser irradiates the bonding agent, melting it. However, because the pad assembly 20, the receiving substrate 10, and the pins of the light-emitting chip 30 transfer heat, laser heating will also cause thermal expansion of the light-emitting chip 30, the pad assembly 20, and the receiving substrate 10.

[0098] Before fabricating the pad group 20 on the receiving substrate 10 of this application, the initial bonding position P1 of the light-emitting chip 30 is first determined on the receiving substrate 10, and the target bonding position P2 is determined based on the predetermined compensation data K. The compensation data K is determined based on the offset between the light-emitting chip 30 and the pad group 20 under normal temperature and bonding environments. The pad group 20 is fabricated at the target bonding position P2. The light-emitting chip 30 is transferred to the receiving substrate 10 under normal temperature environment. Under normal temperature environment, each light-emitting chip 30 is located at the initial bonding position P1, at which time the pins of the light-emitting chip 30 are not aligned with the corresponding pad group 20. Then, the temperature is raised from room temperature to the bonding environment. The light-emitting chip 30, pad group 20, and receiving substrate 10 undergo thermal expansion and deformation. Due to the difference in the coefficients of thermal expansion among the light-emitting chip 30, pad group 20, and receiving substrate 10, the light-emitting chip 30 shifts relative to the receiving substrate 10 from the initial bonding position P1 to the target bonding position P2. At this point, the pins of the light-emitting chip 30 are aligned with the corresponding pad group 20. Before fabricating the pad group 20, this application determines compensation data K based on the offset between the light-emitting chip 30 and the pad group 20, and determines the actual fabrication position of the pad group 20 as the target bonding position P2 based on the compensation data K and the initial bonding position P1. This can reduce the impact of the positional shift caused by the thermal expansion and deformation of the light-emitting chip 30, pad group 20, and receiving substrate 10 on the bonding of the micro-light-emitting diode, improve the production yield of the display panel 100, and improve the display effect of the display panel 100.

[0099] Optionally, the light-emitting chip 30 is a micro LED. The pixel pitch of the micro LED is less than or equal to 50 micrometers.

[0100] Optionally, the substrate material of the light-emitting chip 30 can be sapphire or gallium nitride.

[0101] Optionally, the substrate material of the receiving substrate 10 may be glass or silicon, etc.

[0102] Alternatively, the pad group 20 can be made of metal.

[0103] It can be seen that the coefficients of thermal expansion of the light-emitting chip 30, the receiving substrate 10, and the pad group 20 are different.

[0104] Optionally, the method for manufacturing the display panel 100 further includes the following steps: S01: An initial pad substrate 40 is provided. The initial pad substrate 40 includes a receiving substrate 10 and an initial pad group 21 disposed on the receiving substrate 10. The initial pad group 21 is fabricated on the receiving substrate 10 based on the initial bonding position P1.

[0105] It should be understood that steps S01 to S04 are performed before step S3: determining the target bonding position P2.

[0106] In step S01, it is important to understand that the initial pad substrate 40 is not the actual product of the display panel 100, but rather a process product of the display panel 100. It is only used to determine the compensation data K. After the compensation data K is confirmed, the initial pad substrate 40 can be recycled, and subsequent processes will not transform the initial pad substrate 40 into the actual product of the display panel 100. The material of the initial pad substrate 40 is the same as the material of the actually produced receiving substrate 10 and pad group 20.

[0107] S02: Establish a thermally induced offset model for the initial pad substrate 40 and the light-emitting chip 30.

[0108] In step S02, since the receiving substrate 10 and the initial pad group 21 of the initial pad substrate 40 are made of the same material as the actual production receiving substrate 10 and the pad group 20, a thermally induced offset model is established for the initial pad substrate 40 and the light-emitting chip 30 so as to obtain the offset of the light-emitting chip 30 relative to the initial bonding position P1.

[0109] S03: Determine the thermal offset vector M of the light-emitting chip 30 at the initial bonding position P1 based on the thermal offset model.

[0110] In step S03, the thermally induced offset vector M of the light-emitting chip 30 at the initial bonding position P1 is determined based on the established thermally induced offset model. It is important to understand that the thermally induced offset vector M has not only a vector direction but also a vector length. The vector direction of the thermally induced offset vector M can compensate for the offset direction of the light-emitting chip 30 at the initial bonding position P1, and the vector length of the thermally induced offset vector M can compensate for the offset length of the light-emitting chip 30 at the initial bonding position P1.

[0111] Optionally, the thermally induced offset vector M includes a translation component. The translation component refers to the length by which the light-emitting chip 30 is translated in the same direction.

[0112] Optionally, the thermally induced offset vector M includes a rotation component. The rotation component refers to the angle by which the light-emitting chip 30 rotates.

[0113] The thermally induced offset vector M may include only translation components. The thermally induced offset vector M may also include only rotational components. The thermally induced offset vector M may also include both translational and rotational components simultaneously.

[0114] S04: Determine the compensation data K based on the thermally induced offset vector M.

[0115] In step S04, since the thermally induced offset vector M includes both vector direction and vector length, the compensation data K can be determined based on the thermally induced offset vector M. In this embodiment, before the bonding of the light-emitting chip 30 and the pad group 20 occurs, the position of the pad group 20 on the receiving substrate 10 is pre-set with reverse compensation offset, so that the pad group 20 in the bonding environment can be aligned with the pins of the light-emitting chip 30, thereby improving the bonding yield of the display panel 100.

[0116] Using a one-dimensional coordinate system as a reference, and taking the thermally induced offset vector M as an example that only includes the translation component, this paper explains how to determine the compensation data K based on the thermally induced offset vector M.

[0117] Please see Figure 11 In a normal temperature environment, the position of the light-emitting chip 30 on the receiving substrate 10 is the initial bonding position P1. An initial pad group 21 is fabricated at the initial bonding position P1 to form an initial pad substrate 40. The light-emitting chip 30 is then aligned with the initial pad group 21 in a normal temperature environment.

[0118] Please see Figure 12 Upon heating to the bonding environment, the offset of the light-emitting chip 30 relative to the pad group 20 in the first direction D1 is denoted by the thermally induced offset vector M. The first direction D1 is the direction of the receiving substrate 10, which is also the direction in which the thermal expansion of the receiving substrate 10 is most pronounced. Compensation data K is determined based on the thermally induced offset vector M. The direction of compensation data K is opposite to that of the thermally induced offset vector M, and the length of compensation data K is the same as the length of the thermally induced offset vector M. By setting the pad group 20 according to the initial bonding position P1 and the compensation data K, the offset of the light-emitting chip 30 relative to the pad group 20 and the receiving substrate 10 caused by the difference in their coefficients of thermal expansion can be compensated. This ensures that after heating to the bonding environment, the pins of the light-emitting chip 30 can be aligned with the pad group 20 on the receiving substrate 10.

[0119] This application also provides three methods for establishing thermally induced migration models, which will be described in three subsequent embodiments.

[0120] In the first embodiment of this application: Optionally, the step of establishing a thermally induced displacement model for the initial pad substrate 40 and the light-emitting chip 30 includes: Based on the thermal expansion coefficients of the initial pad substrate 40 and the light-emitting chip 30, the thermally induced offset vector M of the light-emitting chip 30 at the initial bonding position P1 is calculated when the temperature rises from room temperature to the bonding environment.

[0121] In this embodiment, the thermal expansion of the initial pad substrate 40 and the thermal expansion of the light-emitting chip 30 are calculated based on the theory of thermal expansion coefficient to establish a thermally induced displacement model.

[0122] The process of obtaining the thermal expansion coefficient of the initial pad substrate 40 includes obtaining the thermal expansion coefficient of the receiving substrate 10 and obtaining the thermal expansion coefficient of the initial pad group 21.

[0123] After obtaining the coefficient of thermal expansion of the initial pad substrate 40, the temperature difference between the bonding environment and the room temperature environment is calculated, and the thermal expansion of the initial pad substrate 40 is calculated using the temperature difference and the coefficient of thermal expansion of the initial pad substrate 40.

[0124] After obtaining the coefficient of thermal expansion of the light-emitting chip 30, the amount of thermal expansion of the light-emitting chip 30 is calculated using the temperature difference and the coefficient of thermal expansion of the light-emitting chip 30.

[0125] The direction of the thermally induced offset vector M is determined based on the relationship between the thermal expansion coefficients of the light-emitting chip 30 and the initial bonding pad substrate 40. The length of the thermally induced offset vector M is determined based on the thermal expansion amounts of the light-emitting chip 30 and the initial bonding pad substrate 40. Since the direction and length of the thermally induced offset vector M are determined, the thermally induced offset vector M of the light-emitting chip 30 at the initial bonding position P1 can be calculated.

[0126] It should be noted that, in addition to deriving the thermally induced migration model through the theory of thermal expansion coefficient, the thermally induced migration model can also be established by numerical simulation prediction through the establishment of a thermo-mechanical coupled finite element model (FEA).

[0127] Optionally, after the step of transferring and bonding each light-emitting chip 30 to the corresponding pad group 20 of the receiving substrate 10, the following step is further included: Obtain the actual offset vector between the light-emitting chip 30 and the corresponding pad group 20, and adjust the compensation data K according to the actual offset vector.

[0128] In the first embodiment, since the thermally induced offset model is derived from the theory of thermal expansion coefficient, the thermally induced offset vector M given by the thermally induced offset model is the theoretical offset vector. In the actual bonding environment, other environmental variables exist, which can cause differences between the actual offset vector and the theoretical offset vector. Therefore, it is also necessary to adjust the compensation data K according to the actual offset vector to further reduce the offset of the bonded light-emitting chip 30 relative to the pad group 20, further reduce the production yield of the display panel 100, and improve the display effect of the display panel 100.

[0129] By calculation, thermally induced offset vectors M at different bonding environment temperatures can be obtained, and the set of thermally induced offset vectors M is the thermally induced offset model.

[0130] In the second embodiment of this application: To avoid redundancy, the second embodiment of this application only describes the differences from the first embodiment of this application.

[0131] The difference between the second embodiment of this application and the first embodiment of this application is that: The first embodiment of this application establishes a thermally induced displacement model by theoretical derivation using the theory of thermal expansion coefficient. The second embodiment of this application establishes a thermally induced displacement model by performing air pressure tests at representative locations on the receiving substrate 10.

[0132] Optionally, the step of establishing a thermally induced displacement model for the initial pad substrate 40 and the light-emitting chip 30 includes: The initial bonding pad substrate 40 is set in a normal temperature environment, and a mark point is set at the initial bonding position P1.

[0133] The initial pad substrate 40 is heated to the bonding environment, and the thermally induced offset vector M is determined according to the displacement direction and displacement distance of the marked point.

[0134] In the second embodiment of this application, when no pad group 20 is provided on the initial pad substrate 40, a marker point is provided at the initial bonding position P1. When a pad group 20 is provided on the initial pad substrate 40, the pad group 20 is the location of the marker point. By observing the movement direction and distance of the marker point during the process of heating from room temperature to bonding environment, the thermally induced offset vector M is obtained.

[0135] The set of thermally induced offset vectors M formed by measuring different bonding environment temperatures constitutes the thermally induced offset model.

[0136] Compared to the first embodiment, the second embodiment only measures the thermal expansion of the receiving substrate 10 and / or the pad group 20, without measuring the thermal expansion of the light-emitting chip 30. Therefore, in the display panel 100 fabricated according to the thermally induced offset vector M obtained in the second embodiment, the actual offset error between the light-emitting chip 30 and the pad group 20 is greater than that according to the first embodiment. However, the implementation of the second embodiment is simpler and does not require obtaining a specific coefficient of thermal expansion. It can replace the first embodiment in situations where accuracy requirements are low, time is tight, and budget is limited, to establish a thermally induced offset model.

[0137] In the third embodiment of this application: The difference between the third embodiment of this application and the first embodiment of this application is that: The first embodiment of this application establishes a thermally induced offset model by theoretical derivation based on the theory of thermal expansion coefficient. The third embodiment of this application establishes a thermally induced offset model by performing a pre-bonding test on the initial pad substrate 40 and the light-emitting chip 30, and measuring the actual offset after pre-bonding.

[0138] Optionally, the step of establishing a thermally induced displacement model for the initial pad substrate 40 and the light-emitting chip 30 includes: The initial bonding pad substrate 40 is set in a normal temperature environment, and the light-emitting chip 30 is placed at the initial bonding position P1.

[0139] The initial bonding pad substrate 40 and the light-emitting chip 30 are heated to the bonding environment, and the thermally induced offset vector M of the light-emitting chip 30 at the initial bonding position P1 is obtained.

[0140] In one embodiment of this application, a light-emitting chip 30 is placed at the initial bonding position P1, and no bonding agent is applied between the light-emitting chip 30 and the initial pad group 21. The thermally induced offset vector M is obtained by observing the direction and distance of movement of the light-emitting chip 30 relative to the initial pad group 21 during the process of heating from room temperature to the bonding environment.

[0141] In another embodiment of the third embodiment of this application, a light-emitting chip 30 is placed at the initial bonding position P1, and a bonding agent is disposed between the light-emitting chip 30 and the initial pad group 21. After heating from room temperature to the bonding environment, the light-emitting chip 30 and the initial pad group 21 are bonded. The thermally induced offset vector M is determined based on the actual offset vector after the light-emitting chip 30 and the initial pad group 21 are bonded.

[0142] Compared to the second embodiment, the third embodiment also measures the thermal expansion of the light-emitting chip 30. Therefore, in the display panel 100 fabricated according to the thermally induced offset vector M obtained in the third embodiment, the actual offset error between the light-emitting chip 30 and the pad group 20 is smaller than the actual offset according to the second embodiment. Furthermore, it eliminates the need to obtain a specific coefficient of thermal expansion, and can replace the second embodiment in establishing a thermally induced offset model in applications requiring high precision.

[0143] In the fourth embodiment of this application: The light-emitting chip 30 includes a plurality of first light-emitting chips 31 and a plurality of second light-emitting chips 32.

[0144] The receiving substrate 10 includes a main body 11 and an edge portion 12 surrounding the main body 11.

[0145] The step of determining multiple initial bonding positions P1 on the receiving substrate 10 for bonding alignment with multiple light-emitting chips 30 includes: Please see Figure 13 On the main body 11, a plurality of first initial bonding positions P11 are determined for bonding and alignment with a plurality of first light-emitting chips 31. On the edge portion 12, a plurality of second initial bonding positions P12 are determined for bonding and alignment with a plurality of second light-emitting chips 32.

[0146] The step of determining the target bonding position P2 of each light-emitting chip 30 on the receiving substrate 10 based on the predetermined compensation data K and the initial bonding position P1 includes: An initial pad substrate 40 is provided, which includes a main body portion 11, an edge portion 12, a first initial pad group 211, and a second initial pad group 212. The first initial pad group 211 is fabricated on the main body portion 11 based on a first initial bonding position P11, and the second initial pad group 212 is fabricated on the edge portion 12 based on a second initial bonding position P12.

[0147] Please see Figure 14 The first thermally induced offset vector M1 of the first light-emitting chip 31 at the first initial bonding position P11 is determined according to the thermally induced offset model, and the second thermally induced offset vector M2 of the second light-emitting chip 32 at the second initial bonding position P12 is determined according to the thermally induced offset model. The length of the first thermally induced offset vector M1 is less than the length of the second thermally induced offset vector M2.

[0148] The first compensation data K1 is determined based on the first thermal offset vector M1, and the second compensation data K2 is determined based on the second thermal offset vector M2.

[0149] Please see Figure 15Based on the first compensation data K1 and the first initial bonding position P11, the first target bonding position P21 of the first light-emitting chip 31 on the receiving substrate 10 is determined. Based on the second compensation data K2 and the second initial bonding position P12, the second target bonding position P22 of the second light-emitting chip 32 on the receiving substrate 10 is determined. The steps for fabricating pad groups 20 corresponding to each light-emitting chip 30 on the receiving substrate 10 according to the target bonding position P2 include: A first pad group 22 is fabricated at the first target bonding location P21, and a second pad group 23 is fabricated at the second target bonding location P22.

[0150] The steps of transferring and bonding each light-emitting chip 30 to the corresponding pad group 20 of the receiving substrate 10 include: Each first light-emitting chip 31 is transferred and bonded to the corresponding first pad group 22 of the receiving substrate 10, and each second light-emitting chip 32 is transferred and bonded to the corresponding second pad group 23 of the receiving substrate 10.

[0151] In the fourth embodiment of this application, it was found during the actual bonding process that the thermal expansion of the edge portion of the initial pad substrate 40 is greater than that of the center portion. Therefore, if the thermally induced offset vector M is obtained only based on the thermal expansion of the edge portion of the initial pad substrate 40, the offset between the light-emitting chip 30 at the center portion of the initial pad substrate 40 and the initial pad group 21 will be too large.

[0152] To address the aforementioned issues, the fourth embodiment of this application, adapting to local conditions, sets first compensation data K1 and second compensation data K2 based on the varying expansion amounts in different regions of the receiving substrate 10. This reduces the offset between the light-emitting chip 30 in the central portion of the receiving substrate 10 and the pad group 20, while also reducing the offset between the light-emitting chip 30 and the pad group 20 in the edge portions of the receiving substrate 10. This improves the production yield of the display panel 100 and enhances its display performance.

[0153] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0154] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0155] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0156] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: A receiving substrate has a main body and an edge portion disposed around the main body; and Multiple pad groups are disposed on the main body and the edge portion, and the pad groups are configured to bond light-emitting chips; The spacing between two adjacent pad groups on the main body is greater than the spacing between two adjacent pad groups on the edge.

2. The display panel as described in claim 1, characterized in that, The multiple pad groups include multiple first pad groups and multiple second pad groups, with the multiple first pad groups disposed on the main body and the multiple second pad groups disposed on the edge portion; The ratio of the spacing between two adjacent first pad groups to the spacing between two adjacent second pad groups is greater than or equal to 1.

01.

3. The display panel as described in claim 2, characterized in that, The difference between the spacing between two adjacent first pad groups and the spacing between two adjacent second pad groups is greater than or equal to 1 micrometer.

4. The display panel as described in claim 2, characterized in that, The ratio of the spacing between two adjacent first pad groups to the spacing between two adjacent second pad groups is less than or equal to 1.

5.

5. The display panel as described in claim 2, characterized in that, The difference between the spacing between two adjacent first pad groups and the spacing between two adjacent second pad groups is less than or equal to 70 micrometers.

6. The display panel as described in claim 2, characterized in that, The spacing between two adjacent first pad groups is less than or equal to 200 micrometers; The spacing between two adjacent second pad groups is greater than or equal to 134 micrometers.

7. The display panel as described in claim 2, characterized in that, In a plan view of the display panel, the ratio of the area of ​​the main body to the area of ​​the receiving substrate is in the range of 0.4 to 0.

8.

8. The display panel as described in claim 2, characterized in that, When the ambient temperature is a first temperature, the ratio of the spacing between two adjacent first pad groups to the spacing between two adjacent second pad groups is a first ratio value; When the ambient temperature is the second temperature, the ratio of the spacing between two adjacent first pad groups to the spacing between two adjacent second pad groups is the second ratio value; Wherein, the first temperature is lower than the second temperature, and the first ratio is greater than the second ratio.

9. The display panel as described in claim 8, characterized in that, In the plan view of the display panel, When the ambient temperature is the first temperature, the ratio of the area of ​​the edge portion to the area of ​​the main body portion is the third ratio. When the ambient temperature is the second temperature, the ratio of the area of ​​the edge portion to the area of ​​the main body portion is the fourth ratio. The third ratio is greater than the fourth ratio.

10. The display panel as claimed in claim 2, characterized in that, The display panel also includes: Multiple first light-emitting chips, wherein the first light-emitting chips are bonded to the first pad group; Multiple second light-emitting chips are bonded to the second pad group; The distance between two adjacent first light-emitting chips is greater than the distance between two adjacent second light-emitting chips.

11. The display panel as claimed in claim 10, characterized in that, Each of the first light-emitting chips includes two first electrodes, and each of the first pad groups includes two spaced-apart first sub-pads. The first electrodes are bonded to the first sub-pads, and the bonding offset between the first electrodes and the first sub-pads is less than or equal to 3 micrometers; and / or, Each of the second light-emitting chips includes two second electrodes, and each of the second pad groups includes two spaced-apart second sub-pads. The second electrodes are bonded to the second sub-pads, and the bonding offset between the second electrodes and the second sub-pads is less than or equal to 3 micrometers.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1-11.

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