Package structure and forming method thereof, electronic device

Abstract

A packaging structure and its forming method, as well as an electronic device, are disclosed. The packaging structure is formed by etching a substrate surface to create multiple recessed holes. A conductive layer formed on the substrate includes a filling structure that fills the recessed holes and an interconnect structure that covers and connects the filling structure. Because the filling structure in the conductive layer fills the recessed holes, compared to a conductive layer consisting only of interconnect structures, the contact area between the conductive layer and the substrate is increased, thereby improving the mechanical bonding force between the conductive layer and the substrate. During subsequent heat treatment or in the working environment, it can resist interfacial stress caused by mismatch in thermal expansion coefficients, making delamination or peeling failure less likely between the substrate and the conductive layer, thus improving the service life and reliability of the packaging structure.

Description

TECHNICAL FIELD

[0001] The application relates to the field of semiconductors, and in particular to a packaging structure and a forming method thereof, and an electronic device. BACKGROUND

[0002] In the field of semiconductor packaging technology, in order to meet the stringent requirements of chip integration and signal transmission rate for high-performance computing, artificial intelligence and other applications, packaging substrate materials are undergoing technological innovation from traditional organic resin substrates to new inorganic material substrates.

[0003] Glass substrates have application potential in advanced packaging structures such as high-density flip-chip ball grid array (FCBGA) due to their excellent thermal stability, high mechanical strength and excellent high-frequency low-loss electrical properties.

[0004] In the specific practice of applying glass substrates to advanced packaging, a key process step is to form a conductive network on the glass substrate, and there are still many problems to be further solved. SUMMARY

[0005] The problem solved by the embodiments of the present disclosure is to provide a packaging structure and a forming method thereof, and an electronic device, to improve the service life and reliability of the packaging structure.

[0006] The application provides a forming method of a packaging structure, comprising: providing a substrate; performing etching treatment on the substrate to form a plurality of recessed holes on the surface of the substrate; forming a conductive layer on the substrate, the conductive layer comprising a filling structure filling the recessed holes and an interconnection structure covering and connecting the filling structure, the interconnection structure being formed on the surface of the substrate.

[0007] Optionally, the step of performing etching treatment on the substrate comprises: performing selective modification treatment on the substrate to form a plurality of first modified regions in the substrate; and removing the plurality of first modified regions to form the plurality of recessed holes.

[0008] Optionally, the substrate comprises a first surface and a second surface opposite to each other; in the step of performing selective modification treatment on the substrate, the first modified regions are formed on the first surface and / or the second surface; and in the step of forming a conductive layer on the substrate, the filling structure is formed in the recessed holes on the first surface and / or the second surface.

[0009] Optionally, in the step of performing etching treatment on the substrate, a through hole penetrating through the substrate is also formed; and in the step of forming a conductive layer on the substrate, the conductive layer further comprises a conductive pillar filling the through hole, and the interconnection structure connects and covers the conductive pillar.

[0010] Optionally, in the step of forming a plurality of recessed holes on the substrate surface, the recessed holes are located on the side of the through holes and are spaced apart from the through holes.

[0011] Optionally, in the step of forming a conductive layer on the substrate, the interconnect structure, the filling structure, and the conductive pillars are an integral structure.

[0012] Optionally, the step of selectively modifying the substrate further includes: forming a plurality of second modified regions in the substrate; and in the step of removing a plurality of first modified regions, removing a plurality of second modified regions to form a plurality of through holes.

[0013] Optionally, the step of selectively modifying the substrate includes using a laser-induced process with a first energy to form a first modified region for constituting the recessed hole; using a laser-induced process with a second energy to form a second modified region for constituting the through hole, wherein the second energy is greater than the first energy; or, using a single laser-induced process to simultaneously form the first modified region and the second modified region in the substrate.

[0014] Optionally, the substrate is a glass substrate.

[0015] Optionally, in the step of forming a conductive layer on the substrate, the interconnect structure includes extended conductive lines, and a plurality of the filling structures are spaced apart along the extension direction of the conductive lines.

[0016] Optionally, the shape of the recessed hole includes a hemispherical recess or a disc-shaped recess.

[0017] Optionally, in the step of forming a plurality of recessed holes on the substrate surface, the depth of the recessed holes does not exceed one-half of the substrate thickness.

[0018] Optionally, the method for forming the packaging structure further includes: forming a seed layer on the surface of the substrate and the inner surface of the recessed hole before forming the conductive layer on the substrate; the step of forming the conductive layer on the substrate includes: forming a conductive material on the seed layer; and processing the conductive material using a subtractive process or a semi-additive process to form the conductive layer.

[0019] Optionally, the step of forming a seed layer on the substrate surface and the inner surface of the recessed hole includes: physical vapor deposition, atomic layer deposition, or chemical vapor deposition.

[0020] Optionally, the step of forming the conductive material on the seed layer includes electroplating or chemical plating.

[0021] The present invention provides a packaging structure, comprising: a substrate; a plurality of recessed holes located on the surface of the substrate; a conductive layer located on the substrate, the conductive layer including a filling structure filling the recessed holes, and an interconnect structure covering and connecting the filling structure, the interconnect structure being located on the surface of the substrate.

[0022] Optionally, the substrate includes a first surface and a second surface facing away from each other; the recessed hole is located on the first surface and / or the second surface.

[0023] Optionally, the packaging structure further includes: a through-hole penetrating the substrate; a conductive post located in the through-hole, and the interconnect structure connecting to and covering the conductive post.

[0024] Optionally, the interconnect structure, filling structure, and conductive pillars are integrated into one structure.

[0025] Optionally, the recessed hole is located on the side of the through hole and is spaced apart from the through hole.

[0026] Optionally, the substrate is a glass substrate.

[0027] Optionally, the interconnect structure includes extended conductive lines, and the filling structures are spaced apart along the extension direction of the conductive lines.

[0028] Optionally, the shape of the recessed hole includes a hemispherical recess or a disc-shaped recess.

[0029] Optionally, the depth of the recessed hole does not exceed one-half the thickness of the substrate.

[0030] Optionally, the material of the conductive layer includes copper.

[0031] The present invention provides an electronic device, including: the aforementioned packaging structure.

[0032] Compared with the prior art, the technical solution of the invention has the following advantages: The packaging structure formation method provided in this invention involves etching a substrate surface to form multiple recessed holes. A conductive layer formed on the substrate includes a filling structure that fills the recessed holes and an interconnect structure that covers and connects the filling structure. Because the filling structure in the conductive layer fills the recessed holes, compared to a conductive layer consisting only of interconnect structures, the contact area between the conductive layer and the substrate is increased, thereby improving the mechanical bonding force between them. During subsequent heat treatment or in the working environment, it can resist interfacial stress caused by mismatched coefficients of thermal expansion, making delamination or peeling failure less likely between the substrate and the conductive layer, thus improving the service life and reliability of the packaging structure.

[0033] The packaging structure provided in this invention includes a substrate, a plurality of recessed holes on the surface of the substrate, and a conductive layer on the substrate. The conductive layer includes a filling structure that fills the recessed holes and an interconnect structure that covers and connects the filling structure. The interconnect structure is located on the surface of the substrate. Because the filling structure in the conductive layer fills the recessed holes, compared with the case where the conductive layer only includes the interconnect structure, the contact area between the conductive layer and the substrate is increased, thereby improving the mechanical bonding force between the conductive layer and the substrate. During subsequent heat treatment or in the working environment, it can resist the interfacial stress caused by the mismatch of thermal expansion coefficients, making it less likely for delamination or peeling failure to occur between the substrate and the conductive layer, thus improving the service life and reliability of the packaging structure. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0035] Figure 1 This is a flowchart of the method for forming the packaging structure according to an embodiment of the present invention; Figures 2 to 10 This is a schematic diagram of the key steps in the method for forming the packaging structure according to an embodiment of the present invention. Detailed Implementation

[0036] As is known from the background art, there is a significant difference in the coefficient of thermal expansion (CTE) between glass materials and copper materials used as conductive networks. Copper has a CTE of approximately 17 ppm / ℃, while glass has a CTE of only 3-4 ppm / ℃. This significant thermal mismatch generates substantial thermo-mechanical coupling stress at the copper-glass interface during temperature cycling in substrate manufacturing and service. This stress can easily lead to delamination failure between the two materials or cause macroscopic cracking of the glass substrate in stress concentration areas, thus seriously threatening the long-term reliability of the device.

[0037] To address these challenges, existing technologies primarily employ two approaches. One mainstream method involves pre-depositing an organic buffer layer on the glass substrate surface as a stress-absorbing medium to mitigate CTE mismatch between the copper traces and the glass. However, organic buffer layers are typically transparent materials, making it difficult to optically inspect the uniformity and integrity of the organic buffer layer on the substrate surface. Furthermore, uneven thickness or surface irregularities may occur during deposition, which weakens the flatness advantage of the glass substrate itself, affecting the exposure and focusing accuracy and yield of subsequent circuit patterning, and also exacerbating the skin effect in high-frequency signal transmission, increasing signal loss.

[0038] Another mainstream method is to embed copper traces into grooves formed inside the glass through laser-induced etching. While this maintains the flatness advantage of the glass substrate, it introduces new problems. First, during the wet etching of deep grooves, the aspect ratio of the holes restricts the mass transport of the etching solution deep within the grooves. This results in insufficient supply of fresh reactants and difficulty in removing reaction products, a phenomenon known as the "pool effect." Consequently, the bottom of the etched grooves exhibits an arc shape rather than the expected square profile, which is detrimental to the formation of subsequent traces. Second, embedding large sections of copper traces into the glass substrate, although resulting in good bonding at room temperature, leads to significant expansion forces due to the large volume of copper during thermal cycling. This exerts severe tensile stress on the surrounding brittle glass material, triggering microcracks and ultimately causing the entire glass substrate to burst and fail.

[0039] To address the aforementioned technical problems, the packaging structure formation method provided in this invention involves etching a substrate surface to form multiple recessed holes. A conductive layer formed on the substrate includes a filling structure that fills the recessed holes and an interconnect structure that covers and connects the filling structure. Because the filling structure in the conductive layer fills the recessed holes, compared to a conductive layer consisting only of interconnect structures, the contact area between the conductive layer and the substrate is increased, thereby improving the mechanical bonding force between them. During subsequent heat treatment or in the working environment, it can resist interfacial stress caused by mismatched coefficients of thermal expansion, making delamination or peeling failure less likely between the substrate and the conductive layer, thus improving the service life and reliability of the packaging structure. The technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the invention.

[0040] This invention provides a method for forming an encapsulation structure. Figure 1 This is a flowchart of the method for forming the packaging structure according to an embodiment of the present invention; Figures 2 to 10This is a schematic diagram of the key steps in the method for forming the packaging structure according to an embodiment of the present invention.

[0041] Combination Figure 1 ,refer to Figure 2 Substrate 100 is provided.

[0042] The substrate 100 serves as a base platform for subsequent packaging structure formation methods, in which recessed holes and conductive layers are formed on the substrate 100.

[0043] It should be noted that the method for forming the package structure is used to form a flip-chip ball grid array (FCBGA) package structure. The flip-chip ball grid array package structure has high requirements for the dimensional stability, wiring density, and signal integrity of the substrate 100.

[0044] In some embodiments, the substrate 100 includes a glass substrate. Glass substrates have advantages such as good thermal stability, high mechanical strength, and high signal transmission speed and low loss when used as a medium.

[0045] As an example, substrate 100 is a plain glass substrate, such as alkali-free glass or quartz glass. Plain glass substrates have high flatness, thus preparing the substrate for subsequent laser-induced processing and patterning processes. In other embodiments, substrate 100 may also be coated glass. Compatibility with coated glass allows this method to be combined with pretreatment processes aimed at improving surface energy, enhancing adhesion, or achieving other specific functions, thereby expanding its application possibilities in different process routes and product requirements.

[0046] The substrate 100 includes a first surface 100a and a second surface 100b that are opposite to each other.

[0047] The substrate 100 includes a first surface 100a and a second surface 100b that are opposite to each other. In subsequent processes, a conductive layer will be formed on the first surface 100a and the second surface 100b of the substrate 100, which is beneficial to improving the integration of the subsequently formed packaging structure.

[0048] Combination Figure 1 ,refer to Figure 3 and Figure 4 The substrate 100 is etched to form a plurality of recessed holes 101 on the surface of the substrate 100.

[0049] Multiple recessed holes 101 are formed on the surface of the substrate 100 by etching. The recessed holes 101 prepare for the subsequent formation of a filling structure. The filling structure formed in the recessed holes 101 can increase the contact area between the conductive layer and the substrate 100, thereby increasing the bonding force between the conductive layer and the substrate 100. It can resist the interfacial stress caused by the mismatch of thermal expansion coefficients and reduce the probability of delamination or peeling of the conductive layer.

[0050] As an example, the shape of the recessed hole 101 includes a hemispherical recess or a dished recess. The hemispherical recess or dished recess has a smooth curved surface profile without sharp corners, which makes it easier to achieve high morphological uniformity of the recessed hole 101, thereby resulting in high uniformity of the subsequently formed filling structure, which is beneficial to improving the reliability of the packaging structure.

[0051] In some embodiments, in the step of forming a plurality of recessed holes 101 on the surface of substrate 100, the depth of the recessed holes 101 does not exceed half the thickness of substrate 100.

[0052] The depth of the recessed via 101 does not exceed half the thickness of the substrate 100. This shallow depth results in a smaller volume of the filling structure within the recessed via 101. Consequently, the total stress on the substrate 100 caused by thermal expansion and contraction of the filling structure in the recessed via 101 during temperature changes is relatively small, reducing the risk of substrate 100 cracking due to stress and improving the reliability of the packaging structure.

[0053] It should be noted that multiple recessed holes 101 are arranged at intervals.

[0054] The multiple recessed holes 101 are arranged at intervals, so that when the temperature of the package structure changes, even if the conductive layer subsequently formed in the recessed holes 101 undergoes thermal expansion or contraction, the filling structure can provide multiple dispersed anchoring points for the conductive layer, thereby reducing the possibility of delamination or peeling failure between the substrate 100 and the conductive layer, which helps to ensure the structural integrity of the substrate 100 and improve the performance of the subsequent package structure.

[0055] Specifically, the etching process of the substrate 100 includes: selectively modifying the substrate 100 to form a plurality of first modified regions 103 in the substrate 100; removing the plurality of first modified regions 103 to form a plurality of recessed holes 101.

[0056] The substrate 100 is selectively modified. A material region to be removed from the substrate 100, namely the first modified region 103, is predefined in the substrate 100. The material in the first modified region 103 has a difference in etching selectivity between it and the unmodified substrate material. Then, the material in the first modified region 103 is removed by utilizing the etching selectivity between the modified region and the unmodified substrate material, thereby forming a plurality of recessed holes 101.

[0057] In some embodiments, the selective modification process includes laser-induced processing. Laser-induced processing emits a laser beam of specific wavelength and energy to induce physical or chemical changes at predetermined locations and depths in the substrate 100, thereby modifying the material of the substrate 100 and forming modified regions. Laser-induced processing can predefine the location and shape of the recessed holes 101 within the substrate 100 in a non-contact manner.

[0058] As an example, laser-induced processing uses laser energy to locally modify a glass substrate, such as creating microcracks or altering the material density. The depth and shape of the modified region are determined by the laser energy, scanning speed, and focusing position. For instance, by controlling the laser focus and energy distribution, modified regions exhibiting hemispherical or dish-shaped depressions can be induced.

[0059] Specifically, the step of selectively modifying the substrate 100 further includes: forming a plurality of second modified regions 104 in the substrate 100; and in the step of removing a plurality of first modified regions 103, removing a plurality of second modified regions 104 to form a plurality of through holes 105.

[0060] By forming the first modified region 103 and the second modified region 104 in the selective modification process and removing the first modified region 103 and the second modified region 104 simultaneously in the removal process, the method for forming the encapsulation structure is simplified and the formation efficiency of the encapsulation structure is improved.

[0061] As an example, a first modified region 103 and a second modified region 104 are simultaneously formed in a substrate 100 using a single laser-induced process.

[0062] By employing a single laser-induced process to simultaneously form the first modified region 103 and the second modified region 104 in the substrate 100, processing time can be saved, processing efficiency can be improved, and alignment errors caused by multiple processes to form the first modified region 103 and the second modified region 104 can be avoided. During the single laser-induced process, laser parameters, such as energy and focal position, are dynamically controlled to form the first modified region 103 and the second modified region 104 at different positions and depths on the substrate 100 in one go.

[0063] In other embodiments, the step of selectively modifying the substrate 100 includes using laser-induced processing with a first energy to form a first modified region 103 for constituting a recessed hole 101; and using laser-induced processing with a second energy to form a second modified region 104 for constituting a through hole 105, wherein the second energy is greater than the first energy. By using a graded processing method with first and second energies, the depths of the first modified region 103 and the second modified region 104 can be precisely controlled, which is beneficial for manufacturing recessed holes 101 and through holes 105 that meet the requirements.

[0064] The first modified region 103 and the second modified region 104 have a higher etch selectivity relative to the substrate 100 material of the substrate 100, thereby reducing damage to the substrate 100 in the unmodified region while the substrate 100 material in the first modified region 103 and the second modified region 104 is removed quickly during the removal process.

[0065] It should be noted that in the selective modification process, because the laser beam can penetrate the substrate 100, a first modification region 103 can be formed on the same side of the substrate 100 on both the first surface 100a and the second surface 100b. This makes the modification process of the substrate 100 material convenient and quick, without the need to flip the substrate 100, thereby simplifying the process flow and eliminating the need for alignment, which is beneficial to improving the production efficiency and yield of the packaging structure.

[0066] In some embodiments, during the step of selectively modifying the substrate 100, a first modified region 103 is formed on the first surface 100a and / or the second surface 100b, so that the filling structure can be smoothly formed in the first modified region 103 in the subsequent step of forming a conductive layer.

[0067] As an example, such as Figure 3 As shown, the first modified region 103 simultaneously forms the first surface 100a and the second surface 100b. In other embodiments, the first modified region 103 may be formed only on the first surface 100a, or only on the second surface 100b.

[0068] In some embodiments, the step of removing the first modified region 103 includes immersing the substrate 100 in an etching solution for wet etching.

[0069] By utilizing the different etching selectivity ratios of the first modified region 103 and the unmodified substrate 100 to the wet etching solution, the substrate 100 is immersed in the etching solution for wet etching, selectively removing the substrate 100 material in the modified first modified region 103, forming multiple recessed holes 101 in the substrate 100, in preparation for the subsequent formation of a filling structure.

[0070] As an example, etching solutions include hydrofluoric acid (HF)-based etchants.

[0071] It should be noted that in the step of forming a plurality of recessed holes 101 on the surface of the substrate 100, the recessed holes 101 are located on the side of the through holes 105 and are spaced apart from the through holes 105.

[0072] The recessed via 101 is disposed on the side of the through-hole 105 and spaced apart from it, so that the recessed via 101 used to form the filling structure and the through-hole 105 used for vertical interconnection are spatially separated. This ensures that the filling structure subsequently formed in the recessed via 101 and the conductive pillars formed in the through-hole 105 do not interfere with each other during operation. Moreover, the recessed via 101 disposed around the through-hole 105 can anchor the conductive pillars formed in the through-hole 105, resisting interfacial stress caused by mismatch in thermal expansion coefficients during subsequent heat treatment or in the working environment. This makes it less likely for delamination or peeling failure to occur between the substrate 100 and the conductive layer, improving the service life and reliability of the packaging structure.

[0073] As an example, the through hole 105 may be a vertical hole or an hourglass-shaped hole.

[0074] The shape of the through-hole 105 defines the shape of the conductive pillars subsequently formed in the through-hole 105. The opening diameter of the hourglass-shaped hole near the two ends of the first surface 100a and the second surface 100b is larger than the diameter of the middle part of the hourglass-shaped hole. The structure of the hourglass-shaped hole can provide a larger process window for the subsequent deposition of the seed layer 106 and electroplating filling, making it easier for conductive material to enter and fill the through-hole 105, thereby reducing the probability of voids or defects in the conductive pillars in the through-hole 105, and improving the reliability of the electrical connection between the first surface 100a and the second surface 100b of the substrate 100.

[0075] Combination Figure 1 ,refer to Figures 5 to 10 ,in Figure 9 yes Figure 8 Top view, Figure 10 yes Figure 8 A partial schematic diagram. A conductive layer 102 is formed on the substrate 100. The conductive layer 102 includes a filling structure 1022 that fills the recessed hole 101, and an interconnect structure 1021 that covers and connects the filling structure 1022. The interconnect structure 1021 is formed on the surface of the substrate 100.

[0076] The packaging structure formation method provided in this embodiment of the invention involves etching a substrate 100 surface to form multiple recessed holes 101. A conductive layer 102 formed on the substrate 100 includes a filling structure 1022 filling the recessed holes 101 and an interconnect structure 1021 covering and connecting the filling structure 1022. Because the filling structure 1022 in the conductive layer 102 fills the recessed holes 101, compared to the case where the conductive layer 102 only includes the interconnect structure 1021, the contact area between the conductive layer 102 and the substrate 100 is increased, thereby improving the mechanical bonding force between the conductive layer 102 and the substrate 100. During subsequent heat treatment or in the working environment, it can resist interfacial stress caused by mismatch in thermal expansion coefficients, making it less prone to delamination or peeling failure between the substrate 100 and the conductive layer 102, thus improving the service life and reliability of the packaging structure.

[0077] It should be noted that the first surface 100a and the second surface 100b of the glass substrate have high surface flatness. By utilizing the inherent flatness of the first surface 100a and the second surface 100b, the transmission quality of high-frequency signals can be improved, the signal attenuation caused by the skin effect can be reduced, and the electrical performance of the packaging structure can be improved.

[0078] Specifically, in the step of forming a conductive layer 102 on the substrate 100, a filling structure 1022 is formed in a recessed hole 101 on the first surface 100a and / or the second surface 100b.

[0079] As an example, filling structures 1022 are formed in the recessed holes 101 of the first surface 100a and the second surface 100b of the substrate 100, which are used to anchor points for the conductive layer 102 to be formed simultaneously on the opposite first surface 100a and the second surface 100b of the substrate 100. The filling structures 1022 increase the contact area between the conductive layer 102 and the substrate 100, thereby improving the mechanical bonding force between the conductive layer 102 and the substrate 100. In subsequent heat treatment or working environment, it can resist the interfacial stress caused by the mismatch of thermal expansion coefficients, making it less likely for delamination or peeling failure to occur between the substrate 100 and the conductive layer 102, thus improving the service life and reliability of the packaging structure.

[0080] In other embodiments, the filling structure 1022 may also be formed only in the recessed hole 101 of the first surface 100a or the second surface 100b.

[0081] It should be noted that in the step of forming the conductive layer 102 on the substrate 100, the interconnect structure 1021 includes extended conductive lines, and the filling structure 1022 is arranged along the extension direction of the conductive lines.

[0082] The filling structure 1022 is arranged along the extension direction of the interconnect structure 1021, so that the structure for mechanical anchoring can be located below the interconnect structure 1021. During the heat treatment process, it can specifically resist the delamination or peeling failure caused by the mismatch of the thermal expansion coefficient of the interconnect structure 1021, thereby improving the service life and reliability of the packaging structure.

[0083] In some embodiments, the method for forming the package structure further includes: in the step of etching the substrate 100, a through hole 105 is formed through the substrate 100; in the step of forming a conductive layer 102 on the substrate 100, the conductive layer 102 further includes a conductive pillar 1023 filling the through hole 105, and an interconnect structure 1021 connects to and covers the conductive pillar 1023.

[0084] In the etching process of substrate 100, through-holes 105 are formed through substrate 100. Conductive pillars 1023 formed in through-holes 105 form a vertical electrical connection channel between the first surface 100a and the second surface 100b of substrate 100. Since interconnection structure 1021 covers and connects conductive pillars 1023, signal transmission and power distribution between the first surface 100a and the second surface 100b of substrate 100 are facilitated, providing a structural basis for the design and integration of complex circuits and improving the integration of the packaging structure.

[0085] It should be noted that in the step of forming the conductive layer 102 on the substrate 100, the interconnect structure 1021, the filling structure 1022 and the conductive pillar 1023 are an integral structure.

[0086] The interconnect structure 1021, the fill structure 1022, and the conductive pillar 1023 are integrated into one structure. That is, the interconnect structure 1021, the fill structure 1022, and the conductive pillar 1023 are formed in the same metallization process. There are no interfaces between any two of the interconnect structure 1021, the fill structure 1022, and the conductive pillar 1023. During operation, the mechanical stress transmitted from the interconnect structure 1021 to the fill structure 1022 and the conductive pillar 1023 can be smoothly transferred, and there is no high contact resistance at the connection points between them. This results in the conductive layer 102 having low heat loss and high structural strength, which is beneficial to improving the mechanical reliability and electrical performance of the packaging structure.

[0087] In some embodiments, the method for forming the packaging structure further includes: before forming the conductive layer 102 on the substrate 100, forming a seed layer 106 on the surface of the substrate 100 and the inner surface of the recessed hole 101 (e.g., ...). Figure 5 (As shown).

[0088] By forming a seed layer 106 on the surface of the substrate 100 and the inner surface of the recessed hole 101, a conductive base and adhesion interface are provided for the subsequent growth of conductive materials. In particular, the seed layer 106 on the inner surface of the recessed hole 101 enables the conductive material to be successfully formed in the recessed hole 101.

[0089] As an example, the seed layer 106 is a multilayer film structure, including an adhesion layer near the substrate 100 and a seed body layer formed on the adhesion layer.

[0090] The adhesion layer serves to adhere the substrate 100 to the seed body layer, improving the bonding force between the metal and non-metal materials through chemical bonding or physical adsorption. The seed body layer provides a lattice-matched or affinity-friendly surface for the subsequent growth of conductive materials, acts as a nucleus growth point in the electroplating or electroless plating process, and provides a uniformly distributed current for electroplating.

[0091] The adhesive layer uses a metal with good adhesion to glass, such as titanium (Ti), chromium (Cr), or titanium-tungsten alloy (TiW). The thickness of the adhesive layer is between 10 nanometers and 50 nanometers, which ensures adhesion without affecting conductivity.

[0092] The seed body layer is made of the same or similar material as the main metal to be electroplated, such as copper (Cu) or nickel (Ni). The thickness of the seed body layer is between 50 nanometers and 200 nanometers, which ensures the continuity of the seed body layer film while having a sufficiently low sheet resistance to support the uniform conduction of the subsequent electroplating current.

[0093] In some embodiments, the step of forming a seed layer 106 on the first surface 100a, the second surface 100b of the substrate and the inner surface of the recessed hole 101 includes: physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD). It should be noted that the seed layer 106 is also conformally formed in the through hole 105.

[0094] Magnetron sputtering is a physical vapor deposition process. In magnetron sputtering, a substrate 100 is placed in a vacuum environment, and high-energy particles bombard a metal target, such as a Ti target or a Cr target, causing target atoms to be sputtered and deposited on the first surface 100a, the second surface 100b, the recessed via 101, and the through-hole 105 of the substrate 100. By sputtering different targets sequentially, an adhesion layer and a seed body layer can be formed sequentially. Physical vapor deposition is characterized by its fast deposition rate and good adhesion to the substrate 100.

[0095] Atomic layer deposition (ALD) involves alternating the introduction of different precursor gases to induce a self-limiting surface chemical reaction on the first surface 100a and the second surface 100b of the substrate 100, growing a thin film layer by layer in atomic layers. ACD can achieve films with high conformal coverage, and is particularly suitable for filling through-holes 105 with high aspect ratios, allowing the seed layer 106 to have high thickness uniformity on the inner wall of the through-hole 105.

[0096] Chemical vapor deposition (CVD) introduces a gaseous reactant containing the desired deposition element into a reaction chamber. Through plasma excitation, a solid film is formed on the first surface 100a, the second surface 100b, the recessed via 101, and the inner surface of the through-hole 105 of the substrate 100. CVD also exhibits good step coverage capabilities.

[0097] The step of forming a conductive layer 102 on the substrate 100 includes: forming a conductive material 107 (such as a seed layer 106 and the surface of the substrate 100) on the seed layer 106 and the surface of the substrate 100. Figure 6 (As shown); the conductive material 107 is processed using a subtractive process (Tenting Process) or a semi-additive process (SAP) to form a conductive layer 102.

[0098] By forming conductive material 107 on seed layer 106, the recessed hole 101 is filled and the surface of substrate 100 is covered with metal. Finally, the conductive material 107 is patterned using subtractive or semi-additive processes to form the circuit pattern of interconnect structure 1021.

[0099] As an example, conductive material 107 is a metal with excellent electrical conductivity, including copper (Cu), which has high electrical conductivity, good ductility, and a mature electroplating process.

[0100] As an example, the step of forming conductive material 107 on seed layer 106 includes an electroplating process or an electroless plating process.

[0101] In the electroplating process, a substrate 100 with a seed layer 106 is used as the cathode and immersed in an electrolyte containing copper ions (such as copper sulfate). A direct current is applied, and the current flows through the conductive seed layer 106 across the entire substrate 100, including the first surface 100a, the second surface 100b, the recessed via 101, and the through-hole 105. This drives the copper ions in the electrolyte to be reduced and deposited as metallic copper on the surface of the seed layer 106. By controlling the current density and electroplating time, the growth rate and final thickness of the copper layer can be precisely controlled.

[0102] Electroless plating requires no external power source and is carried out in an electroless plating solution containing metal ions and a reducing agent. Through a catalytic reduction reaction on the surface of the seed layer 106, the metal ions are reduced and deposited in the first surface 100a, the second surface 100b, the recessed hole 101, and the through hole 105 of the substrate 100. Electroless plating can form a conductive material 107 with a very uniform thickness.

[0103] The conductive material 107 grows directly on the seed layer 106. The conductive material 107 grows from the bottom and sidewalls of the recessed hole 101 and gradually fills towards the center and the hole opening until it completely fills the recessed hole 101, forming a filling structure 1022.

[0104] Specifically, the conductive material 107 is processed using a subtractive or semi-additive process to form a conductive layer 102.

[0105] As an example, the steps of a subtractive process include: Figure 7 As shown, the conductive material 107 is thinned; then, a dry film is formed on the conductive material 107, and the dry film used as a mask is retained in the line area to be retained by exposure and development process; the conductive material 107 exposed by the dry film is removed by using an etching solution; after removing the conductive material 107 exposed by the dry film, the remaining dry film is removed, and the remaining conductive material 107 serves as the conductive layer 102.

[0106] As an example, dry films include polymer-based photoresists.

[0107] It should be noted that the first surface 100a and the second surface 100b of the glass substrate have high surface flatness, which is beneficial to improving the formation quality of the conductive layer 102 in the step of removing the conductive material 107 exposed by the dry film on the first surface 100a and the second surface 100b.

[0108] It should be noted that in the step of processing the conductive material 107 using the subtractive process, the seed layer 106 exposed by the dry film is also removed.

[0109] As another example, the steps of the semi-additive process include: forming a dry film on the seed layer 106, exposing and developing the dry film to expose the seed layer 106 in the area where the conductive layer 102 is to be formed, forming an electroplating pattern template; and electroplating the substrate 100 as a cathode to grow conductive material 107 in the exposed seed layer 106 area to form the conductive layer 102.

[0110] It should be noted that the semi-additive process also includes: removing the dry film after forming the conductive layer 102, and removing the exposed seed layer 106.

[0111] The method for forming the package structure further includes: after forming the conductive layer 102, forming an insulating layer (not shown in the figure) on the substrate 100 and the conductive layer 102 to prepare for the subsequent formation of a multilayer circuit structure.

[0112] An insulating layer is formed on the substrate 100 and the conductive layer 102 to provide a flat, processable new base surface for the subsequent formation of another circuit layer, thereby realizing the vertical stacking of the package structure and forming a multi-layer circuit structure.

[0113] In some embodiments, the step of forming an insulating layer on the substrate 100 and the conductive layer 102 includes: providing a build-up medium; covering the conductive layer 102 and the exposed surface of the substrate 100 with the build-up medium using a laminator; and curing the build-up medium to form an insulating layer.

[0114] As an example, build-up media include photosensitive or non-photosensitive polymer films, such as ABF (Ajinomoto Build-up Film).

[0115] It should be noted that the thickness of the uplift dielectric layer needs to be greater than the thickness of the conductive layer 102 it covers, so that the uplift dielectric layer can wrap around the sidewalls of the conductive layer 102.

[0116] Accordingly, refer to Figures 8 to 10 , Figure 9 yes Figure 8 Top view, Figure 10 yes Figure 8 A partial schematic diagram shows that an embodiment of the present invention provides a packaging structure including: a substrate 100 (e.g., Figure 8 As shown); multiple recessed holes 101 (as shown) Figure 8 As shown), located on the surface of substrate 100; conductive layer 102 (as shown) Figure 8 As shown, the conductive layer 102 is located on the substrate 100 and includes a filling structure 1022 that fills the recessed hole 101 and an interconnect structure 1021 that covers and connects the filling structure 1022. The interconnect structure 1021 is located on the surface of the substrate 100.

[0117] The packaging structure provided in this embodiment of the invention includes a substrate 100, a plurality of recessed holes 101 located on the surface of the substrate 100, and a conductive layer 102 located on the substrate 100. The conductive layer 102 includes a filling structure 1022 filling the recessed holes 101, and an interconnect structure 1021 covering and connecting the filling structure 1022. The interconnect structure 1021 is located on the surface of the substrate 100. Because the filling structure 1022 in the conductive layer 102 fills the recessed holes 101, compared with the case where the conductive layer 102 only includes the interconnect structure 1021, the contact area between the conductive layer 102 and the substrate 100 is increased, thereby improving the mechanical bonding force between the conductive layer 102 and the substrate 100. In subsequent heat treatment or working environment, it can resist the interface stress caused by the mismatch of thermal expansion coefficients, making it less likely for delamination or peeling failure to occur between the substrate 100 and the conductive layer 102, thus improving the service life and reliability of the packaging structure.

[0118] The substrate 100 serves as the structural basis of the packaging structure. The flip-chip ball grid array (FCBGA) packaging structure places high demands on the dimensional stability, wiring density, and signal integrity of the substrate 100.

[0119] In some embodiments, the substrate 100 includes a glass substrate. Glass substrates have advantages such as good thermal stability, high mechanical strength, and high signal transmission speed and low loss when used as a medium.

[0120] As an example, substrate 100 is a plain glass substrate, such as alkali-free glass or quartz glass. Plain glass substrates have high flatness. In other embodiments, substrate 100 may also be glass with a coating.

[0121] The substrate 100 includes a first surface 100a and a second surface 100b that are opposite to each other.

[0122] The substrate 100 includes a first surface 100a and a second surface 100b that are opposite to each other. The conductive layer 102 is located on the first surface 100a and the second surface 100b of the substrate 100, which is beneficial to improving the integration of the packaging structure.

[0123] It should be noted that the first surface 100a and the second surface 100b of the glass substrate have high surface flatness. By utilizing the inherent flatness of the first surface 100a and the second surface 100b, the transmission quality of high-frequency signals can be improved, the signal attenuation caused by the skin effect can be reduced, and the electrical performance of the packaging structure can be improved.

[0124] The recessed holes 101 on the surface of the substrate 100 provide process space for the filling structure 1022. The filling structure 1022 can increase the contact area between the conductive layer 102 and the substrate 100, and increase the bonding force between the conductive layer 102 and the substrate 100. This can resist the interfacial stress caused by the mismatch of thermal expansion coefficients and reduce the probability of the conductive layer 102 delamination or peeling.

[0125] As an example, the shape of the recessed hole 101 includes a hemispherical recess or a dished recess. The hemispherical recess or dished recess has a smooth curved surface profile without sharp corners, which makes it easier to make the morphology of the recessed hole 101 more uniform, thereby making the filling structure 1022 more uniform and improving the reliability of the packaging structure.

[0126] In some embodiments, the depth of the recessed hole 101 does not exceed half the thickness of the substrate 100.

[0127] The depth of the recessed hole 101 does not exceed half the thickness of the substrate 100, meaning that the recessed hole 101 is relatively shallow, and the corresponding filling structure 1022 in the recessed hole 101 has a small volume. Therefore, when the temperature changes, the total stress on the substrate 100 caused by the thermal expansion and contraction of the filling structure 1022 in the recessed hole 101 is small, reducing the risk of substrate 100 cracking due to stress and improving the reliability of the packaging structure.

[0128] It should be noted that multiple recessed holes 101 are arranged at intervals.

[0129] Multiple recessed holes 101 are arranged at intervals, so that when the temperature of the package structure changes, even if the conductive layer 102 in the recessed hole 101 undergoes thermal expansion or contraction, the filling structure 1022 can provide multiple dispersed anchoring points for the conductive layer 102, thereby reducing the possibility of delamination or peeling failure between the substrate 100 and the conductive layer 102, which helps to ensure the structural integrity of the substrate 100 and improve the performance of the package structure.

[0130] It should be noted that the recessed hole 101 is located on the side of the through hole 105 and is spaced apart from the through hole 105.

[0131] The recessed hole 101 is disposed on the side of the through hole 105 and spaced apart from the through hole 105, so that the recessed hole 101 located in the filling structure 1022 is spatially separated from the through hole 105 used for vertical interconnection. This ensures that the filling structure 1022 located in the recessed hole 101 and the conductive post 1023 located in the through hole 105 do not interfere with each other during operation. Moreover, the recessed hole 101 disposed around the through hole 105 can anchor the conductive post 1023 located in the through hole 105, and can resist the interfacial stress caused by the mismatch of thermal expansion coefficients during subsequent heat treatment or in the working environment, so that delamination or peeling failure is less likely to occur between the substrate 100 and the conductive layer 102, thereby improving the service life and reliability of the packaging structure.

[0132] As an example, the through hole 105 may be a vertical hole or an hourglass-shaped hole.

[0133] The shape of the through-hole 105 defines the shape of the conductive pillar 1023 located within the through-hole 105. The opening diameter of the hourglass-shaped hole near the two ends of the first surface 100a and the second surface 100b is larger than the diameter of the middle part of the hourglass-shaped hole. The structure of the hourglass-shaped hole can provide a larger process window for the deposition of the seed layer 106 and the electroplating filling, making it easier for conductive material to enter and fill the through-hole 105, thereby reducing the probability of voids or defects in the conductive pillar 1023 in the through-hole 105, and improving the reliability of the electrical connection between the first surface 100a and the second surface 100b of the substrate 100.

[0134] The conductive layer 102 is located on the substrate 100. The conductive layer 102 includes a filling structure 1022 that fills the recessed hole 101, and an interconnect structure 1021 that covers and connects the filling structure 1022. The interconnect structure 1021 is located on the surface of the substrate 100.

[0135] Because the filling structure 1022 in the conductive layer 102 fills the recessed hole 101, compared with the case where the conductive layer 102 only includes the interconnect structure 1021, the contact area between the conductive layer 102 and the substrate 100 is increased, thereby improving the mechanical bonding force between the conductive layer 102 and the substrate 100. In subsequent heat treatment or working environment, it can resist the interface stress caused by the mismatch of thermal expansion coefficients, making it less likely for delamination or peeling failure to occur between the substrate 100 and the conductive layer 102, thus improving the service life and reliability of the packaging structure.

[0136] Specifically, the substrate 100 includes a first surface 100a and a second surface 100b that are opposite to each other; and a recessed hole 101 located on the first surface 100a and / or the second surface 100b.

[0137] As an example, both the recessed holes 101 on the first surface 100a and the second surface 100b of the substrate 100 have filling structures 1022. The filling structures 1022 increase the contact area between the conductive layer 102 and the substrate 100, allowing anchoring points for the conductive layer 102 to be present simultaneously on the opposite first surface 100a and the second surface 100b of the substrate 100. This improves the mechanical bonding force between the conductive layer 102 and the substrate 100, and during subsequent heat treatment or in the working environment, it can resist interfacial stress caused by mismatched coefficients of thermal expansion. This makes it less likely for delamination or peeling failure to occur between the substrate 100 and the conductive layer 102, improving the service life and reliability of the packaging structure. In other embodiments, the recessed holes 101 on either the first surface 100a or the second surface 100b of the substrate 100 may also have filling structures 1022.

[0138] It should be noted that the interconnection structure 1021 includes extended conductive lines, and the filling structure 1022 is arranged at intervals along the extension direction of the conductive lines.

[0139] The filling structure 1022 is arranged at intervals along the extension direction of the interconnect structure 1021, so that the structure for mechanical anchoring can be located below the interconnect structure 1021. During heat treatment, it can specifically resist the delamination or peeling failure caused by the mismatch of the thermal expansion coefficient of the interconnect structure 1021, thereby improving the service life and reliability of the packaging structure.

[0140] The packaging structure also includes: a through hole 105 that penetrates the substrate 100; a conductive post 1023 located in the through hole 105, and an interconnect structure 1021 connecting to and covering the conductive post 1023.

[0141] Through-hole 105 penetrates substrate 100. Conductive post 1023 in through-hole 105 forms a vertical electrical connection channel between the first surface 100a and the second surface 100b of substrate 100. Because interconnect structure 1021 covers and connects conductive post 1023, signal transmission and power distribution between the first surface 100a and the second surface 100b of substrate 100 are facilitated, providing a structural basis for the design and integration of complex circuits and improving the integration of the packaging structure.

[0142] It should be noted that the interconnect structure 1021, the filling structure 1022, and the conductive pillar 1023 are an integral structure.

[0143] The interconnect structure 1021, the fill structure 1022, and the conductive pillar 1023 are integrated into one structure. That is, the interconnect structure 1021, the fill structure 1022, and the conductive pillar 1023 are formed in the same metallization process. There are no interfaces between any two of the interconnect structure 1021, the fill structure 1022, and the conductive pillar 1023. During operation, the mechanical stress transmitted from the interconnect structure 1021 to the fill structure 1022 and the conductive pillar 1023 can be smoothly transferred, and there is no high contact resistance at the connection points between them. This results in the conductive layer 102 having low heat loss and high structural strength, which is beneficial to improving the mechanical reliability and electrical performance of the packaging structure.

[0144] The packaging structure also includes a seed layer 106, located on the surface of the substrate 100 and the surface of the recessed hole 101.

[0145] The seed layer 106 on the surface of the substrate 100 and the inner surface of the recessed hole 101 provides a good growth interface for the conductive layer 102, resulting in a high formation quality of the conductive layer 102.

[0146] As an example, the seed layer 106 is a multilayer film structure, including an adhesion layer near the surface of the substrate 100 and a seed body layer located on the adhesion layer.

[0147] The adhesion layer serves to adhere the substrate 100 to the seed body layer, improving the bonding force between the metal and non-metal materials through chemical bonding or physical adsorption. The seed body layer provides a lattice-matched or affinity-friendly surface for the conductive layer, acting as a nucleation point during electroplating or electroless plating, and providing a uniformly distributed current for electroplating.

[0148] The adhesive layer uses a metal with good adhesion to glass, such as titanium (Ti), chromium (Cr), or titanium-tungsten alloy (TiW). The thickness of the adhesive layer is between 10 nanometers and 50 nanometers, which ensures adhesion without affecting conductivity.

[0149] The seed body layer is made of the same or similar material as the main metal being electroplated, such as copper (Cu) or nickel (Ni). The thickness of the seed body layer is between 50 nanometers and 200 nanometers, which ensures the continuity of the seed body layer film while having a sufficiently low film resistance, thereby improving the uniform conduction of the electroplating current.

[0150] As an example, the conductive layer 102 is a metal with excellent electrical conductivity, including copper (Cu), which has high electrical conductivity, good ductility, and a mature electroplating process.

[0151] The packaging structure also includes an insulating layer (not shown in the figure) located on the substrate 100 and the conductive layer 102.

[0152] An insulating layer is located on the substrate 100 and the conductive layer 102 to provide a processable surface for the subsequent formation of another layer of circuitry.

[0153] It should be noted that the thickness of the insulating layer needs to be greater than the thickness of the conductive layer 102 it covers, so that the cured insulating layer wraps around the sidewalls of the conductive layer 102.

[0154] Accordingly, the present invention also provides an electronic device. The electronic device includes a package structure according to any embodiment.

[0155] The packaging structure is a component of electronic devices. As can be seen from the foregoing analysis, the packaging structure provided by the embodiments of the present invention can reduce the risk of component microcracks or connection damage caused by internal shrinkage stress, improve the stability and reliability of the packaging structure, thereby improving the yield and consequently improving the quality of electronic devices.

[0156] Among them, electronic devices can be smartphones, wearable devices, video game devices, etc.

[0157] The packaging structure of the present invention can be formed using the forming method described in the foregoing embodiments, or it can be formed using other forming methods. For a detailed description of the packaging structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0158] While the embodiments of the present invention have been disclosed above, the invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the invention should be determined by the scope defined in the claims.

Claims

1. A method for forming an encapsulation structure, characterized in that, include: Provide substrate; The substrate is etched to form multiple recessed holes on its surface; A conductive layer is formed on the substrate, the conductive layer including a filling structure that fills the recessed holes and an interconnect structure that covers and connects the filling structure, the interconnect structure being formed on the surface of the substrate.

2. The method as described in claim 1, characterized in that, The step of etching the substrate includes: The substrate is selectively modified to form a plurality of first modified regions in the substrate; Multiple first modified regions are removed to form the multiple recessed holes.

3. The method as described in claim 2, characterized in that, The substrate includes a first surface and a second surface that are opposite to each other; In the step of selectively modifying the substrate, the first modified region is formed on the first surface and / or the second surface; In the step of forming a conductive layer on the substrate, the filling structure is formed in the recessed hole on the first surface and / or the second surface.

4. The method as described in claim 1, characterized in that, In the step of etching the substrate, a through hole is also formed through the substrate; In the step of forming a conductive layer on the substrate, the conductive layer further includes conductive pillars that fill the through-holes, and the interconnect structure connects to and covers the conductive pillars.

5. The method as described in claim 4, characterized in that, In the step of forming a plurality of recessed holes on the surface of the substrate, the recessed holes are located on the side of the through holes and are spaced apart from the through holes.

6. The method as described in claim 4, characterized in that, In the step of forming a conductive layer on the substrate, the interconnect structure, the filling structure, and the conductive pillars are an integral structure.

7. The method as described in claim 2, characterized in that, The step of selectively modifying the substrate further includes forming a plurality of second modified regions in the substrate; In the step of removing multiple first modified regions, multiple second modified regions are also removed to form multiple through holes.

8. The method as described in claim 7, characterized in that, The step of selectively modifying the substrate includes using a laser-induced process with a first energy to form a first modified region for constituting the recessed hole; and using a laser-induced process with a second energy to form a second modified region for constituting the through hole, wherein the second energy is greater than the first energy. Alternatively, a single laser-induced process can be used to simultaneously form the first modified region and the second modified region in the substrate.

9. The method as described in claim 1, characterized in that, The substrate is a glass substrate.

10. The method as described in claim 1, characterized in that, In the step of forming a conductive layer on the substrate, the interconnect structure includes extended conductive lines, and a plurality of the filling structures are spaced apart along the extension direction of the conductive lines.

11. The method as described in claim 1, characterized in that, The shape of the recessed hole includes a hemispherical recess or a dish-shaped recess.

12. The method as described in claim 1, characterized in that, In the step of forming a plurality of recessed holes on the surface of the substrate, the depth of the recessed holes does not exceed one-half of the thickness of the substrate.

13. The method as described in claim 1, characterized in that, The method for forming the packaging structure further includes: before forming the conductive layer on the substrate, forming a seed layer on the surface of the substrate and the inner surface of the recessed hole; The step of forming a conductive layer on the substrate includes: forming a conductive material on the seed layer; and processing the conductive material using a subtractive or semi-additive process to form the conductive layer.

14. The method as described in claim 13, characterized in that, The step of forming a seed layer on the substrate surface and the inner surface of the recessed hole includes: physical vapor deposition, atomic layer deposition, or chemical vapor deposition.

15. The method as described in claim 13, characterized in that, The step of forming the conductive material on the seed layer includes electroplating or electroless plating.

16. A packaging structure, characterized in that, include: substrate; Multiple recessed holes are located on the surface of the substrate; A conductive layer is located on the substrate, the conductive layer including a filling structure that fills the recessed holes and an interconnect structure that covers and connects the filling structure, the interconnect structure being located on the surface of the substrate.

17. The packaging structure as described in claim 16, characterized in that, The substrate includes a first surface and a second surface that are opposite to each other; The recessed hole is located on the first surface and / or the second surface.

18. The packaging structure as described in claim 16, characterized in that, The packaging structure further includes: Through-hole, penetrating the substrate; A conductive post is located in the through hole, and the interconnect structure connects to and covers the conductive post.

19. The packaging structure as described in claim 18, characterized in that, The interconnect structure, filling structure, and conductive pillars are integrated into one structure.

20. The packaging structure as described in claim 18, characterized in that, The recessed hole is located on the side of the through hole and is spaced apart from the through hole.

21. The packaging structure as described in claim 16, characterized in that, The substrate is a glass substrate.

22. The packaging structure as described in claim 16, characterized in that, The interconnect structure includes extended conductive lines, and the filling structures are spaced apart along the extension direction of the conductive lines.

23. The packaging structure as described in claim 16, characterized in that, The shape of the recessed hole includes a hemispherical recess or a dish-shaped recess.

24. The packaging structure as described in claim 16, characterized in that, The depth of the recessed hole does not exceed one-half the thickness of the substrate.

25. The packaging structure as described in claim 16, characterized in that, The conductive layer is made of copper.

26. An electronic device, characterized in that, Includes the packaging structure as described in any one of claims 16 to 25.

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