Memory devices and methods for improving write-read turnaround time

Abstract

A memory includes interface circuitry for receiving at least one write command. Multiple memory banks are organized into multiple memory bank groups and operate according to a corresponding memory bank group timing sequence. Each of the multiple memory banks includes a memory cell array. Multiple write buffers temporarily store write data associated with at least one write command. Write buffer selection circuitry egresses the temporarily stored write data from a selected buffer among the multiple write buffers based on the memory bank group timing sequence and directs the egressed write data to a given array of memory cell arrays.

Description

Technical Field

[0001] This disclosure relates to memory systems, memory controllers, memory devices, and related methods. Attached Figure Description

[0002] Embodiments of this disclosure are illustrated in the accompanying drawings by way of example rather than limitation, and in the drawings, the same reference numerals refer to similar elements, wherein:

[0003] Figure 1 An embodiment of a memory system employing a memory controller and at least one memory device is illustrated.

[0004] Figure 2 The diagram illustrates the operation. Figure 1 The advanced steps employed by the memory system.

[0005] Figure 3 The diagram illustrates the relationship between... Figure 1 A specific embodiment of a write buffer circuit used in memory systems.

[0006] Figure 4 The timing diagram illustrates the write-read turnaround bubble associated with memory access operations on a memory system without a write buffer enabled.

[0007] Figure 5 The timing diagram illustrates the streamlined write-read turnaround bubble associated with memory access operations in a memory system with multiple write-enabled buffers.

[0008] Figure 6 The diagram illustrates a timing diagram showing the write-read turnaround bubble associated with memory access operations in a memory system with multiple write buffers that sequentially back off cached data, regardless of bank or bank group conflicts.

[0009] Figure 7 The diagram illustrates a streamlined write-read turnaround bubble associated with memory access operations in a memory system with multiple write buffers that sequentially back off cached data, minimizing the impact of bank and bank group conflicts.

[0010] Figure 8 The diagram illustrates the command truth table for the DDR protocol, demonstrating the availability of explicit quit commands.

[0011] Figure 9A An embodiment of a DDR DIMM including a register clock driver (RCD) chip is illustrated.

[0012] Figure 9BThe diagram illustrates the target Figure 9A The DDR DIMM uses a shared CA bus topology.

[0013] Figure 9C The diagram illustrates the target of... Figure 9A The timing diagram of the commands generated and transmitted by the RCD chip, and Figure 9B This corresponds to the shared CA bus topology.

[0014] Figure 10A Another embodiment of a DDR DIMM including a register clock driver (RCD) chip is illustrated.

[0015] Figure 10B The diagram shows... Figure 10A The CA bus topology is a dedicated per-rank architecture for DDR DIMMs.

[0016] Figure 10C The diagram illustrates the process of... Figure 10A The timing diagram of the commands generated and transmitted by the RCD chip, and Figure 10B This corresponds to the dedicated CA bus topology.

[0017] Figure 11 The diagram illustrates multiple DDR DIMMs, with their corresponding RCD chips communicating with the memory controller.

[0018] Figure 12 The illustration shows a memory system using a DDR DIMM, which includes an RCD chip and multiple data buffer chips.

[0019] Figure 13 The diagram shows the settings. Figure 12 Another detail of an embodiment of the write buffer circuit device in the RCD chip and data buffer chip.

[0020] Figure 14 The diagram shows Figure 13 The truth table of the broadcast communication (BCOM) bus for BCOM circuit devices.

[0021] Figure 15A This diagram illustrates a timing sequence of a streamlined write-read turnaround bubble implemented using a write buffer circuitry in at least one data buffer chip, from the perspective of the memory controller.

[0022] Figure 15B The timing diagram illustrates the write-read cycle bubble of a device with write buffer circuitry disabled in at least one data buffer, from the perspective of the data buffer chip.

[0023] Figure 15CThis diagram illustrates the timing of a simplified write-read turnaround bubble with the write buffer circuitry enabled in at least one data buffer, from the perspective of the data buffer chip.

[0024] Figure 16 An embodiment of a three-dimensional (3D) DRAM architecture with various potential locations of the write buffer circuitry described herein is illustrated.

[0025] Figure 17 An embodiment of a high-bandwidth memory (HBM) architecture with various potential locations of write buffer circuitry as described herein is illustrated. Detailed Implementation

[0026] Memory devices, modules, controllers, systems, and related methods are disclosed. In one embodiment, a memory is disclosed. The memory includes interface circuitry for receiving at least one write command. Multiple memory banks are organized into multiple memory bank groups and operate according to a corresponding memory bank group timing. Each of the multiple memory banks includes a memory cell array. Multiple write buffers temporarily store write data associated with at least one write command. Write buffer selection circuitry egresses the temporarily stored write data from a selected buffer among the multiple write buffers based on the memory bank group timing and directs the egressed write data to a given array in the memory cell array. In some embodiments, the write buffer selection circuitry egresses write data in response to explicit and / or implicit commands. In some embodiments, the write buffer circuitry is included in the memory device of the memory. Other embodiments may include the write buffer circuitry by using one or more buffer chips. By employing write buffer circuitry to temporarily store write data and egressing the stored write data based on the memory bank group timing, a reduction in write-to-read turnaround time can be achieved, thereby reducing latency parameters.

[0027] Now refer to Figure 1A memory system (generally labeled 100) is illustrated, including a memory controller 102 coupled to one or more memory devices 104 via a signaling medium 106. In one embodiment, the memory controller 102 is a dynamic random access memory (DRAM) controller, wherein the memory devices 104 are implemented as DRAM memory devices. In some embodiments, the memory controller 102 and memory devices 104 may be embodied as integrated circuits or chips. Other embodiments may employ the memory controller 102 as circuitry in a host central processing unit (CPU) (not shown). Specific embodiments of the DRAM memory controller 102 and memory 104 may be compatible with various DRAM standards, including Double Data Rate (DDR) variants, Low Power DDR (LPDDR) versions, High Bandwidth (HBM), Graphics DDR (GDDR) types, and Multiplexed DDR (MDDR) types. Other embodiments may include multi-chip modules, such as those employing stacked memory dies or stacked packages. Additional embodiments may stack memory dies and logic dies together in a common package or stack them in separate packages. Other embodiments may employ multiple memory devices on a substrate (not shown) in accordance with a memory module configuration for high-capacity applications.

[0028] Continue to refer to Figure 1 One embodiment of the memory controller 102 includes a write queue circuitry 108 for temporarily storing copies of command information associated with each write command, such as bank group address, bank address, auto-precharge information, and mask information. In some embodiments, the write queue circuitry 108 of the memory controller 102 also temporarily stores data associated with each write command. The memory controller 102 also includes a read queue circuitry 110 that temporarily stores information associated with each read command issued to the memory device 104 in a similar manner to the write queue circuitry 108. In some embodiments, the memory controller 102 includes a prioritization circuitry 112 for reordering one or more operations of the write queue circuitry 108 and / or the read queue circuitry 110, thereby prioritizing certain write and / or read operations over others based on bank group timing. As explained more fully below, prioritizing certain operations over others, from the memory controller's perspective, can reduce latency associated with write-to-read timing bubbles.

[0029] Also refer to Figure 1In one embodiment, each memory device 104 includes a memory interface circuitry 114 for handling communication between the memory controller 102 and the memory core circuitry 116 of the memory device 104. In another embodiment, the memory core circuitry 116 is organized according to a memory bank architecture having multiple independently addressable memory bank groups 118 and 120. Each memory bank group includes multiple memory banks 122, which are addressable via corresponding memory bank addresses. Each memory bank 122 includes an array of memory cells 124, where individual cells are selectively accessed via unique row and column addresses.

[0030] Continue to refer to Figure 1 To reduce the number of clock cycles (often referred to as write-to-read turnaround time) before read data associated with a read operation can begin to be transferred along the data bus (followed immediately by write data transfer along the data bus), memory system 100 employs write buffer circuitry 126. This is described below and as... Figure 1 As shown, the write buffer circuitry 126 can be located at one of a plurality of locations, either inside or outside the chip. In one embodiment, the write buffer circuitry 126 includes a first storage device for storing control information corresponding to a given write operation, such as bank group address, bank address, auto-precharge information, and mask information. The write buffer circuitry 126 includes a second storage device for storing write data associated with each write operation. The write buffer circuitry 126 typically responds to explicit or implicit command information (including predetermined conditions) to deactivate temporarily stored control information and transmit write data to the addressing portion of the memory core circuitry 116 of the memory device 104. The following embodiments provide further details regarding the types of commands and conditions that can be used to control the write buffer circuitry 126. In some embodiments, register circuitry (not shown) can be located on or outside the memory device 104 to provide register programmability for enabling / disabling specific circuitry associated with commands (explicit / implicit) and conditions of the intended form and / or various other configurable options described herein.

[0031] Also refer to Figure 1In some embodiments, multiple write buffers may be employed in the write buffer circuitry 126, wherein one or more of the multiple write buffers correspond to multiple bank groups 118 and 120 of the memory device 104. Depending on the application, the write buffer circuitry 126 may be located within the chip itself of the memory device 104, such as in the memory interface circuitry 114 of 128, or in the memory core circuitry 116 of 130 (associated with the first bank group 118), or in each bank 122 of 134 or 136. The following describes... Figures 3 to 8 Additional details are described for an embodiment of the write buffer circuitry arrangement that is internal to the chip. In some embodiments, the write buffer circuitry arrangement 126 may be located externally to the chip, such as in a buffer chip or chipset of 138. The following describes... Figures 9A to 15C Further details of an embodiment of an external-to-chip write buffer circuit device are described below.

[0032] Figure 2 The diagram illustrates the relevant aspects. Figure 1 One embodiment of a high-level flowchart of the operation method of the memory system 100 is used to reduce the idle time of the data interface, which is manifested when a read operation occurs after a write operation. Idle time is often referred to as the write-read turnaround bubble and can impact memory system performance. At 202, the memory controller 102 issues current write command information to the memory device 104 for the current write operation. In some embodiments, the write command information includes write buffer selection information for selecting a write buffer from a plurality of write buffers in the write buffer circuitry 126. At 204, control information and write data corresponding to the write command information are directed to the write buffer circuitry 126. At 206, in response to an explicit command, or at 208, in response to an implicit command, at 210, based on timing associated with the plurality of bank groups 118 and 120, the previously cached write data stored in the selected write buffer and the associated control information are deferred from the selected write buffer to the memory core circuitry 116 of the memory device 104. In one embodiment, at 211, write buffer selection can be implicitly determined by an agreement between memory controller 102 and memory device 104. In a specific example, such as where each write buffer has its unique identification number, the selected write buffer might be an empty buffer with the lowest identification number. If no empty buffer exists, the selected write buffer is the least recently accessed write buffer. Implicit determination of write buffer selection reduces the amount of information that needs to be transferred between memory controller 102 and the write buffer, thereby reducing the bandwidth consumed by the command.

[0033] Continue to refer to Figure 2 Because the previously written data has been cached near the memory core circuitry device 116, the data reaches the memory core circuitry device 116 much faster than it propagates from the memory controller 102. At 212, this reduced latency allows the memory controller 102 to issue subsequent read commands to the memory device 104 earlier, resulting in read data being transmitted along the data path of the memory interface circuitry device 114 within a shorter idle interval (bubble) after the write data has been transferred to the memory core circuitry device 116.

[0034] Figure 3 The diagram shows Figure 1 This is a specific embodiment of the write buffer circuitry 126. In this particular embodiment, the write buffer circuitry 126 is disposed as an internal circuitry on the memory device 104, having corresponding command / address (CA) path 302 and data (DQ) path 304. (See above regarding...) Figure 1 As described, the write buffer circuit device 126 can be located in multiple locations inside the chip, such as the memory interface 114, the memory bank circuit device 118, or the memory bank circuit device 122.

[0035] Also refer to Figure 3 The write buffer CA path 302 includes a control circuit 306 that receives incoming CA information, such as chip identification information, memory bank group address information, and memory bank address information. Based on the received CA information, the control circuit 306 generates a read / write selection control signal, which is fed along a first control path 307. This path typically activates / deactivates a first group of multiple write buffers 308 in the write buffer CA path 302 and a second group of multiple write buffers 310 in the write buffer data path 304. Although not shown, when the CA information relates to a read command, the CA information corresponding to the read command is directly fed to the memory core circuitry 116 without entering the write buffer CA path.

[0036] Continue to refer to Figure 3When CA information involves a write operation, control circuitry 306 generates a write buffer input selection signal (fed along control path 312) and a write buffer output selection signal (fed along control path 314). In response to the write buffer input selection signal, the first input multiplexer 316 in the write buffer CA path 302 directs the received CA information to the selected (based on the value of the write buffer input selection signal) write buffer from the first set of write buffers 308. The second input multiplexer 318 in the write buffer data path 304 directs the received write data to the selected (based on the value of the write buffer input selection signal) write buffer from the second set of write buffers 310. In response to the write buffer output selection signal, the first output multiplexer 320 in the write buffer CA path 302 deprecates previously cached CA information from the selected (based on the value of the write buffer output selection signal) write buffer from the first set of write buffers 308. The second output multiplexer 322 in the write buffer data path 304 writes previously cached write data into the buffer from the selected write buffer (based on the value of the write buffer output selection signal) from the second set of write buffers 310.

[0037] Also refer to Figure 3 The write buffer data path 304 includes a read data path 324 that bypasses the second set of write buffers 310 and includes a serializer 326 for serializing read data from the core for transmission along the data interface DQ. The write data path 328 includes the second set of write buffers 310 and a deserializer 330 for deserializing write data received from the data interface DQ. First selectors 332, second selectors 334, and third selectors 336 activate certain read or write circuits, such as read bypass path 324 or write data path 328, respectively, in response to read / write selection signals generated by the control circuitry device 306 to complete a given data transfer operation.

[0038] Now refer to Figure 4The diagram presents a timing diagram, showing detailed timing intervals for a DDR-6400 memory device without write buffer circuitry, to help illustrate the background of how typical write-read bubbles are generated. The diagram is shown from the perspective of the DDR memory device, with clock cycles shown at 402, commands shown at 404, data transfer along the data interface shown at 406, and memory core activity shown at 408. The diagram generally shows the timing associated with the first read command RD at 410, followed by the first write command WR at 412. The number of clock cycles between the issuance of the first read command at 410 and the first write command at 412 is controlled by the memory controller 102 and constrained by the read-to-write timing interval RTW shown at 414. A similar timing constraint (i.e., the write-to-read WTR timing interval shown at 416) is controlled by the memory controller 102 to appropriately issue a second read command RD at 418, taking into account the various delays associated with the previous write operation.

[0039] Also refer to Figure 4 In response to the first read command at 410, memory core 116 performs various read-related sub-operations, which occupy memory core 116 within an interval, such as at 420. When the CAS latency (CL) timing constraint shown at 422 expires, at 423, this constraint is defined as the clock cycle delay between the internal first read command RD at 410 and the availability of the first output read data bit. Once read data begins to be transmitted along the data interface at 423, at 424, memory core 116 is immediately available for the next memory access operation (here, the first write operation). However, the write data associated with the write command WR at 412 is restricted to the data interface by the CAS write latency (CWL) timing interval at 426, and at 425, is defined by the memory manufacturer's standard as the clock cycle delay between the internal write command WR at 412 and the availability of the first input write data bit. After the write data has propagated along the data interface, at 428, the data is fed to memory core 116. Although memory core 116 can be used to receive write data at the same time as 424, the actual write data is not fed to memory core 116 until time 428, resulting in an idle delay interval 430 within several clock cycles of memory core 116.

[0040] Continue to refer to Figure 4The idle delay interval 430 has a significant impact on the timing of future operations. As described above, at 418, the second read RD command is restricted from being issued by the memory controller 102 until the WTRU interval expires, partly due to the anticipation of the idle delay interval 430. In response to the second read RD command at 418, the memory core 102 performs a read-related sub-operation at 432, which occupies the memory core 116 during the read interval. After the second CL timing interval shown at 434, at 436, the second read data begins to be transmitted along the data interface. The duration of the time interval between the transmission of the last written data bit and the first subsequent read data bit along the data interface (referred to herein as the write-to-read turnaround bubble) is a direct result of the duration of the memory core idle time interval 430.

[0041] Figure 5 The diagram illustrates the inclusion of multiple write buffers. Figure 1 How does the write buffer circuitry reduce the memory core idle time interval 430 and correspondingly shorten the write-to-read turnaround time? Figure 5 The timing diagram and Figure 4 The timing diagram is similar, although it has an additional set of timing intervals (at 502) corresponding to three write buffers, which store the individual write data corresponding to three write commands (at 504, 506, and 508). For this particular example, the three write buffers are assumed to be empty, so the write operation does not affect the memory core. After the last write command (at 508), the read command RD (at 510) is executed in the write-to-read WTRU time (which is much less than...). Figure 4 The WTR interval is then received by the memory device. The reason for reducing the WTR interval is that the memory controller 102 determines that there will be a small memory core idle time interval because the write data corresponding to the three write commands 504, 506, and 508 are not fed to the memory core 116, but are stored in the write buffer. Therefore, the subsequent read command RD in 510 can be issued by the memory controller 102 earlier, resulting in the read data arriving at the data interface (in 512). The duration of the time interval between the last write data bit corresponding to the third write command in 508 and the first subsequent read data bit transmitted along the data interface (i.e., the result written to the read turnaround bubble) is significantly shorter than the WTR interval. Figure 4 Examples.

[0042] Including multiple write buffers provides a way to shorten the write-to-read turnaround bubble, especially when the write buffers are initially empty. Therefore, it is necessary to keep write buffer resources available as needed to maintain a minimum bubble. Furthermore, when dealing with bank architectures, the order in which each of the multiple write buffers is retired can further optimize the reduction of the write-to-read bubble.

[0043] Figure 6 The diagram illustrates the relationship between... Figure 5 A similar timing diagram is used, but with added detail to the memory core by showing the activity in three bank groups (at 602), which utilize three write buffers (at 604) using a wiping sequence based on when written data is stored in the write buffers. Since the three write buffers (at 604) have previously written data stored, a series of three write commands (at 606, 608, and 610) along the data interface generate three write data bursts (at 612, 614, and 616), which are directed to bank group 0, bank group 1, and bank group 2, respectively. At 618, a separate read command for accessing read data from bank group 2 is received by the memory device. At 620, the write buffer storing the previously written data for bank group 0 wipes the previously written data back to the memory core, while at 622 and 624, the write buffers for bank groups 1 and 2 wipe the previously written data for bank groups 1 and 2, respectively. Since the last write data to the memory core occurs on memory bank group 2 of the core, an idle delay interval 626 occurs within memory bank group 2 of the memory core for several clock cycles. The memory controller 102 takes the idle delay interval 626 into account, resulting in read data being applied to the data interface in 628. The resulting write to the read turnaround bubble is shown in 630.

[0044] Figure 7 The illustration shows a method to further reduce [the impact of memory bank timing] by sorting the write buffer eviction order. Figure 6 The write to read turnover bubble. Figure 7 The timing diagram and Figure 6The timing diagrams are almost identical, but instead of wiping the write buffer based on the length of time previously written data has been stored in the write buffer, the wiping sequence is based on known memory bank timing conflicts between previous write operations and subsequent read operations on the same memory bank group. For example, using write commands directed to memory banks 0, 1, and 2, and read commands directed to memory bank 2, wiping previously written data directed to memory bank 2 from write buffer 2 allows the memory bank 2 portion of the memory core to perform a read-self operation earlier for the read command (at 704), enabling the read data to be placed on the data interface earlier (at 706). Figure 6 Compared to bubble 630, this produces a shorter duration write-to-read timing bubble (in 708).

[0045] The ability to erase previously written data from a given write buffer can be performed in various ways. Generally, a desirable overall approach to erasing written data is to do so in a way that reduces the latency of subsequent read operations. In one embodiment, an explicit erase command specifying a unique write buffer to erase written data can be issued by the memory controller 102 as part of the CA information received by the memory device 104. Figure 8 The command truth table for the current DDR5 command protocol is shown, which has unused bits for read and write operations (in 802, 804, 806, 808, 810, and 812). In one embodiment, using two to three command bits from the available unused bits in the DDR5 command protocol would support the ability to select one of four to eight write buffers to write data.

[0046] In addition to using explicit commands to specify that a given write buffer should erase written data to the memory core, implicit rule sets can be employed to optimally erase written data from multiple write buffers. For example, an implicit command to erase data might occur if another write operation is directed to a memory device while data is in a write buffer. Another example is when a read or write operation is directed to a memory device in a different or "non-target" row, triggering an implicit command to erase data from a given write buffer. Figure 8 The truth table specifies that in the second cycle of a two-cycle command, CS_n = low controls the on-chip termination of the non-target row for write, read, and mode register read (MRR) commands. Therefore, the CS_n = low state can be used as a signal to initiate implicit wiping, where the controller and memory devices cooperate such that the detection of the non-target row (NTR) signal indicates that wiping should occur if one or more write buffers are full. In one embodiment, the write buffers are ordered from 0 to N and then wrap back to 0.

[0047] While most of the above discussion pertains to the memory device side of the memory system, in one embodiment, the memory controller 102 typically manages which data is evicted and when it is evicted. Furthermore, this involves ensuring that internal core resources do not conflict with read and write operations. Further, when data is evicted from the write buffer, the correct memory device page in the memory core's addressable bank should be enabled. The memory controller 102 also tracks which memory devices 104 have data in their write buffers 126 and the corresponding addresses of the write buffers 126. Finally, the memory controller 102 is also responsible for considering the timing of memory devices 104 and the entire memory channel. These timing constraints are managed at the row, bank, bank group, row, and channel levels.

[0048] For certain embodiments involving buffered memory modules, such as dual in-line memory modules with registers (RDIMM), multiplexer combined column DIMMs (MCRDIMM), and multi-column buffered DIMMs (MRDIMM), various write buffer retreat operations can be directed to or offloaded to one or more buffer IC chips, such as registered clock driver (RCD) chips. The assistance provided by one or more buffer IC chips can prove useful in saving command bandwidth between memory controller 102 and memory device 104 and improving execution time.

[0049] Now refer to Figure 9A One embodiment of the memory system 900 includes a memory controller 902 coupled to at least one memory module 904. In one embodiment, the memory module 904 is in the form of a dual in-line memory module (DIMM) comprising a first group of memory devices organized in a first row 906 and mounted on the front side 908 of the module substrate. A second group of memory devices, organized in a second row 912, is mounted on the back side 910 of the substrate. A buffer IC chip 914 is also mounted on the front side of the module substrate and includes: a main interface 916 coupled to the memory controller 902 via a command / address (CA) bus 918; and an auxiliary interface 920 coupled to the first and second rows of memory devices 906 and 912.

[0050] In some embodiments, each of the two rows 906 and 912 can be further subdivided to support multiple independent channels. For example, the memory devices in the left subgroup collectively form a first channel "Channel A," and the memory devices in the right subgroup collectively form a second channel "Channel B." The main interface 916 receives command / address information via the main CA bus DCA and receives chip selection information for the two rows 906 and 912 via the corresponding control buses DCS0 and DCS1. In one embodiment, the auxiliary interface 920 includes a first channel CA bus 922 supporting channel A and a second channel CA bus 924 supporting channel B. Figure 9B As shown, the second channel bus 924 of the auxiliary interface 920 includes a first copy of the CA bus for the second channel CHANNEL B (in 925) and a second copy of the CA bus for the second channel CHANNEL B (in 927). The first copy of the CA bus 925 includes an auxiliary CA bus QCAA that transmits a delayed version of the CA information received by the main CA bus DCA. Corresponding auxiliary chip select buses QCS0A and QCS0B transmit delayed versions of signals received from the corresponding main control buses DCS0 and DCS1. The second copy of the CA bus 927 is formed similarly to the first copy of the CA bus 925. In some embodiments, due to the organization of the memory devices such that the front memory devices form a first row 906 and the rear memory devices form a second row 912, each copy of the CA bus 925 and 927 is shared between rows 906 and 912. The left side of the memory module 904 is formed similarly to the right side.

[0051] Figure 9C The timing diagram illustrates an example of how buffer IC chip 914 can generate multiple output commands executed in parallel from a single input command received from memory controller 902. At 926, the input write command Wr is received via the main CA bus DCA. In one embodiment, the input write command may include extended command bits to specify a leech operation for a selected write buffer in a non-target row. In other embodiments, the chip select control signal provided by main interface 916 is kept low, which can indicate that a leech operation will be performed on a non-target row. Figure 9CIn Figure 928, this configuration is illustrated for the control bus DCS1. The auxiliary interface 920 of the buffer chip 914 transmits write commands (in 930) and associated buffer delays tPDM along the auxiliary CA bus QCA, and transmits corresponding chip select signals for the two rows along the auxiliary chip select buses QCS0_n and QCS1_n (where “n” represents a copy of the CA bus, such as in 925 or 927). Therefore, write commands (for the target row) (in 930) and swipe commands (for the non-target row) (in 932) are fed to the memory device of the selected channel for parallel execution.

[0052] Figure 10A The diagram illustrates memory system 1000, and... Figure 9A The memory system is similar, but the memory module 1002 has an RCD chip 1004, and the memory devices in the lower row are organized into the first row RANK 0, and the memory devices in the upper row are organized into the second row RANK 1. Figure 10B The diagram shows Figure 10A More details on the right side of memory module 1002. This top / bottom row topology is suitable for reserving a separate CA bus for each row, where bus QCAA serves the first row RANK 0 and QCAB serves the second row RANK 1. In this configuration, RCD chip 1004 is free to send different operations to each row without necessarily using non-target commands, such as those described above. Figure 10C The diagram illustrates the relationship between... Figure 9C A similar timing diagram shows how an input write command (at 1006) can cause the RCD chip 1004 to generate multiple output commands, such as a write command (at 1008) and a dedicated exit command (at 1010), to save host-side command bandwidth and provide improved execution timing.

[0053] Figure 11 An embodiment of memory system 1100 is illustrated, wherein memory system 1100 and Figures 9A to 9CThe system 900 is similar, but includes a first memory module 1102 and a second memory module 1104. The first memory module 1102 includes a first RCD chip 1106, which is coupled to the memory controller 1108 via a CA bus DCA and chip select buses DCS0 and DCS1. The first chip select bus DCS0 provides a first row select signal for the first row RANK 0 of the memory devices on the front side of the memory module 1102, while the second chip select bus DCS1 provides a second row select signal for the second row RANK 1 of the memory devices on the back side of the module 1102. The second memory module 1104 is configured similarly, with the CA bus DCA shared with the first memory module 1102, and has a second RCD chip 1110, coupled to the memory controller 1108 via the CA bus DCA and chip select buses DCS2 (for the third row RANK 2 of the memory devices on the front side) and DCS3 (for the fourth row RANK 3 of the memory devices on the back side).

[0054] During runtime, the configuration of memory system 1100 allows multiple operations to be performed in parallel in response to a single command received from the host. For example, memory controller 1108 can issue a write command to the first row RANK 0 via the first RCD chip 1106. The second RCD chip 1110 can recognize that it is a non-target row in the right channel through the aforementioned non-target row mechanism and begin a queuing operation for the third row RANK2 in the right channel. Furthermore, if the second RCD chip 1110 realizes that no command has been issued to the left channel, it can only queuing for the second row RANK 1 in the left channel. These actions may be part of "agreed" rules so that memory controller 1108 knows that these operations will be initiated internally and can manage core timing and memory bank utilization, and keep track of which write buffers are full or empty.

[0055] The above embodiments typically involve using write buffer circuitry arrangements disposed on memory devices, such as DRAM integrated circuit (IC) chips. The embodiments described below achieve similar advantages, but the write buffer circuitry arrangements are not disposed on the memory device, but rather located externally to the chip, such as within one or more buffer IC chips coupled to one or more memory devices using memory modules or other forms of inter-chip substrates.

[0056] Figure 12An embodiment of a memory system 1200 is illustrated, which includes a memory controller 1202 coupled to a memory module 1204. The memory module 1204 includes not only an RCD chip 1206 but also a plurality of data buffer chips 1208 cooperating with the RCD chip 1206 to form a buffer chipset 1210. Since the RCD chip 1206 typically handles caching of control information for a given write operation, the data buffer chips 1208 typically cache the write data corresponding to the write operation. For one embodiment, the above... Figures 1 to 8 The described write buffer circuitry may be included in buffer chipset 1210, wherein the write data buffer is included in data buffer chip 1208, and the write CA buffer is included in RCD chip 1206. Although Figure 12 The RCD chip 1206 and the data buffer chip 1208 are shown as separate, but in some embodiments, the functions of the RCD chip 1206 and the data buffer chip 1208 can be combined into a single integrated circuit (IC) buffer chip.

[0057] Figure 13 Further details are provided for one embodiment of the write buffer circuitry used in the buffer chipset 1210. While this circuitry is related to the above-mentioned... Figure 3The circuitry described for the write buffer circuitry 300 is similar, but the interrelationships between the buffer chips cause some separation between the first portion of the storage control information and the second portion of the storage write data of the buffer circuitry. With this in mind, one embodiment of the RCD chip 1206 employs a master or input CA interface 1304, which includes a CA receiver 1306 that receives a 7-bit CA signal via a CA bus DCA. A chip select receiver 1308 receives a 2-bit chip select signal via a chip select bus DCS. The received CA signal is deserialized by a deserializer 1310 and fed to the write CA buffer logic 1312. The write CA buffer logic 1312 includes a write buffer control circuitry 1314 that provides control signals for the input selector 1316 and the output or fading selector 1318. A plurality of write CA buffers 1320 are disposed between the selectors 1316 and 1318 and provide temporary storage for command information associated with a given write operation. The write buffer control circuitry 1314, in response to chip selection information in the form of an extended fade-out command or a non-target fade-out command, selects and transmits write data from a given buffer among a plurality of write CA buffers 1320 via an output selector 1318 to fade the relevant control information to a specified address of the core circuitry for a given memory device of the module. The output selector 1318 feeds the selected control information to the broadcast communication BCOM encoder 1322 to generate BCOM command information, which is then transmitted to the auxiliary or output interface 1324. In one embodiment, the BCOM encoding may conform to… Figure 14 The BCOM command truth table is shown.

[0058] Also refer to Figure 13 The output interface 1324 includes a clock domain crossover circuit 1326, which synchronizes the BCOM signal, the uncoded write buffer output, the chip select signal, and the corresponding transmit and receive clocks txclk and rxclk. The first part of the synchronization information (including the BCOM signal BCOM and the data buffer chip select signal BCS) is sent to each data buffer 1208 via the transmit circuit device 1330. Figure 12 The second part of the synchronization information (including the auxiliary interface CA signal QCA and the chip select signal QCS) is sent via the transmitting circuit device 1330 to the appropriate row / channel of the memory device associated with the specific RCD chip 1206.

[0059] Continue to refer to Figure 13One embodiment of the data buffer chip 1208 includes a main data interface 1332 that supports bidirectional data transmission in half-byte or 4-bit granularity. The main data interface 1332 includes a data transceiver circuit 1334 that receives write data for write operations and transmits read data for read operations. A differential strobe transceiver circuit 1336 receives source-synchronous write timing information for the write data and transmits a source-synchronous read strobe signal to assist in read data transmission. A BCOM receiver circuit 1338 receives the BCOM signal BCOM and the BCOM chip select signal BCS_n from the RCD chip 1206 and feeds the received information to the transaction control circuitry.

[0060] Also refer to Figure 13 The data buffer chip 1208 includes write buffer logic 1342, configured in a similar manner to the write buffer logic 1312 of the RCD chip 1206, including write buffer control circuitry 1344 that provides control signals to the input selector 1346 and the output or fade-out selector 1348. Multiple write data buffers 1350 are disposed between selectors 1346 and 1348 and provide temporary storage for write data associated with a given write operation. In response to the transaction control circuitry 1340, the write buffer control circuitry 1344 selects which write data buffers to store new write data via the input selector 1346 and selects which write data buffers to fade-out via the output selector 1348.

[0061] Continue to refer to Figure 13 The hidden write data passed to the output selector 1348 is serialized by the serializer 1350 and sent by the transmitter 1351 to the auxiliary data bus MDQ of the data buffer 1208 along with the accompanying differential strobe signal generated by the differential strobe generation circuit 1352. It is also sent by the strobe transmitter 1354 along the auxiliary strobe paths MDQS_t and MDQS_c.

[0062] Figure 15A From memory system 1200 ( Figure 12 The timing diagram of the memory controller 1202 in the buffer memory module 1204 shows the issued write command stream (at 1502) followed by read commands (at 1504). For illustration, the read command at 1504 is distributed by the memory controller 1202 over multiple clock cycles corresponding to the write-to-read turnaround time following the last write command, and it is expected that the write buffer circuitry provided on the buffer memory module 1204 will reduce the write-to-read turnaround time.

[0063] Figure 15B From memory system 1200 ( Figure 12 The timing diagram for data buffer 1208 in the figure shows the write buffer circuitry disabled. At 1508, with the write buffer circuitry disabled, the write data corresponding to the write command 1502 stream cannot be transmitted again along the auxiliary data bus MDQ of the data buffer until the data buffer-related propagation delays tPD2 and tPDMb expire. Conversely, when the write buffer circuitry is enabled, the data buffer propagation delay is effectively hidden, as... Figure 15C As shown in timing diagram 1510, this allows the last portion of the written data (in 1512) to be read from the write command 1502 stream within an interval (shown as T), resulting in a reduction of the write-to-read turnaround time by the interval T.

[0064] While the above embodiments describe how write buffer circuitry can be implemented on a standard DDR5 DRAM memory device or in a buffer chip coupled to a standard DDR5 DRAM memory device, write buffer circuitry can also be used in other DRAM memory device architectures. Figure 16 The diagram illustrates a high-level exploded view of a three-dimensional (3D) DRAM device (typically labeled 1600). The 3D DRAM includes a master die 1602, which includes an external memory interface 1604 for communicating with a memory controller (not shown). The master die 1602 includes a memory core 1606 organized into a memory bank group 1605, which has memory banks 1607 arranged in a manner similar to those of a standard DDR memory device. Multiple auxiliary dies 1608 are stacked on the master die 1602, wherein the auxiliary dies 1608 are formed similarly to the master die 1602, but do not have the external memory interface 1604. Through-silicon vias (such as at 1609) interconnect the auxiliary dies 1608 with the master die 1602 so that the external memory interface 1604 is shared by all dies.

[0065] as Figure 1Various locations within the memory device 104, 3D DRAM 1600, are well-suited for embodiments employing the write buffer circuitry described herein. For example, the control portion of the write buffer circuitry of the main die 1602 may be located within the external memory interface 1604, such as at 1610 or 1612, or within the bank circuitry 1605 (at 1614), or within the bank circuitry 1607 (at 1616). Similarly, the data portion of the write buffer circuitry may be located within the external memory interface 1604, such as at 1618, or within the bank circuitry 1605 (at 1620), or within the bank circuitry (at 1622). For the auxiliary die 1608, the write buffer circuitry may be located in any of the aforementioned locations on the main die 1602, except for the external memory interface 1604 (which is only included in the main die 1602).

[0066] Figure 17 The diagram illustrates a high-level exploded view of a high-bandwidth memory (HBM) device (typically labeled 1700). The HBM memory device 1700 includes a base die 1702 and a memory interface circuitry 1704 for communicating with a memory controller (not shown). Stacked on the base die 1702 are multiple DRAM dies 1706, each including a memory core 1708, organized into a bank group with memory banks in a manner similar to that of a standard DDR memory device. Through-silicon vias (not shown) interconnect the DRAM dies 1706 with the base die 1702. As with other DRAM embodiments described herein, for the purpose of employing write buffer circuitry, the control portion of the write buffer circuitry can be located in the memory interface circuitry 1704, such as at 1710 for each channel or at 1712 for each DRAM die 1706, or in the bank group circuitry 1714 (at 1716), or in the bank circuitry 1718 (at 1720). Similarly, the data portion of the write buffer circuitry can be located in memory interface circuitry 1704, such as in 1722 or 1724, or in memory bank circuitry 1714 (in 1726), or in memory bank circuitry 1718 (in 1728).

[0067] Those skilled in the art will understand the relatively simple circuitry used to buffer the write data and related control information for the aforementioned write operation. By employing a write buffer circuitry to temporarily store the write data and selectively wiping out the stored write data based on the memory bank timing, a reduction in write-to-read turnaround time can be achieved.

[0068] When data is received in a computer system via one or more computer-readable media, such data and / or instruction-based representations of the circuit described above can be processed within the computer system by a processing entity (e.g., one or more processors), in conjunction with the execution of one or more other computer programs (including, but not limited to, netlist generation programs, placement and routing programs, etc.) to generate a representation or image of the physical representation of such circuit. This representation or image can then be used in device fabrication, for example, by generating one or more masks for forming various components of the circuit during device fabrication.

[0069] In the foregoing description and accompanying drawings, specific terms and drawing symbols have been described to provide a full understanding of this disclosure. In some cases, terms and symbols may imply specific details not required to practice aspects of this disclosure. For example, in alternative embodiments, any particular number of bits, signal path width, signaling or operating frequency, component circuitry or device, etc., may differ from those described above. Furthermore, the interconnection between circuit elements or blocks of circuitry shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single-conductor signal links may alternatively be multi-conductor signal links. Signal and signaling paths shown or described as single-ended may also be differential, or vice versa. Similarly, in alternative embodiments, signals described or depicted as having a high-state active or low-state active logic level may have opposite logic levels. Component circuitry arrangements in integrated circuit devices may be implemented using metal-oxide-semiconductor (MOS) technology, bipolar technology, or any other technology in which logic and analog circuitry can be implemented. Regarding terminology, a signal is considered "asserted" when it is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a specific condition. Conversely, a signal is considered "deasserted" to indicate that it has been driven (or charged or discharged) to a state other than the asserted state (including high or low logic states, or floating states that may occur when the signal driver circuit transitions to a high impedance state, such as an open-drain or open-collector state). When the signal driver circuit asserts (or deassers, if explicitly stated or indicated by the context) a signal on a signal line coupled between the signal driver circuit and the signal receiver circuit, the signal driver circuit is considered to "output" a signal to the signal receiver circuit. A signal line is considered "activated" when a signal is asserted on the signal line and "deasserted" when the signal is deasserted. Additionally, the prefix symbol " / " before a signal name indicates that the signal is a low-state active signal (i.e., the asserted state is logic low). A line above the signal name (e.g., '...') The term ') is also used to indicate a low-state active signal. The term "coupled" is used herein to refer to both direct connections and connections via one or more intermediate circuits or structures. "Programming" an integrated circuit device may include (e.g., but not limited to): loading control values ​​into registers or other storage circuitry within the device in response to host instructions to control aspects of the device's operation; establishing a device configuration or controlling aspects of the device's operation through a one-time programming operation (e.g., blowing a fuse in the configuration circuitry during device manufacturing); and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also known as bundling) to establish a specific device configuration or aspect of the device. The term "exemplary" is used to indicate an example, not a preference or requirement.

[0070] While aspects of this disclosure have been described with reference to specific embodiments thereof, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of this disclosure. For example, features or aspects of any embodiment may (at least where feasible) be applied in combination with or in place of corresponding features or aspects of any other embodiment. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory, comprising: An interface circuit device for receiving at least one write command; Multiple storage units are organized into multiple storage unit groups and operated according to the corresponding storage unit group timing sequence, and each of the multiple storage units includes a storage cell array; Multiple write buffers are used to temporarily store write data associated with at least one write command; as well as A write buffer selection circuitry device, based on the memory bank timing, evokes temporarily stored write data from a selected write buffer among the plurality of write buffers and directs the evoked write data to a given array in the memory cell array.

2. The memory according to claim 1, wherein: The write buffer selection circuitry includes control circuitry to execute, based on implicit commands, the eviction of temporarily stored write data from the selected write buffer among the plurality of write buffers.

3. The memory according to claim 2, wherein: The implicit command includes the reception of subsequent write commands.

4. The memory according to claim 2, wherein: The implicit command includes receiving non-target row instructions.

5. The memory according to claim 1, wherein: The write buffer selection circuitry includes control circuitry to perform, in response to an explicit command, the temporarily stored write data to be evicted from the selected write buffer among the plurality of write buffers.

6. The memory according to claim 5, wherein: The explicit commands include exit commands in the form of encoded control bits.

7. The memory according to claim 1, wherein: The memory bank group timing includes timing constraints to avoid memory bank group conflicts between the multiple memory bank groups.

8. The memory according to claim 1, wherein: The plurality of write buffers reside in the interface circuitry or are distributed among the plurality of memory banks or groups of memory banks.

9. The memory according to claim 1, wherein: The plurality of write buffers reside in an off-chip buffer circuit device.

10. The memory according to claim 9, wherein: The external buffer circuit device for the chip includes: A command / address (CA) buffer integrated circuit (IC) chip for storing control information associated with the at least one write command; and At least one data buffer IC chip for storing write data associated with the at least one write command.

11. The memory according to claim 1, wherein: Each memory cell array includes dynamic random access memory (DRAM) cells.

12. A dynamic random access memory (DRAM) integrated circuit (IC) memory chip, comprising: Multiple storage units are organized into multiple storage unit groups and operated according to the corresponding storage unit group timing sequence, and each of the multiple storage units includes a storage cell array; An interface circuit device is configured to receive a first write command and a second write command, the first write command being associated with first write data and used to write to the first memory bank among the plurality of memory banks, and the second write command being associated with the second write data. A first write buffer is used to temporarily store the first write data; The second write buffer is used to temporarily store the second write data; as well as A write buffer selection circuit device, based on the memory bank timing, retires temporarily stored first write data and second write data from the first write buffer and the second write buffer according to a priority sequence, and directs the retired first write data and second write data to a selected array in the memory cell array according to the priority sequence.

13. The DRAM IC chip according to claim 12, wherein: The first and second written data that have been hidden are directed to at least one of the multiple memory banks in the same memory bank group.

14. The DRAM IC chip according to claim 12, wherein: The hidden first and second write data are directed to the corresponding memory in the plurality of memory in different memory groups.

15. The DRAM IC chip according to claim 12, wherein: The write buffer selection circuitry includes a control circuitry to implicitly execute the fading of the temporarily stored first write data and the second write data according to the priority sequence.

16. The DRAM IC chip according to claim 12, wherein: The write buffer selection circuitry includes control circuitry to, in response to an explicit command, perform the fading of the temporarily stored first write data and the second write data according to the prioritization sequence.

17. The DRAM IC chip according to claim 12, wherein: The memory bank group timing includes timing constraints to avoid memory bank conflicts between the multiple memory bank groups.

18. The DRAM IC chip according to claim 12, wherein: The plurality of write buffers reside in the interface circuit device or are distributed among the plurality of memory banks or the plurality of memory bank groups.

19. A buffer circuit, comprising: A first write buffer is used to temporarily store first write data associated with a first write command and address information of one of a plurality of memory banks, the plurality of memory banks being organized into a plurality of memory bank groups, the plurality of memory bank groups being operated according to a corresponding memory bank group timing, the first write data originating from the memory controller. A second write buffer is used to temporarily store second write data associated with the second write command and originating from the memory controller; as well as A write buffer selection circuit device, based on the memory bank timing, retires temporarily stored first write data and second write data from the first write buffer and the second write buffer according to a priority sequence, and directs the retired first write data and second write data to a selected memory bank among the plurality of memory banks according to the priority sequence.

20. The buffer circuit arrangement according to claim 19, wherein: The write buffer selection circuitry includes a control circuitry to implicitly execute the fading of the temporarily stored first write data and the second write data according to the priority sequence.

21. The buffer circuit arrangement according to claim 19, wherein: The write buffer selection circuitry includes control circuitry for responding to an explicit command to fade out the temporarily stored first write data and second write data according to the priority sequence.

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