Configurable reset device, multi-chip reset system, electronic device, and reset control method
By integrating a configurable reset device inside the chip die, the problem of a fixed and single reset mode in multi-chiplet systems is solved, enabling flexible reset mode switching and improving system reliability and testing convenience.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-05-09
- Publication Date
- 2026-06-05
Smart Images
Figure CN122152094A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and particularly to a chip design and packaging technology field using a chip-to-chip architecture, especially to a configurable reset device, a multi-chip reset system, an electronic device, and a reset control method. Background Technology
[0002] In the design of high-performance computing chips (such as general-purpose graphics processors), the chiplet architecture has become the mainstream solution. It designs multiple functional modules as independent chip dies and integrates them within the same package structure using advanced packaging technology. The reset system is fundamental to the normal operation of the chip, used to place the internal circuitry into a defined initial state upon power-up or in the event of an abnormality.
[0003] In existing multi-chiplet systems, the reset signal is typically transmitted using a fixed master-slave broadcast pattern. This means that a master chip is designated as the global reset source during system design. After generating a master reset signal, this master chip broadcasts it unidirectionally and centrally to all other slave chips via the encapsulated interconnect structure. Upon receiving the reset signal, each slave chip executes its internal reset sequence.
[0004] However, this fixed reset structure has several shortcomings in practical applications. First, the fixed master-slave mode cannot adapt to diverse product forms. When the same die plays different roles in different products (such as the main chip or coprocessor), it is difficult to flexibly adjust its function in the reset network. Second, due to the reliance on a highly centralized single reset source, if the master die fails, the entire multi-chip system will face the risk of a single point of failure, unable to reset properly. Furthermore, when faced with complex hierarchical and partitioned reset requirements, the fixed broadcast mode struggles to achieve flexible reset domain division, often requiring the introduction of numerous additional global control signal lines, increasing the complexity of package interconnects and design difficulty. In addition, during system-level testing or fault diagnosis, engineers cannot flexibly initiate resets from specific functional nodes as needed, greatly limiting the means of problem isolation and troubleshooting. Summary of the Invention
[0005] This invention provides a configurable reset device, a multi-chip reset system, an electronic device, and a reset control method to solve the defects of the fixed and single reset mode of the chiplet system in the related technology, which leads to limited product form, low system reliability, complex reset timing coordination, and inconvenient testing and debugging.
[0006] This invention provides a configurable reset device integrated inside a die chip, comprising: Local reset source, used to generate a local reset signal; An external reset input interface is provided for receiving an upstream reset signal from outside the chip die. A sensing unit is configured to acquire the operating mode configuration information of the bare chip. A reset arbitration selector is connected to the local reset source, the external reset input interface, and the configuration sensing unit, respectively, and is used to determine an initial reset signal from the local reset signal and the upstream reset signal according to the working mode configuration information. The reset output driving unit is connected to the configuration sensing unit and the reset arbitration selector, respectively, and is used to selectively transmit the target reset signal generated based on the initial reset signal to the downstream node outside the chip die according to the working mode configuration information.
[0007] According to the configurable reset device provided by the present invention, the working mode corresponding to the working mode configuration information includes at least one of slave mode, master mode, automatic arbitration mode, and independent mode; In the slave mode, the reset arbitration selector is configured to ignore the local reset signal and select the upstream reset signal as the initial reset signal, and the reset output driving unit is configured to enable reset signal forwarding output to the downstream node; In the main mode, the reset arbitration selector is configured to ignore the upstream reset signal and select the local reset signal as the initial reset signal, and the reset output drive unit is configured to enable reset signal drive output to the downstream node; In the automatic arbitration mode, the reset arbitration selector is configured to generate the initial reset signal when either the local reset signal or the upstream reset signal is valid, and the reset output drive unit is configured to enable the reset signal drive output to the downstream node. In the independent mode, the reset arbitration selector is configured to select the local reset signal as the initial reset signal, and the reset output drive unit is configured to disable the reset signal output to the downstream node.
[0008] According to a configurable reset device provided by the present invention, the chip die includes a first pin and a second pin; The configuration sensing unit is also used to obtain the input direction configuration information of the chip die; The device further includes an input pin selection circuit, which is connected to the first pin, the second pin, and the external reset input interface, respectively. The input pin selection circuit is used to selectively connect the first pin or the second pin to the external reset input interface according to the input direction configuration information; The output terminal of the reset output driver unit is connected to both the first pin and the second pin, or the output terminal of the reset output driver unit is connected to the first pin and the second pin that are not configured as the external reset input interface according to the input direction configuration information.
[0009] A configurable reset device according to the present invention further includes a signal processing unit; One end of the signal processing unit is connected to the reset arbitration selector, and the other end is connected to the reset output driving unit. It is used to perform clock domain synchronization and pulse width processing on the initial reset signal to generate an internal reset valid signal. The internal reset valid signal is used to reset the internal logic of the chip die and is provided to the reset output drive unit as the target reset signal.
[0010] According to a configurable reset device provided by the present invention, the local reset signal generated by the local reset source includes at least one of a power-on reset signal, a software-triggerable soft reset signal, and a hardware watchdog timeout reset signal. The configuration sensing unit is electrically connected to at least one of the external general-purpose input / output pins, the internal one-time programmable memory, and the software writable control register of the chip die. The configuration sensing unit is used to generate the operating mode configuration information by acquiring at least one of the level state of the external general-purpose input / output pins, the fuse state of the internal one-time programmable memory, and the stored value of the software writable control register.
[0011] The present invention also provides a multi-chip reset system, including a package structure and a plurality of bare chips integrated within the package structure; The plurality of chip dies includes at least a first chip die and a second chip die, and both the first chip die and the second chip die have an integrated configurable reset device as described above. The reset output drive unit of the first chip die is connected to the external reset input interface of the second chip die through an interconnection structure to form a reset signal relay transmission chain.
[0012] According to a multi-chip reset system provided by the present invention, the interconnect structure includes a dedicated reset signal interconnect line, or the interconnect structure is a general interconnect bus shared between the first chip die and the second chip die.
[0013] According to a multi-chip reset system provided by the present invention, when the working mode of the first chip die is configured as master mode and the working mode of the second chip die is configured as slave mode, the first chip die generates an internal reset and drives a reset signal to be output to the second chip die, and the second chip die synchronously receives and generates an internal reset. When the first chip die is configured to operate in independent mode and the second chip die is configured to operate in master mode, the first chip die and the second chip die each form an isolated independent reset domain based on their respective local reset sources.
[0014] The present invention also provides an electronic device, including a printed circuit board and a multi-chip reset system as described above, mounted on the printed circuit board.
[0015] The present invention also provides a reset control method, applied to a die chip in a multi-chip reset system, comprising: Acquire the local reset signal generated by the local reset source, and receive the upstream reset signal from outside the chip die; Obtain working mode configuration information, and arbitrate the local reset signal and the upstream reset signal according to the working mode configuration information to determine the initial reset signal; A target reset signal is generated based on the initial reset signal, and an internal reset is performed according to the target reset signal; Based on the operating mode configuration information, the target reset signal is selectively transmitted to a downstream node outside the chip die.
[0016] A reset control method provided by the present invention further includes: During system testing or fault diagnosis, obtain dynamic reconfiguration commands; According to the dynamic reconfiguration instruction, the working mode corresponding to the working mode configuration information is reconfigured to the main mode or the independent mode, so as to actively initiate a global reset for the multi-chip reset system or a local reset for the independent reset domain.
[0017] The configurable reset device, multi-chip reset system, electronic device, and reset control method provided by this invention integrate a configuration sensing unit inside the chip die to obtain the current operating mode configuration information. Then, a reset arbitration selector is used to intelligently arbitrate between the local reset signal generated by the local reset source and the upstream reset signal received externally based on the configuration information to determine the initial reset signal. Finally, the reset output driving unit selectively relays the target reset signal to the downstream node based on the configuration information. This structural design breaks the traditional unidirectional, fixed, and centralized reset broadcast mode of multi-chip systems, allowing the same chip die to flexibly configure its operating mode in different package combinations or test scenarios, thereby playing a diverse reset role. This not only effectively avoids the single point of failure risk caused by the failure of a single global reset source, but also eliminates the need for repetitive design to adapt to different product forms, improves the flexibility of hardware interconnection, and simplifies complex reset timing coordination. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is one of the structural schematic diagrams of the configurable reset device provided by the present invention; Figure 2 This is the second schematic diagram of the configurable reset device provided by the present invention; Figure 3 This is a schematic diagram of the structure of the multi-chip reset system provided by the present invention; Figure 4 This is a schematic diagram of the topology of multiple chip die interconnects provided by the present invention; Figure 5 This is a flowchart illustrating the reset control method provided by the present invention. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0021] In the design of high-performance computing chips such as general-purpose computing on graphics processing units (GPGPUs), the chiplet architecture has gradually become the mainstream solution in the industry in order to effectively balance process cost, yield, design flexibility, and overall performance. In the chiplet architecture, multiple functional modules (such as computing cores, caches, input / output controllers, etc.) are typically designed as independent dies, and these independent dies are highly integrated into the same package through advanced packaging technologies such as silicon interposers and organic substrates (such as 2.5D / 3D packaging).
[0022] The reset system is fundamental to ensuring the normal operation of a chip. Its main function is to place the internal circuitry into a defined initial state when the system is powered on or when an abnormality occurs. In complex chiplet systems, the reset signal must be transmitted correctly and efficiently between multiple dies. In related technologies, chiplet system reset typically employs a fixed master-slave broadcast mode. At the beginning of the system design, one master die (such as an input / output die or a master compute die) is designated as the global reset source. When the reset conditions are met, this master die generates a master reset signal and broadcasts it unidirectionally and centrally to all other slave dies through the internal interconnect structures of the package (such as microbumps, through-silicon vias, redistribution layer traces, etc.). Each slave die, upon receiving the reset signal, executes its internal reset sequence.
[0023] However, this unidirectional, centralized fixed reset structure has certain drawbacks in practical applications. First, it lacks flexibility and limits product form factors. A fixed master-slave reset structure cannot flexibly adapt to diverse product forms. For example, when a chip die is used as a master controller or coprocessor in different products, its role in the reset network should change accordingly. To accommodate these different roles, related technologies often require designing different versions of the die separately or introducing complex logic switching circuits internally. This significantly increases chip design cycle time, tape-out costs, and subsequent inventory management costs.
[0024] Second, there is a risk of single point of failure. Due to the use of a highly centralized single global reset source, if the main control die or its reset source fails partially, the entire multi-chip package system will face the risk of being unable to reset normally, resulting in a significant reduction in the overall fault tolerance and reliability of the system.
[0025] Third, reset timing coordination is complex. As multi-chiplet systems grow in scale, complex hierarchical and partitioned reset requirements often arise within the system. For example, chips A and B may be required to reset first, followed by chips C and D. However, the fixed broadcast pattern described above makes it difficult to achieve flexible reset domain partitioning. To meet this complex sequential reset timing, related designs typically require the introduction of additional dedicated control signal lines, which increases the complexity of package interconnects and the difficulty of hardware design.
[0026] Fourth, debugging and testing are inconvenient. During testing or system-level debugging, engineers often want to be able to initiate a global or local reset from any functional die in order to quickly isolate and locate faults. However, the aforementioned fixed master-slave mode does not support this reset initiation mechanism at all, which brings great inconvenience to system fault diagnosis and testing verification.
[0027] To address this, the present invention provides a configurable reset device integrated inside a chip die, thereby overcoming the aforementioned drawbacks. Figure 1 This is one of the structural schematic diagrams of the configurable reset device provided by the present invention, such as... Figure 1 As shown, the configurable reset device 100 is integrated inside the die, and the configurable reset device 100 includes: Local reset source 110 is used to generate a local reset signal; An external reset input interface 120 is used to receive an upstream reset signal from outside the chip die; The sensing unit 130 is configured to acquire the working mode configuration information of the chip die. The reset arbitration selector 140 is connected to the local reset source 110, the external reset input interface 120 and the configuration sensing unit 130 respectively, and is used to determine the initial reset signal from the local reset signal and the upstream reset signal according to the working mode configuration information; The reset output drive unit 150 is connected to the configuration sensing unit 130 and the reset arbitration selector 140 respectively, and is used to selectively transmit the target reset signal generated based on the initial reset signal to the downstream node outside the chip die according to the working mode configuration information.
[0028] Specifically, the configurable reset device is integrated inside the die, typically located on the top layer of the die or at the boundary of the reset domain. This device mainly includes a local reset source, an external reset input interface, a configuration sensing unit, a reset arbitration selector, and a reset output driver unit.
[0029] As the foundation for normal chip operation, the local reset source typically refers to the on-chip standard reset generation circuit, which is mainly responsible for placing the internal circuitry into a defined initial state when the die is powered on or when an abnormality occurs. In practical applications, the local reset signal generated by this local reset source can include a power-on reset signal generated by the power monitoring unit, a software-triggerable soft reset signal, or a hardware watchdog timeout reset signal, etc., which enables the chip die to have self-initialization capabilities.
[0030] An external reset input interface is used to receive upstream reset signals from outside the die. In multi-chip package systems, there is a need to transmit reset signals between dies, and this external reset input interface serves as the hardware channel for receiving upstream signals. Here, "outside the die" typically refers to upstream nodes on the internal interconnect structure of the package (such as other master or slave dies). Upstream reset signals can be transmitted to this external reset input interface through the physical interconnect structure within the package layer (such as metal traces on the silicon interposer, organic substrate traces, or microbumps).
[0031] To enable a single-chip design to adapt to different product roles (such as sometimes acting as a master chip and sometimes as a coprocessor), the device introduces a configuration-aware unit. This unit is essentially a state read or sense logic that can dynamically or statically acquire the current operating mode assigned to the chip die. The operating mode configuration information determines the role the die plays in the entire reset network, such as whether it acts as a master source (or master node) initiating a reset, a slave die (or slave node) receiving a reset, or a completely isolated independent node.
[0032] The reset arbitration selector is essentially a controlled multiplexer or arbitration logic circuit. It receives reset signals from both on-chip (i.e., the local reset source) and off-chip (i.e., the external reset input interface), and performs logical judgment and selection based on the current operating mode provided by the configuration sensing unit. For example, when the operating mode configuration information indicates that the current die is the master node, the reset arbitration selector will ignore the external reset signal and directly select the local reset signal; when the operating mode configuration information indicates that the current die is the slave node, it will select the upstream reset signal from the external source; or in some modes, it will logically OR the two signals as the result. The signal output after filtering or logical operation by the reset arbitration selector serves as the initial reset signal for subsequent reset processing of this die.
[0033] The reset output driver unit is connected to both the configuration sensing unit and the reset arbitration selector. Based on the operating mode configuration information, it selectively transmits the target reset signal, generated from the initial reset signal, to downstream nodes outside the chip die. This unit acts as the control outlet for downstream reset signal transmission and includes enable control logic. Here, the target reset signal generated from the initial reset signal can be either directly output as the target reset signal or a high-quality internal valid reset signal generated after clock domain synchronization, pulse width processing, and deghosting within the chip before being output as the target reset signal. The reset output driver unit again refers to the operating mode configuration information to determine whether to enable the outward drive path. If the configuration allows, the target reset signal will be driven to a dedicated reset interconnect or a shared bus, and propagated to other downstream dies, forming a reset chain.
[0034] It is understood that, by integrating a configurable reset device, including a configuration sensing unit, a reset arbitration selector, and a reset output driver unit, into the chip die, this invention allows the same chip design to flexibly change its reset routing logic by acquiring configuration information without requiring internal logic modifications. This design transforms the traditional centralized broadcast reset mode into a programmable mode, enabling each chip die to act not only as a reset receiver but also as a reset initiator or relay, thereby improving the flexibility of multi-chip system design and reducing tape-out and inventory costs for different product forms.
[0035] The apparatus provided in this invention integrates a sensing unit within the die to obtain current operating mode configuration information. Then, a reset arbitration selector uses this configuration information to intelligently arbitrate between a local reset signal generated by a local reset source and an externally received upstream reset signal to determine the initial reset signal. Finally, a reset output driving unit selectively relays the target reset signal to downstream nodes based on this configuration information. This structural design breaks the traditional unidirectional, fixed, and centralized reset broadcast mode of multi-chip systems, allowing the same die to flexibly configure its operating mode in different package combinations or test scenarios, thus playing diverse reset roles. This not only effectively avoids the single-point-of-failure risk caused by the failure of a single global reset source but also eliminates the need for repetitive design to adapt to different product forms, improving the flexibility of hardware interconnection and simplifying complex reset timing coordination.
[0036] Based on any of the above embodiments, the working mode corresponding to the working mode configuration information includes at least one of slave mode, master mode, automatic arbitration mode, and independent mode; In the slave mode, the reset arbitration selector 140 is configured to ignore the local reset signal and select the upstream reset signal as the initial reset signal, and the reset output drive unit 150 is configured to enable reset signal forwarding output to the downstream node. In the main mode, the reset arbitration selector 140 is configured to ignore the upstream reset signal and select the local reset signal as the initial reset signal, and the reset output drive unit 150 is configured to enable the reset signal drive output to the downstream node. In the automatic arbitration mode, the reset arbitration selector 140 is configured to generate the initial reset signal when either the local reset signal or the upstream reset signal is valid, and the reset output drive unit 150 is configured to enable the reset signal drive output to the downstream node. In the standalone mode, the reset arbitration selector 140 is configured to select the local reset signal as the initial reset signal, and the reset output drive unit 150 is configured to disable the reset signal output to the downstream node.
[0037] Specifically, the working modes corresponding to the working mode configuration information can include slave mode, master mode, automatic arbitration mode, independent mode, etc. These working modes can be defined by configuring mode bits (e.g., MODE[1:0]). The configuration sensing unit can obtain the corresponding working mode configuration information by reading the value of the mode bits. Under different working modes, the execution logic of resetting the arbitration selector and resetting the output drive unit is as follows: In slave mode (e.g., when the mode bit is configured as MODE[1:0]=00), the current die acts as a slave receiver and relay node in the entire reset network. In this mode, the reset arbitration selector ignores the local reset signal and selects the upstream reset signal as the initial reset signal. This means that when the chip starts up or malfunctions, it does not rely on its own reset generation logic, but relies entirely on the reset command transmitted from the upstream of the package interconnect link. At the same time, the reset output driver unit is configured to enable the forwarding of reset signals to downstream nodes. In this way, while the current die completes its own synchronous reset, it will relay the valid reset signal to the downstream die, thus forming a complete reset chain.
[0038] In master mode (e.g., when the mode bit is configured as MODE[1:0]=01), it indicates that the current die is assigned the master role of initiator of global or local reset (e.g., when used as the master chip). In this case, the reset arbitration selector ignores the upstream reset signal (i.e., masks external input) and selects the local reset signal as the initial reset signal. This means that the reset behavior of this die is entirely controlled by its own local reset source (e.g., local power-on reset or watchdog timer). Simultaneously, the reset output drive unit is configured to enable reset signal drive output to downstream nodes. Thus, after generating a valid reset, the master die can actively drive the signal to the external package interconnect, propagating it downstream and controlling other slave dies to perform synchronous resets.
[0039] In automatic arbitration mode (e.g., when the mode bit is configured as MODE[1:0]=10), the system aims to achieve high reliability and multi-master redundancy. In this mode, the reset arbitration selector is configured to generate an initial reset signal when either the local reset signal or the upstream reset signal is valid. Specifically, in circuit implementation, the reset arbitration selector can simultaneously monitor the local reset source and the external reset source (i.e., the external reset input interface) by performing a logic OR operation. As long as either signal is detected as valid, it can be used as the initial reset signal to trigger the reset of this chip. Furthermore, the reset output drive unit is also configured to enable the reset signal drive output to downstream nodes, continuing to propagate this valid reset signal outward. This ensures that even if one of the centralized reset sources in the system fails, as long as other redundant reset sources (local or upstream) can generate a reset signal, the entire multi-chip system can still be reset normally, effectively avoiding single points of failure.
[0040] In standalone mode (i.e., isolated mode, such as when the mode bit is configured as MODE[1:0]=11), it is suitable for scenarios in complex heterogeneous computing architectures that require flexible division of the reset domain, such as when the die is used as an independent computing unit that does not need to be reset in conjunction with other dies. In this case, the reset arbitration selector will select the local reset signal as the initial reset signal, that is, it is only controlled by its own reset source, blocking the influence of any external reset input. At the same time, the reset output driver unit is configured to disable the reset signal output to downstream nodes (e.g., disable its internal enable control). In this way, the die completely isolates itself into an independent and safe reset domain, and its reset behavior is not affected by external interference, nor does it affect the operating status of other external nodes.
[0041] By setting and refining the specific control logic of slave mode, master mode, automatic arbitration mode and independent mode, the embodiments of the present invention enable the reset device to not only easily build a flexible master-slave reset chain, but also support a multi-master redundant architecture to improve system reliability, and an independent reset domain isolation to meet the needs of complex system partition management, which greatly facilitates system-level testing and fault diagnosis.
[0042] Based on any of the above embodiments Figure 2 This is a second schematic diagram of the configurable reset device provided by the present invention, as shown below. Figure 2 As shown, the chip die includes a first pin 210 and a second pin 220; The configuration sensing unit 130 is also used to acquire the input direction configuration information of the chip die; The device further includes an input pin selection circuit 160, which is connected to the first pin 210, the second pin 220 and the external reset input interface 120 respectively. The input pin selection circuit 160 is used to selectively turn on the first pin 210 or the second pin 220 to the external reset input interface 120 according to the input direction configuration information. The output terminal of the reset output driving unit 150 is connected to both the first pin 210 and the second pin 220, or the output terminal of the reset output driving unit 150 is connected to a pin of the first pin 210 and the second pin 220 that is not configured as the external reset input interface 120 according to the input direction configuration information.
[0043] It should be noted that, based on the above embodiments, in order to solve the physical rotation interconnection (i.e., die rotation) problem faced when reusing chips with the same structure in advanced 2.5D / 3D packaging, the embodiments of the present invention have further optimized the external physical interface and pin selection logic of the configurable reset device.
[0044] Specifically, in chiplet systems, to maximize cost amortization, identical dies are typically manufactured using the same mask. During high-density packaging, to minimize the data line connection distance between adjacent dies and avoid trace crossings, engineers often rotate a die 180 degrees on the physical plane. Once a die is rotated, pins originally located on one side (e.g., the north side) will move to the other side (e.g., the south side). If the reset input pin is hardcoded, the reset trace on the package substrate needs to take a large loop or cross, which is unacceptable in high-density advanced packaging. To address this, chips are typically designed with physical interfaces reserved on both the north and south sides (or symmetrically positioned). Therefore, the first and second pins in this embodiment refer to these two reserved physical interfaces.
[0045] To accommodate the aforementioned physical rotation, the configuration sensing unit is also used to acquire the input direction configuration information of the chip die. This input direction configuration information (e.g., defined by the mode bit MODE[2]) is used to indicate whether the current reset signal is input from the forward direction (e.g., from north to south) or the reverse direction (e.g., from south to north).
[0046] Accordingly, the configurable reset device also includes an input pin selection circuit (e.g., internal multiplexer logic), which is connected to the first pin, the second pin, and the external reset input interface, respectively. It acts as a hardware routing switch, selectively connecting the first pin or the second pin to the external reset input interface based on the input direction configuration information. The choice of which physical pin to use as the actual reset signal input is dynamically defined through pure logic configuration.
[0047] Simultaneously, regarding the output of the reset signal, the output terminal of the reset output driver unit is connected to both the first and second pins. Alternatively, the output terminal of the reset output driver unit is connected to a pin among the first and second pins that is not configured as an external reset input interface, according to the input direction configuration information. In other words, the output terminal is also controlled by this input direction configuration information or directly uses a broadcast connection to ensure that the reset signal is output from the pin opposite to the input pin. In this way, regardless of whether the die is placed upright or upside down on the package substrate, only the input direction configuration information needs to be changed to maintain the shortest possible straight-line connection for the external reset interconnect traces, such as running straight from north to south.
[0048] For example, when the input direction configuration information indicates that the current reset signal is input from the positive direction (e.g., from north to south), the first pin located on the north side can be turned on to the external reset input interface, that is, the first pin is used as the input terminal of the external reset signal (i.e., as the reset_in pin), and the second pin located on the south side is used as the output terminal of the reset signal (i.e., as the reset_out pin).
[0049] This invention addresses the pin misalignment problem in rotary packaging of identical chip dies by introducing input direction configuration information and an input pin selection circuit. This design ensures that reset interconnects in extremely high-density advanced packaging always maintain the shortest and most direct connection method, avoiding complex routing and crossings, thereby reducing the complexity and design difficulty of the package substrate interconnection.
[0050] Based on any of the above embodiments, the configurable reset device 100 further includes a signal processing unit 170; One end of the signal processing unit 170 is connected to the reset arbitration selector 140, and the other end is connected to the reset output driving unit 150. It is used to perform clock domain synchronization and pulse width processing on the initial reset signal to generate an internal reset valid signal. The internal reset valid signal is used to reset the internal logic of the chip die and is provided to the reset output drive unit 150 as the target reset signal.
[0051] It should be noted that, considering that there are often multiple asynchronous signals across clock domains in a multi-chip system, in order to ensure the reliability of the reset action and avoid false triggering, the signal processing mechanism inside the configurable reset device has been further improved in this embodiment of the invention.
[0052] Specifically, the configurable reset device also includes a signal processing unit (also known as a synchronization and pulse width processing unit). In terms of circuit connections, one end of the signal processing unit is connected to the reset arbitration selector, and the other end is connected to the reset output drive unit. This unit is mainly used to perform clock domain synchronization and pulse width processing on the initial reset signal to generate an internal reset valid signal.
[0053] The initial reset signal, initially filtered by the reset arbitration selector, may originate from a different clock domain or be a purely asynchronous external input. Direct use of this signal could interfere with internal level-sensitive logic circuits. Therefore, the signal processing unit first performs clock domain synchronization on it, typically synchronizing it to the main clock domain of the chip die. Next, it performs pulse width processing to ensure that the output reset pulse meets the minimum pulse width requirements of the chip's internal circuitry, thereby filtering out glitches that may occur during line transmission and ultimately generating a high-quality, glitch-free internal reset signal.
[0054] After generating this high-quality signal, on the one hand, the internal reset valid signal is used to reset the internal logic of the chip die, ensuring that all logic modules such as the computing core and cache inside the chip can be safely placed into a defined initial state; on the other hand, this internal reset valid signal is provided to the reset output driver unit as the target reset signal. This means that when downstream nodes need to obtain a reset signal from this die, they do not receive the unprocessed raw asynchronous signal, but rather a high-quality target reset signal that has been processed and synchronized by this chip die, thus ensuring the stability of the reset signal throughout the entire reset chain transmission process.
[0055] This invention, by adding a signal processing unit to perform clock domain synchronization and pulse width processing on the initial reset signal, effectively eliminates the risk of glitches and accidental touches generated during the asynchronous reset signal transmission process. This not only ensures the reliability of the internal logic reset of this die, but also provides a high-quality reset source for downstream dies, thereby improving the stability of the entire multi-chip reset system in complex electrical environments.
[0056] Based on any of the above embodiments, the local reset signal generated by the local reset source 110 includes at least one of a power-on reset signal, a software-triggerable soft reset signal, and a hardware watchdog timeout reset signal. The configuration sensing unit 130 is electrically connected to at least one of the external general-purpose input / output pins, the internal one-time programmable memory, and the software writable control register of the chip die. The configuration sensing unit 130 is used to generate the operating mode configuration information by acquiring at least one of the level state of the external general-purpose input / output pins, the fuse state of the internal one-time programmable memory, and the stored value of the software writable control register.
[0057] Specifically, regarding the source of the reset signal, the local reset signal generated by the local reset source can include a power-on reset signal, a software-triggerable soft reset signal, and a hardware watchdog timeout reset signal. Specifically, when the chip is first connected to power, the on-chip power monitoring unit automatically generates a power-on reset signal; during system operation, the operating system or underlying firmware can generate a software-triggerable soft reset signal by writing to specific registers; and when the chip enters an infinite loop or experiences a serious hardware anomaly, it triggers a hardware watchdog timeout reset signal. These standard reset generation circuits collectively constitute the chip's local reset source, providing the foundation for it to function as a master node or an independent node.
[0058] To acquire configuration information, the configuration sensing unit is electrically connected to at least one of the following: external general-purpose input / output (GPIO) pins, internal one-time programmable memory, and software-writable control registers on the chip die. The configuration sensing unit can acquire operating mode configuration information (such as the MODE bit in the aforementioned embodiment) by detecting the level state of the external GPIO pins, reading the fuse state of the internal one-time programmable memory, or reading the stored value of the software-writable control register.
[0059] In practical applications, this design offers great flexibility. For example, for static settings with a fixed product form after packaging, the operating mode can be determined by detecting the external level state of the GPIO pins (such as pulling the pins up or down during board mounting); or permanent hardware fixation can be achieved by reading the programming state of the internal one-time programmable memory. Alternatively, for system debugging, testing, or scenarios requiring dynamic reconfiguration, dynamic settings can be achieved by reading the stored values in the software-writable control register. Engineers can temporarily modify the value of this register via software instructions, changing the chip's operating mode at any time, such as switching from slave mode to master mode to initiate a partial reset to isolate problems. The configuration sensing unit integrates one or more of the above hardware and software states to ultimately generate a specific operating mode configuration information for use by the reset arbitration selector.
[0060] The embodiments of the present invention provide diverse local reset source triggering mechanisms and support multi-dimensional configuration awareness methods such as pin level status, fuse status of one-time programmable memory, and software registers, enabling the device to support configuration requirements from static hardware fixation to dynamic software reconfiguration. This not only facilitates the adaptation of the same chip to different product forms at the factory, but also facilitates subsequent system-level testing and fault diagnosis.
[0061] Based on any of the above embodiments Figure 3 This is a schematic diagram of the multi-chip reset system provided by the present invention, as shown below. Figure 3 As shown, the system includes a packaging structure 310 and multiple bare chips integrated within the packaging structure; The plurality of chip dies include at least a first chip die 320 and a second chip die 330, and the first chip die 320 and the second chip die 330 are both internally integrated with a configurable reset device 100 as described in any of the above embodiments. The reset output drive unit of the first chip die 320 is connected to the external reset input interface of the second chip die 330 through an interconnection structure to form a reset signal relay transmission chain.
[0062] Specifically, based on the configurable reset device provided in the above embodiments, this invention provides a multi-chip reset system from a system-level architecture perspective. For example... Figure 3 As shown, this multi-chip reset system includes a package structure and multiple die-cut chips integrated within the package structure. The package structure typically refers to a physical carrier formed using advanced packaging technologies (such as 2.5D or 3D advanced packaging technologies), containing a silicon interposer, organic substrate, and other media for high-density interconnection between the dies. The multiple die-cut chips refer to the independent functional modules (such as computing cores, caches, input / output controllers, etc.) that were originally a single large chip, which are then integrated within the same package structure to work collaboratively.
[0063] To achieve flexible reset management, at least two of the multiple chip dies (such as the first chip die and the second chip die) integrate a configurable reset device as described in any of the above embodiments. This means that neither the first chip die (such as Die A) nor the second chip die (such as Die B) is a traditional unidirectional reset receiving node, but rather possesses bidirectional, configurable intelligent relay node capabilities.
[0064] In terms of physical and logical connections, the reset output driver unit of the first die is connected to the external reset input interface of the second die through an interconnect structure, forming a reset signal relay transmission chain. Specifically, the target reset signal processed by the first die (e.g., configured in master or relay mode) is output outward through its internal reset output driver unit and transmitted along the interconnect structure inside the package; while the external reset input interface of the second die (e.g., configured in slave mode) is connected to this interconnect structure to receive the signal. Through this end-to-end connection, multiple dies in the system form a chain topology, and the reset network within the entire package changes from a fixed central broadcast type to a flexible programmable network type, allowing the reset signal to be transmitted in an orderly manner in the reset chain formed by the dies.
[0065] The system provided in this invention integrates configurable reset devices into each die of a multi-chip package system and connects them end-to-end using an interconnect structure to form a reset signal relay transmission chain. This breaks the limitations of the traditional unidirectional broadcast reset architecture. This system architecture can flexibly construct the reset dependency relationship between dies according to specific product definitions, thereby improving the compatibility of large-scale chiplet systems in different application scenarios.
[0066] Based on any of the above embodiments, and according to different chip interconnect design specifications, the interconnect structure includes a dedicated reset signal interconnect line, or the interconnect structure is a general interconnect bus shared between the first chip die and the second chip die.
[0067] Specifically, in a direct hardware interconnect implementation, the interconnect structure can be a dedicated reset signal interconnect. In this case, the reset output pin (e.g., reset_out pin) of the first die and the reset input pin (e.g., reset_in pin) of the second die are directly connected point-to-point via the physical interconnect structure within the package layer. These dedicated physical interconnect structures can be metal traces on a silicon interposer, traces on an organic substrate, or micro-bumps between adjacent dies. The advantage of this approach is direct signal transmission, simple timing, and no need for complex protocol parsing, making it suitable for scenarios with extremely high reset response speed requirements and relatively abundant wiring resources.
[0068] In another implementation, the interconnect structure can be a shared universal interconnect bus between the first and second chip dies. In high-density chiplet systems, to conserve valuable physical pin resources, a set of high-speed parallel or serial communication buses may exist between the first and second chip dies. These could be parallel lines for data transmission, or internal interconnect buses based on standards such as PCIe (Peripheral Component Interconnect Express) or UCIe (Universal Chiplet Interconnect Express). In this case, the reset signal is packaged or mapped into this shared communication data line. The first chip die translates the reset state into a specific bus message or in-band / out-of-band signal for transmission. The second chip die's input interface receives the bus data, parses the corresponding reset command, and passes it to the internal configurable reset device. This approach significantly reduces pin overhead.
[0069] The embodiments of the present invention provide two selectable interconnect structures: dedicated reset interconnects and shared general-purpose interconnect buses. This satisfies the requirements for dedicated routing with low latency and direct control, while also adapting to the design requirements of saving physical pins by multiplexing through a shared bus under extremely high integration, thereby reducing the interconnect complexity of the Chiplet advanced package.
[0070] Based on any of the above embodiments Figure 4 This is a schematic diagram of the topology of multiple chip die interconnections provided by the present invention, such as... Figure 4As shown, the multi-chip reset system includes die A, Die B, and Die A' arranged from top to bottom. These three dies are connected end-to-end by physical traces on an advanced packaging substrate, forming a top-down reset signal relay transmission chain. It should be noted that the lettering of the bottom Die A' is inverted, indicating that it underwent a 180-degree rotation during physical packaging, corresponding to a rotational interconnect scenario.
[0071] For each die, PORSTn represents the local reset source, with the suffix 'n' indicating that it is active low, i.e., a locally generated power-on reset signal; rst_n_in and rst_n_out represent the output terminals of the external reset input interface and the reset output driver unit, respectively; the I and O boxes represent the physical pins at the die boundary, where I indicates the pin currently configured as an input and O indicates the pin currently configured as an output. The I / O pins located on the top and bottom sides of the die are the first and second pins, respectively.
[0072] like Figure 4 As shown, taking the die DieA as an example, the trapezoid on the left represents the input pin selection circuit. Based on the operating mode configuration information, it determines whether to connect the upper or lower physical pin to rst_n_in. Solid lines represent the physical traces that are active under the current pin direction configuration, while dashed lines represent non-active spare traces. The trapezoid in the middle represents the reset arbitration selector, used to select between the local reset source (PORSTn) and the external upstream reset signal (rst_n_in). The trapezoid on the right represents the reset output driver unit, where 1'b1 represents the constant logic high level 1 in the hardware description language. Furthermore, PU at the I / O pin represents the internal pull-up resistor. It should be understood that since both the reset signals PORSTn and rst_n_in are active low, the chip will only perform a reset when the input is 0. If an input pin (I port) is not connected to any signal externally, it may generate an indeterminate low-level pulse, leading to an unexpected erroneous reset of the chip. By adding PU to the input pin, the level of this floating pin can be pulled high to the default high level, thus ensuring that the chip is always in a safe non-reset state when there is no real external reset signal input.
[0073] In terms of specific interconnection paths and logic configurations, DieA, acting as the starting point of the reset chain (such as the master node), has an internal reset arbitration selector that ignores the external reset signal rst_n_in and instead selects the reset signal PORSTn generated by the local reset source. This signal enters the chip and triggers DieA's own reset. Subsequently, this valid reset signal is routed to the O (output) pin on the physical south side (bottom) of DieA through the internal reset output driver unit on the right side. At this point, DieA completes its internal reset and enables downward reset signal driving.
[0074] DieB, acting as a relay in the reset chain (such as a slave node), has its physical north (top) I (input) pin directly connected to the south O pin of DieA via internal vertical interconnect traces. The reset signal enters DieB from this point, passes through its internal input pin selection circuitry to reach rst_n_in, causing DieB to generate an internal synchronous reset. Simultaneously, DieB continues its relay function, routing the reset signal through its internal logic to its south O pin, forwarding it to downstream nodes.
[0075] Finally, DieA' serves as the end of the reset chain (like a rotated slave node). To maximize package area utilization and minimize trace distances between adjacent dies, DieA' is rotated 180 degrees in the physical plane. Using an input pin select circuit, the south-facing O pin of DieB can be directly connected via the shortest straight-line distance to the pin currently facing north on DieA' (i.e., the pin facing south before rotation). By configuring the input direction information, DieA' dynamically defines this physical pin as an I pin to receive signals and maps it to the internal rst_n_in to complete its own reset. If there are other dies below, DieA' can also output the reset signal from its bottom pin, and so on, forming a reset chain.
[0076] Based on any of the above embodiments, when the first chip die 320 is configured to operate in master mode and the second chip die 330 is configured to operate in slave mode, the first chip die 320 generates an internal reset and drives a reset signal to be output to the second chip die 330, and the second chip die 330 synchronously receives and generates an internal reset. When the first chip die 320 is configured to operate in independent mode and the second chip die 330 is configured to operate in master mode, the first chip die 320 and the second chip die 330 respectively form isolated independent reset domains based on their respective local reset sources.
[0077] It should be noted that, based on the above multi-chip reset system, in order to demonstrate the reset workflow of the entire system under different configurations, this embodiment of the invention takes a system composed of a first chip die (such as Die A) and a second chip die (such as Die B) as an example to explain in detail the specific control logic under two typical working scenarios.
[0078] In the first scenario (such as building a master-slave synchronous reset chain), the first die is configured as master and the second die as slave. The first die generates an internal reset and drives a reset signal to the second die, which then synchronously receives and generates its own internal reset. In practical applications, for example, external GPIO levels can be used to configure DieA as master and DieB as slave. When the system powers on or an abnormality occurs, DieA's local reset source generates a pulse. DieA's reset arbitration selector selects this local signal, generating an internal reset after clock domain synchronization. Simultaneously, it drives the target reset signal to the interconnect via its reset output pin (e.g., the reset_out pin). DieB receives the reset signal from DieA via its reset input pin (e.g., the reset_in pin). Since it is in slave mode, it selects this external input signal and generates its own internal reset after synchronization. In this way, the synchronous sequential reset of the entire multi-chip system is completed.
[0079] In the second scenario (such as building independent reset domains in heterogeneous computing), the first die is configured to operate in independent mode and the second die in master mode. In this case, the first and second dies form isolated independent reset domains based on their respective local reset sources. For example, when DieB is used as an independent coprocessor in heterogeneous computing and needs its own independent reset control, DieA can be configured in independent mode and DieB in master mode. In this case, DieA's reset arbitration selector is only controlled by its own local reset source and disables external reset drive outputs, thus having no external impact. Similarly, DieB is only controlled by its own local reset source and can further act as the master controller, driving its reset signal to other downstream dies (such as DieC). Therefore, DieA and DieB, which were originally physically connected, are logically isolated into two independent reset domains that do not interfere with each other.
[0080] The embodiments of the present invention provide a solid hardware foundation for complex sequential reset timing by utilizing simple mode configuration without requiring a large number of additional global control lines. At the same time, it can meet the needs of flexible segmentation and isolation of the reset domain in heterogeneous computing, and significantly reduce the complexity and design difficulty of system-level interconnection.
[0081] Based on any of the above embodiments, the present invention also provides an electronic device, including a printed circuit board and a multi-chip reset system as described in any of the above embodiments, mounted on the printed circuit board.
[0082] Specifically, this invention provides an electronic device designed to apply the highly flexible and reliable multi-chip reset system described above to practical physical terminals. In practical applications, this electronic device can be a server equipped with a high-performance GPGPU computing card, an accelerated computing node, a high-end personal computer, or a dedicated graphics processing workstation. The printed circuit board (PCB), as the physical support and electrical connection substrate, provides the power supply network for the multi-chip reset system (i.e., chip modules after advanced 2.5D / 3D packaging) and a high-speed communication link for interaction with other external system components. The multi-chip reset system, as a single packaged device, is mounted on the PCB using solder balls or slots.
[0083] By employing the aforementioned multi-chip reset system in electronic devices, this invention enables the electronic devices to possess extremely high reliability during the underlying hardware initialization and fault recovery phases. A single die's reset source failure will not cause the entire device to lock down or become paralyzed. Furthermore, during the production testing and fault diagnosis phases of the equipment, engineers can easily initiate a partial reset from a specific die to isolate and locate the problem, thereby improving the overall maintenance efficiency of the electronic devices.
[0084] The reset control method provided by the present invention will be described below. The reset control method described below can be referred to in correspondence with the configurable reset device described above.
[0085] Based on any of the above embodiments Figure 5 This is a flowchart illustrating the reset control method provided by the present invention, as shown below. Figure 5 As shown, this method is applied to a bare chip in a multi-chip reset system, and the method includes: Step S10: Obtain the local reset signal generated by the local reset source, and receive the upstream reset signal from outside the chip die; Step S20: Obtain working mode configuration information, and arbitrate the local reset signal and the upstream reset signal according to the working mode configuration information to determine the initial reset signal; Step S30: Generate a target reset signal based on the initial reset signal, and perform an internal reset according to the target reset signal; Step S40: Based on the operating mode configuration information, selectively transmit the target reset signal to a downstream node outside the chip die.
[0086] It should be noted that the method provided in this embodiment of the invention is mainly applied to chip dies in a multi-chip reset system, such as the independent functional dies in a GPGPU system using the Chiplet architecture. By changing the traditional central broadcast unidirectional reset logic, it gives each die the ability to autonomously judge and flexibly route reset signals.
[0087] Specifically, the chip die monitors the local reset signals generated by its internal standard reset generation circuits (such as power-on reset, watchdog timeout, etc.) in real time; at the same time, it listens for reset commands from upstream nodes of the external package interconnect via its external reset input interface (such as pins connected to the internal physical traces or shared bus of the advanced package).
[0088] The chip die perceives its current system role, or operating mode configuration information, such as master mode, slave mode, independent mode, or automatic arbitration mode, by detecting the level of external GPIO pins and reading the status of internal one-time fuses or control registers. Subsequently, the internal arbitration logic selects or masks signals based on this mode information. For example, in slave mode, the local reset signal is ignored and the upstream reset signal is selected; in master mode, the upstream reset signal is ignored and the local reset signal is selected, thus determining the initial reset signal that should be responded to.
[0089] To prevent asynchronous signals or glitches from damaging the delicate internal logic circuits, the die needs to perform clock domain synchronization and minimum pulse width filtering on the initial reset signal selected in the previous arbitration step, transforming it into a high-quality internal valid reset signal (i.e., the target reset signal). Subsequently, this target reset signal is used to safely place the internal circuitry of the chip into a defined initial state, completing its own reset action.
[0090] While completing its own reset, the die again determines whether to propagate the reset action outward based on the current operating mode. If it is in master or slave relay mode, the output driver is enabled, transmitting a high-quality target reset signal along the package interconnect to the downstream die; if it is in independent isolation mode, the output is disabled, blocking further propagation of the reset chain.
[0091] The method provided by this invention breaks the constraints of fixed master-slave reset timing. Through the processing flow of acquisition mode, arbitration signal, internal reset, and selective output, each chip die in the system can operate independently like an intelligent routing node. This not only provides a general control logic for building complex hierarchical and partitioned reset networks, but also enhances the robustness of large-scale multi-chip systems in complex environments and computing scenarios.
[0092] Based on any of the above embodiments, considering that engineers often face the challenge of difficulty in isolating local faults due to the hardening of reset networks during the testing and debugging phase after chip tape-out, this embodiment of the invention further proposes a reset control strategy based on dynamic reconfiguration. The method also includes: During system testing or fault diagnosis, obtain dynamic reconfiguration commands; According to the dynamic reconfiguration instruction, the working mode corresponding to the working mode configuration information is reconfigured to the main mode or the independent mode, so as to actively initiate a global reset for the multi-chip reset system or a local reset for the independent reset domain.
[0093] Specifically, in practical engineering, when a multi-chip system undergoes system-level verification on a test platform or encounters suspected deadlock or other faults during actual operation, the test platform or underlying diagnostic firmware can send dynamic reconfiguration instructions to a specific target chip die through channels such as debug interfaces and control buses. This instruction typically manifests as a temporary rewriting of a specific mode bit (such as the MODE bit) in the die's internal software-writable control register.
[0094] When the target chip die receives and parses the reconfiguration instruction, its configuration awareness unit immediately updates its current operating mode. For example, a normal computing die that was originally in slave mode can be temporarily reconfigured to master mode. At this time, the engineer can use the die's local reset source to force a new reset. Since it has been promoted to master mode, the reset signal will propagate downstream along the interconnect network, achieving a forced global reset of part or the entire multi-chip system. Alternatively, a die suspected of being faulty can be temporarily reconfigured to an independent mode, cutting off its connection with the external reset network. This allows for local reset and state isolation analysis of only the faulty die without affecting the operation of other normal dies.
[0095] This invention, by introducing a mechanism for obtaining dynamic reconfiguration instructions and temporarily changing the operating mode, allows engineers to flexibly initiate global or local resets from any functional die during the testing or diagnostic phase, overcoming the physical limitations of hardware connections. This greatly facilitates system-level testing and fault diagnosis.
[0096] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0097] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, some of the above technical solutions (such as working mode configuration, etc.) can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a read-only memory, random access memory, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments.
[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A configurable reset device, characterized in that, Integrated within the die, including: Local reset source, used to generate a local reset signal; An external reset input interface is provided for receiving an upstream reset signal from outside the chip die. A sensing unit is configured to acquire the operating mode configuration information of the bare chip. A reset arbitration selector is connected to the local reset source, the external reset input interface, and the configuration sensing unit, respectively, and is used to determine an initial reset signal from the local reset signal and the upstream reset signal according to the working mode configuration information. The reset output driving unit is connected to the configuration sensing unit and the reset arbitration selector, respectively, and is used to selectively transmit the target reset signal generated based on the initial reset signal to the downstream node outside the chip die according to the working mode configuration information.
2. The configurable reset device according to claim 1, characterized in that, The working mode configuration information includes at least one of the following working modes: slave mode, master mode, automatic arbitration mode, and independent mode. In the slave mode, the reset arbitration selector is configured to ignore the local reset signal and select the upstream reset signal as the initial reset signal, and the reset output drive unit is configured to enable reset signal forwarding output to the downstream node; In the main mode, the reset arbitration selector is configured to ignore the upstream reset signal and select the local reset signal as the initial reset signal, and the reset output drive unit is configured to enable reset signal drive output to the downstream node; In the automatic arbitration mode, the reset arbitration selector is configured to generate the initial reset signal when either the local reset signal or the upstream reset signal is valid, and the reset output drive unit is configured to enable the reset signal drive output to the downstream node. In the independent mode, the reset arbitration selector is configured to select the local reset signal as the initial reset signal, and the reset output drive unit is configured to disable the reset signal output to the downstream node.
3. The configurable reset device according to claim 1, characterized in that, The bare chip die includes a first pin and a second pin; The configuration sensing unit is also used to obtain the input direction configuration information of the chip die; The device further includes an input pin selection circuit, which is connected to the first pin, the second pin, and the external reset input interface, respectively. The input pin selection circuit is used to selectively connect the first pin or the second pin to the external reset input interface according to the input direction configuration information; The output terminal of the reset output driver unit is connected to both the first pin and the second pin, or the output terminal of the reset output driver unit is connected to the first pin and the second pin that are not configured as the external reset input interface according to the input direction configuration information.
4. The configurable reset device according to any one of claims 1 to 3, characterized in that, It also includes a signal processing unit; One end of the signal processing unit is connected to the reset arbitration selector, and the other end is connected to the reset output driving unit. It is used to perform clock domain synchronization and pulse width processing on the initial reset signal to generate an internal reset valid signal. The internal reset valid signal is used to reset the internal logic of the chip die and is provided to the reset output drive unit as the target reset signal.
5. The configurable reset device according to any one of claims 1 to 3, characterized in that, The local reset signal generated by the local reset source includes at least one of the following: a power-on reset signal, a software-triggerable soft reset signal, and a hardware watchdog timeout reset signal. The configuration sensing unit is electrically connected to at least one of the external general-purpose input / output pins, the internal one-time programmable memory, and the software writable control register of the chip die. The configuration sensing unit is used to generate the operating mode configuration information by acquiring at least one of the level state of the external general-purpose input / output pins, the fuse state of the internal one-time programmable memory, and the stored value of the software writable control register.
6. A multi-chip reset system, characterized in that, This includes a packaging structure and multiple bare chips integrated within the packaging structure; The plurality of chip dies includes at least a first chip die and a second chip die, and both the first chip die and the second chip die have an integrated configurable reset device as described in any one of claims 1 to 5. The reset output drive unit of the first chip die is connected to the external reset input interface of the second chip die through an interconnection structure to form a reset signal relay transmission chain.
7. The multi-chip reset system according to claim 6, characterized in that, The interconnect structure includes a dedicated reset signal interconnect line, or the interconnect structure is a general interconnect bus shared between the first chip die and the second chip die.
8. The multi-chip reset system according to claim 6, characterized in that, When the first chip die is configured to operate in master mode and the second chip die is configured to operate in slave mode, the first chip die generates an internal reset and drives a reset signal to be output to the second chip die, and the second chip die receives the signal synchronously and generates an internal reset. When the first chip die is configured to operate in independent mode and the second chip die is configured to operate in master mode, the first chip die and the second chip die each form an isolated independent reset domain based on their respective local reset sources.
9. An electronic device, characterized in that, Includes a printed circuit board and a multi-chip reset system as described in any one of claims 6 to 8 mounted on the printed circuit board.
10. A reset control method, characterized in that, Chip dies used in multi-chip reset systems include: Acquire the local reset signal generated by the local reset source, and receive the upstream reset signal from outside the chip die; Obtain working mode configuration information, and arbitrate the local reset signal and the upstream reset signal according to the working mode configuration information to determine the initial reset signal; A target reset signal is generated based on the initial reset signal, and an internal reset is performed according to the target reset signal; Based on the operating mode configuration information, the target reset signal is selectively transmitted to a downstream node outside the chip die.
11. The reset control method according to claim 10, characterized in that, Also includes: During system testing or fault diagnosis, obtain dynamic reconfiguration commands; According to the dynamic reconfiguration instruction, the working mode corresponding to the working mode configuration information is reconfigured to the main mode or the independent mode, so as to actively initiate a global reset for the multi-chip reset system or a local reset for the independent reset domain.