Storage device, storage controller, and data write operation method of storage controller

Abstract

Provided are a storage device, a storage controller, and a data write operation method of a storage controller, the storage controller including a memory storing instructions; and a processor configured to execute the instructions and cause the storage controller to: sequentially operate based on a request received from a host, identify a type of a mapping entry between a logical address included in the request and a physical address of a non-volatile memory device; manage a first mapping table including one or more mapping entries of a first type; and manage a second mapping table including one or more mapping entries of a second type, wherein the one or more mapping entries of the first type correspond to data of a first capacity, and wherein the one or more mapping entries of the second type correspond to data of a second capacity.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0177529, filed on December 3, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor memory devices, and more specifically, to memory devices providing multiple logic-to-physical (L2P) mappings, memory controllers, and methods for writing data to memory controllers. Background Technology

[0003] Data write or read operations on a solid-state drive (SSD) device can be performed based on mapping or translation operations between logical and physical addresses. An SSD device can store the mapping between logical and physical addresses in a non-volatile memory device, while the mapping information can be configured in the volatile memory device and then used.

[0004] As the capacity of SSD devices increases, the size of the address-mapped data also increases, which may necessitate expanding the size of the volatile memory space. However, there are limitations on the size of the memory space that can be provided for address space mapping. Therefore, there is a need for apparatus and methods for efficiently managing the mapping table of SSD devices. Summary of the Invention

[0005] A storage device and its operation method for providing multiple L2P mappings are provided, which can efficiently store data and efficiently manage storage space based on the mapping between logical addresses and physical addresses.

[0006] According to one aspect of the disclosure, a memory controller for controlling a non-volatile memory device includes: a memory storing one or more instructions; and at least one processor configured to execute the one or more instructions individually or jointly, wherein the one or more instructions, when executed by the at least one processor, cause the memory controller to: instruct sequential operation based on a request received from a host; identify the type of mapping entries between logical addresses and physical addresses of the non-volatile memory device included in the request; manage a first mapping table including one or more mapping entries of a first type; and manage a second mapping table including one or more mapping entries of a second type, wherein the one or more mapping entries of the first type correspond to data of a first capacity, and wherein the one or more mapping entries of the second type correspond to data of a second capacity.

[0007] According to one aspect of the disclosure, a data write operation method for a storage controller includes: receiving a request and one or more logical addresses from a host; identifying, based on the request, a mapping type between the one or more logical addresses and one or more physical addresses of a non-volatile memory device of the storage controller; generating a mapping entry between the one or more logical addresses and the one or more physical addresses; updating the relationship between the types of the mapping entries; and writing data to the physical address included in the mapping entry.

[0008] According to one aspect of the disclosure, a storage device includes: a non-volatile memory device configured to store data; and a storage controller configured to control the non-volatile memory device, wherein the storage controller includes: a memory storing one or more instructions; and at least one processor configured to execute the one or more instructions individually or jointly, wherein the one or more instructions, when executed by the at least one processor, cause the storage controller to: receive a request and one or more logical addresses from a host; and, based on the request, identify a type of mapping entry between the one or more logical addresses and a physical address of the non-volatile memory device, wherein the mapping entry includes a first type mapping entry corresponding to data of a first capacity and a second type mapping entry corresponding to data of a second capacity.

[0009] According to one aspect of the disclosure, a memory controller for controlling a non-volatile memory device includes: a memory storing one or more instructions; and at least one processor configured to execute the one or more instructions individually or jointly, wherein the one or more instructions, when executed by the at least one processor, cause the memory controller to: identify the type of a mapping entry between a logical address included in a request and a physical address of the non-volatile memory device, based on a request from a host instructing sequential operation; and manage a mapping table including one or more mapping entries, wherein the mapping table is configured to identify the type of mapping entry for a logical address, wherein the mapping table further includes: a first type mapping region including one or more first type mapping entries corresponding to data of a first capacity; and a second type mapping region including one or more second type mapping entries corresponding to data of a second capacity.

[0010] According to one aspect of the disclosure, a data write operation method for a storage controller includes: receiving a request and one or more logical addresses from a host; identifying, based on the request, a mapping type between the one or more logical addresses and one or more physical addresses of a non-volatile memory device of the storage controller; updating a mapping entry included in a mapping region; updating the relationship between the one or more logical addresses and the types of the mapping entries corresponding to the one or more logical addresses; and writing data to the physical address included in the mapping entry.

[0011] According to one aspect of the disclosure, a storage device includes: a non-volatile memory device configured to store data; and a storage controller configured to control the non-volatile memory device, wherein the storage controller includes: a memory storing one or more instructions; and at least one processor configured to execute the one or more instructions individually or jointly, wherein the one or more instructions, when executed by the at least one processor, cause the storage controller to: receive a request and one or more logical addresses from a host; and, based on the request, identify a type of mapping entry between the one or more logical addresses and a physical address of the non-volatile memory device, wherein the mapping entry includes a first type mapping entry corresponding to data of a first capacity and a second type mapping entry corresponding to data of a second capacity. Attached Figure Description

[0012] The above and other aspects and features of specific embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings.

[0013] Figure 1 This is a block diagram illustrating a storage system according to one or more embodiments of the present disclosure.

[0014] Figure 2 This illustrates one or more embodiments according to the present disclosure. Figure 1 A block diagram of an example storage controller.

[0015] Figure 3 This illustrates one or more embodiments according to the present disclosure. Figure 1 Block diagram of a non-volatile memory device.

[0016] Figure 4 This is a block diagram illustrating an example of a storage controller managing storage space according to one or more embodiments of the present disclosure.

[0017] Figure 5A This illustrates one or more embodiments according to the present disclosure. Figure 2 A block diagram of an example mapping table for a Flash Translation Layer (FTL) block.

[0018] Figure 5B This illustrates one or more embodiments according to the present disclosure. Figure 2 A block diagram of an example mapping table for FTL blocks.

[0019] Figure 6 This illustrates one or more embodiments according to the present disclosure. Figure 5A A block diagram of an example mapping table.

[0020] Figure 7 This illustrates one or more embodiments according to the present disclosure. Figure 5A A block diagram of an example mapping table.

[0021] Figure 8 This illustrates one or more embodiments according to the present disclosure. Figure 5A A block diagram of an example mapping table.

[0022] Figure 9 This is a flowchart illustrating an example of a data write operation method of a storage controller according to one or more embodiments of the present disclosure.

[0023] Figure 10 This is a flowchart illustrating an example of a data read operation method of a storage controller according to one or more embodiments of the present disclosure.

[0024] Figure 11 This is a flowchart illustrating an example of a storage controller updating a mapping table according to one or more embodiments of the present disclosure.

[0025] Figure 12 This is a block diagram illustrating a system according to one or more embodiments of the present disclosure. Detailed Implementation

[0026] In the following description, embodiments of the present disclosure will be described in detail to the extent that those skilled in the art can implement the present disclosure.

[0027] As used throughout this detailed description, the components described by reference to terms such as “unit,” “module,” “block,” “device or component,” “circuit or circuit system,” and the functional blocks shown in the accompanying drawings, will be implemented using software, hardware, or a combination thereof. In one or more embodiments, the software may be or include machine code, firmware, embedded code, source code, application software, and / or a combination thereof. In one or more embodiments, the hardware may be or include electrical circuits, electronic circuits (analog or digital circuits), processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, and / or a combination thereof. As used herein, multiple “units,” “modules,” “components,” and “blocks” may be implemented as a single component, or a single “unit,” “module,” “component,” and “block” may include multiple components.

[0028] It will be understood that when an element is referred to as being “connected” to or “connected” to another element, the element may be directly or indirectly connected to that other element, wherein an indirect connection includes “connection via a wireless communication network”.

[0029] Furthermore, when a component "comprises" or "includes" an element, the component may also include other elements, without excluding other elements, unless there is a specific description to the contrary.

[0030] As used herein, the expressions “at least one of a, b, or c” and “at least one of a, b, and c” indicate “only a”, “only b”, “only c”, “both a and b”, “both a and c”, “both b and c”, and “all of a, b, and c”.

[0031] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, the disclosure should not be limited by these terms. These terms are used only to distinguish one element from another.

[0032] As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0033] For ease of description, identification codes may be used with respect to any methods or processes described herein, but are not intended to indicate the order of each step or operation. Each step or operation may be performed in a different order than shown unless the context clearly indicates otherwise. One or more steps or operations may be omitted unless the disclosure context clearly indicates otherwise.

[0034] Various actions, behaviors, blocks, steps, etc., in the flowchart can be executed in the order they are presented, in different orders, or simultaneously. Furthermore, in one or more embodiments, without departing from the scope of the disclosure, some of the actions, behaviors, blocks, steps, etc., may be omitted, added, modified, skipped, etc.

[0035] Figure 1 This is a block diagram illustrating a storage system according to one or more embodiments of the present disclosure. (Refer to...) Figure 1 The storage system 10 may include a host 11 and a storage device 100. The storage system 10 can store data and manage the stored data.

[0036] In one or more embodiments, the storage system 10 may be included in various systems or devices. For example, the storage system 10 may be a system (such as a computing system, communication system, automotive system, or cloud system), or may be included in a system (such as a computing system, communication system, automotive system, or cloud system). As another example, the storage system 10 may be included in an electronic device (such as a laptop computer, tablet PC, personal digital assistant (PDA), wearable device, or camera), but the above devices are examples, and the scope of this disclosure is not limited thereto.

[0037] Host 11 can perform various operations on storage system 10. In one or more embodiments, host 11 can be or be implemented as a processor or system-on-a-chip (SoC). For example, host 11 can be a processor (such as a central processing unit (CPU) or application processor (AP)) or SoC. In one or more embodiments, host 11 can execute applications, source code, programs, etc. For example, host 11 can execute applications via a processor or SoC and can perform operations instructed by the applications.

[0038] Host 11 may read data required for an operation from storage device 100, or may store data generated by the operation in storage device 100. Host 11 may send a request REQ indicating an operation to be performed by storage device 100 or including such operation to storage device 100. Host 11 may receive a response RES from storage device 100 corresponding to data or an operation performed by storage device 100. Host 11 may send a request REQ indicating a data write or read operation to storage device 100. In one or more embodiments, host 11 may receive a response RES from storage device 100 corresponding to the completion of a data write, or a response RES indicating the completion of a data read and including the read data.

[0039] In one or more embodiments, host 11 may include a buffer for storing data. For example, host 11 may include a buffer (or buffer memory) (such as static random access memory (SRAM) or dynamic RAM (DRAM)) and may temporarily store data in the buffer, or store source code or executable files of an application to be executed. Host 11 may generate data to be written to storage device 100 based on the above operations. In one or more embodiments, request REQ or response RES may have a format conforming to any standard (e.g., Serial Advanced Technology Attachment (SATA) protocol, Universal Flash Storage (UFS) protocol, etc.).

[0040] Storage device 100 can store data from storage system 10. (See reference...) Figure 1 The storage device 100 may include a storage controller 110 and a non-volatile memory device (or non-volatile memory) 120. The storage controller 110 may include a mapping control block 115 and may support multiple L2P mappings (MLP).

[0041] The storage controller 110 controls the overall operation of the storage device 100. In one or more embodiments, the storage controller 110 may allow the non-volatile memory device 120 to perform operations corresponding to a request REQ received by the storage device 100 from the host 11. For example, the storage controller 110 may generate a command corresponding to a request REQ instructing data to be written and may control the non-volatile memory device 120.

[0042] Storage device 100 can generate an address mapping between the logical address of host 11 and the physical address of the non-volatile memory device of storage device 100, and can store data based on the address mapping. As the capacity of the non-volatile memory device of storage device 100 increases, the capacity of the memory (e.g., volatile memory) required for the address mapping can increase. As the capacity of the non-volatile memory device increases, the memory space used for address mapping cannot be expanded without constraints (e.g., physically expanded), thus requiring means and methods for more efficiently creating and managing address mappings.

[0043] Mapping control block 115 can determine the type of mapping (L2P mapping) between the logical address of host 11 and the physical address of non-volatile memory device 120 in response to a request REQ. In one or more embodiments, mapping control block 115 can determine the type of L2P mapping based on the request REQ. For example, mapping control block 115 can determine the L2P mapping type based on whether the request REQ indicates a sequential operation. For another example, mapping control block 115 can determine the L2P mapping type based on whether the request REQ indicates a random operation. For example, under the control of mapping control block 115, a first type of L2P mapping can be generated when the operation indicated by the request REQ received by memory controller 110 is a random write operation, and a second type of L2P mapping can be generated when the request REQ indicates a sequential write.

[0044] A multi-L2P mapping (MLP) may include or indicate one or more types of L2P mappings. In one or more embodiments, the corresponding L2P mappings of multiple types may have different sizes (or capacities) of data indicated by one L2P mapping entry for each type. For example, a first type of L2P mapping may indicate 4KB of data for each L2P mapping entry, and a second type of L2P mapping may indicate 16KB of data for each L2P mapping entry. In this case, the size of the data indicated by four first-type L2P mapping entries may be the same as the size of the data indicated by one second-type L2P mapping entry.

[0045] In one or more embodiments, one type of L2P mapping can be managed such that it does not exceed any ratio of the total mapping space. For example, a multiple L2P mapping (MLP) can be managed such that the ratio of the first type of L2P mapping space to the total mapping space does not exceed 80% (i.e., the ratio of the number of first type L2P mapping entries to the total number of allocable mapping entries does not exceed 80%). The size of the memory space indicated by each first type L2P mapping entry and the size of the memory space indicated by each second type L2P mapping entry are examples and should not be construed as limiting the scope of this disclosure. For example, one or more embodiments in which a first type L2P mapping entry indicates 4KB of data and a second type L2P mapping entry indicates 16KB of data may also fall within the scope of this disclosure.

[0046] In one or more embodiments, the ratio between the size of the data indicated by the first type of L2P mapping entry and the size of the data indicated by the second type of L2P mapping entry can be a power of 2. (See also...) Figure 2 and Figures 5A to 11 A more detailed description of the mapping control block 115 and the multiple L2P mapping MLP is provided. (Refer to...) Figure 2 The storage controller 110 is described in more detail.

[0047] Reference Figure 1 As shown in the accompanying drawings, storage device 100 is described as including a storage controller 110 and a non-volatile memory device 120, but the scope of this disclosure is not limited thereto. In one or more embodiments, storage device 100 may include one or more storage controllers and one or more non-volatile memory devices. In one or more embodiments, the storage controller may control multiple non-volatile memory devices and may generate and manage the mapping between logical addresses and physical addresses (of the multiple non-volatile memory devices). Furthermore, the storage controller may write data to each of the multiple non-volatile memory devices or read data from each of the multiple non-volatile memory devices. For example, storage controller 110 may connect to multiple non-volatile memory devices through multiple channels and / or paths, and the corresponding paths may operate in response to the same enable signal.

[0048] Figure 2 This illustrates one or more embodiments according to the present disclosure. Figure 1 A block diagram of an example storage controller. Storage controller 200 may correspond to... Figure 1 Storage controller 110. (See reference...) Figure 2The storage controller 200 may include a host interface block 210, a memory interface block 220, a processing block 230, a flash translation layer (FTL) block 240, a mapping control block 250, a buffer memory block 260, an error correction code (ECC) engine block 270, and an advanced encryption standard (AES) engine block 280.

[0049] Host interface block 210 can be from Figure 1 Host 11 receives the request REQ, or may send the response RES to Figure 1 Host 11. In one or more embodiments, host interface block 210 may exchange request REQ or response RES with host 11 in the form of packets. For example, host interface block 210 may receive requests from host 11. Figure 1 The host 11 receives and will be by Figure 1 The non-volatile memory device 120 performs operations or is about to write... Figure 1 The request REQ corresponding to the data in the non-volatile memory device 120. In another example, the host interface block 210 can communicate with the data from the non-volatile memory device 120. Figure 1 Operations performed by or from the non-volatile memory device 120 Figure 1 The response RES corresponding to the data read by the non-volatile memory device 120 is sent to Figure 1 The host 11. In one or more embodiments, the host interface block 210 may be implemented to conform to a standard protocol (such as the SATA protocol or the UFS protocol).

[0050] Memory interface block 220 can write Figure 1 Data sent from non-volatile memory device 120 Figure 1 The non-volatile memory device 120, or capable of receiving from Figure 1 The data read by the non-volatile memory device 120. In one or more embodiments, the memory interface block 220 may be implemented to conform to standard protocols (such as Toggle or Open AND-NOT (NAND) Flash Interface (ONFI)).

[0051] Processing block 230 controls the overall operation of storage controller 200. In one or more embodiments, processing block 230 may be implemented as any processing unit or may include any processing unit. For example, processing block 230 may be implemented as a central processing unit (CPU) or may include a CPU.

[0052] In one or more embodiments, processing block 230 may allow storage controller 200 to perform operations related to storage controller 200. Figure 1 The host 11 receives the operation corresponding to the request REQ. For example, processing block 230 can parse the command included in the request REQ and transmit the parsing result to the memory interface block 220. Figure 1The non-volatile memory device 120. In another example, processing block 230 can generate a command corresponding to the request REQ, and the generated command and the commands to be written included in the request REQ can be transmitted via memory interface block 220. Figure 1 Data transfer from non-volatile memory device 120 to Figure 1 The non-volatile memory device 120.

[0053] FTL block 240 can perform several functions (such as address mapping, wear leveling, and garbage collection). Wear leveling can be used to allow for uniform usage. Figure 1 The blocks in the non-volatile memory device 120 are implemented using techniques to prevent excessive degradation of specific blocks (e.g., firmware techniques for balancing the erase count of physical blocks). Garbage collection refers to the method used to ensure that existing blocks are erased after the valid data of the existing blocks are copied to the new blocks. Figure 1 The technology for the available capacity of the non-volatile memory device 120. Address mapping operation refers to the operation used to transfer data from the memory device 120. Figure 1 The logical address received by host 11 is translated into a physical address for use in storing the actual data. Figure 1 Operation in the non-volatile memory device 120.

[0054] In one or more embodiments, FTL block 240 may support multiple L2P mappings (MLPs). For example, FTL block 240 may provide a first type of L2P mapping and a second type of L2P mapping. In one or more embodiments, FTL block 240 may be based on... Figure 1 Host 11 receives the request REQ and determines the logical address included in the request REQ. Figure 1 The L2P mapping type between the physical addresses of the non-volatile memory device 120.

[0055] In one or more embodiments, FTL block 240 may generate or manage a mapping table for address mapping operations. In one or more embodiments, the mapping table may include various types of mapping entries. The description of FTL block 240 performing address mapping operations using a mapping table is not limited thereto. For example, FTL block 240 may implement address mapping or address mapping supporting multiple L2P mappings based on any data structure other than a table structure.

[0056] In one or more embodiments, the range of physical addresses included in a first type of L2P mapping (or mapping entry) may differ from the range of physical addresses included in a second type of L2P mapping (or mapping entry). In one or more embodiments, the space storing data corresponding to the first type of L2P mapping entry and the space storing data corresponding to the second type of L2P mapping entry may be physically separate from each other. For example, a "first storage space storing data corresponding to the first type of L2P mapping entry" may be a storage space having a different physical distinction (e.g., chip, channel, path, plane, or block) than a "second storage space storing data corresponding to the second type of L2P mapping."

[0057] Mapping control block 250 determines the type of L2P mapping. Mapping control block 250 can correspond to... Figure 1 Mapping control block 115. In one or more embodiments, mapping control block 250 may determine the type of L2P mapping corresponding to the received logical address based on a request REQ. For example, when the request REQ indicates random operation, mapping control block 250 may determine the generation of a first type L2P mapping or a first type L2P mapping entry. In one or more embodiments, mapping control block 250 may control multiple L2P mappings (MLPs) based on control FTL block 240.

[0058] The Multi-L2P Mapping MLP is described as including two types of L2P mappings or generating two types of L2P mapping entries, but the scope of this disclosure is not limited thereto. In one or more embodiments, the Multi-L2P Mapping MLP includes three or more types of L2P mappings or generates three or more types of L2P mapping entries. The criteria used by Mapping Control Block 250 to select or determine the first type of L2P mapping or the second type of L2P mapping are examples, and the scope of this disclosure is not limited thereto.

[0059] Buffer memory block 260 may store data required for the operation of storage controller 200. In one or more embodiments, buffer memory block 260 may (temporarily) store a mapping table generated by FTL block 240 (e.g., a multiple L2P mapping MLP implemented in the mapping table). In one or more embodiments, processing block 230 may control the overall operation of storage controller 200 based on access to data stored in buffer memory block 260.

[0060] In one or more embodiments, buffer memory block 260 may temporarily store data to be written. Figure 1 The non-volatile memory device 120 or from Figure 1 The non-volatile memory device 120 reads data. For example, the buffer memory block 260 can temporarily store data including data read from... Figure 1The host 11 receives the write data in the request REQ and can provide the write data to the memory interface block 220. Figure 1 The non-volatile memory device 120.

[0061] In one or more embodiments, buffer memory block 260 may include a volatile memory device. For example, buffer memory block 260 may include a dynamic random access memory (DRAM) device or a static RAM (SRAM) device. In one or more embodiments, buffer memory block 260 may also include ROM storing firmware or firmware code for configuring the storage controller 200.

[0062] ECC Engine Block 270 can be used from Figure 1 The non-volatile memory device 120 performs error detection and correction functions on the read data. More specifically, the ECC engine block 270 can generate parity bits for the write data to be written into the non-volatile memory device 120, and the generated parity bits can be stored together with the write data. Figure 1 In the non-volatile memory device 120. When data is from Figure 1 When the non-volatile memory device 120 is read, the ECC engine block 270 can retrieve the data along with the read data from... Figure 1 The non-volatile memory device 120 reads the parity bit to correct errors in the read data and can output the corrected read data.

[0063] AES engine block 280 can perform encryption or decryption operations on data input to storage controller 200. In one or more embodiments, AES engine block 280 can perform encryption or decryption operations on received data based on at least one or more of various encryption and / or decryption algorithms (such as symmetric key algorithms).

[0064] In one or more embodiments, the mapping table may be stored in Figure 1 The mapping table is stored in the non-volatile memory device 120 and can be loaded into the buffer memory block 260 according to the operation of the memory controller 200. For example, when the FTL block 240 performs an address mapping operation, part or all of the mapping table stored in the non-volatile memory device 120 can be loaded into the buffer memory block 260 and can be accessed by the block in the memory controller 200. In this case, the mapping table can be implemented using multiple L2P mappings and can include one or more first-type L2P mapping entries and one or more second-type L2P mapping entries. Optionally, the mapping table may also include one or more other types of L2P mapping entries.

[0065] In one or more embodiments, the mapping table may be a page mapping table or may include a page mapping table. In one or more embodiments, the mapping table may also include additional mapping tables. For example, the mapping table may be implemented as a multi-level mapping table that also includes page mapping tables and additional mapping tables. Hereinafter, the mapping table is described as a page mapping table, but the scope of this disclosure should not be construed as limited thereto. Multiple mapping tables may exist, managed by FTL block 240 or mapping control block 250. For example, FTL block 240 or mapping control block 250 may create, modify, or manage a first page mapping table and a second page mapping table.

[0066] Figure 2 Each box in the above description is an example, and the scope of this disclosure is not limited thereto. In one or more embodiments, the storage controller 200 may not include at least a portion of the blocks described above. Figure 2 The partitioning of each block can be a functional partition, and this disclosure is not limited to physically or in hardware implementing each block. In one or more embodiments, at least a portion of the functionality of a block can be performed by other blocks. In one or more embodiments, at least a portion or all of the functionality of a block can be performed by other blocks. For example, all or part of the functionality of at least one of FTL block 240, mapping control block 250, ECC engine block 270, and AES engine block 280 can be implemented by processing block 230. For example, the operation of mapping control block 250 can be defined in firmware stored in buffer memory block 260 (e.g., read-only memory (ROM) within buffer memory block 260).

[0067] Figure 3 This is a detailed illustration of one or more embodiments according to the present disclosure. Figure 1 A block diagram of a non-volatile memory device. The non-volatile memory device 300 may correspond to... Figure 1 Non-volatile memory device 120. (Refer to...) Figure 3 The non-volatile memory device 300 may include a memory cell array 310, a row decoder block 320, a page buffer block 330, a voltage generation block 340, a data input / output (I / O) block 350, a buffer block 360, and a control logic block 370. (See also...) Figure 3 A detailed description of a non-volatile memory device 300 according to one or more embodiments of the present disclosure.

[0068] In one or more embodiments, the non-volatile memory device 300 may include memory cells of any structure. For example, the non-volatile memory device 300 may include NAND flash memory cells. Hereinafter, for ease of description, the non-volatile memory device 300 is described as a NAND flash memory device, but the scope of this disclosure is not limited thereto. It should be understood that one or more embodiments of the non-volatile memory device 300 including other types of memory cells (such as ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), or spin-transfer torque MRAM (STTMRAM)) are also within the scope of this disclosure.

[0069] Memory cell array 310 may include multiple memory blocks BLK1 to BLKz (where z can be a positive integer). Each of memory blocks BLK1 to BLKz may include multiple memory cells. Each of memory blocks BLK1 to BLKz may be connected to line decoder block 320 via at least one ground select line GSL, a word line WL, and at least one string select line SSL. A portion of the word line WL may be used as a dummy word line. Memory blocks BLK1 to BLKz may be connected to page buffer block 330 via multiple bit lines BL. Multiple memory blocks BLK1 to BLKz may be connected to multiple bit lines BL respectively.

[0070] In one or more embodiments, each of the plurality of memory blocks BLK1 to BLKz can be a unit of the erase operation. Memory cells belonging to each of the memory blocks BLK1 to BLKz can be erased simultaneously. In another embodiment, each of the plurality of memory blocks BLK1 to BLKz can be divided into sub-blocks. Each of the plurality of sub-blocks can be a unit of the erase operation, and plurality of memory cells belonging to each sub-block can be erased simultaneously. Hereinafter, "erasure unit" may refer to a unit of the erase operation, and an erase unit may be a memory block or a sub-block.

[0071] Each of the memory blocks BLK1 through BLKz may include multiple pages. Each page may be connected to a word line WL. Each page may be a unit for a write operation.

[0072] Each bit written to each memory cell in a page can form a logical page. For example, when three bits are written to a memory cell, a physical page can include three logical pages. In another example, when one bit is written to a memory cell, a physical page can include one logical page. A logical page or a physical page can be the unit of a read operation.

[0073] The line decoder block 320 can decode the line address RAD received from the buffer block 360, and can control the voltage to be applied to the serial select line SSL, word line WL and ground select line GSL based on the decoded line address RAD.

[0074] Page buffer block 330 can be connected to memory cell array 310 via multiple bit lines BL. Page buffer block 330 can be connected to data I / O block 350 via multiple data lines DL. Page buffer block 330 can operate under the control of control logic block 370.

[0075] When the non-volatile memory device 300 performs a programming operation, the page buffer block 330 can store data to be written to the memory cell. The page buffer block 330 can apply a voltage corresponding to each of the multiple bit lines BL based on the stored data. When the non-volatile memory device 300 performs a read operation, or a verification read of a programming or erasing operation, the page buffer block 330 can sense the voltage of each bit line BL and store the sensed result.

[0076] Voltage generation block 340 generates voltages for the operation of non-volatile memory device 300. In one or more embodiments, voltage generation block 340 can generate multiple voltages based on power supply voltage VCC. For example, voltage generation block 340 can generate voltage VTG by converting or processing power supply voltage VCC, and the generated voltage VTG can be transmitted to line decoder block 320 or page buffer block 330. In one or more embodiments, voltage generation block 340 can operate under the control of control logic block 370.

[0077] Data I / O block 350 can be connected to page buffer block 330 via multiple data lines DL. Data I / O block 350 can receive column address CA from buffer block 360. Data I / O block 350 can output data read from page buffer block 330 to buffer block 360 based on column address CA. Data I / O block 350 can transfer data received from buffer block 360 to page buffer block 330 based on column address CA.

[0078] The buffer block 360 can be accessed from an external device (e.g., Figure 2 The storage controller 200 receives commands CMD or address values ​​ADDR and can exchange data DATA with external devices. Buffer block 360 operates under the control of control logic block 370. Buffer block 360 can transmit commands CMD to control logic block 370, transmit the row address RAD of address value ADDR to row decoder block 320, and transmit the column address CA of address value ADDR to data I / O block 350. Buffer block 360 can exchange data "DATA" with data I / O block 350.

[0079] Control logic block 370 can be controlled via an external device (e.g., Figure 2The storage controller 200 receives the control signal CTRL. The control logic block 370 allows the buffer block 360 to route commands CMD, address values ​​ADDR, and data DATA. The control logic block 370 decodes the commands CMD received from the buffer block 360 and can control the non-volatile memory device 300 according to the decoded commands.

[0080] In one or more embodiments, the non-volatile memory device 300 can be manufactured in a bonding manner. A memory cell array 310 can be manufactured on a first wafer, and a line decoder block 320, a page buffer block 330, a data I / O block 350, a buffer block 360, and a control logic block 370 can be manufactured on a second wafer. The non-volatile memory device 300 can be implemented by bonding the first and second wafers such that the upper surfaces of the first and second wafers face each other.

[0081] In another embodiment, the non-volatile memory device 300 can be fabricated in a cell-on-periphery (COP) manner. Peripheral circuitry, including a row decoder block 320, a page buffer block 330, a data I / O block 350, a buffer block 360, and a control logic block 370, can be implemented on a substrate. The memory cell array 310 can be implemented above the peripheral circuitry. Vias can be used to connect the peripheral circuitry and the memory cell array 310.

[0082] Figure 4 This illustrates one or more embodiments according to the present disclosure. Figure 2 Storage controller management Figure 3 A block diagram illustrating an example of the storage space SM of a non-volatile memory device. According to embodiments of this disclosure, reference is made to... Figures 2 to 4 An embodiment of a storage controller 200 managing the storage space SM of a non-volatile memory device 300 is described.

[0083] Reference Figures 1 to 4 The storage space SM may include a user area UA, a reserved area RA, and a meta area MA. Each of the user area UA, the reserved area RA, and the meta area MA may include multiple erase units.

[0084] Storage controller 200 may configure the user area UA as a storage space accessible to host 11. Storage controller 200 may choose not to provide a reserved area RA to host 11. In one or more embodiments, storage controller 200 may use the reserved area RA to improve the performance of the non-volatile memory device 300. For example, storage controller 200 may use the reserved area RA as replacement memory for bad blocks or as backup memory.

[0085] Similarly, storage controller 200 may not provide the meta-region MA to host 11. In one or more embodiments, storage controller 200 may store metadata required for the operation of storage device 100 in the meta-region MA. For example, storage controller 200 may store mapping tables (e.g., in which multiple L2P mappings MLP are implemented) generated or managed by FTL block 240 in the meta-region MA.

[0086] The storage controller 200 can divide the user area UA into multiple logical areas LU1 to LUx (hereinafter, "x" indicates the number of logical areas). Each of the logical areas LU1 to LUx may include one or more memory blocks or erase units. In one or more embodiments, each of the logical areas LU1 to LUx may be configured to support random write (RW), sequential write (SW), or partitioned write (ZW).

[0087] Storage controller 200 can manage logical regions LU1 to LUx using a mapping table. In one or more embodiments, storage controller 200 can manage logical regions LU1 to LUx based on a mapping table in which multiple L2P mappings (MLPs) are implemented. In one or more embodiments, the type of L2P mapping for each of the logical regions LU1 to LUx can be different. For example, data in the first logical region LU1 can be managed using a first type of L2P mapping, or data in the second logical region LU2 can be managed using a second type of L2P mapping. In one or more embodiments, storage controller 200 can load part or all of the mapping table stored in the meta-region MA into buffer memory block 260 and use it.

[0088] pass Figure 4 The described embodiments of the storage controller 200 managing storage space SM are examples and should not be construed as limiting the scope of this disclosure. In one or more embodiments, a shared write booster buffer (SWBB) of fixed or variable capacity may be further allocated to user area UA, or a dedicated write booster buffer (DWBB) of fixed or variable capacity may be further allocated to user area UA. In one or more embodiments, the type of memory cells in the SWBB area may be single-level cell (SLC), and may be used as space for SLC backup during write operations of storage device 100.

[0089] Figure 5A This is a block diagram illustrating an example of a mapping table according to one or more embodiments of the present disclosure. Mapping table 400 may correspond to... Figures 1 to 4 The mapping table, and implement Figure 2A multi-L2P mapping MLP. In one or more embodiments, the mapping table 400 may be derived from... Figure 2 The FTL block 240 or mapping control block 250 manages the mapping table 400. In one or more embodiments, at least part or all of the mapping table 400 may be stored in... Figure 2 The buffer memory block 260 or the non-volatile memory device 300 (e.g., Figure 4 In the meta-region MA).

[0090] In one or more embodiments, the mapping table 400 may have any data structure. For example, the mapping table 400 may have a data structure such as a bitmap or a table. In one or more embodiments, the mapping table 400 may include a combination of multiple data structures. For example, a first portion of the mapping table 400 may include a bitmap, and a second portion of the mapping table 400 may include a table.

[0091] Reference Figure 5A The mapping table 400 may include a mapping distinction region 410, a first-type mapping region 420, and a second-type mapping region 430. For ease of description or functionalization, Figure 5A Each of the regions can be subdivided, and this disclosure is not limited thereto. In one or more embodiments, Figure 5A Each of the regions can include or be implemented as any data structure (e.g., bitmap, table, etc.).

[0092] exist Figure 5A In the following figures, logical addresses may refer to or include addresses assigned by a host (e.g., Figure 1 The host 11) manages or accesses addresses (such as logical addresses, logical block addresses (LBAs), or logical page numbers (LPNs). Similarly, physical addresses may refer to or include addresses used for managing non-volatile memory devices (e.g., Figure 1 The non-volatile memory device 120) or the address (such as a physical address, physical block address, or physical page number PPN) accessing the non-volatile memory device. Hereinafter, it is described that a logical address is a logical page number and a physical address is a physical page number; however, it should be understood that this disclosure can be applied to address formats other than those specified.

[0093] Mapping distinguishes regions 410 and can be managed Figure 1 The L2P mapping type for each logical address of host 11 is specified. In one or more embodiments, the mapping differentiation region 410 may store or manage L2P mapping type information for logical addresses or type information for L2P mapping entries corresponding to logical addresses. For example, the mapping differentiation region 410 may manage or store information about whether each logical address is included in a first type of L2P mapping entry or a second type of L2P mapping entry.

[0094] In one or more embodiments, it can be based on Figure 1 The request REQ determines the L2P mapping type for each logical address in the mapping differentiation region 410. For example, when the request REQ received by the storage device 100 indicates a random operation (e.g., random write), the corresponding logical address can be managed based on a first type of L2P mapping. For another example, when the request REQ indicates a sequential operation (e.g., sequential write), the corresponding logical address can be managed based on a second type of L2P mapping. In one or more embodiments, the mapping differentiation region 410 can be implemented using a bitmap structure. However, this is merely an example, and the scope of this disclosure is not limited thereto. Reference will be made to... Figures 6 to 9 The mapping distinguishes region 410 in more detail.

[0095] Each of mapping regions 420 and 430 may include one or more mapping entries. In one or more embodiments, each mapping entry may include information about... Figure 1 Information about the logical address of host 11 and about Figure 3 Information about the physical address of the non-volatile memory device 300. In one or more embodiments, each of the mapping entries may have a type corresponding to mapping regions 420 and 430. For example, a mapping entry in the first type mapping region 420 may be a first type mapping entry, and a mapping entry in the second type mapping region 430 may be a second type mapping entry.

[0096] exist Figure 5A In the following figures, the first type of mapping entries can be compared with... Figure 1 and Figure 2 The first type of L2P mapping entries are the same as or similar to, or may be the same as, the first type of L2P mapping entries. Figure 1 and Figure 2 The first type of L2P mapping entry corresponds to this. Figure 5A The second type of mapping entries in the following figures can be compared with... Figures 1 to 2 The second type of L2P mapping entries are the same as or similar to, or may be the same as, the second type of L2P mapping entries. Figures 1 to 2 The second type of L2P mapping entry corresponds to this.

[0097] The first type mapping area 420 can manage first type L2P mappings. The first type mapping area 420 may include or store one or more first type mapping entries. For example, the first type mapping area 420 can manage first type L2P mappings through first type mapping entries.

[0098] In one or more embodiments, a first type mapping entry may indicate or correspond to data of a first capacity. For example, a first type mapping entry may indicate 4KB of data, but this is an example, and the scope of this disclosure is not limited thereto. In one or more embodiments, the first type mapping region 420 may be implemented based on a table structure, but this is an example, and the scope of this disclosure is not limited thereto. (Refer to...) Figures 6 to 9 A more detailed description of the first type of mapping region 420.

[0099] The second-type mapping area 430 can manage second-type L2P mappings. The second-type mapping area 430 may include or store one or more second-type mapping entries. For example, the second-type mapping area 430 can manage second-type L2P mappings through second-type mapping entries.

[0100] In one or more embodiments, a second-type mapping entry may indicate or correspond to data of a second capacity. For example, a second-type mapping entry may indicate 16KB of data, but this is an example, and the scope of this disclosure is not limited thereto. In one or more embodiments, the second-type mapping region 430 may be implemented based on a table structure, but this is an example, and the scope of this disclosure is not limited thereto. (Refer to...) Figures 6 to 9 The second type of mapping region 430 is described in more detail.

[0101] In one or more embodiments, the ratio of one of the mapping regions 420 and 430 may be managed to be less than a threshold. For example, the number or capacity of first-type mapping entries included in the first-type mapping region 420 may be managed to be less than 80% of the maximum number or capacity of allocatable mapping entries that can be included in the mapping table 400. However, this is an example, and the scope of this disclosure is not limited thereto. In one or more embodiments, the ratio of mapping regions 420 and 430 may be determined by... Figure 2 The mapping control block 250 manages the mapping. In one or more embodiments, the size or capacity of the first type of mapping entry may be the same as (e.g., substantially the same as) the size or capacity of the second type of mapping entry.

[0102] Figure 5A Mapping table 400 is an example, and the scope of this disclosure is not limited thereto. It should be understood that embodiments excluding at least a portion of the described regions are also within the scope of this disclosure. One or more embodiments of mapping table 400 that do not map the regions 410 may also fall within the scope of this disclosure. In this case, Figure 2 The mapping control block 250 can manage the mapping entry type and can manage the mapping regions 420 and 430 that store the generated mapping entries.

[0103] Figure 5B This illustrates one or more embodiments according to the present disclosure. Figure 2 A block diagram of the mapping table managed by the FTL blocks. (See reference...) Figure 5B The mapping table MTS can include a first mapping table MT1 and a second mapping table MT2. The mapping table MTS can implement... Figure 1 and Figure 2 A multi-L2P mapping MLP. In one or more embodiments, the mapping table MTS can be derived from... Figure 2 The FTL block 240 or mapping control block 250 manages the mapping table MTS. In one or more embodiments, at least some or all of the mapping table MTS may be stored in... Figure 2 The buffer memory block 260 or the non-volatile memory device 300 (e.g., Figure 4 In the meta-region MA).

[0104] The first mapping table MT1 may include mapping entries of a first type. In one or more embodiments, the first mapping table MT1 may include... Figure 5A The first type of mapping entry. The first mapping table MT1 can be compared with... Figure 5A The first type of mapping region 420 is the same as or similar to it.

[0105] The second mapping table MT2 may include second type mapping entries. In one or more embodiments, the second mapping table MT2 may include... Figure 5A The second type of mapping entry. The second mapping table MT2 can be compared with... Figure 5A The second type of mapping region 430 is the same as or similar to it.

[0106] Figure 5A Mapping table 400 and Figure 5B The mapping table MTS is an example, and the scope of this disclosure is not limited thereto. It should also be understood that by combining... Figure 5A Mapping table 400 or Figure 5B One or more embodiments of the mapping table MTS used to manage various types of L2P mappings are also within the scope of this disclosure. For example, Figure 2 The FTL block 240 and the mapping control block 250 can manage the address mapping between logical addresses and physical addresses through multiple mapping tables MTS and mapping distinction areas 410.

[0107] In one or more embodiments, the location storing data corresponding to a first type of mapping entry and the location storing data corresponding to a second type of mapping entry may be physically separated from each other. For example, refer to Figure 4 When data corresponding to a first type of mapping entry is stored in a first logical region LU1, data corresponding to a second type of mapping entry may not be stored in the first logical region LU1. In one or more embodiments, the location where data corresponding to a first type of mapping entry is stored and the location where data corresponding to a second type of mapping entry is stored may be different from each other and may be physically separated from each other, based on a channel, path, plane, or chip.

[0108] exist Figure 5A and Figure 5BThe description indicates that mapping table 400 or mapping table MTS includes both types of mapping regions, but the scope of this disclosure is not limited thereto. In one or more embodiments, mapping table 400 may further include mapping regions "including mapping entries corresponding to sizes other than the first capacity or the second capacity". In this case, mapping differentiation region 410 may also manage mapping types other than the first type or the second type of logical address. Figure 5A and Figure 5B The accompanying drawings illustrate that the data size indicated by the first type of mapping entry is smaller than the data size indicated by the second type of mapping entry, but this disclosure should not be construed as limited thereto.

[0109] In the following text, for ease of description, the following is described. Figure 2 The FTL block 240 and mapping control block 250 are based on... Figure 5A The mapping table described is used to manage address mappings, but the scope of this disclosure is not limited thereto. It should be understood that the embodiments described below can be similarly applied without departing from the technical spirit of this disclosure. Figure 5B The mapping table MTS.

[0110] Figure 6 This is a detailed illustration of one or more embodiments according to the present disclosure. Figure 5A A block diagram of the mapping table. Mapping table 500 can correspond to... Figure 2 and Figure 5A The mapping table. (Refer to...) Figure 6 The mapping table 500 may include a mapping distinction region 510, a first-type mapping region 520, and a second-type mapping region 530. (Refer to...) Figures 1 to 6 A detailed description of a mapping table according to one or more embodiments of this disclosure.

[0111] Mapping distinguishes region 510, which can correspond to Figure 5A The mapping distinction region 510. In one or more embodiments, the mapping distinction region 510 may include mapping types corresponding to a plurality of logical addresses. For example, the mapping distinction region 510 may include a mapping type for each of four logical addresses. In one or more embodiments, the mapping distinction region 510 may be implemented as a bitmap, and each bit within the bitmap may indicate a mapping type for a plurality of logical addresses.

[0112] exist Figure 6In the mapping region 510, the bitmap may include bit "1001". The most significant bit (MSB) may indicate the mapping type of LPN1 to LPN4. Bits (e.g., the remaining bits in the bitmap of mapping region 510 excluding the most significant bit) may sequentially indicate the mapping types of LPN5 to LPN8, LPN9 to LPN12, and LPN13 to LPN16, respectively. In one or more embodiments, bits in each bitmap of mapping region 510 may indicate the physical address of the corresponding logical address and mapping regions 520 and 530 where mapping entries are generated or stored. For example, when a bit in mapping region 510 has a logical value "1", this may indicate that the mapping entry for the corresponding logical address is stored in the first type mapping region 520.

[0113] In one or more embodiments, the number of logical addresses indicated by a bit of the mapping distinction region 510 can be the ratio (or the maximum value of the ratio) between the size of the data indicated by the second type of mapping entry and the size of the data indicated by the first type of mapping entry. Figure 6 In this context, the data indicated by the first type of mapping entry can have a size of 4KB, and the data indicated by the second type of mapping entry can have a size of 16KB. Therefore, one bit of the mapping distinction region 510 can indicate the mapping type of four logical addresses.

[0114] The first type of mapping region 520 can correspond to Figure 5A The first type mapping region 420. The first type mapping region 520 may include first type mapping entries. For example, a first type mapping entry may indicate data with a size or capacity of 4KB. The first type mapping entry may map LPN1 to PPNa1, LPN2 to PPNa2, and LPN3 and LPN4 to PPNa3 and PPNa4, respectively. Because each of the second and third most significant bits in the mapping distinction region 510 is "0", the first type mapping region 520 may not include mapping entries for LPN5 to LPN12. The first type mapping region 520 may include mapping entries for each of LPN13 to LPN16 (e.g., LPN13 to LPN16 are mapped to PPNa5 to PPNa8, respectively).

[0115] The second type of mapping region 530 can correspond to Figure 5AThe second type mapping region 430 may include second type mapping entries. For example, a second type mapping entry may indicate data with a size of 16KB. The second type mapping entry may map LPN5 to LPN8 to PPNb1 and LPN9 to LPN12 to PPNb2. In one or more embodiments, the size of the data pointed to by the physical address of the first type mapping region 520 and the physical address of the second type mapping region 530 may be different from each other. For example, PPNb2 of the first mapping entry M1 may indicate data with a size or capacity of 4KB, and PPNb2 of the second mapping entry M2 may indicate data with a size or capacity of 16KB. In one or more embodiments, the size of the first type mapping entry of the first type mapping region 520 may be (e.g., substantially) the same as the size of the second type mapping entry of the second type mapping region 530. For example, both the first mapping entry M1 and the second mapping entry M2 may have a size or capacity of 4 bytes.

[0116] Figure 7 This is a detailed illustration of one or more embodiments according to the present disclosure. Figure 5A A block diagram illustrating an example of a mapping table. Mapping table 600 may correspond to... Figure 2 and Figure 5A The mapping table. (Refer to...) Figure 7 The mapping table 600 may include a mapping distinction region 610, a first-type mapping region 620, and a second-type mapping region 630. (Refer to...) Figures 1 to 7 A detailed description of a mapping table according to one or more embodiments of this disclosure.

[0117] Mapping distinction region 610 can indicate the mapping type of logical addresses. Mapping distinction region 610 can be compared with... Figure 6 The mapping distinction region 510 is the same. The first type mapping region 620 may include one or more first type mapping entries. The first type mapping region 620 may be similar to... Figure 6 The first type of mapping region 520 is the same.

[0118] The second-type mapping region 630 may include one or more second-type mapping entries. In one or more embodiments, the second-type mapping entries within the second-type mapping region 630 may map physical addresses starting from one or more consecutive physical addresses corresponding to logical addresses. For example, a second-type mapping entry may include PPNa5, where PPNa5 is a physical page number starting from consecutive physical page numbers corresponding to LPN5 to LPN8.

[0119] exist Figure 7In this second type of mapping region 630, LPN5 to LPN8 can be mapped to PPNa5, and LPN9 to LPN12 can be mapped to PPNa9. In one or more embodiments, the size of the data indicated by the physical address included in the first type of mapping entry can be the same as the size of the data indicated by the physical address included in the second type of mapping entry. For example, the size of the data indicated by the physical address included in the first mapping entry M1 (i.e., PPNa2) can be the same as the size of the data indicated by the physical address (or physical page number, i.e., PPNa9) included in the third mapping entry M3.

[0120] In one or more embodiments, the size of the first type mapping entry in the first type mapping region 620 may be the same as (e.g., substantially) the size of the second type mapping entry in the second type mapping region 630. For example, both the first mapping entry M1 and the third mapping entry M3 may have a size of 4 bytes.

[0121] Figure 8 This is a detailed illustration of one or more embodiments according to the present disclosure. Figure 5A A block diagram illustrating an example of a mapping table. Mapping table 700 may correspond to... Figure 2 and Figure 5A The mapping table. (Refer to...) Figure 8 The mapping table 700 may include a mapping distinction region 710, a first-type mapping region 720, and a second-type mapping region 730. (Refer to...) Figures 1 to 8 A detailed description of a mapping table according to one or more embodiments of this disclosure.

[0122] Mapping distinction region 710 can indicate the mapping type of logical addresses. Mapping distinction region 710 can be compared with... Figure 6 The mapping distinguishes regions 510 or Figure 7 The mapping distinction region 610 is the same. The first type mapping region 720 may include one or more first type mapping entries. The first type mapping region 720 may be similar to... Figure 6 The first type of mapping region 520 or Figure 7 The first type of mapping region 620 is the same.

[0123] The second-type mapping region 730 may include one or more second-type mapping entries. In one or more embodiments, the second-type mapping entries within the second-type mapping region 730 may map logical addresses starting from consecutive logical addresses to physical addresses. For example, a second-type mapping entry may map LPN5, which is a logical page number starting from LPN5 to LPN8, to PPNb1, which is the corresponding physical page number.

[0124] In one or more embodiments, the size of the data indicated by the physical address of the first type mapping region 720 may be different from the size of the data indicated by the physical address of the second type mapping region 730. For example, the size of the data indicated by the physical address of the first type mapping region 720 may be 4KB, and the size of the data indicated by the physical address of the second type mapping region 730 may be 16KB.

[0125] In one or more embodiments, the size of the first type mapping entry in the first type mapping region 720 may be the same as (e.g., substantially) the size of the second type mapping entry in the second type mapping region 730. For example, both the first mapping entry M1 and the fourth mapping entry M4 may have a size or capacity of 4 bytes.

[0126] The description includes Figure 8 The physical address in the second type of mapping entry and Figure 6 The second type of mapping region 530 (e.g., the physical address of the second type of mapping region 530) is the same as or similar, but the scope of this disclosure is not limited thereto. In one or more embodiments, it is described that includes Figure 8 The physical address in the second type of mapping entry and Figure 7 The second type of mapping region 630 (e.g., the physical address of the second type of mapping region 630) is the same as or similar, but the scope of this disclosure is not limited thereto.

[0127] exist Figures 6 to 8 The configuration of the mapping tables shown and described in detail herein is illustrative, and the scope of this disclosure is not limited thereto. It should also be understood that... Figures 6 to 8 The described mapping entries are combined in one or more embodiments within the scope of this disclosure. Figures 6 to 8 The document describes a first type of mapping entry with the same size as a second type of mapping entry, but the scope of this disclosure is not limited thereto. For example, it should be understood that one or more embodiments in which the length of the first type of mapping entry is less than 4 bytes and the length of the second type of mapping entry is 4 bytes are also within the scope of this disclosure. Figures 6 to 8 The table only describes 16 logical addresses and their mapping entries, but it should be understood that the mapping table may also include mapping entries that are the same as or similar to those described above.

[0128] exist Figures 6 to 8 This document describes a mapping table including two types of L2P mappings, but this is only an example. It should be understood that one or more embodiments also include additional types of L2P mappings within the scope of this disclosure. In one or more embodiments, the mapping entries corresponding to the additional types may include those that can be mapped via... Figures 6 to 8The mapping between one or more logical addresses and one or more physical addresses of the same or similar form is described. In one or more embodiments, the size of the mapping entry corresponding to the additional type may be the same as the size of the first type mapping entry or the size of the second type mapping entry (e.g., substantially the same).

[0129] exist Figures 5A to 8 The ratio between the size of the data indicated by the second mapping entry and the size of the data indicated by the first mapping entry is an example. It should be understood that embodiments with different values ​​for these ratios are also within the scope of this disclosure. For example, the size of the data indicated by the first type mapping entry may be 4KB, and the size of the data indicated by the second type mapping entry may be 32KB. In this case, each bit of the mapping distinction region may indicate a mapping type of 8 logical addresses. In one or more embodiments, the mapping table may also include one or more additional mapping regions (such as a third type mapping region). For example, a third type mapping region may manage a third type of L2P mapping through third type mapping entries, and a third type mapping entry may indicate or correspond to data with a third capacity.

[0130] The description of a bitmap in a mapping partition region indicates a mapping type for multiple logical addresses, but the scope of this disclosure is not limited thereto. It should be understood that one or more embodiments in which multiple bits (e.g., two bits) indicate mapping types for multiple logical addresses are also within the scope of this disclosure. For example, mapping table 500 may also include a third type of mapping region. A third type of mapping entry may indicate data with a size or capacity of 64KB, and every two bits in the bitmap of mapping partition region 510 may indicate the mapping type for the corresponding 16 logical addresses (since the ratio between 64KB and 4KB is 16). For example, when the value of the bit corresponding to the logical address in the bitmap is “00”, the logical address may be managed as a first type of mapping entry. When the value of the bit is “01”, the logical address may be managed as a second type of mapping entry. When the value of the bit is “10”, the logical address may be managed as a third type of mapping entry, but this is an example, and the disclosure is not limited thereto. Even in this case, the ratio between the number of a particular type of mapping entry and the number of all allocable mapping entries may be managed so as not to exceed a threshold.

[0131] The description of a mapping region being implemented as a bitmap structure is merely an example, and it should be understood that one or more embodiments implemented as data structures other than bitmaps are also within the scope of this disclosure. In one or more embodiments, the locations storing multiple data entries corresponding to various types of mapping entries may be physically separated from each other. For example, a first location storing data corresponding to a first type of mapping entry, a second location storing data corresponding to a second type of mapping entry, or a third location storing data corresponding to a third type of mapping entry may be physically separated from each other. For example, the first, second, and third locations may differ from each other and may be physically separated from each other based on a channel, path, plane, or chip.

[0132] Figures 5A to 8 The mapping table can be increased Figure 2 The efficient use of the limited memory space within the buffer memory block 260 allows for the writing of large amounts of data to or reading from the non-volatile memory devices included in the storage device. Furthermore, Figures 5A to 8 The mapping table 400 determines the mapping type based on factors such as the access type of the data, thereby providing a storage device with high efficiency for data writing or data reading by using the limited memory capacity of the buffer memory block 260.

[0133] Figure 9 This illustrates one or more embodiments according to the present disclosure. Figure 1 A flowchart illustrating an example of a data write operation method for a storage device. (Refer to...) Figures 1 to 9 An example describing a data write operation method for a storage device.

[0134] In operation S110, the storage device 100 may receive a write request. In one or more embodiments, the write request may include... Figure 1 The logical address managed by host 11. For example, storage device 100 can receive a request REQ "including a logical address and indicating a write operation" through host interface block 210.

[0135] In operation S120, storage device 100 may determine the next operation based on the request REQ. In one or more embodiments, storage device 100 may determine the next operation based on the type of operation indicated by the request REQ. For example, storage device 100 may determine the next operation based on whether the request REQ indicates a sequential write. In one or more embodiments, storage device 100 may identify the type of operation indicated by the request REQ through mapping control block 250, and may identify the next operation. For example, when a request REQ indicating a sequential write is received, storage device 100 may proceed to operation S140. On the other hand, when no request REQ indicating a sequential write is received (e.g., when a request REQ indicating a random write is received), storage device 100 may proceed to operation S130.

[0136] In operation S130, storage device 100 may identify the next operation based on whether there is reserved space in the first type mapping region 420. In one or more embodiments, storage device 100 may identify the next operation based on whether the number of first type mapping entries exceeds a threshold. For example, when the number of first type mapping entries is equal to the threshold, storage device 100 may determine that there is no reserved space in the first type mapping region 420 and proceed to operation S140. For another example, when the number of first type mapping entries is less than the threshold, storage device 100 may determine that there is reserved space in the first type mapping region 420 and proceed to operation S150.

[0137] In one or more embodiments, the storage device 100 may determine whether reserved space exists in the first type of mapping region 420 via the mapping control block 250 or the FTL block 240. Operation S130 describes identifying the next operation based on the number of first type mapping entries, but the scope of this disclosure is not limited thereto. For example, the storage device 100 may perform operation S130 based on a comparison between the ratio of the number of first type mapping entries to the number of all allocable mapping entries and a threshold.

[0138] In operation S140, storage device 100 may update the second type mapping region 430. In one or more embodiments, FTL block 240 may generate a second type mapping entry that includes the relationship between received logical addresses and one or more physical addresses (e.g., Figures 6 to 8 (Second type mapping entries). For example, storage device 100 can update the second type mapping region 430 by adding created (or generated) second type mapping entries to the second type mapping region 430.

[0139] In operation S150, storage device 100 may update first type mapping region 420. In one or more embodiments, FTL block 240 may generate first type mapping entries including the relationship between received logical addresses and one or more physical addresses (e.g., Figures 6 to 8 (The first type of mapping entry). For example, storage device 100 can update the first type mapping region 420 by adding the generated first type mapping entry to the first type mapping region 420. Storage device 100 can proceed to operation S160 after operation S140 or operation S150.

[0140] In one or more embodiments, the size or capacity of the data indicated by the second type of mapping entry may be greater than the size or capacity of the data indicated by the first type of mapping entry. For example, the first type of mapping entry may indicate data of size 4KB, and the second type of mapping entry may indicate data of size 16KB. However, this is an example, and the scope of this disclosure is not limited thereto.

[0141] In operation S160, storage device 100 may update the mapping partition region. In one or more embodiments, FTL block 240 or mapping control block 250 may update the mapping partition region 410 corresponding to the logical address included in the request REQ. For example, FTL block 240 or mapping control block 250 may update the bits of the bitmap within the mapping partition region 410 corresponding to the logical address.

[0142] In operation S170, storage device 100 may refer to mapping table 400 to write data to the physical address corresponding to the logical address. In one or more embodiments, storage controller 200 may send the physical address and data generated by referring to mapping table 400 stored in buffer memory block 260 to non-volatile memory device 300 via memory interface block 220.

[0143] pass Figure 9 The operation of the described storage device 100 is exemplary, and the scope of this disclosure is not limited thereto. In one or more embodiments, simultaneous execution is possible. Figure 9 At least some of the operations. In one or more embodiments, Figure 9 At least some of the operations can be performed in a different order. Figure 9 The document describes two types of mapping entries being managed, but this is merely an example. It should be understood that one or more embodiments of writing data to the non-volatile memory device 300 by updating or referencing the mapping table 400, which includes and manages additional types of mapping entries, are also within the scope of this disclosure.

[0144] Figure 10 This illustrates one or more embodiments according to the present disclosure. Figure 1A flowchart illustrating an example of a data read operation method for a storage device. (Refer to...) Figures 1 to 8 and Figure 10 A method for reading data from a storage device 100 according to one or more embodiments of the present disclosure is described.

[0145] In operation S210, the storage device 100 may receive a read request. In one or more embodiments, the read request may include... Figure 1 The logical address managed by host 11. For example, storage device 100 can receive a request REQ "including a logical address and indicating a read operation" through host interface block 210.

[0146] In operation S220, storage device 100 may determine a mapping region corresponding to the received logical address. In one or more embodiments, FTL block 240 or mapping control block 250 may refer to mapping differentiation region 410 to determine the mapping region corresponding to the logical address. For example, when the value of the bit corresponding to the logical address in the bitmap of mapping differentiation region 410 is logic 1, storage controller 200 may determine that the mapping entry between the logical address and the physical address is included in first type mapping region 420. For another example, when the value of the bit corresponding to the logical address in the bitmap of mapping differentiation region 410 is logic 0, storage controller 200 may determine that the mapping entry between the logical address and the physical address is included in second type mapping region 430.

[0147] In operation S230, the storage device 100 may determine the next operation based on the determination in operation S220. When it is determined in operation S220 that the mapping entry of the logical address is included in the first type of mapping region, the storage device 100 may proceed to operation S240. When it is determined in operation S220 that the mapping entry of the logical address is included in the second type of mapping region, the storage device 100 may proceed to operation S250.

[0148] In operation S240, storage device 100 may refer to first type mapping region 420 to obtain the physical address corresponding to the logical address. For example, storage device 100 may obtain the physical address corresponding to the logical address based on one or more first type mapping entries corresponding to the logical address. In operation S250, storage device 100 may refer to second type mapping region 430 to obtain the physical address corresponding to the logical address. For example, storage device 100 may obtain the physical address corresponding to the logical address based on one or more second type mapping entries corresponding to the logical address. Storage device 100 may terminate operation S240 or operation S250, and then proceed to operation S260 (i.e., storage device 100 may proceed to operation S260 after operation S240 or operation S250).

[0149] In operation S260, storage device 100 can read data from non-volatile memory device 300 using the obtained physical address. In one or more embodiments, storage controller 200 can send commands and physical addresses corresponding to logical addresses to non-volatile memory device 300 and receive data from non-volatile memory device 300 via memory interface block 220. After operation S260, storage device 100 can transfer the read data to... Figure 1 Host 11.

[0150] pass Figure 10 The operation of the described storage device 100 is exemplary, and the scope of this disclosure is not limited thereto. In one or more embodiments, simultaneous execution is possible. Figure 10 At least some of the operations. In one or more embodiments, Figure 10 At least some of the operations can be performed in a different order. Figure 10 The document describes two types of mapping entries being managed, but this is merely an example. It should be understood that one or more embodiments of reading data from the non-volatile memory device 300 by updating or referencing the mapping table 400, which includes and manages additional types of mapping entries, are also within the scope of this disclosure.

[0151] Figure 11 This illustrates one or more embodiments according to the present disclosure. Figure 2 A flowchart illustrating an example of a mapping table update operation method for a storage controller. (See also...) Figures 2 to 8 and Figure 11 Describe in detail how to update mapping table 400.

[0152] In operation S310, the storage controller 200 may receive data from the storage controller. Figure 1 The host 11 receives the logical address in the request REQ. In operation S320, the storage controller 200 may refer to the mapping table 400 to determine whether an L2P mapping for the logical address exists. In one or more embodiments, the storage controller 200 may determine whether an existing L2P mapping (or existing mapping entry) for the received logical address exists via FTL block 240. When an existing L2P mapping (or existing mapping entry) for the logical address received in operation S310 exists, the storage controller 200 may proceed to operation S330. On the other hand, when no existing L2P mapping (or existing mapping entry) for the logical address received in operation S310 exists, the storage controller 200 may proceed to operation S380.

[0153] In operation S330, the storage controller 200 can determine the mapping type of the received logical address or the type of the mapping entry for the received logical address based on the request REQ. The storage controller 200 can perform operations related to... Figure 9 Operation S120 or Figure 10 The operation S220 is the same as or similar to the operation S330. In one or more embodiments, the storage controller 200 may perform operation S330 via the mapping control block 250.

[0154] In one or more embodiments, the storage controller 200 may determine the mapping type of the received logical address or the type of the corresponding mapping entry based on the type of operation indicated by the request. For example, when a request REQ indicating a sequential operation is received, the storage controller 200 may determine, based on the request REQ, to generate a second type mapping entry including the received logical address within a second type mapping region 430. For another example, when a request REQ indicating a random operation is received, the storage controller 200 may determine, based on the request REQ, to generate a first type mapping entry including the received logical address within a first type mapping region 420.

[0155] In operation S340, the storage controller 200 may determine whether the type of the mapping entry determined in operation S330 is the same as the type of an existing mapping entry for the logical address. In one or more embodiments, the storage controller 200 may perform operation S340 via the mapping control block 250. In one or more embodiments, the storage controller 200 may refer to the mapping differentiation region 410 in the mapping table 400 to determine the type of an existing mapping entry for the logical address, and may determine whether the type of an existing mapping entry for the logical address is the same as the type of the mapping entry determined in operation S330.

[0156] When it is determined that the type of the mapping entry determined in operation S330 is the same as the type of an existing mapping entry, the storage controller 200 may proceed to operation S350. When it is determined that the type of the mapping entry determined in operation S330 is not the same as the type of an existing mapping entry, the storage controller 200 may proceed to operation S360.

[0157] In operation S350, the storage controller 200 may update a mapping entry of a previous type. In one or more embodiments, the storage controller 200 may update a mapping entry of a previous type via FTL block 240. For example, the storage controller 200 may change one or more physical addresses corresponding to one or more logical addresses in a mapping entry to one or more new physical addresses to which data will be written. After operation S350, the storage controller 200 may terminate the L2P mapping update operation.

[0158] In operation S360, the storage controller 200 may generate or update new types of mapping entries. In one or more embodiments, the storage controller 200 may update new types of mapping entries via FTL block 240. For example, the storage controller 200 may generate new types of mapping entries that include mappings between one or more logical addresses and one or more physical addresses to which data will be written.

[0159] In operation S360, the storage controller 200 can generate new types of mapping entries and remove existing mapping entries. The mapping entries generated (or updated) in operations S350 and S360 can be stored in the corresponding mapping areas 420 and 430.

[0160] In operation S370, the storage controller 200 may update the mapping distinction region. In one or more embodiments, the storage controller 200 may perform operation S370 via FTL block 240 or mapping control block 250. For example, the storage controller 200 may update the mapping type (or the type of mapping entry) of the logical address received in operation S310 within the mapping distinction region 410 to change it to a new type. For example, FTL block 240 may change the value of the bits in the bitmap within the mapping distinction region 410 corresponding to the portion of the received logical address or the bitmap to match the new type. After operation S370, the storage controller 200 may terminate the L2P mapping update operation.

[0161] In operation S380, the storage controller 200 may generate a new mapping entry. In one or more embodiments, the storage controller 200 may generate a new mapping entry for a logical address based on an operation that is the same as or similar to operations S120 to S150. For example, the storage controller 200 may generate a first type of mapping entry or a second type of mapping entry based on whether the request REQ indicates a sequential operation or a random operation (e.g., a second type of mapping entry may be generated based on a request REQ indicating a sequential operation, and a first type of mapping entry may be generated based on a request REQ indicating a random operation).

[0162] In operation S390, the storage controller 200 may update the mapping distinction region 410. In one or more embodiments, the storage controller 200 may update the portion of the mapping distinction region 410 corresponding to one or more received logical addresses. The storage controller 200 may perform operation S390 in the same or similar manner as in operation S370. For example, when the mapping distinction region 410 includes a bitmap indicating the type of a mapping entry, the type of the mapping entry indicated by one or more logical addresses may be updated by updating the value of the bit in the bitmap corresponding to one or more logical addresses.

[0163] pass Figure 11The operation of the described storage controller 200 is exemplary, and the scope of this disclosure is not limited thereto. In one or more embodiments, simultaneous operations may be performed... Figure 11 At least some of the operations. In one or more embodiments, Figure 11 At least some of the operations can be performed in a different order.

[0164] Figure 12 This is a diagram illustrating a system 1000 employing a storage device according to one or more embodiments of the present disclosure. Generally, Figure 12 System 1000 can be a mobile system (such as a mobile phone, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device). However, Figure 12 System 1000 is not limited to mobile systems. For example, system 1000 can be a system such as a personal computer, laptop computer, server, media player, or automotive device (such as a navigation device).

[0165] Reference Figure 12 The system 1000 may include a main processor 1100, memories 1200a and 1200b and storage devices 1300a and 1300b, and may also include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communicator (or communication device) 1440, a display 1450, a speaker 1460, a power supply (or power supply device) 1470 and a connection interface 1480.

[0166] The main processor 1100 controls the overall operation of the system 1000, and more specifically, controls the operation of the remaining components of the system 1000. The main processor 1100 can be implemented using a general-purpose processor, a special-purpose processor, or an application processor.

[0167] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to one or more embodiments, the main processor 1100 may also include an accelerator 1130, which is dedicated circuitry for high-speed data computation, such as artificial intelligence (AI) data computation. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented on a separate chip physically independent of any other component of the main processor 1100.

[0168] Memory 1200a and 1200b may be used as the main memory device of system 1000. Each of memory 1200a and 1200b may include volatile memory (such as SRAM and / or DRAM) and may also include non-volatile memory (such as flash memory, PRAM and / or RRAM). Memory 1200a and 1200b may be implemented in the same package as main processor 1100.

[0169] Storage devices 1300a and 1300b can be used as non-volatile storage devices that store data regardless of power supply, and can have a larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and non-volatile memory (NVM) 1320a and 1320b that store data under the control of storage controllers 1310a and 1310b. Each of non-volatile memories 1320a and 1320b may include two-dimensional (2D) flash memory or three-dimensional vertical NAND (V-NAND) flash memory, or may include different types of non-volatile memory (such as PRAM and / or RRAM).

[0170] Storage devices 1300a and 1300b may be included in system 1000 in a physically separate state from main processor 1100, or may be implemented within the same package as main processor 1100. Furthermore, storage devices 1300a and 1300b may be detachably coupled to other components of system 1000 via an interface (such as connection interface 1480, described later) in the form of a solid-state device (SSD) or memory card. Such storage devices 1300a and 1300b may include, but are not limited to, devices using application standards (such as Universal Flash Storage (UFS), embedded multimedia card (eMMC), or Non-Volatile Memory Fast (NVMe)).

[0171] In one or more embodiments, each of the storage devices 1300a and 1300b may be or may include a reference. Figures 1 to 11 The described storage device 100. In one or more embodiments, each of the storage controllers 1310a and 1310b may be or may include references. Figures 1 to 11 The memory controller 110 is described. Each of the non-volatile memories 1320a and 1320b may be or may include references. Figures 1 to 11 The non-volatile memory device 120 is described.

[0172] Image capturing device 1410 can capture still or moving images and may include a camera, video camera and / or webcam.

[0173] User input device 1420 can receive various types of data input by the user of system 1000, and may include a touchpad, keypad, keyboard, mouse and / or microphone.

[0174] Sensor 1430 can detect various types of physical quantities that can be obtained from outside the system 1000, and can convert the detected physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0175] The communicator 1440 can transmit signals to other devices outside the system 1000 or receive signals from other devices outside the system 1000 according to various communication protocols. The communicator 1440 may be implemented as including an antenna, a transceiver, and / or a modem.

[0176] The display 1450 and speaker 1460 can be used as output devices for users to output visual and auditory information to the system 1000.

[0177] The power supply 1470 can appropriately convert power supplied from a battery embedded in the system 1000 and / or an external power source to supply power to each component of the system 1000.

[0178] The connection interface 1480 provides a connection between the system 1000 and an external device that connects to the system 1000 and is able to exchange data with the system 1000. The connection interface 1480 can be implemented using various interfaces, such as Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, External SATA (e-SATA) interface, Small Computer Small Interface (SCSI) interface, Serial Attached SCSI (SAS) interface, Peripheral Component Interconnect (PCI) interface, PCIe (PCIe) interface, NVM Fast (NVMe) interface, IEEE 1394 interface, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Universal Flash Storage (UFS) interface, Embedded Universal Flash Storage (eUFS) interface, and Compact Flash (CF) card interface.

[0179] The above description relates to detailed embodiments for carrying out this disclosure. This disclosure may include embodiments in which the design is simply or easily modified, as well as the embodiments described above. Furthermore, techniques that are easily modified and implemented using the above embodiments may be included in this disclosure. While this disclosure has been described with reference to the above embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

[0180] According to one or more embodiments of the present disclosure, a storage device and a method of operating the same are provided for providing multiple L2P mappings, which can efficiently store data and efficiently manage storage space based on an efficient method of mapping between logical addresses and physical addresses.

[0181] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A memory controller for controlling a non-volatile memory device, the memory controller comprising: The mapping control block is configured to: identify the type of mapping entry between the logical address in the request and the physical address of the non-volatile memory device, based on the sequential operation indicated by the request received from the host; as well as The flash translation layer block is configured to: manage a first mapping table containing one or more mapping entries of a first type; and manage a second mapping table containing one or more mapping entries of a second type. Wherein, one or more mapping entries of the first type correspond to data of the first capacity, and Among them, one or more mapping entries of the second type correspond to data of the second capacity.

2. The storage controller according to claim 1, wherein, The second capacity is greater than the first capacity.

3. The storage controller according to claim 2, wherein, The ratio between the first capacity and the second capacity is a power of two.

4. The storage controller according to claim 1, wherein, The ratio of the maximum number of one or more mapping entries of the first type to the maximum number of allocatable mapping entries in the first and second mapping tables is less than a threshold.

5. The storage controller according to any one of claims 1 to 4, wherein, The flash translation layer block is configured as follows: Manage bitmaps corresponding to one or more logical addresses, wherein the bitmaps indicate the mapping type of the one or more logical addresses.

6. The storage controller according to claim 5, wherein, The value of each corresponding bit in the bitmap indicates whether one or more logical addresses corresponding to the corresponding bit are included in a first type of mapping entry or a second type of mapping entry.

7. The storage controller according to claim 5, in, The second capacity is greater than the first capacity, and The number of logical addresses corresponding to one bit of the bitmap corresponds to the ratio between the second capacity and the first capacity.

8. The storage controller according to claim 5, further comprising: The buffer memory block is configured as follows: Load the first mapping table and / or the second mapping table and store the data.

9. A data write operation method for a storage controller, the data write operation method comprising: Receive a request and one or more logical addresses from the host; Based on the request, identify the mapping type between the one or more logical addresses and one or more physical addresses of the non-volatile memory device; Generate mapping entries between the one or more logical addresses and the one or more physical addresses; Update the type of the mapping entry; as well as Write the data to the physical address included in the mapping entry.

10. The data writing operation method according to claim 9, in, Mapping entries are included in multiple mapping tables, and The plurality of mapping tables include: A first mapping table, comprising one or more mapping entries of a first type corresponding to data of a first capacity; and The second mapping table includes one or more mapping entries of a second type corresponding to the data of the second capacity.

11. The data writing operation method according to claim 10, wherein, The steps for identifying the mapping type include: identifying the mapping type based on whether the operation indicated by the request is a sequential operation.

12. The data writing operation method according to claim 10, further comprising: Manage the first mapping table and the second mapping table.

13. The data writing operation method according to claim 12, wherein, The number of one or more mapping entries of the first type is less than the threshold.

14. The data writing operation method according to claim 12, in, The steps of managing the first mapping table and the second mapping table include: managing the mapping type of the one or more logical addresses; and managing the bitmap, and In this context, a bit in the bitmap indicates the type of one or more corresponding logical address mapping entries.

15. The data writing operation method according to claim 11, in, The second capacity is greater than the first capacity, and The step of identifying the mapping type includes: identifying the mapping entry as a second type based on the fact that the operation indicated by the request is a sequential operation.

16. A storage device, comprising: A non-volatile memory device configured to store data; as well as The memory controller is configured to control the non-volatile memory device. The storage controller includes: a host interface block configured to receive a request and one or more logical addresses from a host; and a mapping control block configured to, based on the request, identify the type of mapping entry between the one or more logical addresses and the physical address of a non-volatile memory device. The mapping entries include a first type of mapping entry corresponding to data of the first capacity and a second type of mapping entry corresponding to data of the second capacity.

17. The storage device according to claim 16, wherein, The storage controller also includes: a flash translation layer block, configured to manage multiple mapping tables, and The plurality of mapping tables include: The first mapping table includes mapping entries of the first type; and The second mapping table includes second-type mapping entries.

18. The storage device according to claim 17, in, The first capacity is smaller than the second capacity, and The flash translation layer block is configured to generate a second type of mapping entry for the one or more logical addresses based on the order of the request instruction.

19. The storage device according to claim 17, wherein, The number of first-type mapping entries is less than the threshold.

20. The storage device according to claim 17, wherein, The storage controller also includes a buffer memory block configured to load a first mapping table and / or a second mapping table.

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