Storage controller, storage system, and method of operating a storage controller

Abstract

Embodiments of this disclosure provide a storage controller, a storage system, and a method of operating the storage controller. The storage system includes a non-volatile memory device. The non-volatile memory device includes a plurality of memory blocks and a storage controller, the storage controller being configured to access the non-volatile memory device using block addresses of the memory blocks. The storage controller is configured to: receive a plurality of first reliability levels mapped to logical block addresses from the non-volatile memory device; map access frequency information included in dataset management information received from a host to a plurality of second reliability levels; update the plurality of first reliability levels to a plurality of second reliability levels based on logical block address range information in the dataset management information; and access the non-volatile memory device by using a block address corresponding to one of the plurality of second reliability levels, allocated based on the access address, based on an access command and an access address received from the host.

Description

Technical Field

[0001] This disclosure generally relates to a storage controller, a storage system, and methods for operating the storage controller. Background Technology

[0002] Semiconductor memory devices can be broadly classified into volatile memory and non-volatile memory. Volatile memory (such as DRAM or SRAM) has fast read and write speeds, but may lose stored data when power is turned off. On the other hand, non-volatile memory can retain data even when no power is supplied.

[0003] Non-volatile memories include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0004] With advancements in semiconductor manufacturing technology, the integration density and capacity of memory devices are continuously increasing. High integration can reduce manufacturing costs. However, as memory devices become more integrated, their size decreases, and their structure changes, various previously unidentified problems may emerge. These newly discovered problems can corrupt the data stored in the memory device, thereby compromising its reliability. Therefore, there is a continuous need for methods and devices to improve the reliability of memory devices. Summary of the Invention

[0005] This disclosure provides a storage system for providing data with improved reliability based on dataset management information received from a host.

[0006] In general, in some aspects, this disclosure provides a storage system comprising: a non-volatile memory device including a plurality of memory blocks; and a storage controller configured to access the non-volatile memory device using block addresses of the memory blocks, wherein the storage controller is configured to: receive from the non-volatile memory device a plurality of first reliability levels mapped to logical block addresses; map access frequency information included in dataset management information received from a host to a plurality of second reliability levels; update the plurality of first reliability levels to the plurality of second reliability levels based on logical block address range information of the dataset management information; and, when receiving an access command and an access address from the host, access the non-volatile memory device using a block address corresponding to one of the plurality of second reliability levels allocated based on the access address.

[0007] In general, in some other aspects, this disclosure provides a storage controller comprising: a host interface configured to receive dataset management information from a host, the dataset management information including access frequency information and logical block address (LBA) range information; a memory interface configured to access a non-volatile memory device using a block address; a memory configured to store mapping information between multiple access frequency information, multiple reliability levels, and address information of the non-volatile memory device; and a control processing unit configured to access the non-volatile memory device in response to a command from the host, wherein the control processing unit is configured to: receive an access command and an access address from the host; select a reliability level of the LBA range to which the access address belongs from multiple LBA range information; allocate a block address of the non-volatile memory device corresponding to the selected reliability level; and control the access command to be executed at the allocated block address of the non-volatile memory device.

[0008] In general, among other aspects, this disclosure provides a method for operating a memory controller, the method comprising: receiving reliability information for each memory block from a non-volatile memory device; receiving dataset management information from a host, the dataset management information including access frequency information and logical block address (LBA) range information; configuring a mapping table for reliability level information, the reliability level information being mapped to the access frequency information, the LBA range information, and the reliability information respectively; receiving an access command including an access address from the host; and allocating memory blocks of the non-volatile memory device based on the reliability level information mapped to LBA range information corresponding to the access address, and accessing the allocated memory blocks.

[0009] The technical aspects of this disclosure are not limited to those described above, and other technical aspects not explicitly stated will be readily understood by those skilled in the art from the following description. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating an example of a storage system.

[0011] Figure 2 This is a block diagram showing an example of a storage controller.

[0012] Figure 3 This is a block diagram illustrating an example of a non-volatile memory device.

[0013] Figure 4An example of LBA range information included in the dataset management information sent by the host is shown.

[0014] Figure 5 An example of access frequency information included in the dataset management information sent by the host is shown.

[0015] Figure 6 This is an example mapping table showing the mapping between access frequency information and modified reliability levels.

[0016] Figure 7 This is a mapping table showing an example of the mapping between the modified reliability level and LBA range information.

[0017] Figure 8 This is a mapping table that shows an example of the mapping between reliability levels and block address regions of non-volatile memory devices.

[0018] Figure 9 and Figure 10 This is a flowchart illustrating an example of how a storage system operates.

[0019] Figure 11 This is a diagram illustrating an example of a system in which a storage system is applied.

[0020] Figure 12 This is a diagram illustrating an example of a data center in which memory is used. Detailed Implementation

[0021] Figure 1 This is a block diagram illustrating an example of a storage system 10.

[0022] Storage system 10 may include host 110 and storage device 120. Additionally, storage device 120 may include storage controller 130 and non-volatile memory (NVM) device 140. In some examples, host 110 may include host controller 111 and host memory 121. Host memory 121 may be used as a buffer memory, temporarily storing data to be sent to or received from storage device 120.

[0023] Storage device 120 may include a storage medium for storing data in response to a request from host 110. For example, storage device 120 may include at least one of a solid-state drive (SSD), embedded memory, or removable external memory. If storage device 120 is an SSD, it may conform to the Non-Volatile Memory Fast (NVMe) standard. If storage device 120 is embedded memory or external memory, it may conform to the Universal Flash Storage (UFS) or Embedded Multimedia Card (eMMC) standard. Host 110 and storage device 120 may each generate and transmit data packets according to their respective standard protocols.

[0024] In some embodiments, when the non-volatile memory device 140 in storage device 120 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 120 may include a variety of other types of non-volatile memory. For example, storage device 120 may employ magnetic RAM (MRAM), spin-transfer torque MRAM (STT-MRAM), conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM (RRAM), and various other types of memory.

[0025] In some implementations, the host controller 111 and host memory 121 may be implemented as separate semiconductor chips. Alternatively, in some implementations, the host controller 111 and host memory 121 may be integrated on the same semiconductor chip. For example, the host controller 111 may be one of several modules provided in the application processor, which may be implemented as a system-on-a-chip (SoC). Additionally, the host memory 121 may be embedded memory within the application processor, or external non-volatile memory or memory module located outside the application processor.

[0026] The host controller 111 can manage operations such as storing data from a buffer in the host memory 121 (e.g., writing data) in the non-volatile memory device 140, or storing data from the non-volatile memory device 140 (e.g., reading data) in a buffer.

[0027] The storage controller 130 may include a host interface 131, a memory interface 132, and a central processing unit (CPU) 133. Additionally, the storage controller 130 may also include a flash translation layer (FTL) 134, a buffer memory 135, and an error correction code (ECC) engine 136. The storage controller 130 may also include working memory (not shown), in which the flash translation layer 134 is loaded, and data access operations to the non-volatile memory device 140 may be controlled by the CPU 133 executing the flash translation layer 134.

[0028] The storage controller 130 may, for example, receive reliability information for each memory block from the non-volatile memory device, and dataset management information including access frequency information and logical block address (LBA) range information from the host 110. The storage controller 130 may, for example, configure and store a mapping table for reliability level information, which maps access frequency information, LBA range information, and reliability information respectively. When the storage controller 130 receives an access command from the host 110, it may allocate memory blocks in the non-volatile memory device 140 based on the reliability level information mapped to the LBA range information to which the access address belongs. The storage controller can then access the allocated memory blocks.

[0029] Whenever the storage controller 130 receives dataset management information, it can update the mapping table of reliability level information.

[0030] Host interface 131 can send data packets to and receive data packets from host 110. Data packets sent from host 110 to host interface 131 may include commands or data to be written to non-volatile memory device 140, and data packets sent from host interface 131 to host 110 may include responses to commands or data retrieved from non-volatile memory device 140. Memory interface 132 can send data to non-volatile memory device 140 to non-volatile memory device 140, or can receive data read from non-volatile memory device 140. This memory interface 132 may be designed to conform to standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0031] The flash translation layer 134 can perform various functions, such as address mapping, wear leveling, and garbage collection. Address mapping translates logical addresses received from host 110 into physical addresses for actually storing data in non-volatile memory device 140. Wear leveling is an operation used to prevent excessive degradation of specific blocks by ensuring uniform use of blocks in non-volatile memory device 140. Wear leveling can be implemented, for example, through firmware techniques that balance the erase counts of physical blocks. Garbage collection is an operation used to protect the available capacity in non-volatile memory device 140 by copying valid data from blocks to new blocks and then erasing the old blocks.

[0032] ECC engine 136 can perform error detection and error correction on read data read from non-volatile memory device 140. More specifically, ECC engine 136 can generate parity bits for write data to be written into non-volatile memory device 140, and the parity bits generated in this way can be stored in non-volatile memory device 140 along with the write data. When reading data from non-volatile memory device 140, ECC engine 136 can use the parity bits read from non-volatile memory device 140 along with the read data to correct errors in the read data and output the corrected read data.

[0033] Figure 2 This is a block diagram showing an example of a storage controller 200. Figure 3 This is a block diagram illustrating an example of a non-volatile memory device 300. Figure 4 An example of LBA range information included in the dataset management information sent by the host is shown, and Figure 5 An example of access frequency information included in the dataset management information sent by the host is shown. Figure 6 This is an example mapping table showing the mapping between access frequency information and modified reliability levels, and Figure 7 This is an example mapping table showing the mapping between modified reliability levels and LBA range information, and Figure 8 This is a mapping table that shows an example of the mapping between reliability levels and block address regions of non-volatile memory devices.

[0034] In some implementations, when the storage system is powered on, the storage controller 200 receives multiple first reliability levels (e.g., such as...) mapped to logical block addresses from the non-volatile memory device 140 during the initialization phase. Figure 8As shown in Table 600 (here referred to as Table 3), the storage controller 200 can map and store access frequency information included in the dataset management information received from the host 110 to multiple second reliability levels. The storage controller 200 can update multiple previously stored first reliability levels to multiple second reliability levels based on the LBA range (Logical Block Address Range) information of the dataset management information.

[0035] When the storage controller 200 subsequently receives an access command and an access address from the host 110, the storage controller 200 can perform the operation corresponding to the access command at the block address of a non-volatile memory device of one of a plurality of updated second reliability levels based on the access address.

[0036] For example, the storage controller 200 may include a host interface 210, a memory interface 220, a reliability matching controller 231, a first memory 232 serving as dedicated memory for the reliability matching controller 231, an LBA range matching controller 241, a second memory 242 serving as dedicated memory for the LBA range matching controller 241, a loss level matching controller 251, and a loss level memory 252 serving as dedicated memory for the loss level matching controller 251. Each component of the storage controller 200 is connected via a system bus.

[0037] The host interface 210 and the memory interface 220 can be implemented as Figure 1 The host interface 131 and memory interface 132 are included.

[0038] Host 110 can send dataset management information to storage controller 200. (See reference) Figure 4 and Figure 5 The host 110 sends data set management information to the storage controller 200. This data management information includes access frequency information and logical block address (LBA) region information defined in the NVMe specification (ver. 1.3).

[0039] Based on the NVMe specification (ver. 1.3), data set management information is information from host 110 to storage device 120 notifying data characteristics. As an example, data set management information may include data characteristics, data usage patterns, data retention characteristics, or unused memory blocks. Storage controller 200 can be based on... Figure 4 The dataset management information shown includes LBA range information and Figure 5The access frequency information shown determines whether data within the LBA range is considered hot or cold data. The LBA range information for dataset management can be, for example, region information where the entire logical block address of the non-volatile memory device 140 is divided into 256 regions. For instance, this region information can classify memory blocks of the non-volatile memory device into single-level cells, multi-level cells, three-level cells, and four-level cells.

[0040] In some implementations... Figure 1 The CPU 133 may include a reliability matching controller 231, an LBA range matching controller 241, and a loss level matching controller 251. Alternatively, in some embodiments, Figure 1 The CPU 133 may include a reliability matching controller 231, and Figure 1 The FTL 134 in the figure can be implemented as including an LBA range matching controller 241 and a loss level matching controller 251.

[0041] In some implementations, the first memory 232, the second memory 242, and the wear-level memory 252 can be implemented as volatile memory. For example, they can be implemented as SRAM, double data rate synchronous DRAM (DDRSDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), and dual in-line memory module (DIMM). The first memory 232, the second memory 242, and the wear-level memory 252 can be initialized whenever the storage system 10 is powered on.

[0042] When the reliability matching controller 231 receives dataset management information from the host 110 ( Figure 9 When using the DSM Hint, the reliability matching controller 231 maps multiple reliability levels (NBRLs) to each of the multiple access frequency information included in the dataset management information. For example, if the dataset management information includes M access frequency information, and the storage controller 200 sets it to an N-level reliability level different from M, then the reliability matching controller 231 maps the access frequency information and the reliability level information to different levels. For example, the reliability level can be information that distinguishes data characteristics based on at least one attribute of the non-volatile memory device, such as programming / erasing (P / E) cycles, data retention time, bit error rate (BER), read endurance, temperature sensitivity, and durability.

[0043] The first memory 232 may store data representing the mapping between multiple reliability levels and access frequency information. For example, the data stored in the first memory 232 may include a mapping table (e.g., an access reliability table) between access frequency information and reliability level information for different levels. For example, refer to... Figure 6 If there are N access frequency information items and 16 reliability levels, some access frequency information items can be grouped together and matched by a reliability level. For example, reliability level 0 can be mapped to data from access frequency information 0 and access frequency information 1. In various implementations, depending on the implementation method, the access frequency information can be set as frequently accessed hot data in ascending order, and the number of tags in the reliability level can be set in ascending or descending order relative to the access frequency information.

[0044] In this case, the reliability level stored in the first memory 232 can be referred to as the modified reliability level.

[0045] When the storage system is initialized, the LBA range matching controller 241 loads a loss level table between multiple LBA range information and the initial reliability level from the loss level memory 252, and first stores the loaded loss level table in the second memory 242. Upon receiving dataset management information from the host 110, the initial reliability level based on the multiple LBA range storage can be updated to a modified reliability level mapped according to access frequency information. For example, as... Figure 7 As shown, the second memory 242 can store multiple LBA range information as mapping information between modified reliability levels. That is, the LBA range matching controller 241 stores a mapping table 500, which establishes the correlation between the mapping table 400 stored in the first memory 242 and the mapping table 600 stored in the loss level memory 252.

[0046] During the initialization phase, the loss level matching controller 251 can send a reliability level request to the non-volatile memory device 140, and after sending the reliability level request, receive multiple initial reliability level information from the non-volatile memory device. That is, the loss level matching controller 251 can receive an initial reliability level from multiple initial reliability level information mapped to block addresses within the non-volatile memory device 140. The initial reliability level is also referred to as the first reliability level. The modified reliability level is also referred to as the second reliability level.

[0047] The wear level memory 252 can store mapping information of logical block addresses for each of a plurality of first reliability levels received from the non-volatile memory device. The mapping information includes a wear level table that maps multiple initial reliability levels from multiple initial reliability level information received from the non-volatile memory device 140 to logical block addresses. (See reference...) Figure 8For example, the wear level memory 252 can store a wear level table 600, which maps k logical block addresses of multiple logical blocks in the non-volatile memory device 140 to N first reliability levels (k is a natural number greater than N). For example, the wear level memory 252 can store a wear level table 600, which maps 16 initial reliability level information to multiple logical block ranges in the non-volatile memory device 140.

[0048] In some implementations, the loss level table 600 and the second table 500 may be stored as address translation mapping tables of the flash translation layer (FTL).

[0049] Non-volatile memory device 300 (see Figure 3 This can correspond to a non-volatile memory device 140 (see...) Figure 1 The non-volatile memory device 300 may include an interface 310 for communicating with the memory controller 200 and a plurality of memory blocks 320.

[0050] The non-volatile memory device 300 can independently map reliability levels to each memory block, and the access intensity of each memory block can vary depending on its reliability level. For example, a memory block with reliability level 0 can be allocated to a location for storing frequently accessed hot data, while a memory block with reliability level M-2 can be allocated to a location for storing rarely accessed cold data.

[0051] Figure 9 and Figure 10 This is a flowchart illustrating an example of how a storage system operates.

[0052] refer to Figure 9 When the storage system is started (S701), the initialization process is executed.

[0053] When the loss level matching controller 251 sends a reliability level request to the non-volatile memory device 140, the loss level matching controller 251 receives information about multiple logic block ranges in response to the reliability level request (S702, S703). The loss level matching controller 251 initializes the reliability level information, maps the multiple logic block range information received from the non-volatile memory device 140 to the initialized reliability level information, and stores it as loss level table 600, Table 3 (S705).

[0054] Simultaneously, the reliability matching controller 231 initializes the reliability information previously stored in the first memory 232 (S704). Additionally, the LBA range matching controller 241 deletes the previously stored mapping information from the second memory 242 and stores the loss level table 600 received via the loss level matching controller 251 (S706, S707). At this point, the initialization process can be performed by the firmware.

[0055] When the storage controller 200 receives Data Set Management Information (DSM Hints) from the host 110 (S708), the reliability matching controller 231 maps the access frequency information included in the DSM Hints to multiple preset reliability levels. For example, the reliability matching controller 231 maps M access frequency information to N reliability levels and stores them as an access frequency-reliability mapping table 400, Table 1 (S710).

[0056] During the initialization process in S707, the LBA range matching controller 241 updates the initial reliability level stored in the second memory 242 to the modified reliability level based on the LBA range information included in the dataset management information DSMHints and the reliability level information mapped by the reliability matching controller 231 (S712). At this time, the number of initial reliability levels set in S705 is the same as the number of reliability levels set in S709.

[0057] The reliability level can be classified into multiple reliability levels based on at least one of the following attributes of the non-volatile memory device 140: P / E cycle, data retention time, bit error rate (BER), read endurance, temperature sensitivity, or durability.

[0058] refer to Figure 10 When storage system 10 is in Figure 9 After initialization and in operation (S801), the storage controller 200 can receive access commands and access addresses from the host 110.

[0059] When the storage controller 200 receives an access command and an access address from the host 110 (S802), the LBA range matching controller 241 checks (or extracts) the reliability level information mapped to the LBA range to which the access address belongs (S804). The loss level matching controller 251 allocates a logical block range to execute the access command based on the verified reliability level information (S805), and the non-volatile memory device 300 executes the access command at the allocated block address (S808). For example, if the access command is a data write command, data from the host 110 is written to the allocated block.

[0060] As described above, the storage system 10 pre-stores mapping information by classifying the logical blocks of the non-volatile memory device 140 into reliability levels based on the data characteristics according to the dataset management information. When frequently accessed hot data or metadata is written, the storage system 10 can write the data to a location corresponding to the reliability level based on the data characteristics, such as... Figure 3 This is shown in the non-volatile memory device 300. Therefore, the reliability of the data in the memory device 120 is improved.

[0061] Figure 11 This is a diagram illustrating an example of a system 1000 in which a storage system is applied.

[0062] Figure 11 A system 1000 with a storage device is shown. Figure 11 System 1000 can be a mobile system, such as a mobile phone, smartphone, tablet PC, wearable device, medical device, or Internet of Things (IoT) device. However, Figure 11 The system 1000 is not limited to mobile systems and can be a personal computer, laptop computer, server, media player, or car device such as a navigation system.

[0063] refer to Figure 11 The system 1000 may include a main processor 1100, memory 1200a and 1200b and storage devices 1300a and 1300b, and may also include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470 and a connection interface 1480.

[0064] The main processor 1100 can control the overall operation of the system 1000, and more specifically, the operation of other components constituting the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0065] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an embodiment, the main processor 1100 may also include an accelerator 1130, which is dedicated circuitry for high-speed data computation, such as artificial intelligence (AI) data computation. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a separate chip physically independent of other components of the main processor 1100.

[0066] Memory 1200a and 1200b can be used as the main memory of system 1000 and can include volatile memory such as SRAM and / or DRAM, but can also include non-volatile memory such as flash memory, PRAM and / or RRAM. Memory 1200a and 1200b can be implemented in the same package as main processor 1100.

[0067] Storage devices 1300a and 1300b can be used as non-volatile storage devices that store data regardless of power supply, and can have a relatively large storage capacity compared to memories 1200a and 1200b. In some embodiments, storage devices 1300a and 1300b may include storage controllers 1310a and 1310b, and non-volatile memories (NVMs) 1320a and 1320b that store data under the control of storage controllers 1310a and 1310b. Non-volatile memories 1320a and 1320b may include two-dimensional (2D) or three-dimensional (3D) vertical NAND (V-NAND) flash memory, but may also include other types of non-volatile memories, such as PRAM and / or RRAM.

[0068] Storage devices 1300a and 1300b may be included in system 1000 in a physically separate state from main processor 1100, or may be implemented in the same package as main processor 1100. Alternatively, storage devices 1300a and 1300b may be in the form of solid-state drives (SSDs) or memory cards, and may be detachably connected to other components of system 1000 via an interface, such as connection interface 1480 described below. Storage devices 1300a and 1300b may be devices conforming to standard protocols such as Universal Flash Storage (UFS), embedded multimedia card (eMMC), or Non-Volatile Memory Fast (NVMe), but are not limited thereto.

[0069] Storage devices 1300a and 1300b can be implemented as Figures 1 to 10 The storage system 10 described herein. Storage devices 1300a and 1300b can store AI model-related data in memory blocks with high reliability levels, where data retention is critical. Therefore, when the system 1000 operates on-device AI chipsets and applications, it can enhance data reliability and performance by storing data in different memory block locations within storage devices 1300a and 1300b according to dataset management prompts that categorize memory blocks based on reliability levels.

[0070] Figure 12 This is a diagram illustrating an example of a data center in which storage devices are used.

[0071] Application server 2100 can access memory 2120n or storage device 2150n included in another application server 2100n via network 2300. It can also access memory 2220-2220m or storage device 2250-2250m included in storage servers 2200-2200m via network 2300. Therefore, application server 2100 can perform various operations on data stored in application servers 2100-2100n and / or storage servers 2200-2200m. For example, application server 2100 can execute commands to move or copy data between application servers 2100-2100n and / or storage servers 2200-2200m. In this scenario, data can be sent from storage devices 2250-2250m of storage servers 2200-2200m via storage devices 2220-2220m, or directly to storage devices 2120-3120n of application servers 2100-2100n. Data sent over network 2300 can be encrypted to ensure security and privacy. The storage devices 2150-2150n and 2250-2250m included in application server 2100 or storage server 2200 can be implemented as follows: Figures 1 to 10 The storage system 10 described herein.

[0072] Controller 2251 can control the overall operation of storage device 2250. In some embodiments, controller 2251 may include static random access memory (SRAM). Controller 2251 may write data to NAND flash memory 2252 in response to a write command, or it may read data from NAND flash memory 2252 in response to a read command. For example, when writing data to NAND flash memory 2252 in response to a write command, controller 2251 may refer to a mapping table of reliability level information stored in DRAM 2253 and write the data to the memory block of NAND flash memory 2252 corresponding to the allocated block address.

[0073] For example, write and / or read commands can be provided from processor 2210 in storage server 2200, processor 2210m in another storage server 2200m, or processors 2110 and 2110n in application servers 2100 and 2100n. DRAM 2253 can temporarily store (buffer) data to be written to or read from NAND flash memory 2252. Additionally, DRAM 2253 can store metadata. Here, metadata refers to data generated by controller 2251 to manage user data or NAND flash memory 2252. For example, DRAM 2253 can store data based on... Figures 1 to 10 The dataset management information described herein is used to set up a mapping table for reliability level information. For example, DRAM 2253 may include a first table, a wear level table, and a second table. The first table maps access frequency information defined in the dataset management information to modified reliability levels. The wear level table maps multiple block addresses of non-volatile memory devices 2252-2252m to multiple initial reliability levels. The second table maps initial reliability levels to modified reliability levels based on LBA range information included in the dataset management information. Memory device 2250 may include a security element (SE) for security or privacy.

Claims

1. A storage system, the storage system comprising: A non-volatile memory device, the non-volatile memory device comprising a plurality of memory blocks; as well as A storage controller configured to access the non-volatile memory device using the block address of the memory block. The storage controller is configured as follows: Receive multiple first reliability levels from the non-volatile memory device that are mapped to logical block addresses of the non-volatile memory device. Receive dataset management information from the host. The access frequency information included in the dataset management information is mapped to multiple second reliability levels. Based on the logical block address range information of the dataset management information, the plurality of first reliability levels are updated to the plurality of second reliability levels, and Based on receiving an access command and access address from the host, the non-volatile memory device is accessed by using a block address corresponding to one of the plurality of second reliability levels, which is assigned to a logical block address based on the access address.

2. The storage system of claim 1, wherein, The storage controller includes: A reliability matching controller, configured to map the plurality of second reliability levels to the access frequency information included in the dataset management information; and A first memory is configured to store data representing the mapping between the plurality of second reliability levels and the access frequency information.

3. The storage system according to claim 2, wherein, The first memory includes: An access reliability table is configured to map M access frequency information to N levels of second reliability. Where M and N are distinct natural numbers equal to or greater than 2.

4. The storage system according to claim 1, wherein, The storage controller includes: A loss level matching controller, configured to (i) send a reliability level request to the non-volatile memory device, and (ii) receive the plurality of first reliability levels from the non-volatile memory device after sending the reliability level request; and A loss level memory, configured to store mapping information of the logical block addresses of each of the plurality of first reliability levels received from the non-volatile memory device.

5. The storage system according to claim 4, wherein, The loss-level memory includes: A loss level table, configured to map k logical block addresses of a plurality of logical blocks in the non-volatile memory device to N levels of the first reliability level. Where k is a natural number greater than N.

6. The storage system according to claim 4, wherein, The storage controller includes: A second memory, configured to store mapping information describing the mapping between multiple logical block address ranges and reliability levels; and Logical block address range matching controller, the logical block address range matching controller being configured as follows: First mapping information describing the mapping between the plurality of logical block address ranges and the plurality of first reliability levels is loaded from the loss level memory. During the initialization of the storage system, the first mapping information is stored in the second memory, and After receiving the dataset management information, the plurality of first reliability levels are updated to the plurality of second reliability levels based on the plurality of logical block address range information.

7. The storage system according to claim 1, wherein, The second reliability level classifies the memory blocks of the non-volatile memory device into single-level cells, multi-level cells, three-level cells, and four-level cells.

8. A storage controller, the storage controller comprising: A host interface configured to receive dataset management information from a host, the dataset management information including access frequency information and logical block address range information; A memory interface configured to access a non-volatile memory device using a block address; The memory is configured to store mapping information that describes (i) a plurality of reliability levels and (ii) a plurality of access frequency information or address information of the non-volatile memory device; as well as A control processing unit configured to access the non-volatile memory device based on commands from the host. The control processing unit is configured as follows: Receive access commands and access addresses from the host. Among multiple logical block address ranges, select the reliability level associated with the corresponding logical block address range to which the accessed address belongs. For the access command, allocate a block address for the non-volatile memory device corresponding to the selected reliability level, and The access command is executed at the allocated block address of the non-volatile memory device.

9. The storage controller according to claim 8, wherein, The memory includes: The first table includes M access frequency information items, which are defined in the dataset management information and mapped to N levels of modified reliability levels. A loss level table, comprising multiple block addresses of the non-volatile memory device mapped to N initial reliability levels; and The second table includes the initial reliability level, which is mapped to the modified reliability level in the first table based on the logical block address range information included in the dataset management information. Where M and N are distinct values ​​and are natural numbers equal to or greater than 2.

10. The storage controller according to claim 9, wherein, The non-volatile memory device includes a plurality of memory blocks, each memory block being configured with a single initial reliability level having N levels of initial reliability levels mapped to the block address of the corresponding memory block.

11. The storage controller according to claim 9, wherein, The loss level table and the second table are configured to be stored as an address translation mapping table for the flash translation layer.

12. The storage controller according to claim 9, wherein, The control processing unit is configured to update the mapping information in the first table each time it receives dataset management information from the host, which describes the mapping between the access frequency information and the modified reliability level.

13. The storage controller of claim 12, wherein, The control processing unit is configured to update the mapping information in the second table each time it receives the dataset management information from the host, which describes the mapping between the logical block address range information and the modified reliability level.

14. The storage controller according to claim 8, wherein, The non-volatile memory device includes multiple memory blocks, and The logical block address range information is configured to classify the memory blocks into single-level units, multi-level units, three-level units, and four-level units.

15. A method of operating a memory controller, the method of operating the memory controller comprising: Receive reliability information for each memory block from the non-volatile memory device; Receive dataset management information from the host, the dataset management information including access frequency information and logical block address range information; Configure a mapping table for reliability level information, wherein the reliability level information is mapped to the access frequency information, the logical block address range information, and the reliability information, respectively. Receive an access command, including the access address, from the host; Based on the reliability level information mapped to the logical block address range information corresponding to the access address, memory blocks of the non-volatile memory device are allocated; as well as Access the allocated memory block.

16. The method of operating a memory controller according to claim 15, wherein, The storage controller is configured to update the mapping table of the reliability level information each time it receives the dataset management information.

17. The method of operating a memory controller according to claim 15, wherein, The mapping table includes: The first table includes M access frequency information items, which are defined in the dataset management information and mapped to N levels of modified reliability levels. A loss level table, comprising multiple block addresses of a non-volatile memory device mapped to N initial reliability levels; and The second table includes the initial reliability level, which is mapped to the modified reliability level in the first table based on the logical block address range information included in the dataset management information. Where M and N are natural numbers equal to or greater than 2 and have different values.

18. The method of operating a memory controller according to claim 17, wherein, The reliability information for each memory block includes N levels of initial reliability levels mapped to each corresponding memory block of the non-volatile memory device.

19. The method of operating a memory controller according to claim 15, wherein, The mapping table is initialized each time the storage system is powered on.

20. The method of operating a memory controller according to claim 17, wherein, The modified reliability levels classify memory blocks into N reliability levels based on at least one of the programming / erase cycle, data retention time, bit error rate, read endurance, temperature sensitivity, or robustness of the non-volatile memory device.

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