A cross-clock domain DMA control system and method

Abstract

The application discloses a cross-clock domain DMA control system and method, and relates to the chip design field.The control system comprises a polling arbitrator module, a request FIFO module and a response FIFO module;the polling arbitrator module is connected to a plurality of peripheral channel, is used for polling arbitration of the DMA request signal of the plurality of peripheral channel, and dynamically shields the request signal of the channel that has been arbitrated, and according to the response signal, the shielding state of the corresponding peripheral channel is removed;the input end of the request FIFO module is connected to the polling arbitrator module, and is used for synchronizing the arbitrated DMA request signal from the first clock domain to the second clock domain in real time;the output end of the response FIFO module is connected to the polling arbitrator module, and is used for synchronizing the response signal of the second clock domain from the second clock domain to the first clock domain in real time.The application solves the technical problems that the access interval time of different CH channels is long in the prior art, and the efficiency of the DMA access of the CH channel is low.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a cross-clock domain DMA control system and method. Background Technology

[0002] In chip design, due to power saving, low power consumption, or other requirements, different clock domains are often used. Each clock domain contains multiple peripheral modules, which typically require Direct Memory Access (DMA). DMA is designed to reduce CPU involvement time, allowing modules to complete data access with the memory (MEM) before notifying the CPU. In existing technologies, one method involves using a multi-cycle synchronization register to handshake the REQ requests and ACK responses from peripheral modules, enabling peripheral modules in clock domain A to access the MEM in clock domain B.

[0003] In existing technologies, such as Figure 1 Clock domain A has multiple peripheral modules, each corresponding to a CH channel. When multiple CH0~7 channels need to access MEM via DMA, the arbitrator first arbitrates one of the CH0~7 channels according to a specific arbitration strategy. The REQ request of this channel CH is synchronized to clock domain B through the REQ SYNC multi-cycle synchronization register, usually for 2 cycles. After the REQ request is synchronized to clock domain B, it is then arbitrated with other CH channels in clock domain B before accessing MEM memory. The ACK response is finally synchronized to clock domain A through the ACK SYNC multi-cycle synchronization register and responds to the corresponding CH channel, completing the entire cross-clock domain DMA direct memory access. The REQ and ACK SYNC multi-cycle synchronization registers form the CDC cross-clock domain circuit. Because there is only one CDC module, the DMA access intervals for multiple CH channels are too long. Assuming this multi-cycle synchronization register has two cycles, the A clock domain REQ is synchronized to the B clock domain for two B clock cycles, i.e., 2*T(B). The B clock domain ACK is synchronized to the A clock domain for two A clock cycles, i.e., 2*T(A). Each CH channel access requires waiting for 2*T(B) + 2*T(A) time before the next CH channel access. For a fixed-priority arbiter, when two high-priority CH channels perform consecutive DMA accesses, other CH channels need to wait even longer.

[0004] Therefore, it is urgent to find a solution to the problem that existing technologies with only one CDC module result in excessively long DMA access intervals and low access efficiency for multiple CH channels. Summary of the Invention

[0005] This invention provides a cross-clock domain DMA control system and method, which can solve the technical problems of long access intervals between different CH channels and low efficiency of DMA access in the prior art. The technical solution is as follows:

[0006] In a first aspect, embodiments of the present invention provide a cross-clock domain DMA control system, including: a polling arbitrator module, a request FIFO module, and a response FIFO module;

[0007] The polling arbitrator module is connected to multiple peripheral channels and is used to poll and arbitrate the DMA request signals of the multiple peripheral channels, dynamically block the request signals of the arbitrated channels, and release the blocking state of the corresponding peripheral channels according to the response signals.

[0008] The input of the request FIFO module is connected to the polling arbitrator module, and is used to synchronize the arbitrated DMA request signal from the first clock domain to the second clock domain in real time.

[0009] The output of the response FIFO module is connected to the polling arbitrator module and is used to synchronize the response signal of the second clock domain from the second clock domain to the first clock domain in real time.

[0010] In some embodiments of the present invention, the polling arbitrator module includes an arbitration unit, a shielding unit, and a detection unit;

[0011] The arbitration unit is connected to multiple peripheral channels and is used to poll and arbitrate the DMA request signals of the multiple peripheral channels to obtain the arbitration result, and transmit the DMA request signal of the channel corresponding to the arbitration result to the request FIFO module.

[0012] The shielding unit is communicatively connected to the arbitration unit and is used to dynamically shield request signals from channels that have already been arbitrated.

[0013] The detection unit is communicatively connected to the arbitration unit and the shielding unit, and is used to acquire the shielding status and response signals of multiple peripheral channels in real time, and release the shielding status of the corresponding peripheral channel according to the response signal.

[0014] In some embodiments of the present invention, the shielding unit includes multiple flag bits, which are configured one-to-one with multiple peripheral channels; the flag bits are used to perform a logical OR operation with the arbitration result and the shielding status of the previous cycle in each cycle to indicate the shielding status of the channel in real time.

[0015] In some embodiments of the present invention, the detection unit includes generating a release signal for the corresponding peripheral channel based on the response signal; the shielding unit clears the flag bit of the corresponding channel in the shielding state to zero based on the release signal.

[0016] In some embodiments of the present invention, in each clock cycle, the arbitration unit performs a bitwise AND operation between the request signal of the peripheral channel and the inverted value of the MASK register, and performs priority arbitration on the result.

[0017] In some embodiments of the present invention, the system further includes a storage access module, which is used to perform access operations on the memory according to the arbitration result obtained by the polling arbitrator module, and generate a corresponding response signal according to the access result.

[0018] In some embodiments of the present invention, the system further includes a multiplexer;

[0019] The multiplexer is located in the second clock domain;

[0020] The selection terminal of the multiplexer is connected to the output terminal of the request FIFO module, and the multiple data input terminals of the multiplexer respectively receive access addresses and write data from multiple peripheral channels;

[0021] The multiplexer is used to send the access address and write data of the channel corresponding to the arbitration result to the storage access module according to the arbitration result obtained by the polling arbitrator module.

[0022] In some embodiments of the present invention, both the request FIFO module and the response FIFO module are asynchronous FIFOs with a depth greater than one.

[0023] Secondly, the present invention also provides a cross-clock domain DMA control method, applied to the cross-clock domain DMA control system as described in any of the preceding claims, comprising:

[0024] After obtaining DMA requests from multiple peripheral channels, the polling arbitrator module is controlled to select the target channel according to the polling strategy through a dynamic masking mechanism.

[0025] The identifier of the target channel is written into the request FIFO module and output in the second clock domain after cross-clock domain synchronization;

[0026] In the second clock domain, the address and data of the corresponding channel are selected according to the identifier to access the memory of the second clock domain and obtain the response signal;

[0027] The response signal is written into the response FIFO module, and after cross-clock domain synchronization, it returns to the first clock domain; and the shielding state of the peripheral channel corresponding to the response signal in the polling arbitrator module is released.

[0028] In some embodiments of the present invention, controlling the polling arbitrator module to select the target channel according to the polling strategy through a dynamic masking mechanism includes:

[0029] Valid requests for peripheral channels are filtered based on the current shielding status.

[0030] Arbitrate the highest priority request from the valid requests and use it as the arbitration result to determine the target channel;

[0031] Update the shielding status and add the currently arbitrated peripheral channel to the shield.

[0032] The beneficial effects of the technical solutions provided by some embodiments of the present invention include at least the following: After arbitrating a REQ request signal for a certain peripheral channel, the polling arbitrator module temporarily blocks the REQ of the current peripheral channel, allowing the REQs of other peripheral channels to enter the next round of arbitration until all peripheral channels can send request signals. Upon receiving a response signal, the blocking signal is cleared, and a new round of arbitration begins. The polling arbitrator ensures that each CH channel has a chance to receive a response. The request signal from the polling arbitrator module is written to the request FIFO module. The request FIFO module reads the REQ request synchronized to the second clock domain of the MEM. After the ACK response, it is written to the response FIFO module. The response FIFO module reads the ACK synchronized to the first clock domain of the peripheral CH channel and responds to the corresponding CH channel. The request FIFO module and the response FIFO module support different depths, allowing for the writing and reading of multiple REQs and ACKs, enabling rapid multiple DMA accesses, ensuring that multiple CH channels perform pipelined cross-clock domain access to the MEM, and efficiently completing DMA direct memory access. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A system architecture diagram of an embodiment of the cross-clock domain DMA control system provided by the present invention;

[0035] Figure 2 CH channel dma_if interface and timing diagram for multiple peripheral channels;

[0036] Figure 3 This is a structural diagram of an asynchronous FIFO;

[0037] Figure 4 A schematic diagram of DMA access in a pipelined manner;

[0038] Figure 5 This is a circuit diagram of the shielding unit;

[0039] Figure 6 This is a circuit diagram of the detection unit;

[0040] Figure 7 The schematic diagram shows the arbitration unit, shielding unit, and detection unit.

[0041] Figure 8 This is a flowchart of an embodiment of the cross-clock domain DMA control method provided by the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0043] Please see Figure 1 This application provides a cross-clock domain DMA control system, including: a polling arbitrator module, a request FIFO module, and a response FIFO module;

[0044] The polling arbitrator module is connected to multiple peripheral channels and is used to poll and arbitrate the DMA request signals of the multiple peripheral channels, dynamically block the request signals of the arbitrated channels, and release the blocking state of the corresponding peripheral channels according to the response signals.

[0045] It should be noted that the polling arbitrator module acts as a scheduler in this application. When multiple peripheral channels compete for the right to access memory MEM at the same time, it serves each subject in a fixed, cyclical order to ensure that each subject can get an equal opportunity, thereby avoiding some low-priority subjects from being "starved".

[0046] It should be noted that, Figure 2The present invention defines the CH channel dma_if interface and timing diagram for multiple peripheral channels, including the ch_dma_req, ch_dma_we, ch_dma_addr, ch_dma_wdat, ch_dma_rdat and ch_dma_ack signals. `ch_dma_req` is the channel's request signal; setting it to 1 indicates a DMA access request is being initiated. `ch_dma_we` is the channel's read / write indicator; setting it to 1 indicates a write request, and setting it to 0 indicates a read request. It is only valid when `ch_dma_req` is 1. `ch_dma_addr` is the channel's read / write request address; it is only valid when `ch_dma_req` is 1. `ch_dma_wdat` is the channel's write request data; it is only valid when both `ch_dma_req` and `ch_dma_we` are 1. `ch_dma_rdat` is the channel's read request data; it is only valid when it is a read request and `ch_dma_ack` is 1. `ch_dma_ack` is the channel's response request; setting it to 1 indicates that the read / write request has been responded to, and the next request can begin.

[0047] The input of the request FIFO module is connected to the polling arbitrator module, and is used to synchronize the arbitrated DMA request signal from the first clock domain to the second clock domain in real time; the output of the response FIFO module is connected to the polling arbitrator module, and is used to synchronize the response signal from the second clock domain to the first clock domain in real time.

[0048] It should be noted that the FIFO module requests that the request commands generated by the arbitrator be safely and reliably synchronized from the first clock domain to the second clock domain. When the processing speed of the second clock domain is temporarily unable to keep up with the speed at which the first clock domain generates requests, the requests are cached to avoid data loss. This allows the first clock domain to issue multiple requests continuously without having to wait for the previous request to be processed, thus achieving a pipelined operation.

[0049] Furthermore, the response signal (and read data) after the memory access is completed is synchronized from the second clock domain back to the first clock domain to ensure that the response is correctly associated with the initial request and delivered to the correct channel. It should be further noted that the request FIFO module and the response FIFO module have identical structures, but their data bit widths may be wider.

[0050] Please see Figure 3 , Figure 3This is a typical asynchronous FIFO structure diagram. The left side represents the write end of the first clock domain, and the right side represents the read end of the second clock domain. `winc` enables write, `wdat` represents the data being written, `wfull` is the write-full indicator, `rinc` enables read, `rdat` represents the read data, and `rempty` is the read-empty indicator. When data is written, `wptr` changes and becomes the GC Gray code, which is then synchronized to `w2r_wptr`. After `w2r_wptr` changes, it is compared with `rptr`, setting `rempty` to 0, indicating that there is data in the FIFO and it can be read. When multiple data are written to the FIFO but not read, `wptr` is compared with `r2w_rptr`, setting `wfull` to 1, indicating that the FIFO is full and no more data can be written. Only when data is read, `rptr` changes and becomes the GC Gray code, which is then synchronized to `r2w_rptr`. `r2w_rptr` is compared with `wptr`, setting `wfull` to 0, before new data can be written.

[0051] In this embodiment, after the polling arbitrator module arbitrates a REQ request signal for a certain peripheral channel, it temporarily blocks the REQ of that peripheral channel, allowing the REQs of other peripheral channels to enter the next round of arbitration. This continues until all peripheral channels can send their request signals. Once a peripheral channel receives a response signal, the blocking signal is cleared, and a new round of arbitration begins. The polling arbitrator ensures that each CH channel has a chance to receive a response. The request signal from the polling arbitrator module is written to the request FIFO module. The request FIFO module synchronizes the REQ request to the second clock domain of the MEM and reads it out. After the ACK response, it is written to the response FIFO module. The response FIFO module synchronizes the ACK to the first clock domain of the peripheral CH channel and reads it out, responding to the corresponding CH channel. The request FIFO module and the response FIFO module support different depths, allowing for the writing and reading of multiple REQs and ACKs, enabling rapid multiple DMA accesses and ensuring that multiple CH channels can perform pipelined cross-clock domain access to the MEM, efficiently completing DMA direct memory access.

[0052] However, in existing technologies, all requests from different channels are first arbitrated in one clock domain, and the winning request is then transmitted to another clock domain via a synchronizer. After processing, the response is transmitted back via another synchronizer. Each request and response requires two or more clock cycles to synchronize. Under high load, multiple requests can only pass through this single-pathway sequentially, resulting in extremely long channel waiting times, making pipelined operation impossible, and leading to low system throughput. Therefore, in a specific embodiment of the present invention, the polling arbitrator module includes an arbitration unit, a shielding unit, and a detection unit.

[0053] The arbitration unit is connected to multiple peripheral channels and is used to poll and arbitrate the DMA request signals of the multiple peripheral channels to obtain the arbitration result, and transmit the DMA request signal of the channel corresponding to the arbitration result to the request FIFO module.

[0054] The shielding unit is communicatively connected to the arbitration unit and is used to dynamically shield request signals from channels that have already been arbitrated.

[0055] The detection unit is communicatively connected to the arbitration unit and the shielding unit, and is used to acquire the shielding status and response signals of multiple peripheral channels in real time, and release the shielding status of the corresponding peripheral channel according to the response signal.

[0056] In this embodiment, in each clock cycle, the arbitration unit first performs a logical AND operation on the inverse of the original channel request signal and the masking status signal, i.e., valid request = CH_REQ & ~MASK, thereby filtering out channel requests that have been marked as "busy" by the masking unit, ensuring that only the currently qualified channel enters the next stage. Then, the arbitration unit encodes the selected valid request vector with a fixed priority (usually CH0 has the highest priority and CH7 has the lowest), scans from the highest priority, and selects the first valid request as the winner of this round of arbitration. When the arbitration unit outputs a new arbitration result (e.g., CH1 wins, REQ[7:0]=8'b0000_0010), the masking unit will set the corresponding channel position in the masking register to a high level in the next clock cycle (set MASK[1] to 1), thereby temporarily "freezing" the arbitration qualification of the channel, forcing the arbitration unit to serve the requests of other channels in subsequent cycles, thus avoiding the continuous occupation of a single channel and laying the foundation for fairness. When the detection unit indicates that a DMA access to a certain channel has been completed (for example, DET[7:0]=8'b0000_0010 indicates that the response of CH1 has been returned), the masking unit will clear the corresponding channel bit in the mask register (clear MASK[1] to 0) in the next clock cycle. This allows the channel to immediately regain its arbitration eligibility, enabling it to initiate a new DMA request, thereby realizing the rapid reclamation of channel resources and the pipelined operation of the system, such as Figure 4 As shown, this greatly improves throughput.

[0057] In one specific embodiment, please refer to Figure 5 , Figure 5 This is a circuit diagram of the shielding unit.

[0058] Input signals include: DET[7:0] response return, REQ[7:0] arbitration result, clk and rst (clock and reset signals).

[0059] Core Logic (OR-AND-Register Update Loop): The RTL_OR gate performs a bitwise OR operation on DET[7:0] and REQ[7:0]. Bits in REQ[7:0] that are 1 indicate the newly winning channel in this round, which needs to be added to the mask (corresponding bit set to 1). Bits in DET[7:0] that are 1 indicate the channel that has received a response, which needs to be unmasked (corresponding bit set to 1, but note the next step). AND Operation (Invert and Clear Logic): The RTL_AND gate is key, executing (DET | REQ) & MASK_reg_in_i. MASK_reg_in_i is the inverted value of the current MASK register (~MASK[7:0]). Register Operation (State Maintenance): The RTL_REG_ASYNC register latches the calculation result of the above RTL_AND gate on each rising edge of the clock, and outputs the new MASK[7:0] state.

[0060] In another specific embodiment, please refer to Figure 6 , Figure 6 This is a circuit diagram of the detection unit.

[0061] Input signals: Response FIFO module _rdat[7:0], 8 bits of data read from the response FIFO module, each bit representing the response of one channel. ACK_FIFO_rempty: The "empty" flag of the response FIFO module. When it is 1, it indicates that the FIFO is empty and there is no valid data.

[0062] Core logic: A conditional selector, the behavior of which is controlled by a condition S. When ACK_FIFO_rempty == 1'b0 (i.e., the FIFO is not empty): S = 1'b0. In this case, the MUX selects port I0 and outputs the values ​​of ACK_FIFO_rdat[7:0] unchanged. When ACK_FIFO_rempty == 1'b1 (i.e., the FIFO is empty): S = default. In this case, the MUX selects port I1, and I1 is also connected to ACK_FIFO_rdat[7:0].

[0063] Output signal: DET[7:0], which is a release signal or a detection signal. When it is 8'b0000_0001, it means "a response to CH0 has been detected, and a request is made to release the shielding of CH0".

[0064] It should be noted that during multiple channel arbitrations, such as when CH0~7 request simultaneously, CH0 has the highest priority. In cycle_0, the REQ module of the REQ polling arbitrator has REQ[7:0]=8'b0000_0001, indicating that CH0 wins, and REQ[7:0]=8'h1 is written to the request FIFO module; in cycle_1, the MASK module has MASK[7:0]=8'b0000_0001, indicating that CH0's request is blocked, then REQ[7:0]=8'b0000_0010, indicating that CH1 wins, and REQ[7:0]=8'h2 is written to the request FIFO module; in cycle_2, the MASK module has MASK[7:0]=8'b0000_001 1. If the requests for CH0 and CH1 are blocked, then REQ[7:0] = 8'b0000_0100, indicating that CH2 wins, and REQ[7:0] = 8'h4 is written to the request FIFO module; and so on until all requests are written to the request FIFO module. At this time, MASK[7:0] = 8'b1111_1111, that is, all requests are blocked, and the REQ polling arbiter stops working. When the REQ detection unit in the REQ polling arbitration detects that the response FIFO module reads out the corresponding ACK response in sequence, it clears the corresponding bit of MASK[7:0] to 0 and lets this CH channel re-enter the REQ polling arbiter.

[0065] Figure 7This section describes the principles of the REQ arbitration unit, MASK masking unit block, and REQ detection unit. REQ[7:0] and DET[7:0] are logical operations, and MASK[7:0] is a register that is updated in each cycle. ① In the REQ arbitration unit, request signals from CH0~7 are combined into CH_REQ[7:0], which is then inverted with the MASK[7:0] register and subjected to a bitwise AND operation to obtain REQ_P[7:0]. Finally, priority judgment is performed to generate the corresponding REQ[7:0]. ② In the MASK masking unit, the MASK[7:0] register is ANDed with the inverted MAKS_C[7:0] in each cycle, and then subjected to a bitwise OR operation with REQ[7:0] to update the register, determining whether each bit is cleared or set to 1. ③ In the REQ detection unit, if DET[7:0] detects that the rempty value on the right side of the ACK FIFO is set to 0, then rdat[7:0] is saved, i.e., ACK[7:0]. For example, in cycle_0, MASK[7:0]=0, CH_REQ[7:0]=8'b0000_0011 (indicating that CH0 and 1 have REQ requests), REQ[7:0]=8'b0000_0001. In cycle_1, MASK[7:0]=8'b0000_0001, REQ[7:0]=8'b0000_0010. In cycle_2, MASK[7:0]=8'b0000_0011, REQ[7:0]=8'b0000_0000. CH0 and 1 are both masked, meaning that arbitration has been completed and the data has been sent to REQ_FIFO, waiting for ACK. In a FIFO response, if in cycle_3, ACK[7:0]=8'b0000_0001, that is, DET[7:0]=8'b0000_0001, bit 0 of MASK[7:0] will be cleared in the next cycle. Then in cycle_4, MASK[7:0]=8'b0000_0010. If CH0 has a new request at this time, it can enter the REQ arbitrator module for arbitration.

[0066] In some embodiments of the present invention, the system further includes a storage access module 14, which is used to perform access operations on the memory according to the arbitration result obtained by the polling arbitrator module, and generate a corresponding response signal according to the access result.

[0067] In this embodiment, when valid data (rempty is low) appears at the read end of the request FIFO module, the storage access module starts working. It reads the value of rdat[7:0], for example, 8'b0000_0100 clearly indicates that the channel currently requiring service is CH2. Subsequently, the storage access module (or its adjacent MUX module) selects the access parameters for the corresponding channel from the data bus shared by all channels according to the channel ID. These parameters include: the ch_dma_wdat read / write control signal, the memory address to be accessed by ch_dma_addr, and the data to be written to memory by ch_dma_wdat. After obtaining complete access information, the storage access module interacts with the memory controller according to a standard memory access protocol (such as AXI, AHB, or a custom bus protocol) to complete this DMA transfer. This includes write access, which writes the ch_dma_wdat data to the memory location specified by ch_dma_addr, and read access, which reads data from the memory location specified by ch_dma_addr. After the access operation is completed (for a write operation, i.e., the address and data have been successfully received; for a read operation, i.e., the read data has been returned), the storage access module generates a response signal. After generating the response, the storage access module enables its write enable signal winc and writes the assembled response data to the write end of the response FIFO. For example, if a 32-bit read data is returned to CH2, the data written to the response FIFO might be {32'hAAAA_BBBB, 8'b0000_0100}.

[0068] Based on the above-described cross-clock domain DMA control system, this invention also provides a cross-clock domain DMA control method. Please refer to [link to relevant documentation]. Figure 8 ,include:

[0069] S801. After obtaining DMA requests from multiple peripheral channels, control the polling arbitrator module to select the target channel according to the polling strategy through a dynamic masking mechanism.

[0070] S802. Write the identifier of the target channel into the request FIFO module, and output it in the second clock domain after cross-clock domain synchronization;

[0071] S803. In the second clock domain, the address and data of the corresponding channel are selected according to the identifier to access the memory of the second clock domain and obtain the response signal.

[0072] S804. Write the response signal into the response FIFO module, return to the first clock domain after cross-clock domain synchronization, and remove the shielding state of the peripheral channel corresponding to the response signal in the polling arbitrator module.

[0073] In this embodiment, after the polling arbitrator module arbitrates a REQ request signal for a certain peripheral channel, it temporarily blocks the REQ of the current peripheral channel, allowing the REQs of other peripheral channels to enter the next round of arbitration. This continues until all peripheral channels can send their request signals. After a peripheral channel receives a response signal, the blocking signal is cleared, and a new round of arbitration begins. The polling arbitrator ensures that each CH channel has a chance to receive a response. The request signal processed by the polling arbitrator module is written to the request FIFO module. The request FIFO module synchronizes the REQ request to the second clock domain of the MEM and reads it out. After the ACK response is received, it is written to the response FIFO module. The response FIFO module synchronizes the ACK to the first clock domain of the peripheral CH channel and reads it out, responding to the corresponding CH channel. The request FIFO module and the response FIFO module support different depths, allowing for the writing and reading of multiple REQs and ACKs, enabling rapid multiple DMA accesses and ensuring that multiple CH channels can perform pipelined cross-clock domain access to the MEM, efficiently completing DMA direct memory access.

[0074] The above description discloses only preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A cross-clock domain DMA control system, characterized in that, include: Polling arbitrator module, request FIFO module, and response FIFO module; The polling arbitrator module is connected to multiple peripheral channels and is used to poll and arbitrate the DMA request signals of the multiple peripheral channels, dynamically block the request signals of the arbitrated channels, and release the blocking state of the corresponding peripheral channels according to the response signals. The input of the request FIFO module is connected to the polling arbitrator module, and is used to synchronize the arbitrated DMA request signal from the first clock domain to the second clock domain in real time. The output of the response FIFO module is connected to the polling arbitrator module and is used to synchronize the response signal of the second clock domain from the second clock domain to the first clock domain in real time.

2. The cross-clock domain DMA control system according to claim 1, characterized in that, The polling arbitrator module includes an arbitration unit, a shielding unit, and a detection unit; The arbitration unit is connected to multiple peripheral channels and is used to poll and arbitrate the DMA request signals of the multiple peripheral channels to obtain the arbitration result, and transmit the DMA request signal of the channel corresponding to the arbitration result to the request FIFO module. The shielding unit is communicatively connected to the arbitration unit and is used to dynamically shield request signals from channels that have already been arbitrated. The detection unit is communicatively connected to the arbitration unit and the shielding unit, and is used to acquire the shielding status and response signals of multiple peripheral channels in real time, and release the shielding status of the corresponding peripheral channel according to the response signal.

3. The cross-clock domain DMA control system according to claim 2, characterized in that, The shielding unit includes multiple flag bits, which are configured one-to-one with multiple peripheral channels. The flag bits are used to perform a logical OR operation with the arbitration result and the shielding status of the previous cycle in each cycle to indicate the shielding status of the channel in real time.

4. The cross-clock domain DMA control system according to claim 3, characterized in that, The detection unit includes generating a release signal for the corresponding peripheral channel based on the response signal; the shielding unit clears the flag bit of the corresponding channel in the shielding state according to the release signal.

5. The cross-clock domain DMA control system according to claim 2, characterized in that, In each clock cycle, the arbitration unit performs a bitwise AND operation between the request signal of the peripheral channel and the inverted value of the MASK register, and performs priority arbitration on the result.

6. The cross-clock domain DMA control system according to claim 1, characterized in that, The system also includes a storage access module, which is used to access the memory according to the arbitration result obtained by the polling arbitrator module, and generate a corresponding response signal according to the access result.

7. The cross-clock domain DMA control system according to claim 6, characterized in that, The system also includes a multiplexer; The multiplexer is located in the second clock domain; The selection terminal of the multiplexer is connected to the output terminal of the request FIFO module, and the multiple data input terminals of the multiplexer respectively receive access addresses and write data from multiple peripheral channels; The multiplexer is used to send the access address and write data of the channel corresponding to the arbitration result to the storage access module according to the arbitration result obtained by the polling arbitrator module.

8. The cross-clock domain DMA control system according to claim 1, characterized in that, Both the request FIFO module and the response FIFO module are asynchronous FIFOs with a depth greater than one.

9. A cross-clock domain DMA control method, applied to the cross-clock domain DMA control system as described in any one of claims 1-8, characterized in that, include: After obtaining DMA requests from multiple peripheral channels, the polling arbitrator module is controlled to select the target channel according to the polling strategy through a dynamic masking mechanism. The identifier of the target channel is written into the request FIFO module and output in the second clock domain after cross-clock domain synchronization; In the second clock domain, the address and data of the corresponding channel are selected according to the identifier to access the memory of the second clock domain and obtain the response signal; The response signal is written into the response FIFO module and returned to the first clock domain after cross-clock domain synchronization. And remove the shielding state of the peripheral channel corresponding to the response signal in the polling arbitrator module.

10. The cross-clock domain DMA control method according to claim 9, characterized in that, The control module for the polling arbitrator selects the target channel according to the polling strategy through a dynamic masking mechanism, including: Valid requests for peripheral channels are filtered based on the current shielding status. Arbitrate the highest priority request from the valid requests and use it as the arbitration result to determine the target channel; Update the shielding status and add the currently arbitrated peripheral channel to the shield.

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