FPGA-based computing data precision optimization processing method and system

Abstract

The application provides a FPGA-based calculation data precision optimization processing method and system, relates to the technical field of FPGA numerical calculation precision optimization, and comprises the following steps: loading obtained numerical calculation original data into a precision demand dynamic prediction model for analysis, and generating a data precision feature profile; performing self-adaptive preprocessing and initial precision repair based on the data precision feature profile, and generating preprocessed data and corresponding expected precision configuration suggestions; distributing the preprocessed data to multiple parallel calculation pipelines in the FPGA according to the expected precision configuration suggestions; in the calculation process of each calculation pipeline, dynamically collecting error feature tensors at multiple precision key path nodes defined in advance; and the precision key path nodes at least include output ports of pipeline register groups, conversion interfaces of data with different precision formats, and read data ports of cross-clock-domain synchronous FIFOs. The application can realize dynamic prediction, real-time compensation and closed-loop optimization of calculation precision.

Description

Technical Field

[0001] This invention relates to the field of FPGA numerical calculation accuracy optimization technology, and in particular to a method and system for optimizing the accuracy of computational data based on FPGA. Background Technology

[0002] In fields such as industrial control, AI inference, and high-performance scientific computing, FPGAs, with their high throughput, low latency, and customizability due to their parallel computing architecture, have become the core hardware carrier for carrying out high-precision numerical calculation tasks. In these scenarios, the accuracy of the calculated data directly determines the validity of the final output results. For example, in the closed-loop control of industrial servo motors, deviations in the calculation accuracy of parameters such as current and speed will directly affect the control accuracy and operational stability.

[0003] The current technical deficiency of FPGA-based numerical computation solutions lies in the lack of dynamic self-adaptation capability in the accuracy configuration and error compensation strategy of the computation pipeline. Specifically, in the deployment phase of the FPGA computing system, existing technologies pre-set the computational bit width, error monitoring node location, and compensation parameters of each computation pipeline based on offline simulation data or empirical values. During subsequent computation, this configuration remains static and cannot respond to dynamically changing internal and external factors in the computation chain, such as the dynamic range fluctuation of the original input data, timing delay drift of the pipeline register set, and data transmission jitter across clock domain FIFOs.

[0004] The above defects will cause an imbalance between computational accuracy and resource utilization. When the dynamic range of input data exceeds the preset bit width, irreversible accuracy loss is likely to occur due to truncation. If it is lower than the preset bit width, it will cause redundant occupation of FPGA resources and reduce throughput. Moreover, the error of critical path nodes is difficult to compensate accurately, and the static strategy cannot match the real-time error characteristics of the critical path, resulting in error accumulation. The output accuracy stability cannot meet the requirements of high-precision scenarios. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method and system for optimizing the accuracy of computational data based on FPGA, which can realize dynamic prediction, real-time compensation and closed-loop optimization of computational accuracy, and take into account both the high-precision computing requirements and the efficient utilization of FPGA hardware resources.

[0006] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: Firstly, a method for optimizing the accuracy of computational data based on FPGA, the method comprising: The acquired raw numerical calculation data is loaded into the accuracy requirement dynamic prediction model for analysis to generate a data accuracy feature profile; based on the data accuracy feature profile, adaptive preprocessing and initial accuracy repair are performed to generate preprocessed data and corresponding expected accuracy configuration suggestions. Based on the expected accuracy configuration recommendations, the preprocessed data is distributed to multiple parallel computing pipelines in the FPGA; During the computation process of each computation pipeline, error feature tensors are dynamically acquired at multiple predefined precision critical path nodes; the precision critical path nodes include at least the output port of the pipeline register group, the conversion interface for data of different precision formats, and the read data port of the cross-clock domain synchronous FIFO; A dynamic error spatial distribution model is constructed based on multiple error feature tensors collected by each computing pipeline within the same computing cycle. Based on the geometric optimization algorithm of the maximum coverage position of the elliptical plane, the dynamic error spatial distribution model is analyzed to generate a real-time error compensation vector corresponding to the current computing cycle. The intermediate results in the corresponding computation pipeline are compensated in real time by using a real-time error compensation vector to generate compensated intermediate results. The system aggregates the compensated intermediate results from all computational pipelines, performs data fusion and standardizes the accuracy format, generates the final result data, and extracts the accuracy evaluation features of the final result data. Based on the historical sequence of accuracy assessment characteristics and dynamic error spatial distribution model, and combined with the expected accuracy configuration suggestions, feedback is provided to adjust the computational bit width of each computing pipeline and the configuration strategy of the accuracy critical path nodes.

[0007] Secondly, an FPGA-based computational data accuracy optimization processing system includes: The dynamic prediction and preprocessing module is used to load the acquired raw numerical calculation data into the accuracy requirement dynamic prediction model for analysis and generate a data accuracy feature profile; based on the data accuracy feature profile, adaptive preprocessing and initial accuracy repair are performed to generate preprocessed data and corresponding expected accuracy configuration suggestions. The pipeline dynamic allocation module is used to allocate preprocessed data to multiple parallel computing pipelines in the FPGA based on the expected accuracy configuration suggestions. The error feature tensor acquisition module is used to dynamically acquire error feature tensors at multiple predefined precision critical path nodes during the computation process of each computation pipeline; the precision critical path nodes include at least the output port of the pipeline register group, the conversion interface for data of different precision formats, and the read data port of the cross-clock domain synchronous FIFO. The dynamic error compensation module is used to construct a dynamic error spatial distribution model based on multiple error feature tensors collected by each computing pipeline within the same computing cycle; it analyzes the dynamic error spatial distribution model based on the geometric optimization algorithm of the maximum coverage position of the elliptical plane and generates a real-time error compensation vector corresponding to the current computing cycle; and it uses the real-time error compensation vector to compensate the intermediate results in the corresponding computing pipeline in real time and generate compensated intermediate results. The data fusion and accuracy assessment module is used to aggregate the compensated intermediate results from all computational pipelines, perform data fusion and accuracy format unification, generate final result data, and extract accuracy assessment features from the final result data. The closed-loop feedback optimization module is used to adjust the computational bit width of each computational pipeline and the configuration strategy of the precision critical path nodes based on the historical sequence of the accuracy evaluation characteristics and the dynamic error spatial distribution model, combined with the expected accuracy configuration suggestions.

[0008] The above-described solution of the present invention has at least the following beneficial effects: By constructing a dynamic prediction and preprocessing mechanism for accuracy requirements, dynamic allocation of FPGA parallel computing pipelines is achieved. Error feature tensors are dynamically collected at accuracy-critical path nodes to construct a dynamic error spatial distribution model. A geometric optimization algorithm for the maximum coverage position of an elliptical plane is used to generate real-time error compensation vectors, completing multi-pipeline data fusion and accuracy evaluation. Simultaneously, a closed-loop feedback adjustment mechanism for the configuration strategy of computational bit width and accuracy-critical path nodes is established. Therefore, this overcomes the core defect of existing FPGA-based numerical computing schemes, which lack dynamic self-adaptation capability in computational pipeline accuracy configuration and error compensation strategies. It solves the technical problems of imbalance between computational accuracy and resource utilization, and the inability to accurately compensate for critical path node errors, which continue to accumulate. Thus, dynamic prediction, real-time compensation, and closed-loop optimization of computational accuracy are realized, which not only ensures the accuracy and stability of numerical computing results but also improves the utilization of FPGA hardware resources and computational throughput, effectively meeting the needs of application scenarios such as industrial control, AI inference, and high-performance rational computing. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating the FPGA-based computational data accuracy optimization processing method provided in an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of an FPGA-based computational data accuracy optimization processing system provided in an embodiment of the present invention. Detailed Implementation

[0011] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0012] like Figure 1 As shown, embodiments of the present invention propose a method for optimizing computational data accuracy based on FPGA, the method comprising the following steps: Step 1: Load the acquired raw numerical calculation data into the accuracy requirement dynamic prediction model for analysis to generate a data accuracy feature profile; perform adaptive preprocessing and initial accuracy repair based on the data accuracy feature profile to generate preprocessed data and corresponding expected accuracy configuration suggestions. Step 2: Based on the expected accuracy configuration recommendations, distribute the preprocessed data to multiple parallel computing pipelines in the FPGA; Step 3: During the computation process of each computation pipeline, error feature tensors are dynamically acquired at multiple predefined precision critical path nodes; the precision critical path nodes include at least the output port of the pipeline register group, the conversion interface for data of different precision formats, and the read data port of the cross-clock domain synchronous FIFO. Step 4: Construct a dynamic error spatial distribution model based on multiple error feature tensors collected by each computing pipeline within the same computing cycle; analyze the dynamic error spatial distribution model based on the geometric optimization algorithm of the maximum coverage position of the elliptical plane, and generate a real-time error compensation vector corresponding to the current computing cycle. Step 5: Using the real-time error compensation vector, the intermediate results in the corresponding computation pipeline are compensated in real time to generate compensated intermediate results. Step 6: Aggregate the compensated intermediate results from all computational pipelines, perform data fusion and precision format unification, generate the final result data, and extract the precision evaluation features of the final result data. Step 7: Based on the historical sequence of accuracy assessment features and dynamic error spatial distribution model, and combined with the expected accuracy configuration suggestions, feedback is provided to adjust the computational bit width of each computing pipeline and the configuration strategy of the accuracy critical path nodes.

[0013] In this embodiment of the invention, by dynamically predicting accuracy requirements and adaptive preprocessing, data accuracy requirements can be matched in advance and initial accuracy defects can be repaired. Dynamic pipeline allocation is achieved based on expected accuracy configuration, enabling efficient adaptation of data processing and hardware resources. Error feature tensors are dynamically collected at critical path nodes, and real-time compensation vectors are generated by combining the geometric optimization algorithm of the maximum coverage position of the elliptical plane. This can accurately suppress the accumulation of errors during the calculation process. Through multi-pipeline data fusion and accuracy evaluation, the consistency and reliability of the final result are ensured. With the closed-loop feedback adjustment mechanism, the computation bit width and node configuration strategy are dynamically optimized, which can significantly improve the accuracy and stability of numerical calculation, as well as improve the utilization rate of FPGA hardware resources and the computing throughput, effectively adapting to the needs of high-precision computing scenarios such as industrial control and AI inference.

[0014] In a preferred embodiment of the present invention, step 1 above may include: Step 1.1: Load the acquired raw numerical calculation data into the accuracy requirement dynamic prediction model. Specifically, the accuracy requirement dynamic prediction model is based on the classic MobileNet lightweight convolutional neural network (responsible for static multi-dimensional feature extraction) and LSTM long short-term memory network (responsible for temporal dynamic feature capture) as the basic fusion architecture, and carries out targeted improvements: First, determine the basic topology of the fusion architecture, adopt the depthwise separable convolutional layer of MobileNet as the bottom feature extraction unit, retain its combination structure of 1×1 convolutional kernel and 3×3 depthwise convolutional kernel, and adapt it to the local feature parsing of numerical data; set the number of hidden layer units of LSTM network to 128, and optimize the activation function of the gate unit to a combination of Tanh and Sigmoid to enhance the ability to capture the temporal fluctuation features of numerical data.

[0015] Secondly, a dedicated feature processing module for FPGA numerical computing scenarios is added: First, a precision feature perception layer, employing a grouped convolutional structure with the number of groups matching the number of data dimensions, specifically extracts the precision-related basic features of numerical data, adapting to the feature differences in servo motor current / speed data in industrial control, floating-point input parameters in AI inference, and initial data for high-performance scientific computing iterations; second, a dynamic range coding layer, introducing an adaptive quantization coding mechanism to map the amplitude range of data from different scenarios to standardized coding features, solving the adaptation problem of large differences in the dynamic range of data in different scenarios; third, a sensitive dimension labeling layer, embedding a feature importance evaluation unit based on mutual information entropy, labeling the sensitivity dimension level by calculating the correlation entropy value between each data dimension and the final calculation result; and fourth, a sparse feature quantization layer, employing a threshold adaptive adjustment sparse coding strategy to accurately quantify the proportion of effective information in the data. Finally, redundant architecture is pruned. The global average pooling layer and redundant fully connected layer used for image classification in the original MobileNet architecture are removed. The output layer of LSTM is fused with the output of the newly added feature processing module through a splicing layer. Two lightweight fully connected layers are then connected as the output layer to output a structured precision feature profile. The overall architecture is optimized through a model compression algorithm to ensure that the computational overhead is adapted to the high real-time and low power consumption processing requirements of FPGA.

[0016] The model training process adopts a phased strategy of scenario-layered pre-training + global joint fine-tuning: First, a multi-scenario specialized dataset is constructed, covering three major areas: industrial control (current and speed data of servo motors under different loads, including 20 working conditions), AI inference (floating-point input feature data of CNN and Transformer models, including 10 classic models), and high-performance scientific computing (iterative initial data for fluid simulation and finite element analysis, including 8 simulation scenarios), collecting a total of 200,000 sets of original data samples; each set of samples is professionally labeled with four core labels: upper and lower limits of dynamic range, sensitivity level 1 to 5, noise intensity, and sparsity coefficient (0, 1). At the same time, data augmentation processing is performed on the samples, including amplitude micro-perturbation, Gaussian noise superposition, and temporal misorder correction, etc., finally forming a dataset of 150,000 sets of training samples and 50,000 sets of validation samples, which are divided into industrial control sub-dataset, AI inference sub-dataset, and scientific computing sub-dataset according to scenario type. Next, pre-training was carried out for three subsets: when training with the industrial control subset, the number of grouped convolutional kernels of the precision feature perception layer was adjusted to 64 to adapt to the one-dimensional time-series features of current / speed data; when training with the AI ​​inference subset, the quantization interval of the dynamic range encoding layer was optimized to [-1,1] to match the amplitude distribution of floating-point feature data; when training with the scientific computing subset, the threshold sensitivity of the sparse feature quantization layer was improved to adapt to highly sparsity iterative data; the feature parsing accuracy was the core indicator for pre-training of each subset, with 20 training iterations, using the Adam optimizer, and the initial learning rate was set to 0.001.

[0017] The iterative optimization process employs a closed-loop workflow of forward propagation analysis, loss calculation, gradient backpropagation, parameter update, and verification calibration. In each iteration, the current batch of training samples is first input into the model for forward propagation. Local static features of the data are extracted using MobileNet deep separable convolutional layers, and temporal dynamic features are captured using an LSTM network. Then, four newly added dedicated feature layers complete the encoding, labeling, and quantization of accuracy features, ultimately outputting the predicted accuracy feature profile. Subsequently, the loss value between the predicted profile and the sample label is calculated. The loss function uses weighted cross-entropy loss, with a dynamic range prediction error weight of 0.3 and a sensitive dimension of 0.3. The degree annotation error weight is 0.4, and the sparsity coefficient error weight is 0.3, precisely matching the priority requirements of subsequent preprocessing and pipeline configuration. An adaptive momentum gradient descent strategy is used for gradient backpropagation based on the loss value to update the parameters of each layer of the model. L2 regularization constraints are applied to the weights of the MobileNet convolutional layers to avoid overfitting. Gradient clipping is applied to the parameters of the LSTM gated units, with a clipping threshold set to 1.0 to prevent gradient explosion. Different learning rate decay coefficients are set for the parameters of newly added dedicated layers according to the differences in scene characteristics: 0.95 for industrial control scenarios, 0.93 for AI inference scenarios, and 0.97 for scientific computing scenarios. After every 5 iterations, performance is calibrated using a validation dataset. Evaluation metrics include comprehensive feature parsing accuracy, dynamic range prediction error, sensitive dimension annotation consistency, and sparsity coefficient error. If the overall accuracy of the validation set is below 95% or any single metric fails to meet the standard, the learning rate is adjusted (reduced by 0.1 times) and 5 more iterations are added. If the performance fluctuation on the validation set is less than 0.5% for three consecutive iterations, the model training is considered converged.

[0018] Experimental data show that after complete construction and iterative training, the model achieves 99.4% consistency in labeling sensitive dimensions of current / speed data in industrial control scenarios, controls the dynamic range prediction error of AI inference floating-point feature data to within 1.0%, and has a sparsity coefficient error of less than 0.8% for scientific computing iterative data; the accuracy of multi-scenario comprehensive feature parsing reaches 98.9%, an improvement of 23% compared to before layered pre-training; the latency of a single feature parsing is ≤2ms, and the computational overhead is reduced by 32% compared to the original fusion architecture, fully adapting to the real-time and low-power requirements of FPGA.

[0019] After the model completes all construction, phased training, and iterative optimization processes and reaches the preset performance indicators, the full-domain acquisition process of raw numerical computation data is initiated: for industrial control scenarios, real-time current and speed sampling data of servo motors during operation are collected; for AI inference scenarios, input feature matrix data of deep learning models are collected; for high-performance scientific computing scenarios, initial iteration vector data of numerical simulations are collected. Simultaneously, the integrity of the acquired raw data is verified frame by frame, and any abnormal data is discarded and re-acquisition is triggered. After verification, based on the input adaptation rules of the dynamic prediction model for accuracy requirements, the raw data undergoes time-series synchronization alignment, data bit-width normalization, and numerical representation format standardization to ensure that the input attributes of the raw data fully match the model input requirements. Finally, the raw numerical computation data, after acquisition, verification, adaptation, and normalization, is imported batch by batch into the dynamic prediction model for accuracy requirements according to the model input time sequence requirements, completing all data loading operations.

[0020] Step 1.2 involves performing multi-dimensional feature analysis on the raw numerical computation data using a dynamic prediction model for accuracy requirements, outputting a structured profile of data accuracy features. Specifically, this includes: After receiving the adapted and normalized raw numerical computation data, the dynamic prediction model for accuracy requirements initiates a multi-dimensional feature hierarchical analysis process. First, it performs basic attribute pre-analysis to identify the data's numerical type, basic time-series features, and number of data dimensions. For different scenarios such as industrial control servo motor current or speed data, AI inference floating-point input parameters, and initial data for high-performance scientific computing iterations, it matches corresponding analysis templates to ensure that the basic analysis adapts to different scenarios. Then, it initiates a specialized deep analysis of accuracy features: dynamic range analysis uses a sliding window to statistically analyze the extreme values ​​and fluctuations of the data's amplitude, marking instantaneous amplitude mutation points, with the sliding window size appropriately adjusted. The system employs various methods to analyze data sampling frequencies for different scenarios. Sensitive dimension analysis utilizes the model's built-in mutual information entropy evaluation mechanism to calculate the correlation between each data dimension and the error in the calculation results, classifying sensitivity levels and highlighting key sensitive dimensions. The marking rules align with the core computational needs of different scenarios. Noise distribution analysis uses frequency domain analysis to separate effective signals from noise components, identifying noise types and statistically analyzing noise distribution and frequency characteristics. Sparsity analysis uses adaptive thresholds to statistically analyze the proportion of invalid data, calculates the sparsity coefficient, and marks the distribution interval of effective data. Finally, a structured feature profile is generated, integrating all analysis results into a three-level hierarchical structure of basic attributes, specialized precision features, and scenario-adaptive annotations. Standardized coding formats are used to organize each field, ensuring semantic uniqueness and format uniformity, ultimately generating a complete structured data precision feature profile.

[0021] Step 1.3: Based on the dynamic range and sensitivity dimension information included in the structured data precision feature profile, the filtering parameters and numerical scaling coefficients required for preprocessing are adapted and determined. Specifically, this includes: after receiving the structured data precision feature profile, firstly extracting core parameters such as dynamic range, sensitivity level distribution, noise type, and frequency range from the profile; combining the application scenario of the profile annotation, matching the corresponding parameter adaptation strategy, with different scenarios focusing on core requirements such as anti-interference, feature preservation, and accuracy stability; then determining the adaptation of the numerical scaling coefficients: calculating the amplitude span based on the data dynamic range, and determining the amplitude adaptation target range based on the conventional operation bit width of the subsequent FPGA computing pipeline, initially obtaining the theoretical value of the scaling coefficient; adjusting the theoretical value based on data fluctuation, reserving amplitude fluctuation space to avoid data truncation; generating multiple sets of scaling coefficient candidate values, and filtering out the optimal value through simulated scaling verification to ensure that the scaled data is not truncated and the fluctuation fully adapts to the target range.

[0022] Then, the filter parameters are adapted and determined: the filter algorithm type is matched based on the noise type and frequency range; the filter strength is adjusted according to the sensitivity level distribution, a weak filter strength is used for high-sensitivity dimensions to retain effective features, and a strong filter strength is used for ordinary dimensions to improve the noise removal effect. At the same time, the filter details are optimized to adapt to the noise characteristics of different scenarios; the determined filter algorithm and parameter combination are verified by samples to ensure that the noise removal effect and feature preservation effect meet the standards. If they do not meet the standards, the parameters are readjusted; finally, the correlation between the filter parameters and the numerical scaling coefficient is verified to ensure that the data accuracy loss after the two are combined is controllable. Finally, the optimal parameter combination is locked and output to the next execution step.

[0023] Step 1.4: Using the aforementioned filtering parameters and numerical scaling coefficients, adaptive filtering and scaling transformation are performed on the original numerical calculation data to complete initial accuracy repair and generate preprocessed data. Specifically, this includes: obtaining the filtering parameters and numerical scaling coefficients, and initiating the initial accuracy repair process of adaptive filtering and scaling transformation: firstly, processing batches are divided according to the data's sensitivity level, with high-sensitivity dimensions processed first, and filtering is performed frame by frame; after one round of filtering, the noise duty cycle of the data before and after filtering is compared. If the noise duty cycle does not meet the standard, filtering is repeated to avoid over-filtering leading to feature distortion; after filtering, the effective feature retention rate of each dimension is calculated. If it does not meet the standard, the filtering parameters are adjusted and filtering is repeated to ensure that all dimensions meet the feature retention requirements; subsequently, precise numerical scaling processing is performed: scaling down the data according to the determined numerical values... The scaling factor is applied to the filtered complete data sequence point by point for scaling calculation, and the amplitude before and after scaling of each data point is recorded to ensure traceability. During the scaling process, the data amplitude is monitored in real time. If an anomaly point is found that exceeds the target range, a local adjustment is triggered to avoid local accuracy loss caused by overall scaling. After the scaling transformation is completed, the data is uniformly converted into a set numerical format to ensure that the bit width and encoding rules are consistent and adapted to subsequent pipeline processing. Finally, initial accuracy repair verification and preprocessed data generation are performed: the accuracy of the filtered and scaled dataset is evaluated, and the noise duty cycle and amplitude fluctuation adaptability are statistically analyzed. If the standard is not met, the parameters are backtracked and reprocessed. After the standard is met, the preprocessing status of the data is marked, and the parameters and accuracy indicators during the processing are recorded. Finally, low-noise, highly adaptable, and accurate preprocessed data is generated.

[0024] Step 1.5: Based on the preprocessed data generated after initial precision repair, and according to the noise distribution characteristics and sparsity indices contained in the structured data precision feature profile, generate expected precision configuration suggestions to guide the initial configuration of the computational pipeline. Specifically, this includes: firstly, conducting secondary analysis on the preprocessed data and corresponding structured data precision feature profile that has undergone initial precision repair; secondly, reviewing the precision repair effect of the preprocessed data and extracting key indicators such as the actual precision loss value and the proportion of residual noise; thirdly, accurately extracting core information such as noise distribution characteristics, sparsity coefficient, sensitivity level distribution, and dynamic range fluctuation patterns from the structured data precision feature profile; and fourthly, integrating this information into a complete configuration analysis base dataset, combining it with the effective data length, time series period, and other basic attributes of the preprocessed data, to provide a comprehensive basis for subsequent configuration parameter derivation; and fifthly, determining the basic error threshold for computation based on the configuration analysis base dataset: combining the type and intensity of residual noise in the noise distribution characteristics and referring to the actual precision loss value of the preprocessed data, determining the tolerable basic error threshold in the computational pipeline, ensuring that this threshold is lower than the precision loss in the preprocessing stage, and reserving sufficient adjustment space for the error compensation stage.

[0025] Next, the computational bit width range for each data block is determined: Considering the proportion of effective data reflected by the sparsity coefficient, if the proportion of effective data is high, the bit width can be appropriately reduced to save resources; if the proportion of effective data is low, sufficient bit width must be ensured to avoid precision loss. Simultaneously, the amplitude variation pattern reflected by dynamic range fluctuations is referenced; if the fluctuation amplitude is large, the bit width range needs to be expanded to avoid data truncation. Based on this, the computational bit width range for each data block is finally defined by matching the basic requirements for computational accuracy in different scenarios such as industrial control, AI inference, and high-performance scientific computing. Then, the data processing priority is confirmed: based on the sensitivity level distribution results, highly sensitive dimension data is listed as the highest priority to ensure that core data is allocated computing resources first; ordinary dimension data is set to medium priority, and invalid data ranges are set to low priority. Furthermore, considering the real-time requirements of the application scenario, data from latency-sensitive scenarios such as servo motor closed-loop control in the industrial control field are given an additional priority level to ensure low-latency processing of core scenario data.

[0026] After determining the core parameters, the error baseline threshold, the bit width range of each data block, and the data processing priority are systematically integrated according to the logic of scenario adaptation requirements, core configuration parameters, and parameter derivation basis. Scenario adaptation requirements clearly define the core needs of the corresponding application scenario, the core configuration parameters clearly list the derivation results, and the parameter derivation basis details the source of each configuration parameter's derivation (e.g., the bit width range is derived based on sparsity coefficients and dynamic range fluctuations), improving the interpretability of the configuration recommendations. Finally, the integrated configuration recommendations are matched and verified: the bit width range is checked against the hardware capabilities of the FPGA computing pipeline to see if it is within the hardware support range and if the priority rules conform to the FPGA's parallel computing scheduling logic. If mismatches exist (e.g., bit width exceeds the hardware limit), the derivation basis for the bit width is adjusted in reverse, for example, by appropriately reducing the bit width requirement for low-priority data, and the configuration recommendations are re-derived and integrated. After successful verification, the configuration recommendations are standardized using a standardized format to generate the final expected accuracy configuration recommendations, which serve as the direct basis for the initial configuration of the FPGA computing pipeline.

[0027] In a preferred embodiment of the present invention, step 2 above may include: Step 2.1 involves parsing the expected precision configuration suggestion, extracting the computation task type identifier, the required computation bit width range for each data block, and priority instructions. Specifically, this includes: initiating a structured parsing process for the expected precision configuration suggestion, parsing segment by segment according to the hierarchical logic of scenario identifier, data block configuration, and priority definition. First, the computation task type identifier is located and extracted. This identifier includes the scenario affiliation (industrial control, AI inference, high-performance scientific computing) and the core computation type, including both time-series computation, matrix computation, and iterative computation information. Decoding the identifier clarifies the core processing requirements of the task. Next, for each data block of the preprocessed data, the corresponding data block computation bit width range is accurately extracted through association with the unique data block ID, including the minimum guaranteed bit width and the dynamic adjustment upper limit, while recording the precision requirements for bit width adaptation. Finally, priority instructions are extracted. These instructions contain the high, medium, and low priority levels for each data block, as well as scheduling rules under the same priority. After extraction, all information is cross-validated to ensure that the computation task type, data block bit width requirements, and priority instructions correspond one-to-one, with no missing or conflicting information, forming a structured parsing result set.

[0028] Step 2.2: Based on the extracted computation task type identifier, match the predefined computation pipeline template library in the FPGA hardware resources to filter out a set of candidate computation pipelines compatible with the task type. Specifically, this includes: a predefined computation pipeline template library in the FPGA hardware resources, organized using a two-level index structure of scenario and operation type, categorized into three major scenarios: industrial control, AI inference, and high-performance scientific computing. Each scenario is further subdivided into template subsets based on core operation types, including timing operations, matrix operations, and iterative operations, facilitating rapid retrieval and matching; each pipeline template in the library contains a complete attribute description. The information specifically covers compatible task characteristics, supported computation bit width range, core computation unit configuration, storage interface specifications, resource usage baseline values, and pipeline structure parameters. The compatible task characteristics clearly define the combination of applicable scenarios and computation types. The supported computation bit width range includes bit width ranges with different precisions for fixed-point and floating-point operations. The core computation unit configuration clearly defines the computation unit model, quantity, and parallelism. The storage interface specifications clearly define the interface bit width, transmission protocol, and cache capacity. The resource usage baseline values ​​clearly define the basic usage of logic units and storage units. The pipeline structure parameters clearly define the number of pipeline stages, critical path delay, and reserved positions for error monitoring nodes.

[0029] Based on the parsed computation task type identifier, the template subset corresponding to the scenario is first located through a secondary index. Then, the templates within the subset are traversed using feature matching and range adaptation. First, the scenario affiliation and core operation type of the task are matched to filter out the basic compatible templates. Then, it is verified whether the operation bit width range supported by the template completely covers the bit width requirement of the data block, including the minimum guaranteed bit width and the dynamic adjustment upper limit, to further narrow the matching range. Subsequently, the real-time status detection of the computation pipelines corresponding to the matched templates is performed to obtain the current running status, real-time resource utilization rate and remaining throughput capacity of each pipeline. The current running status is divided into idle, running, and fault. The real-time resource utilization rate includes logical and storage resources. Pipelines with faults, resource utilization rates exceeding the safety threshold, or remaining throughput capacity that cannot meet the data block processing requirements are excluded. Finally, a set of candidate computation pipelines with both task compatibility and hardware availability is formed.

[0030] Step 2.3: By combining the computational bit width range and priority instructions, evaluate the current resource usage and throughput of each computational pipeline in the candidate computational pipeline set to determine the target computational pipeline for each preprocessed data block. Specifically, this includes: First, constructing a multi-dimensional evaluation system. This system is guided by the core requirements adaptability and hardware resource matching degree. The core evaluation indicators are the parsed computational bit width range and priority instructions, used to determine the pipeline's ability to support data computation accuracy and its ability to guarantee task real-time performance, respectively. Auxiliary evaluation indicators include the real-time resource utilization rate, remaining throughput capacity, and historical load fluctuation data of the candidate pipelines, used to determine the current resource redundancy, data processing efficiency potential, and load stability of the pipelines, respectively. Based on this evaluation system, first assess each pipeline... Candidate pipelines undergo bit-width compatibility verification to ensure their computational units can stably support the bit-width range of the corresponding data blocks, eliminating pipelines with incompatible bit-widths. Priority is then allocated according to priority levels, matching high-priority data blocks with candidate pipelines that have sufficient remaining throughput and low resource utilization to ensure low-latency processing of core data. For medium and low-priority data blocks, while meeting bit-width requirements, and in accordance with load balancing principles, the data blocks are allocated to pipelines with lighter loads to avoid overloading any single pipeline. After each data block is matched with a candidate pipeline, load estimation is performed. If the estimated pipeline resource utilization exceeds a safe threshold, the allocation scheme is readjusted. Finally, a unique and suitable target computation pipeline is determined for each preprocessed data block, and a mapping table between data blocks and pipelines is generated.

[0031] Step 2.4: Based on the characteristics of the precision computing units supported by the target computing pipeline and the memory interface bit width, the preprocessed data blocks are format-encapsulated and address-mapped to generate pipeline-ready data packets. Specifically, this includes: retrieving detailed hardware attribute parameters of the target computing pipeline, focusing on determining the characteristics of the core precision computing units and the bit width specifications and data transmission protocols of the memory interface. The characteristics of the core precision computing units include fixed-point and floating-point operation modes, supported precision levels, and data format requirements; based on the characteristics of the computing units, the preprocessed data blocks are format-converted to a numerical format that the computing units can directly process, while simultaneously verifying the precision of the converted values. To ensure no precision loss, data blocks are divided according to the storage interface bit width, following the principle of integer multiples of the interface bit width, to avoid data transmission fragmentation. Then, address mapping is performed, mapping the divided data to the target pipeline's dedicated physical storage address space. Different data blocks are distinguished by address offsets to prevent address conflicts. Finally, configuration header information is added to each data block, including the data block ID, target pipeline number, computation bit width requirement, priority identifier, and data length. The data blocks and configuration header information are integrated to generate a pipeline-ready data packet conforming to the pipeline data reception specification. After generation, format verification ensures the data packet can be correctly parsed by the target pipeline.

[0032] Step 2.5 involves scheduling and distributing pipeline-ready data packets to their corresponding target compute pipelines according to priority instructions to complete data allocation. This includes: constructing a three-level scheduling queue based on extracted priority instructions (high, medium, and low priority queues); assigning all pipeline-ready data packets to the corresponding queues according to their priority, with higher priority queues scheduled first; within queues of the same priority, sorting is done using a round-robin scheduling method based on data block IDs to avoid congestion of data of the same priority; after scheduling and sorting, selecting the corresponding high-speed data transmission channel within the FPGA based on the target pipeline number in the data packet configuration header, prioritizing high-priority data packets. First, high-bandwidth channels are matched with the data source to initiate data packet distribution. During distribution, the transmission status is monitored in real time, including transmission rate, bit error rate, and pipeline reception status. For each data packet distributed, a reception acknowledgment signal is awaited from the target pipeline. The acknowledgment signal contains a data packet checksum, which is used to verify whether the data packet has been received completely. If no acknowledgment signal is received or the checksum fails, a retransmission mechanism is triggered. Once all ready data packets have been distributed and passed the reception checksum, and all mapping relationships between the data blocks and the pipeline mapping table have been matched, the allocation of preprocessed data to the FPGA computing pipeline is officially completed.

[0033] In a preferred embodiment of the present invention, step 3 above may include: Step 3.1 involves dynamically analyzing the expected accuracy configuration recommendations and the hardware architecture characteristics of the target computing pipeline. Based on this, error monitoring dimensions and adaptive sampling triggering strategies are generated for each accuracy-critical path node. Specifically, this includes: integrating the expected accuracy configuration recommendations with the determined target computing pipeline characteristic information to build a bidirectional correlation analysis framework between configuration requirements and pipeline characteristics; extracting error control benchmarks, computation bit width ranges, and accuracy assurance levels from the expected accuracy configuration recommendations according to data block priority levels, and determining core requirements such as the error thresholds that high-priority data blocks need to be strictly controlled and the accuracy redundancy requirements for wide-bit-width data; and breaking down the timing of data processing, the signal transmission links of critical paths, the computational delays of each node, and the data buffering mechanisms from the characteristics of the target computing pipeline, and identifying the functional positioning of different nodes in the data flow and the error-prone links.

[0034] Based on the aforementioned framework, dynamic matching analysis is conducted: the accuracy requirements of high-priority data blocks are associated with core computing nodes in the pipeline, and the processing requirements of wide-bit-width data are associated with the bit-width adaptation nodes in the pipeline, clarifying the error-sensitive points of each precision-critical path node; accordingly, differentiated error monitoring dimensions are generated: for nodes through which high-priority data flows, three levels of monitoring dimensions are set: instantaneous error value, error change rate, and error accumulation; for wide-bit-width data processing nodes, the hierarchical monitoring interval of instantaneous numerical error is refined to ensure accurate matching between error monitoring and data characteristics; simultaneously, a refined adaptive sampling triggering strategy is formulated: based on the basic computing cycle of the pipeline, shorter timed sampling intervals are set for high-priority nodes, and regular intervals are set for ordinary nodes; combined with error control benchmarks, amplitude mutation triggering standards are set at two levels: warning threshold and over-limit threshold. When the error mutation amplitude reaches the warning threshold, the sampling frequency is increased; when it reaches the over-limit threshold, sampling is triggered immediately; fluctuation threshold judgment rules are formulated with reference to historical error data. When the error fluctuation amplitude exceeds the preset fluctuation threshold range, sampling is triggered to ensure that sampling covers key error information and achieves dynamic balance of sampling load.

[0035] Step 3.2: Based on the generated error monitoring dimensions, corresponding lightweight error monitoring units are inserted at the output ports of the pipeline register group, the conversion interfaces for data of different precision formats, and the read data ports of the cross-clock domain synchronous FIFO. Specifically, this includes: First, based on the generated error monitoring dimensions, customized design of monitoring logic is carried out for three key nodes: the output ports of the pipeline register group, the conversion interfaces for data of different precision formats, and the read data ports of the cross-clock domain synchronous FIFO. For the register group output ports, based on their corresponding operational bit width and monitoring dimensions, error comparison logic is designed for real-time numerical capture, theoretical standard value retrieval, and difference calculation. The theoretical standard value is generated through pre-stored benchmark data or real-time deduction to ensure the accuracy of the comparison. For the precision format conversion interfaces, difference monitoring logic is designed for pre-conversion data caching, post-conversion data extraction, and bit-by-bit difference identification, focusing on capturing errors caused by bit width truncation and encoding conversion during format conversion. For the cross-clock domain synchronous FIFO read data ports, collaborative monitoring logic is designed for clock timing verification, data integrity checking, and synchronization error calculation, focusing on data read / write deviations caused by clock asynchrony.

[0036] The lightweight error monitoring unit is described and synthesized using hardware description languages ​​such as Verilog or VHDL, and implemented as an embedded hardware monitoring logic. Its core structure includes at least an error calculation submodule, a data caching submodule, and a timing control submodule. The error calculation submodule is responsible for calculating the difference between the node output value and the theoretical standard value in real time. The caching submodule is used to temporarily store error sequences for multiple consecutive periods. The control submodule precisely controls the data acquisition and reporting timing according to an adaptive sampling triggering strategy. This unit adopts a pipelined bypass design, directly connecting to the data output path of the precision critical path node. It captures signals through register insertion, ensuring that the monitoring delay does not exceed one clock cycle and that the logic resource occupancy rate is less than 5% of the corresponding node's hardware resources, thereby achieving uninterrupted, real-time acquisition of error characteristics.

[0037] These customized monitoring logics are lightweighted and encapsulated to remove redundant computation modules, ensuring that the encapsulated monitoring units do not consume excessive processing resources and that the computational latency is much lower than a single computation cycle in the pipeline. Then, following the data flow sequence of the pipeline, the monitoring units are embedded into the corresponding nodes sequentially: first, timing simulation is used to verify the data flow timing after the monitoring units are connected, and after confirming there are no timing conflicts, the association link between the monitoring units and the node data signals is established; then, trial operations are used to verify the signal acquisition capability of the monitoring units, ensuring that the monitoring units can accurately acquire the error-related signals required for the monitoring dimensions. Finally, the embedding and adaptation of all monitoring units are completed, achieving collaborative operation of error monitoring and pipeline data processing.

[0038] Step 3.3, under the control of the adaptive sampling triggering strategy, the instantaneous numerical error, cumulative error trend, and error fluctuation spectrum information of each precision critical path node are synchronously collected through the error monitoring unit. Specifically, this includes: after starting the adaptive sampling triggering mechanism, the trigger clock of all lightweight monitoring units is first kept consistent with the global clock of the target computing pipeline through the global timing synchronization module; the data processing status of each precision critical path node is monitored in real time, and when the triggering conditions are met, such as reaching the timed sampling interval, the error mutation amplitude reaching the warning threshold or the over-limit threshold, or the error fluctuation exceeding the prediction range, all monitoring units are triggered to synchronously execute the acquisition operation; the acquisition process is carried out in layers according to the preset logic: in the instantaneous numerical error acquisition stage, the output value of the node is captured in real time through the error comparison logic of the monitoring unit, the corresponding theoretical standard value is called synchronously, the difference between the two is calculated and recorded, and the timing information of the acquisition time is marked; in the cumulative error trend acquisition stage, the instantaneous error value of multiple consecutive calculation cycles is accumulated through the sliding window mechanism, the mean, maximum and slope of the error within the window are calculated, the change law of error with the cycle is sorted out, and a staged cumulative error trend curve is formed.

[0039] In the error fluctuation spectrum information acquisition stage, noise reduction preprocessing is first performed on multiple consecutive sets of instantaneous error data to remove random interference signals. Then, the frequency components, amplitude distribution, and dominant frequency of the error signal are extracted by the frequency domain decomposition method to generate complete error fluctuation spectrum characteristics. During the acquisition process, in order to avoid data conflicts, various error information is classified and stored in a temporary cache according to the three-dimensional index rules of node identifier, calculation period, and data type. At the same time, a data verification mechanism is set up to check the integrity of the acquired data to ensure that there is no missing or erroneous data.

[0040] Step 3.4 involves aligning and integrating the instantaneous numerical errors, cumulative error trends, and error fluctuation spectrum information collected from multiple precision critical path nodes within the same computation cycle in both time and space dimensions, encapsulating them into a structured error feature tensor. Specifically, this includes: extracting error information from all precision critical path nodes within the same computation cycle from a temporary buffer; initiating time-dimensional alignment processing: using the global clock tick of the target computation pipeline as a benchmark, extracting the time stamp corresponding to each segment of error information, and correcting micro-time-sequence deviations caused by signal transmission delays at different nodes, ensuring that all error information is precisely aligned to the same moment within the same computation cycle, forming a time-synchronized error dataset; subsequently, spatial-dimensional association integration is performed: based on the order of each node in the pipeline data transmission link, a node association graph is constructed to confirm the data flow path from upstream to downstream nodes; based on the graph analysis, causal relationships of error information from different nodes are analyzed, such as the impact of errors output by the upstream register group on downstream format conversion interface errors, and error information with transmission relationships is associated and marked; simultaneously, multi-dimensional error information from the same node is integrated to form a complete error feature set for a single node.

[0041] Finally, a structured encapsulation is performed: the aligned and integrated error data is organized according to a hierarchical structure of periodic information, node association information, single-node error characteristics, and global error summary. The periodic information includes the calculation period number and time series range; the node association information includes the node association graph and transmission relationship markers; the single-node error characteristics include instantaneous numerical error, cumulative error trend curve, and error fluctuation spectrum characteristics; and the global error summary includes the statistical characteristics of all node errors. Auxiliary information such as corresponding data block IDs and monitoring dimension identifiers are added to ensure that the encapsulated error feature tensor information is complete, logically clear, and traceable. Finally, the structured error feature tensor is output to the dynamic error compensation stage.

[0042] In a preferred embodiment of the present invention, step 4 above may include: Step 4.1 involves receiving multiple structured error feature tensors uploaded from multiple precision-critical path nodes of a computation pipeline within the same computation cycle. Specifically, this includes: initiating the reception preparation process, determining the reception rule to only receive structured error feature tensors labeled with the same computation pipeline identifier and the same computation cycle number, and simultaneously enabling time-series synchronization monitoring to ensure all received data corresponds to the same computation time. During the reception process, a three-stage processing approach is adopted: identifier pre-verification, data reception, and secondary verification. First, the pipeline identifier field and computation cycle number field of the data to be received are extracted and preliminarily compared with the preset target pipeline identifier and the current computation cycle number, filtering out invalid data with mismatched identifiers. For data that passes the pre-verification... Data is received frame by frame in sequence, and the timing of data reception is recorded synchronously to ensure the timing consistency of data within the same period. After reception, a second integrity check is performed to verify whether the tensor contains core fields such as period information, node association information, single node error characteristics, and global error summary. At the same time, the data format of each field is checked to ensure that it conforms to the specifications. If there are missing fields, incorrect formats, or corrupted data, a retransmission request is immediately triggered until complete and valid data is obtained. Finally, the error feature tensors that have passed all checks are classified and organized according to node identifiers to form a set of error feature tensors with clear ownership, synchronized timing, and complete data within the same pipeline and period. An index mapping table between tensors and corresponding precision critical path nodes is also established.

[0043] Step 4.2 involves parsing the error space coordinates and multi-dimensional error information contained in each structured error feature tensor, mapping the multi-dimensional error information to an error distribution space based on each precision critical path node. Specifically, this includes: first, initiating a refined parsing process for the error feature tensors, decomposing each tensor in the tensor set one by one: For the error space coordinates, two core pieces of information are parsed: one is the physical location coordinates of the node in the computation pipeline, quantifying the physical installation position of the node into three-dimensional coordinate values ​​using pipeline hardware layout parameters; the other is the data link sequence number, assigning a unique sequence number according to the node's order in the data flow link to form complete error space coordinates; for the multi-dimensional error information, it is parsed according to error type, extracting detailed information such as the specific value of the instantaneous numerical error, key feature points of the cumulative error trend curve, and the frequency components and amplitude distribution of the error fluctuation spectrum. Simultaneously, the timestamps and error levels of each error information are marked. Then, an error distribution space is constructed, with the physical layout direction of the computational pipeline as the X-axis, the data flow direction as the Y-axis, and the error level as the Z-axis. A three-dimensional spatial coordinate system is established, and the error spatial coordinates of each precision critical path node are mapped to base points in the space, forming a spatial grid with nodes as the core. Based on preset mapping rules, the parsed multi-dimensional error information is mapped to the base point position of the corresponding node according to its type. Specifically, instantaneous numerical errors are mapped to numerical labels at the base point, cumulative error trend curves are mapped to trend lines along the data flow direction, and error fluctuation spectrum features are mapped to feature halos around the base point. At the same time, the mapping relationship of each error information is recorded, completing the complete transformation of error information from structured tensors to spatially visualized distribution, ensuring that the distribution of error information in space accurately matches the error state in the actual pipeline.

[0044] Step 4.3: Based on the error space coordinates and the mapped multi-dimensional error information in the error distribution space, a dynamic error space distribution model representing the spatial propagation of errors within the computational pipeline is fitted and generated. Specifically, this includes: preprocessing the mapped data in the error distribution space to remove abnormal error data caused by analytical or mapping deviations; calculating the mean and standard deviation of the error data to set a reasonable threshold range (mean plus or minus 2 standard deviations for industrial control scenarios, and mean plus or minus 1.8 standard deviations for AI inference scenarios); filtering outliers exceeding the threshold to ensure the reliability of the basic data; and then analyzing the upstream and downstream data flow of each precision critical path node in the computational pipeline. Relationships are established, and a link relationship map between nodes is constructed in conjunction with specific application scenarios: In the servo motor closed-loop control pipeline of industrial control scenarios, the focus is on sorting out the low-latency data link from the register output node to the format conversion node, marking the signal transmission delay of the link as approximately 0.08 microseconds, and the bit width adaptation rule as 16-bit fixed-point to 32-bit fixed-point; In the matrix operation pipeline of AI inference scenarios, the focus is on the high-parallelism data link from the cross-clock domain FIFO node to the operation unit node, marking the number of parallel processing paths of the link as 16, and the data sharding rules. By tracing the transmission trajectory of data from upstream nodes to downstream nodes in different scenarios, the possible propagation paths and propagation rate characteristics of errors are confirmed.

[0045] Based on the preprocessed basic data and link association graph, a dynamic error spatial distribution model is constructed. This model is an improvement on the spatiotemporal graph neural network architecture, with three core optimizations tailored to the hardware characteristics and error propagation patterns of the FPGA computing pipeline. First, the adjacency matrix weight calculation method of the graph convolutional layer is optimized. The original graph convolutional layer only considered the node topology relationship, while the improved model incorporates the signal transmission delay and bit width adaptation coefficient of the FPGA pipeline as weight factors, making the adjacency matrix more consistent with the actual error propagation characteristics of the hardware. Second, a new pipeline hardware constraint layer is added, embedding parameters such as the computing power limit, storage interface bandwidth, and clock frequency of each node's computing unit. The clock frequency is 200 MHz in industrial control scenarios and 400 MHz in AI inference scenarios, limiting the error compensation range of the model output to not exceed the physical limits of the hardware. Third, the fully connected layer structure is simplified, reducing the original three fully connected layers to one layer, and adopting a quantized perceptual training method to adapt to the fixed-point operation characteristics of the FPGA and reduce the model's computational latency. In the model building phase, the inputs are defined as the error spatial coordinates of each node, multi-dimensional error information (instantaneous numerical error, cumulative error trend, error fluctuation spectrum), and link correlation characteristics (transmission delay, number of parallel paths, etc.). The outputs are the spatial distribution profile of the error within the pipeline, the propagation direction, the rate, and the error coupling coefficient. For the two core scenarios of industrial control and AI inference, scenario-specific sub-model branches are constructed respectively. The industrial control branch enhances the ability to predict low-latency error propagation, while the AI ​​inference branch enhances the ability to fit the coupling distribution of multi-node errors under high parallelism.

[0046] During the model training phase, a multi-scenario labeled dataset was first constructed: 100,000 sets of error data from servo motor closed-loop control pipelines in industrial control scenarios, covering full-condition data within the motor speed range of 1000 to 5000 rpm; and 80,000 sets of error data from image classification matrix operation pipelines in AI inference scenarios, covering different operation scales with batch sizes from 32 to 256. These datasets were divided into training, validation, and test sets in a 7:2:1 ratio. A training strategy combining pre-training and scenario fine-tuning was adopted. In the pre-training phase, a hybrid dataset was used with the AdamW optimizer, an initial learning rate of 1e^(-3), decaying by 10% every 50 epochs, for 1000 epochs, allowing the model to grasp general error propagation patterns. In the scenario fine-tuning phase, error data from industrial control and AI inference scenarios were used respectively. The corresponding branches were fine-tuned using a dedicated dataset for the scene, with the learning rate reduced to 1e to the power of -4 and 500 iterations. FPGA hardware resource constraints were introduced as a regularization term in the loss function, with a weight of 0.01, penalizing predictions exceeding hardware constraints. The main loss function used mean squared error to minimize the deviation between the prediction and actual errors. The fitting accuracy was verified every 10 rounds during training. Training stopped when the deviation rate between the model's predicted error distribution and the actual collected data on the validation set was consistently below 3%. The final test set verification results showed a model deviation rate of 2.7% in the industrial control scenario, accurately capturing the rapid propagation of errors in low-latency links at the 0.1 microsecond level. The AI ​​inference scenario deviation rate was 2.5%, accurately identifying the error coupling effect during parallel processing of matrix operation units.

[0047] After training, a dynamic error spatial distribution model is generated based on this model: First, the node error data of the current computation cycle is input, and the model outputs the basic outline of the error distribution, representing the overall distribution range of the error in space. Then, the dynamic characteristics of error propagation predicted by the model are incorporated, and error propagation direction arrows and rate annotations are added for corresponding scenarios. In the industrial control scenario, the error propagation rate is annotated as 1.2 GB per second, and the attenuation coefficient of 0.92 when the node error propagates to the format conversion node is output by the annotation register. In the AI ​​inference scenario, the propagation rate is annotated as 2.5 GB per second, and the error coupling coefficient of 16 parallel units is annotated as 0.88, reflecting the spatial distribution, propagation status, and changing trend of the error among the nodes of the computation pipeline in real time. After the model is generated, the fitting accuracy is verified by comparing the model output with the actual collected error data. If the deviation exceeds the allowable range, such as higher than 3%, the link correlation feature weights of the model are adjusted and iterated again until the model can accurately represent the actual error propagation law under different application scenarios. Compared to traditional static error distribution models, this dynamic model improves the accuracy of error propagation prediction by 20%, and by incorporating a hardware constraint layer, it reduces hardware compensation resource usage by 15%, providing accurate and hardware-appropriate error spatial distribution data for subsequent optimization solutions.

[0048] Step 4.4: Using the error distribution geometry defined by the dynamic error spatial distribution model as the optimization object, drive the elliptical plane maximum coverage position geometry optimization algorithm to solve, and obtain the elliptical parameter set that satisfies the preset coverage threshold constraint. The elliptical parameter set includes the ellipse center, major and minor axis directions, and eccentricity. Specifically, it should be noted that the elliptical plane maximum coverage position geometry optimization algorithm is a parameter optimization method based on an elliptical geometric model. Its core lies in approximating the error distribution in two-dimensional or three-dimensional space as an elliptical or ellipsoidal region, and optimizing the ellipse's position, major / minor axis directions, and eccentricity so that the ellipse can cover the high-density region in the error distribution to the maximum extent under the constraint of the preset coverage threshold. The optimization objective can be expressed as finding an ellipse in the geometric space that maximizes the coverage of the high error value region, thereby providing the optimal geometric reference for subsequent error vector compensation. Then, confirm the core boundary of the optimization object, and use the dynamic error spatial distribution model... The complete boundary of the geometric structure of the error distribution defined by the model and the internal error density distribution characteristics are used as the core of optimization. The core objective is to determine the ellipse parameter set so that the ellipse maximizes the coverage of the high error density area while meeting the preset coverage threshold constraint. The preset coverage threshold is set according to the error control benchmark recommended by the expected accuracy configuration. It is usually required to cover more than 90% of the total area of ​​the error distribution area, and the coverage ratio of the high error density area (the area where the error value exceeds the warning threshold) is not less than 95%. After starting the geometric optimization algorithm for the maximum coverage position of the ellipse plane, the parameters are initialized first: the initial position of the ellipse center is determined by comprehensively considering the geometric center of the error distribution area and the cluster center of the high error density area to ensure that the initial position is close to the core error area. The initial direction of the major axis is parallel to the main direction of error propagation and is extracted by the dynamic error space distribution model. The direction of the minor axis is perpendicular to the major axis. The initial length is set according to the ratio of the major axis to the minor axis of the error distribution area. The initial value of the eccentricity is adapted according to the flatness of the error distribution.

[0049] The algorithm proceeds through a process of parameter priority adjustment, precise coverage calculation, double threshold verification, and iterative optimization: parameter adjustment is prioritized based on center position, major / minor axis direction, and eccentricity. First, the center position is shifted to approximate high error density regions; then, the axis direction is adjusted to adapt to the error propagation trajectory; finally, the eccentricity is fine-tuned to optimize the coverage range. During coverage calculation, not only is the overlapping area between the ellipse and the error distribution region calculated, but the effective coverage ratio is also calculated using error density weights to ensure that high error regions are covered first. Simultaneously, it verifies whether the compensation range corresponding to the ellipse parameters is within the effective operating range of the hardware compensation unit. Within the specified interval, the parameters are checked to ensure they do not exceed the physical layout boundaries of the computational pipeline, thus preventing parameters from becoming unfeasible. After each iteration, the effective coverage ratio is compared with a preset threshold. If the threshold is not met, parameters are adjusted according to priority. If the threshold is met, parameters are further fine-tuned to improve the coverage accuracy in high-error areas. When the effective coverage ratio stably meets the threshold constraint and the parameter change is less than the preset threshold for three consecutive iterations, the iteration stops, and the final ellipse parameter set is locked. This set contains the precise three-dimensional coordinates of the ellipse center, the specific orientation angles of the major and minor axes, and the precise value of the eccentricity, providing accurate geometric basis for subsequent compensation vector calculation.

[0050] Step 4.5: Based on the ellipse parameter set, calculate the real-time error compensation vector used for directional and quantitative compensation of errors at each precision critical path node in the vector space, and bind it to the corresponding computation pipeline and computation cycle. Specifically, this includes: based on the final ellipse parameter set and the base point coordinates of each precision critical path node in the error distribution space, initiate the hierarchical calculation process of the real-time error compensation vector: first, combine the error propagation path extracted by the dynamic error spatial distribution model to correct the spatial vector difference between the node base point and the ellipse center, so that the compensation vector direction not only points to the ellipse center, but also cancels the error propagation trend; then, allocate amplitude weights according to error type, where the instantaneous numerical error weight is set to 0.6 to ensure immediate error correction, the cumulative error trend weight is set to 0.3 to suppress error accumulation, and the error fluctuation spectrum feature weight is set to 0.1 to specifically eliminate periodic errors. The amplitude of the compensation vector is determined by weighted calculation, specifically: compensation vector amplitude = (instantaneous numerical error × 0.6) + (cumulative error trend quantization value × 0.3) + (error fluctuation spectrum feature quantization value × 0.1), thereby achieving accurate matching compensation for different types of errors.

[0051] After the calculation is completed, a hierarchical validity verification is performed: for high-priority node errors, the effect of applying compensation vectors under the maximum error scenario is simulated to ensure that the error is reduced to within the error control benchmark after compensation; for ordinary node errors, it is verified that the application of compensation vectors will not introduce new timing deviations; after the verification is passed, a four-dimensional unique binding mechanism of compensation vectors, pipelines, cycles, and nodes is established, and a unique identifier is added to each compensation vector, which includes the physical number of the target computation pipeline, the timing stamp of the corresponding computation cycle, the unique ID of the associated node, and the error type mark, to ensure that the vector ownership is clear and traceable; finally, the bound compensation vectors are stored in a dedicated high-speed cache according to the computation pipeline. The cache adopts a periodic rolling update + priority sorting storage strategy, and expired compensation vectors are cleaned up in real time. Compensation vectors of high-priority nodes are stored in the high-speed access area first, and a two-level index mechanism based on pipeline and cycle is established to ensure that the corresponding compensation vector can be quickly and accurately retrieved in subsequent computation cycles, avoiding mismatch or delay, and ensuring the real-time performance and accuracy of error compensation.

[0052] In a preferred embodiment of the present invention, step 5 above may include: Step 5.1 involves receiving the real-time error compensation vector bound to the current computing pipeline and computing cycle. Specifically, this includes: first, determining the scope of the receiving object, and only receiving real-time error compensation vectors labeled with the current computing pipeline identifier and the current computing cycle number. Invalid vectors from other pipelines or expired cycles are filtered out through dual verification using the pipeline physical number and cycle time stamp. During the receiving process, vector data is received frame by frame according to the set transmission protocol, and the receiving timing of each frame is recorded synchronously to ensure that the received data matches the computation progress of the current computing cycle. After receiving, integrity and validity checks are performed to verify whether the vector contains core information such as compensation components, compensation phase, and associated node identifiers. Simultaneously, the data format is checked to ensure it meets the parsing requirements of the lightweight error monitoring unit. If there is missing information, format errors, or data corruption, a compensation vector retransmission request is immediately triggered until a complete and valid real-time error compensation vector is obtained, ultimately forming a compensation vector set that precisely matches the current computing scenario.

[0053] Step 5.2: Analyze the real-time error compensation vector, extracting the compensation components for each precision critical path node and their corresponding compensation phases. Specifically, this includes: initiating a refined, structured analysis process for the real-time error compensation vector; first, using the unique identifier of the associated node as the core index, splitting the overall data of each compensation vector, accurately extracting the compensation components corresponding to each precision critical path node, and simultaneously analyzing the core attributes of the compensation components, including compensation amplitude, direction of action (positive cancellation or reverse correction), and compensation type (amplitude compensation or phase compensation), ensuring no mismatch between the compensation components and the target nodes; then, focusing on analyzing the compensation phase information, combined with the global time of the FPGA computational pipeline... The clock tick quantifies phase information into specific clock cycle positions, confirming the precise timing for injecting compensation components. For example, the second clock tick after node data reading is completed, the first clock tick when the core arithmetic unit performs operations, and the last clock tick before latching the operation results. Simultaneously, it analyzes the trigger signal conditions corresponding to the phase, such as the data validity signal going high and the arithmetic unit readiness signal being valid, ensuring seamless integration between the injection timing and the node's operational flow. After analysis, a complete association lookup table is generated, containing the node's unique identifier, compensation component amplitude, compensation direction, compensation type, compensation phase (clock cycle), and timing trigger signals. The lookup table is sorted according to the data flow order of the node in the pipeline.

[0054] Step 5.3: Based on the extracted compensation phase, inject each compensation component into the lightweight error monitoring unit at the corresponding precision critical path node. Specifically, this includes: according to the correlation lookup table, first capturing the real-time computation timing status of each precision critical path node in the current computation pipeline; precisely aligning the compensation phase (quantized clock cycle) of each node with the clock tick of the actual computation timing; marking the specific injection time of each compensation component; and then, through a dedicated low-latency, high-bandwidth data channel, transmitting the compensation components corresponding to each node to the lightweight error monitoring unit of the target node. During transmission, a signal integrity verification mechanism is enabled in real-time. The amplitude and timing of the transmitted signal are monitored to avoid signal distortion or packet loss during transmission. Before injecting the compensation component, the working status of the lightweight error monitoring unit is further verified: the unit's buffer idle status, the validity of the signal reception enable signal, and the smoothness of the signal link with the node operation unit are checked. After confirming that the status is normal, the timing trigger signal is waited for, and the compensation component is written into the dedicated buffer area of ​​the monitoring unit at the marked injection time. After the injection is completed, the monitoring unit immediately sends back an acknowledgment signal containing the value of the compensation component. The receiving end checks the consistency between the feedback value and the parsing result to ensure that there is no injection error. Finally, the accurate and timely injection of all compensation components is completed.

[0055] Step 5.4: In the lightweight error monitoring unit, the intermediate results flowing through this node are superimposed or iteratively corrected based on the injected compensation component. Specifically, this includes: continuously monitoring the intermediate results flowing through the corresponding precision critical path nodes in real time, synchronously tracking the timing progress of node operations, and immediately retrieving the injected compensation component from the dedicated buffer when the intermediate result reaches the clock tick corresponding to the compensation action phase and the timing trigger signal is valid; and performing targeted correction operations according to the compensation type and action direction in the correlation lookup table: for instantaneous numerical errors, a reverse superposition strategy is adopted to superimpose the compensation component with the current intermediate result in reverse to directly cancel the instantaneous error; for cumulative errors... For errors that may fluctuate periodically, an iterative correction strategy is adopted. By combining historical error data recorded by the monitoring unit with the current intermediate results, compensation components are gradually applied to suppress the error accumulation trend and avoid over-correction. During the correction process, the data bit width and format specifications of the node operation unit are strictly followed. Bit width adaptation logic is used to ensure that the bit width of the corrected intermediate results does not overflow and the format is not distorted. The intermediate result values ​​before and after correction, compensation component information, clock tick at the correction time, and error type are recorded synchronously to form a complete correction traceability entry. At the same time, the corrected values ​​are checked in real time to see if they are within the preset reasonable range. If they exceed the range, the correction is immediately paused and an alarm is triggered to ensure that the correction process is safe and effective.

[0056] Step 5.5: Synchronize all precision critical path nodes to complete the correction and output the intermediate compensated result after vectorization compensation. Specifically, this includes: constructing a synchronization coordination mechanism for node correction progress using the global clock synchronization signal of the FPGA computation pipeline; real-time acquisition of correction status feedback signals from the lightweight error monitoring units of each precision critical path node, with feedback signals containing correction completion indicators and whether the correction result is valid; summarizing and analyzing the feedback signals: if all nodes report correction completion and the result is valid, then global synchronization correction is confirmed to be complete; if some nodes have not completed correction, a synchronization waiting mechanism is initiated to wait for the correction progress of the incomplete nodes to catch up, with the waiting time not exceeding the current computation cycle. If one-third of the timeout period is exceeded, a fault alarm is triggered and the information of the incomplete node is recorded. If any node reports that the correction is invalid, a local re-correction process is immediately triggered to re-inject the corresponding compensation component and perform the correction operation. After the global synchronous correction is completed, the lightweight error monitoring unit of each node outputs the intermediate results after vectorized compensation according to the normal data flow sequence of the pipeline. Before outputting, the result format and bit width are checked again to ensure that they meet the input requirements of the downstream computing unit. At the same time, the overall status of this synchronous correction, the correction time of each node, the validity of the correction results, and whether there are alarms are recorded in detail in the pipeline operation log, providing accurate data support for the dynamic adjustment and optimization of the subsequent error compensation strategy.

[0057] In a preferred embodiment of the present invention, step 6 above may include: Step 6.1: Synchronously receive the compensated intermediate results output by all computing pipelines in the previous computing cycle according to the global computing clock. This includes: determining the receiving range and synchronization benchmark; receiving only the compensated intermediate results output by all computing pipelines in the previous computing cycle; using the global computing clock as the unified synchronization benchmark; calibrating the timing of each receiving channel through the clock signal to ensure that all receiving operations are precisely matched with the global clock tick; performing receiving operations on the output ports of each computing pipeline one by one according to the set pipeline number order; synchronously recording the corresponding pipeline identifier, the timing stamp of the previous computing cycle, and the receiving time for each set of compensated intermediate results received, ensuring that the relationship between the received data and the pipeline and computing cycle is clear and traceable; monitoring the status of the transmission link in real time during the receiving process; if a receiving delay or signal interruption occurs, immediately triggering the timing compensation mechanism to adjust the receiving timing until the synchronous reception of the compensated intermediate results of all computing pipelines is completed, ultimately forming the original received dataset containing the data of the entire pipeline and the previous cycle.

[0058] Step 6.2 involves performing timestamp alignment and data validity verification on multiple compensated intermediate results received synchronously to filter out invalid data blocks caused by transmission anomalies and generate a set of valid data blocks that have undergone alignment and verification. Specifically, this includes: using the timestamp of the previous computation cycle corresponding to the global computing clock as a reference, initiating the timestamp alignment process, extracting the built-in timestamp of each group of compensated intermediate results in the original received dataset, calibrating the timestamps of all data to the same global clock reference, and eliminating timing deviations caused by transmission delays in different pipelines; then conducting multi-dimensional data validity verification: first verifying whether the data format conforms to the preset output specifications, checking whether the bit width, encoding method, etc. are consistent with the initial configuration; then verifying data integrity, confirming that core fields are not missing and data length meets the standard; finally verifying whether there is distortion during data transmission through CRC cyclic redundancy check; determining data blocks that fail timing alignment or any validity verification as invalid data, recording their corresponding pipeline identifier and error type, and filtering them out from the original dataset; and classifying and organizing the data blocks that pass all verifications according to pipeline identifiers to generate a set of valid data blocks that have undergone timestamp alignment and validity verification.

[0059] Step 6.3: Based on the output precision format defined by each computational pipeline during the initial configuration phase, the set of valid data blocks after alignment and verification is uniformly converted to a preset highest-precision intermediate representation format. This includes: retrieving the output precision format defined by each computational pipeline during the initial configuration phase to confirm the original bit width, numerical type, and other core parameters of the intermediate results after compensation for different pipelines; determining the preset highest-precision intermediate representation format based on the output precision formats of all pipelines. This format's bit width is not lower than the maximum bit width of the original output precision of all pipelines, and the numerical type adopts a universal format compatible with all original types to ensure no precision loss during conversion; for each data block in the valid data block set, a format conversion operation is performed based on the difference between its original output precision format and the highest-precision intermediate representation format: a unified data format conversion is completed through bit width expansion, encoding adaptation, etc., strictly adhering to the principle of numerical conservation during the conversion process to avoid introducing additional errors. After conversion, the conversion result of each data block is verified to confirm that the format is correct and the numerical values ​​are not distorted, ultimately forming a standardized set of data blocks unified in the highest-precision intermediate representation format.

[0060] Step 6.4: Under the preset highest-precision intermediate representation format, a multi-source data fusion strategy is adopted to perform weighted fusion of data from different computing pipelines, generating final result data with a unified precision representation. Specifically, this includes: based on the task priority, data validity verification results, and historical data reliability scores of each computing pipeline, a multi-source data fusion strategy is formulated, assigning differentiated weights to standardized data blocks corresponding to different pipelines. Data from pipelines with high task priority, excellent verification results, and high historical reliability are assigned higher weights. A weighted fusion operation is then performed on the multi-source data in the standardized data block set according to this fusion strategy: first, the values ​​of each data block are adjusted according to their corresponding weights; then, all adjusted data undergoes collaborative overlay processing. During the overlay process, the rationality of the data values ​​is monitored synchronously to avoid numerical overflow or abnormal fluctuations. After fusion, the result data is ensured to maintain the preset highest-precision intermediate representation format. The fusion result is validated to confirm that the result values ​​are within a reasonable computational range. Finally, final result data with a unified precision representation is generated and associated with the corresponding computing cycle and the pipeline identifiers participating in the fusion.

[0061] Step 6.5 involves statistically analyzing the final result data and extracting quantitative indicators, including the overall error distribution variance, the maximum residual error value, and the error convergence trend, as the accuracy evaluation features. Specifically, this includes: conducting a systematic statistical analysis of the generated final result data; first, extracting the deviation information between the final result data and the theoretical standard value; calculating the overall error distribution variance based on this deviation information to quantify the dispersion of errors at all data points; traversing all deviation data and selecting the deviation value with the largest absolute value as the maximum residual error value; retrieving the final result error data from the previous calculation cycle and multiple historical calculation cycles, comparing the error change trends of different cycles, and extracting the error convergence trend. If the error in the current cycle gradually decreases compared to historical cycles, it is determined to be in a convergent state; otherwise, it is in a non-convergent state; organizing the calculated overall error distribution variance, maximum residual error value, and error convergence trend into a set of quantitative indicators, clearly marking the calculation cycle corresponding to each indicator and the identifier of the computational pipeline involved in the calculation; storing this set of quantitative indicators as the accuracy evaluation features in the cache area to provide data support for adjusting the accuracy optimization strategy in subsequent calculation cycles.

[0062] In a preferred embodiment of the present invention, step 7 above may include: Step 7.1: Summarize the accuracy assessment features generated in the current computation cycle and retrieve the historical sequences of the associated dynamic error spatial distribution models. Specifically, this includes: first, extracting the accuracy assessment features generated in the current computation cycle from the feature storage module. These features include quantitative indicators such as the overall error distribution variance, the maximum residual error value, and the error convergence trend. Simultaneously, associate the identifiers of each computation pipeline currently participating in the computation with the computation cycle number to complete the summary and organization of feature information. Then, initiate the historical sequence retrieval process. Using the identifiers of each computation pipeline as the retrieval index and the current computation cycle as the time base, retrieve the associated dynamic error spatial distribution model data from the most recent consecutive computation cycles, such as the last 20 cycles, forming a historical sequence set containing the error distribution status and propagation trends of different cycles. During the retrieval process, verify the completeness and temporal continuity of the historical data, supplement missing historical data fragments, and ensure that the retrieved historical sequences can fully reflect the temporal evolution trajectory of the error spatial distribution. Finally, form an associated dataset of the current accuracy assessment features and the historical error distribution sequences of each pipeline.

[0063] Step 7.2: Based on the retrieved historical sequence analysis, analyze the evolution trend of error spatial distribution. Combined with accuracy assessment characteristics, evaluate the actual performance of the current computing pipeline configuration. Specifically, this includes: based on the retrieved historical sequence set, conduct error spatial distribution evolution trend analysis. By comparing the core characteristics of error distribution in different computing cycles, such as changes in the location of error concentration areas, shifts in propagation paths, and increases or decreases in error amplitude, extract the long-term evolution law of error distribution and determine whether the overall error is converging, diverging, or in a stable fluctuation state; combined with the accuracy assessment characteristics of the current computing cycle, evaluate the actual performance of each computing pipeline configuration from multiple dimensions: one The evaluation criteria are as follows: First, accuracy compliance performance, which involves verifying whether the maximum residual error value is controlled within the allowable range and whether the error distribution variance is within a reasonable range; second, resource utilization performance, which involves correlating the computational bit width configuration of each pipeline and analyzing the matching degree between resource consumption and accuracy output under the current bit width; and third, error control performance, which involves assessing the ability of the existing configuration to suppress errors in conjunction with the error convergence trend. The performance evaluation criteria are refined for different application scenarios. For example, in industrial control scenarios, the focus is on evaluating accuracy compliance performance under low latency, while in AI inference scenarios, the focus is on evaluating the synergistic performance of resource utilization and error control under high parallelism. Finally, a quantitative evaluation report on the actual performance of each computing pipeline configuration is generated.

[0064] Step 7.3 compares the evaluated actual performance with the target performance set in the expected accuracy configuration recommendation to generate configuration adjustment decision vectors for each computing pipeline. Specifically, this includes: retrieving the target performance indicators for each computing pipeline set in the expected accuracy configuration recommendation; confirming core target parameters such as accuracy achievement thresholds, resource consumption limits, error convergence requirements, and hardware adaptation constraints under different scenarios; then conducting a detailed comparison between the generated actual performance evaluation report and the corresponding pipeline's target performance indicators; determining the differences in accuracy achievement, resource utilization efficiency, and error control effectiveness across three core dimensions; and identifying the performance shortcomings and overperformance of each pipeline. For redundant configuration items that meet the target, pipelines with substandard accuracy and diverging error trends generate positive adjustment decisions to improve core configuration parameters. For pipelines with excessive resource usage and excessive accuracy, moderate adjustment decisions to optimize resource allocation are generated. For pipelines whose performance perfectly matches the target, stable decisions to maintain the existing configuration are generated. Then, key information such as the adjustment direction, adjustment range, priority level, hardware constraints, and effective timing of each pipeline is structured and integrated to generate a configuration adjustment decision vector with complete execution basis for each pipeline. This ensures that each decision is supported by corresponding performance comparison data and fully complies with the operating limitations of FPGA hardware.

[0065] The configuration adjustment decision vector is a structured set of control instructions, encapsulated in a vectorized data format. Its content includes at least: target pipeline identifier, configuration category to be adjusted (such as computation bit width, monitoring dimension or sampling strategy, etc.), corresponding adjustment parameter value, execution priority and effective timing. This vector is sent to the corresponding computing pipeline through the internal configuration channel, driving its hardware logic to complete the parameter reconfiguration, thereby realizing closed-loop feedback for accuracy optimization.

[0066] Step 7.4: Adjust the decision vector according to the configuration, dynamically reconfigure the computational bit width of each computing pipeline, and update the error monitoring dimension and sampling triggering strategy of the precision critical path node to generate an updated configuration strategy. Specifically, this includes: adjusting the decision vector according to the generated configuration, initiating the dynamic reconfiguration of each computing pipeline in stages; the first stage involves dynamically adjusting the computational bit width, first verifying whether the hardware resource usage corresponding to the target bit width is within the available margin of the FPGA logic unit and memory unit based on the adjustment magnitude in the decision vector, then pausing non-core auxiliary operations of the pipeline, keeping the core data cache state unchanged, and completing the bit width parameter rewriting of the computing unit in a step-by-step fine-tuning manner; immediately after adjustment, performing a bit width adaptability self-check to confirm that there are no timing errors or data overflow issues in the computation process; the second stage involves updating the error monitoring dimension of the precision critical path node, combined with the effect... The assessment identifies shortcomings in error control and allows for the addition or removal of existing monitoring items. For example, a new dimension for monitoring error fluctuation amplitude can be added to nodes where error fluctuations intensify, and redundant monitoring items without actual error feedback can be removed. Simultaneously, the execution order and data acquisition requirements for each monitoring dimension are redefined. The third stage optimizes the sampling triggering strategy by adjusting the period of timed sampling, the trigger threshold for error mutations, and the judgment conditions for exceeding sampling limits, based on the instructions of the decision vector. This ensures that the sampling frequency and triggering rules adapt to the error change rhythm of the current pipeline. After all adjustments are verified, the new computational bit width parameters for each pipeline, the updated error monitoring dimension system, and the optimized sampling triggering strategy are uniformly encapsulated to form an updated configuration strategy adapted to the characteristics of each pipeline. The corresponding computation cycle and applicable scenarios are also labeled to ensure the relevance and executability of the configuration strategy.

[0067] Step 7.5 synchronizes the updated configuration policy to the corresponding computing pipeline and its precision critical path nodes, completing the closed-loop feedback adjustment. Specifically, this includes: distributing the updated configuration policy according to pipeline identifiers; enabling data verification and packet loss retransmission mechanisms during transmission to ensure that the configuration information is delivered completely and accurately to the target computing pipeline and its associated precision critical path nodes; after obtaining the configuration policy, each receiving end first parses the parameters in the policy, then performs local parameter adaptation verification; after confirming that the new configuration does not conflict with the current node's hardware status and computational flow, it gradually completes the writing and updating of internal parameters; and after the update is complete, it feeds back to the system including the node identifier. The system sends confirmation messages for updated items and their effective status, and summarizes feedback messages from all receiving ends in real time. For nodes that fail to update, the system locates the cause of failure and re-initiates the configuration push until all target pipelines and precision critical path nodes have completed configuration updates and reported successful effectiveness. Finally, the system records the performance comparison basis, decision vector content, various adjustment parameters, update status of each node, and adjustment time in the configuration closed-loop management log. At the same time, the updated configuration policy is synchronously archived to the initial configuration storage module, replacing the original configuration information, thus realizing a complete precision optimization closed-loop feedback from performance evaluation to configuration adjustment to policy implementation.

[0068] like Figure 2 As shown, embodiments of the present invention also provide an FPGA-based computational data precision optimization processing system, including: The dynamic prediction and preprocessing module is used to load the acquired raw numerical calculation data into the accuracy requirement dynamic prediction model for analysis and generate a data accuracy feature profile; based on the data accuracy feature profile, adaptive preprocessing and initial accuracy repair are performed to generate preprocessed data and corresponding expected accuracy configuration suggestions. The pipeline dynamic allocation module is used to allocate preprocessed data to multiple parallel computing pipelines in the FPGA based on the expected accuracy configuration suggestions. The error feature tensor acquisition module is used to dynamically acquire error feature tensors at multiple predefined precision critical path nodes during the computation process of each computation pipeline; the precision critical path nodes include at least the output port of the pipeline register group, the conversion interface for data of different precision formats, and the read data port of the cross-clock domain synchronous FIFO. The dynamic error compensation module is used to construct a dynamic error spatial distribution model based on multiple error feature tensors collected by each computing pipeline within the same computing cycle; it analyzes the dynamic error spatial distribution model based on the geometric optimization algorithm of the maximum coverage position of the elliptical plane and generates a real-time error compensation vector corresponding to the current computing cycle; and it uses the real-time error compensation vector to compensate the intermediate results in the corresponding computing pipeline in real time and generate compensated intermediate results. The data fusion and accuracy assessment module is used to aggregate the compensated intermediate results from all computational pipelines, perform data fusion and accuracy format unification, generate final result data, and extract accuracy assessment features from the final result data. The closed-loop feedback optimization module is used to adjust the computational bit width of each computational pipeline and the configuration strategy of the precision critical path nodes based on the historical sequence of the accuracy evaluation characteristics and the dynamic error spatial distribution model, combined with the expected accuracy configuration suggestions.

[0069] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for optimizing computational data accuracy based on FPGA, characterized in that, The method includes: The acquired raw numerical calculation data is loaded into the accuracy requirement dynamic prediction model for analysis to generate a data accuracy feature profile; based on the data accuracy feature profile, adaptive preprocessing and initial accuracy repair are performed to generate preprocessed data and corresponding expected accuracy configuration suggestions. Based on the expected accuracy configuration recommendations, the preprocessed data is distributed to multiple parallel computing pipelines in the FPGA; During the computation process of each computation pipeline, error feature tensors are dynamically acquired at multiple predefined precision critical path nodes; the precision critical path nodes include at least the output port of the pipeline register group, the conversion interface for data of different precision formats, and the read data port of the cross-clock domain synchronous FIFO; A dynamic error spatial distribution model is constructed based on multiple error feature tensors collected by each computing pipeline within the same computing cycle; the dynamic error spatial distribution model is analyzed to generate a real-time error compensation vector corresponding to the current computing cycle. The intermediate results in the corresponding computation pipeline are compensated in real time by using a real-time error compensation vector to generate compensated intermediate results. The system aggregates the compensated intermediate results from all computational pipelines, performs data fusion and standardizes the accuracy format, generates the final result data, and extracts the accuracy evaluation features of the final result data. Based on the historical sequence of accuracy assessment characteristics and dynamic error spatial distribution model, and combined with the expected accuracy configuration suggestions, feedback is provided to adjust the computational bit width of each computing pipeline and the configuration strategy of the accuracy critical path nodes.

2. The FPGA-based computational data precision optimization processing method according to claim 1, characterized in that, The acquired raw numerical calculation data is loaded into the accuracy requirement dynamic prediction model for analysis to generate a data accuracy feature profile. Adaptive preprocessing and initial precision repair are performed based on data precision feature profiles to generate preprocessed data and corresponding expected precision configuration suggestions, including: The acquired raw numerical calculation data is loaded into the accuracy requirement dynamic prediction model; The original numerical calculation data is analyzed in multiple dimensions using a dynamic prediction model for accuracy requirements, and a structured profile of data accuracy features is output. Based on the dynamic range and sensitive dimension information included in the data precision feature profile of the structured representation, the filtering parameters and numerical scaling coefficients required for preprocessing are adapted and determined. Using the aforementioned filtering parameters and numerical scaling coefficients, adaptive filtering and scaling transformation are performed on the original numerical calculation data to complete the initial accuracy repair and generate preprocessed data. Based on the preprocessed data generated after initial accuracy repair, and according to the noise distribution characteristics and sparsity index contained in the data accuracy feature profile of the structured representation, expected accuracy configuration suggestions are generated to guide the initial configuration of the computational pipeline.

3. The FPGA-based computational data precision optimization processing method according to claim 2, characterized in that, Based on the expected accuracy configuration recommendations, the preprocessed data is distributed to multiple parallel computation pipelines within the FPGA, including: The expected precision configuration suggestion is analyzed, and the computation task type identifier, the required bit width range of each data block, and the priority instructions are extracted. Based on the extracted computation task type identifier, a predefined computation pipeline template library in the FPGA hardware resources is matched to filter out a set of candidate computation pipelines that are compatible with the task type. By combining the range of arithmetic bit widths and priority instructions, the current resource consumption and throughput of each computation pipeline in the candidate computation pipeline set are evaluated to determine the target computation pipeline for each preprocessed data block; Based on the precise computing unit characteristics and storage interface bit width supported by the determined target computing pipeline, the preprocessed data blocks are formatted and address mapped to generate pipeline-ready data packets. Pipeline-ready data packets are scheduled and distributed to the corresponding target computing pipelines according to priority instructions to complete data allocation.

4. The FPGA-based computational data precision optimization processing method according to claim 3, characterized in that, During the computation process of each computation pipeline, error feature tensors are dynamically acquired at multiple predefined precision critical path nodes; The precision-critical path node includes at least the output port of the pipeline register set, the conversion interface for data in different precision formats, and the read data port of the cross-clock domain synchronous FIFO, including: The expected accuracy configuration recommendations and the hardware architecture characteristics of the target computing pipeline are dynamically analyzed, and error monitoring dimensions and adaptive sampling triggering strategies are generated for each accuracy critical path node. Based on the generated error monitoring dimensions, corresponding lightweight error monitoring units are inserted at the output port of the pipeline register group, the conversion interface of data with different precision formats, and the read data port of the cross-clock domain synchronous FIFO. Under the control of the adaptive sampling triggering strategy, the instantaneous numerical error, cumulative error trend and error fluctuation spectrum information of each precision critical path node are collected synchronously through the error monitoring unit. The instantaneous numerical error, cumulative error trend, and error fluctuation spectrum information collected from multiple precision critical path nodes within the same calculation cycle are aligned and integrated in the time and space dimensions, and encapsulated into a structured error feature tensor.

5. The FPGA-based computational data accuracy optimization processing method according to claim 4, characterized in that, A dynamic error spatial distribution model is constructed based on multiple error feature tensors collected by each computing pipeline within the same computing cycle. Based on the geometric optimization algorithm for the maximum coverage position of the elliptical plane, the dynamic error spatial distribution model is analyzed, and a real-time error compensation vector corresponding to the current calculation cycle is generated, including: Receive multiple structured error feature tensors uploaded from multiple precision critical path nodes of a computing pipeline within the same computing cycle; We analyze the error space coordinates and multi-dimensional error information contained in each structured error feature tensor, and map the multi-dimensional error information to the error distribution space with each precision critical path node as the base point; Based on the error space coordinates and the mapped multi-dimensional error information, a dynamic error space distribution model representing the spatial propagation of error within the computational pipeline is fitted and generated in the error distribution space. Using the error distribution geometry defined by the dynamic error spatial distribution model as the optimization object, the geometric optimization algorithm for the maximum coverage position of the elliptical plane is driven to solve the problem, and the elliptical parameter set that satisfies the preset coverage threshold constraint is obtained. The elliptical parameter set includes the ellipse center, the direction of the major axis and the minor axis, and the eccentricity. Based on the ellipse parameter set, a real-time error compensation vector is calculated to provide directional and quantitative compensation for errors at critical path nodes of various precisions in the vector space, and then bound to the corresponding computational pipeline and computation cycle.

6. The FPGA-based computational data accuracy optimization processing method according to claim 5, characterized in that, By using a real-time error compensation vector, intermediate results within the corresponding computational pipeline are compensated in real time, generating compensated intermediate results, including: Receive the real-time error compensation vector that is bound to the current computing pipeline and computing cycle; Analyze the real-time error compensation vector and extract the compensation components for each precision critical path node and their corresponding compensation phases. Based on the extracted compensation phase, each compensation component is injected into the lightweight error monitoring unit at the corresponding accuracy critical path node. In the lightweight error monitoring unit, the intermediate results flowing through this node are superimposed or iteratively corrected based on the injected compensation component. All precision-critical path nodes are synchronized and corrected, and the intermediate results after vectorization compensation are output.

7. The FPGA-based computational data precision optimization processing method according to claim 6, characterized in that, The system aggregates all compensated intermediate results from the computational pipeline, performs data fusion and standardizes the accuracy format, generates the final result data, and extracts the accuracy evaluation features of the final result data, including: Receive the compensated intermediate results output by all computing pipelines in the previous computing cycle in a synchronized manner according to the global computing clock; For multiple compensated intermediate results received synchronously, timestamp alignment and data validity verification are performed to filter out invalid data blocks caused by transmission anomalies and generate a set of valid data blocks that have been aligned and verified. Based on the output precision format defined by each computing pipeline during the initial configuration phase, the set of valid data blocks that have been aligned and verified is uniformly converted to the preset highest precision intermediate representation format. Under the preset highest precision intermediate representation format, a multi-source data fusion strategy is adopted to weight and fuse data from different computing pipelines to generate final result data with uniform precision representation; Statistical analysis is performed on the final result data to extract quantitative indicators, including the overall error distribution variance, the maximum residual error value, and the error convergence trend, as the accuracy evaluation features.

8. The FPGA-based computational data accuracy optimization processing method according to claim 7, characterized in that, Based on the historical sequence of accuracy assessment characteristics and dynamic error spatial distribution model, and combined with expected accuracy configuration suggestions, feedback is provided to adjust the computational bit width of each computational pipeline and the configuration strategy of the accuracy-critical path nodes, including: Summarize the accuracy assessment features generated in the current calculation cycle and retrieve the historical sequence of the associated dynamic error spatial distribution model; Based on the historical sequence analysis of the retrieval, the evolution trend of the spatial distribution of errors is analyzed, and combined with the accuracy evaluation characteristics, the actual performance of the current computing pipeline configuration is evaluated. The actual performance evaluated is compared with the target performance set in the expected accuracy configuration recommendation to generate configuration adjustment decision vectors for each computing pipeline. The decision vector is adjusted according to the configuration, the computational bit width of each computation pipeline is dynamically reconfigured, and the error monitoring dimension and sampling triggering strategy of the precision critical path node are updated to generate an updated configuration strategy. The updated configuration strategy is synchronized to the corresponding computing pipeline and its accuracy-critical path nodes to complete the closed-loop feedback adjustment.

9. An FPGA-based computational data precision optimization processing system, which implements the method as described in any one of claims 1 to 8, characterized in that, include: The dynamic prediction and preprocessing module is used to load the acquired raw numerical calculation data into the accuracy requirement dynamic prediction model for analysis and generate data accuracy feature profiles. Adaptive preprocessing and initial accuracy repair are performed based on data accuracy feature profiles to generate preprocessed data and corresponding expected accuracy configuration suggestions. The pipeline dynamic allocation module is used to allocate preprocessed data to multiple parallel computing pipelines in the FPGA based on the expected accuracy configuration suggestions. The error feature tensor acquisition module is used to dynamically acquire error feature tensors at multiple predefined precision critical path nodes during the computation process of each computation pipeline; the precision critical path nodes include at least the output port of the pipeline register group, the conversion interface for data of different precision formats, and the read data port of the cross-clock domain synchronous FIFO. The dynamic error compensation module is used to construct a dynamic error spatial distribution model based on multiple error feature tensors collected by each computing pipeline within the same computing cycle. Based on the geometric optimization algorithm for the maximum coverage position of the elliptical plane, the dynamic error spatial distribution model is analyzed to generate a real-time error compensation vector corresponding to the current calculation cycle. The real-time error compensation vector is used to compensate the intermediate results in the corresponding calculation pipeline in real time to generate compensated intermediate results. The data fusion and accuracy assessment module is used to aggregate the compensated intermediate results from all computational pipelines, perform data fusion and accuracy format unification, generate final result data, and extract accuracy assessment features from the final result data. The closed-loop feedback optimization module is used to adjust the computational bit width of each computational pipeline and the configuration strategy of the precision critical path nodes based on the historical sequence of the accuracy evaluation characteristics and the dynamic error spatial distribution model, combined with the expected accuracy configuration suggestions.

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