Real-time waveform feature vector extraction method and system for semiconductor testing

Abstract

The application discloses a real-time waveform feature vector extraction method and system for semiconductor testing, and belongs to the technical field of semiconductor chip testing.The stream feature extraction engine and the feature vector packaging module are arranged in the on-board processing unit of the ATE board card, the stream feature extraction engine performs real-time analysis on the original waveform data stream in a real-time stream processing mode, at least one signal integrity feature parameter is extracted, and the feature vector packaging module packages the extracted signal integrity feature parameter into a structured feature vector.In the default mode, only the structured feature vector needs to be uploaded, and when the backtracking condition is triggered, the compressed original waveform data stream is uploaded through the host computer interface module.The original waveform data stream is processed in real time on the ATE board card, and the structured feature vector is selectively uploaded, so that the original data transmission amount is significantly reduced, the bandwidth occupation is reduced, the test time is shortened, and the test efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip testing technology, and in particular to a method and system for real-time waveform feature vector extraction for semiconductor testing. Background Technology

[0002] As the complexity and integration of integrated circuits continue to increase, the performance requirements of automated test equipment (ATE) for semiconductor chip testing are becoming increasingly stringent. ATE systems need to process signals with higher sampling rates, higher precision, and longer sampling durations during testing, leading to an explosive growth in the amount of raw waveform data. In scenarios involving parallel testing of multiple devices under test, the data scale is particularly enormous, placing significant pressure on the testing process.

[0003] The current industry standard testing architecture relies on ATE boards to transmit the collected raw waveform data to a host computer for centralized analysis. This architecture has a fundamental flaw: the transmission of massive amounts of raw data severely consumes network bandwidth resources, resulting in a significant increase in data transmission latency and directly impacting testing cycle efficiency. Simultaneously, the host computer bears a huge data storage burden and consumes additional computing resources to perform subsequent analysis tasks, not only increasing system hardware costs but also further exacerbating testing time overhead due to the lengthy processing flow.

[0004] The aforementioned problems make it difficult for testing efficiency to meet the urgent needs of the modern semiconductor industry for high-speed, low-cost testing. Summary of the Invention

[0005] The purpose of this invention is to provide a real-time waveform feature vector extraction method and system for semiconductor testing, so as to solve the problems of bandwidth bottleneck, high latency and high cost caused by transmitting massive amounts of raw waveform data in the prior art.

[0006] To achieve the above objectives, this invention proposes a real-time waveform feature vector extraction method for semiconductor testing, comprising the following steps: Configuration steps: Configure a streaming feature extraction engine in the onboard processing unit of the ATE board to receive the raw waveform data stream acquired by the analog-to-digital converter in the ATE board; Streaming acquisition and extraction steps: Perform real-time streaming processing on the original waveform data stream and calculate at least one signal integrity feature parameter; Feature vector generation step: Encapsulate the extracted signal integrity feature parameters into a structured feature vector; Selective upload step: Automatic testing and judgment are performed based on the structured feature vector. In the default mode, only the structured feature vector is uploaded to the host computer. If the preset backtracking conditions are met, the system switches to backtracking mode and uploads the original waveform data stream after compression.

[0007] As a further aspect of the present invention: in the streaming acquisition and extraction step, the streaming processing adopts a sliding window or point-by-point processing method, and nanosecond-level latency is achieved in the onboard processing unit through fixed-point number arithmetic and hardware logic multiplexing.

[0008] As a further aspect of the present invention, the structured feature vector is further supplemented with a timestamp, sampling configuration information, and integrity check code.

[0009] As a further aspect of the present invention: in the selective upload step, the backtracking condition is that a certain parameter in the structured feature vector exceeds a preset threshold, or a backtracking instruction is received from the host computer.

[0010] As a further aspect of the present invention, the signal integrity feature parameters include one or more of the following: basic statistics, time-domain features, high-speed serial signal features, and abnormal event flags.

[0011] This invention also proposes a real-time waveform feature vector extraction system for semiconductor testing, comprising: The host computer is used to send out test configuration parameters, receive structured feature vectors, and make test judgments. ATE board, which integrates onboard processing unit and analog-to-digital converter; The streaming feature extraction engine, feature vector encapsulation module, and host computer interface module are deployed in the onboard processing unit. The streaming feature extraction engine is used to perform real-time analysis on the raw waveform data stream output by the analog-to-digital converter and extract at least one signal integrity feature parameter. The feature vector encapsulation module is used to encapsulate the extracted signal integrity feature parameters into structured feature vectors; The host computer interface module is used to upload the structured feature vector or the compressed original waveform data stream to the host computer.

[0012] As a further aspect of the present invention: the streaming feature extraction engine includes a parallel basic statistics unit, a time-domain feature unit, a high-speed serial signal feature unit, and an abnormal event flag unit, which are used to calculate the basic statistics, time-domain features, high-speed serial signal features, and abnormal event flags, respectively.

[0013] As a further aspect of the present invention, the onboard processing unit is also equipped with a trigger and condition judgment module, which is used to monitor whether the feature value exceeds the preset threshold, or to receive instructions from the host computer to determine whether to start the original waveform data stream backtracking mode.

[0014] As a further aspect of the present invention, the onboard processing unit is a dedicated processor or a programmable logic device.

[0015] As a further aspect of the present invention: the host computer interface module includes independent feature channels and raw data channels, which are used to transmit structured feature vectors and compressed raw waveform data streams, respectively.

[0016] The present invention has at least the following beneficial effects: This invention deploys a streaming feature extraction engine and a feature vector encapsulation module within the onboard processing unit of an ATE board. It receives the raw waveform data stream acquired by the analog-to-digital converter in the ATE board. The streaming feature extraction engine performs real-time streaming analysis on the raw waveform data stream, extracting at least one signal integrity feature parameter. The feature vector encapsulation module encapsulates the extracted signal integrity feature parameter into a structured feature vector. In default mode, only the structured feature vector needs to be uploaded. Only when a backtracking condition is triggered is the compressed raw waveform data stream uploaded through the host computer interface module. This invention significantly reduces the amount of raw data transmission by processing the raw waveform data stream in real-time on the ATE board and selectively uploading structured feature vectors, thereby reducing bandwidth usage, shortening test time, and improving test efficiency.

[0017] This invention effectively alleviates the bandwidth bottleneck problem in ATE testing, reducing data transmission volume in typical scenarios by at least two orders of magnitude. Simultaneously, the onboard processing unit employs a programmable logic controller or an embedded multi-core processor for hardware acceleration, ensuring nanosecond-level processing latency and meeting high-speed testing requirements. This design not only reduces the storage and computing resource consumption of the host computer but also simplifies the testing and judgment process through standardized encapsulation of structured feature vectors, thereby improving the overall efficiency and economy of semiconductor chip testing. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall architecture of the system in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the process of the method in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] As mentioned in the background section, in an automated testing scenario for semiconductor chips, signal integrity testing of high-speed serial interface chips is required. The traditional testing method involves the analog-to-digital converter (ADC) of an automated test equipment (ATE) acquiring the raw waveform data output by the chip at extremely high sampling rates and precision. This data volume is enormous; for example, a single test may generate several gigabytes of raw waveform data. Subsequently, this massive amount of raw waveform data is transmitted via a network interface to a host computer for analysis, such as generating eye diagrams and calculating signal integrity parameters like jitter, overshoot, and undershoot. This transmission method leads to severe bandwidth bottlenecks and transmission delays, and the host computer also needs to invest significant storage and computing resources in data processing, thereby extending the testing cycle and increasing testing costs.

[0021] Example 1 Based on this, such as Figure 1 As shown in the figure, this embodiment discloses a real-time waveform feature vector extraction system for semiconductor testing, which mainly includes a host computer, an ATE board, an analog-to-digital converter, an onboard processing unit, a streaming feature extraction engine, a feature vector encapsulation module, and a host computer interface module.

[0022] The host computer refers to the computer system that communicates with and controls the ATE board, typically a PC or workstation. The host computer is responsible for issuing test configuration parameters, receiving structured feature vectors and performing test judgments, data analysis, and user interaction.

[0023] An ATE board is the core hardware module in an automated test equipment. It is responsible for making electrical connections with the device under test (such as a semiconductor chip) and performing signal excitation and acquisition. ATE boards integrate high-speed analog-to-digital converters and digital signal processing capabilities, serving as the fundamental platform for implementing test functions.

[0024] An analog-to-digital converter (ADC) is an electronic device that converts analog signals into digital signals. In an ATE (Automatic Test Equipment) board, the ADC is used to convert analog waveform signals acquired from the device under test (DUT) into a raw digital waveform data stream for subsequent digital processing. The raw waveform data stream is a continuous sequence of unprocessed digital waveform data output by the ADC. This raw waveform data stream contains complete time-domain response information of the DUT during the testing process.

[0025] An onboard processing unit (ATU) refers to a dedicated processor or programmable logic device integrated on an ATE board. Examples include embedded multi-core processors and field-programmable gate arrays (FPGAs). The APU is responsible for performing data processing, algorithm calculations, and control logic locally to reduce the computational burden on the host computer and lower data transmission requirements.

[0026] A streaming feature extraction engine refers to a software module or hardware logic deployed in an onboard processing unit. It is designed to perform real-time analysis of the raw waveform data stream output from an analog-to-digital converter, extracting predefined signal integrity feature parameters. The streaming feature extraction engine operates in a streaming manner, starting processing without waiting for complete data blocks to arrive.

[0027] Signal integrity characteristics refer to various indicators used to quantify and describe the quality of electrical signals. These parameters can reflect whether the signal is distorted, subject to noise interference, or has timing deviations during transmission, such as rise time, fall time, overshoot, undershoot, jitter, and eye diagram parameters. Signal integrity characteristics include one or more of the following: basic statistics, time-domain characteristics, high-speed serial signal characteristics, and abnormal event flags.

[0028] Among them, basic statistics refer to parameters used for preliminary quantitative analysis of waveform data, such as average, maximum, minimum, peak-to-trough, root mean square, standard deviation, and variance. These parameters can quickly summarize the basic characteristics of the waveform, reflecting the DC bias, amplitude range, energy distribution, and fluctuation degree of the signal.

[0029] Time-domain characteristics refer to parameters that directly reflect waveform properties on the time axis, such as rise time, fall time, pulse width, period, duty cycle, overshoot, undershoot, setup time, and hold time. These characteristics are crucial for evaluating the dynamic response, timing performance, and signal edge quality of a signal.

[0030] High-speed serial signal characteristics are parameters specific to high-speed data transmission scenarios, such as eye diagram height, eye diagram width, jitter, noise, inter-symbol interference, and return loss. These characteristics directly affect the communication quality and reliability of high-speed serial links.

[0031] Abnormal event flags are binary or enumerated flags used to indicate the presence of specific abnormal conditions in a waveform. These abnormalities may include, but are not limited to, glitches, underamplitude, overamplitude, signal loss, periodic interruptions, and irregular transitions. Waveform data is monitored in real time using preset thresholds or pattern matching algorithms, and the corresponding flag is set once an event matching the abnormal definition is detected.

[0032] By refining signal integrity feature parameters into one or more of the following: basic statistics, time-domain features, high-speed serial signal features, and abnormal event flags, the comprehensiveness and diagnostic capabilities of onboard real-time waveform feature extraction in ATE (Automatic Test Equipment) systems can be significantly improved. Specifically, basic statistics provide a quick overview of the overall waveform characteristics, aiding in the initial assessment of signal health; time-domain features focus on the dynamic behavior and timing performance of the signal, crucial for evaluating transmission quality and timing margin; high-speed serial signal features are specifically designed for the complexity of high-speed data transmission, revealing key indicators such as eye diagram quality, jitter, and noise, thus effectively assessing the communication reliability of high-speed links; and abnormal event flags can capture sporadic, transient anomalies in real time, avoiding faults that may be missed by traditional sampling methods. The synergistic effect of these multi-dimensional, complementary feature parameters enables the onboard processing unit to perform more refined and comprehensive real-time analysis of the raw waveform data stream. This provides sufficiently rich information for accurate automatic test judgment without uploading large amounts of raw data, greatly improving the accuracy and efficiency of fault detection, reducing the risk of misjudgment and missed judgment, and ultimately optimizing the overall performance and test throughput of the ATE system.

[0033] Furthermore, in this embodiment, the streaming feature extraction engine includes multiple parallel computing units, which are used to calculate basic statistics, time-domain features, high-speed serial signal features, and abnormal event flags, respectively.

[0034] Specifically, multiple parallel computing units refer to multiple independent hardware or software modules designed within the streaming feature extraction engine, capable of executing computational tasks simultaneously. These units can be instantiated based on the logic resources of a programmable logic device (such as an FPGA), for example, by describing different computational logic blocks using a hardware description language and utilizing the parallel processing capabilities of the FPGA to run them concurrently. Alternatively, in an embedded multi-core processor, different feature computation tasks can be assigned to different processor cores or hardware accelerators to achieve instruction-level or data-level parallel processing. This parallel architecture aims to significantly improve data processing throughput and reduce overall computational latency.

[0035] These parallel computing units are specifically designed or configured to efficiently process specific types of signal integrity characteristic parameters. The unit for calculating basic statistics can handle real-time calculations of waveform values ​​such as mean, variance, peak-to-valley, and root mean square. These calculations typically involve simple accumulation and counting operations, which can be efficiently implemented in hardware using pipelined adders and multipliers. The unit for calculating time-domain characteristics focuses on extracting parameters such as rise time, fall time, pulse width, overshoot, and undershoot. These calculations may require detecting specific threshold crossover points in the waveform or performing differentiation operations, which can be implemented using logic units such as comparators, counters, and lookup tables. The unit for calculating high-speed serial signal characteristics targets more complex parameters such as eye diagram height, eye diagram width, inter-symbol interference, and return loss. The unit for anomaly event flags monitors waveforms in real-time for preset anomalies, such as glitches, underamplitude, overamplitude, signal loss, periodic interruptions, and irregular transitions. This is typically achieved through setting thresholds, pattern matching, or state machine logic; once an anomaly is detected, a corresponding flag is immediately generated.

[0036] By designing the streaming feature extraction engine to include multiple parallel computing units, each focusing on different types of signal integrity feature parameters such as basic statistics, time-domain features, high-speed serial signal features, and abnormal event flags, the parallel processing capability of feature extraction can be significantly improved. This architecture avoids the computational bottleneck that may result from a single processing path, enabling the simultaneous real-time calculation of feature parameters of varying complexity. This effectively solves the problem of insufficient real-time performance when multiple complex features need to be calculated simultaneously. Consequently, even when processing high-speed, high-bandwidth raw waveform data streams, the system maintains extremely low nanosecond-level latency, ensuring that the ATE board can obtain timely and accurate feature vectors during automated testing and judgment, greatly improving testing efficiency and diagnostic capabilities.

[0037] The feature vector encapsulation module encapsulates the signal integrity feature parameters extracted by the streaming feature extraction engine into structured feature vectors. A structured feature vector is a data set that organizes multiple signal integrity feature parameters according to a predetermined format. Structured feature vectors represent the key characteristics of the original waveform data stream in a compact and easily parsed form, facilitating rapid testing, judgment, and data storage.

[0038] Furthermore, the structured feature vectors are appended with timestamps, sampling configuration information, and integrity check codes. Specifically, the timestamp records the precise moment the structured feature vectors were generated or extracted. This timestamp is typically generated by a high-precision clock source within the onboard processing unit and appended to the structured feature vectors with nanosecond or microsecond precision. Through the timestamp, the host computer can accurately track the generation time of each structured feature vector, thereby achieving precise time synchronization of the testing process, event sequence analysis, and accurate location of fault occurrences. This is crucial for diagnosing transient problems and analyzing long-term trends. The sampling configuration information contains key parameters of the analog-to-digital converter (ADC) when acquiring the raw waveform data stream, such as sampling rate, quantization bits, input voltage range, trigger mode, and settings for any preprocessing filters. This information is read from the configuration registers of the ADC or onboard processing unit and appended during structured feature vector generation. By providing this sampling configuration information, the host computer can fully understand the acquisition conditions of the raw waveform data stream, thereby correctly interpreting and calibrating the extracted signal integrity feature parameters, ensuring data comparability and consistency between different test conditions or different ATE boards. The integrity check code is a checksum calculated based on the structured feature vector (and possibly timestamps and sampling configuration information). This checksum can be generated using algorithms such as cyclic redundancy check, checksum, or hash function. Before the structured feature vector is encapsulated and ready for upload, the onboard processing unit calculates this checksum and appends it to the structured feature vector. After receiving the structured feature vector, the host computer independently recalculates the checksum and compares it with the received checksum to verify whether any errors or corruption occurred during data transmission.

[0039] In this embodiment, a triggering and condition judgment module is also deployed in the onboard processing unit. Specifically, this triggering and condition judgment module is deployed in the onboard processing unit, and its main function is to act as a decision center, responsible for evaluating the current test status in real time, and controlling the switching of the upload mode of the host computer interface module according to preset logic or external instructions. The triggering and condition judgment module can be implemented by dedicated hardware logic circuits in the onboard processing unit, such as by a programmable logic device (e.g., FPGA) or an application-specific integrated circuit (ASIC), to ensure nanosecond-level response speed and low latency.

[0040] The triggering and condition judgment module continuously monitors the signal integrity feature parameters extracted by the streaming feature extraction engine in real time, specifically monitoring whether the feature values ​​exceed preset thresholds. These preset thresholds are upper or lower limits pre-set based on the specifications of the device under test, test standards, or historical data analysis results. For example, corresponding allowable ranges can be set for feature parameters such as voltage overshoot, undershoot, rise time, fall time, and jitter. When any monitored feature value exceeds its corresponding preset threshold, it indicates a potential risk of signal abnormality or test failure. This monitoring mechanism enables early warning and automatic identification of potential problems.

[0041] In addition to automatic judgment based on onboard real-time monitoring, the trigger and condition judgment module also has the ability to receive instructions from the host computer. As the control center of the entire test system, the host computer can proactively send instructions to the ATE board, requiring it to force it to enter the original waveform data stream backtracking mode, based on a more macro-level test strategy, operator intervention, or more complex offline analysis results.

[0042] The host computer interface module is a key component for data exchange between the ATE board and the host computer. Its main function is to manage and coordinate the transmission of data generated by the ATE board to the host computer. The host computer interface module typically includes a physical layer interface (e.g., high-speed Ethernet, USB 3.0, or a dedicated high-speed serial link) and a corresponding protocol stack to ensure the reliability and efficiency of data transmission. In this embodiment, the host computer interface module includes independent feature channels and raw data channels, used for transmitting structured feature vectors and compressed raw waveform data streams, respectively.

[0043] In the implementation of the above system, the host computer sends test configuration parameters, including feature extraction type, backtracking threshold, and compression algorithm parameters, to the ATE board via a standard communication protocol. The analog-to-digital converter in the ATE board acquires the analog signals from the device under test in real time and converts them into raw waveform data streams. These raw waveform data streams are directly transmitted to the onboard processing unit via an internal bus. The streaming feature extraction engine in the onboard processing unit uses a pipelined architecture to process the raw waveform data stream point-by-point or through a sliding window, calculating and extracting signal integrity feature parameters in real time, such as basic statistics, time-domain features, high-speed serial signal features, and abnormal event flags. The feature vector encapsulation module organizes the extracted signal integrity feature parameters into compact structured feature vectors according to a preset structure, and adds timestamps, sampling configuration information, and integrity check codes to ensure data reliability. The host computer interface module is configured with independent feature channels and raw data channels. It dynamically selects the transmission path based on the output of the trigger and condition judgment module: when the feature parameters do not exceed the threshold and there is no backtracking instruction, it only uploads the structured feature vector through the feature channel; when the feature parameters exceed the limit or a backtracking instruction is received from the host computer, it automatically switches to the raw data channel to transmit the compressed raw waveform data stream.

[0044] This system deploys a streaming feature extraction engine and a feature vector encapsulation module on the onboard processing unit. By combining real-time streaming processing with a selective upload mechanism, it significantly reduces data transmission volume while ensuring the accuracy of test judgments, thereby reducing network bandwidth pressure and test latency. Specifically, feature extraction and encapsulation of the raw waveform data stream are completed locally on the ATE board, avoiding the conventional transmission of massive amounts of raw data. In the default mode, only structured feature vectors need to be uploaded, significantly reducing the data volume compared to the raw waveform data stream. Only when a backtracking condition is triggered is the compressed raw waveform data stream uploaded through the host computer interface module, achieving precise control over data transmission.

[0045] This system effectively alleviates the bandwidth bottleneck in ATE testing, reducing data transmission volume by two orders of magnitude in typical scenarios and significantly shortening the testing cycle. Simultaneously, the onboard processing unit utilizes programmable logic units or embedded multi-core processors for hardware acceleration, ensuring nanosecond-level processing latency and meeting high-speed testing requirements. This design not only reduces the storage and computing resource consumption of the host computer but also simplifies the testing and judgment process through standardized encapsulation of structured feature vectors, thereby improving the overall efficiency and cost-effectiveness of semiconductor chip testing.

[0046] Example 2 like Figure 2 As shown, this embodiment proposes a real-time waveform feature vector extraction method for semiconductor testing, which is applied to the onboard real-time waveform feature vector extraction system for ATE in Embodiment 1.

[0047] First, in the configuration step, the host computer sends test configuration parameters to the ATE board. The onboard processing unit of the ATE board (e.g., a programmable logic device) is configured with a streaming feature extraction engine. This streaming feature extraction engine is ready to receive the raw waveform data stream acquired by the analog-to-digital converter in the ATE board. For example, the configuration parameters may specify signal integrity features that need to be calculated in real time, including peak voltage, rise time, fall time, jitter, eye height, and eye width.

[0048] The next step is streaming acquisition and extraction. When the chip under test (DUT) starts operating and outputs a signal, the analog-to-digital converter (ADC) acquires its raw waveform data stream in real time and directly inputs it into the streaming feature extraction engine within the onboard processing unit. The streaming feature extraction engine performs real-time streaming processing on the raw waveform data stream. For example, the streaming feature extraction engine uses a sliding window approach to process each fixed-length waveform data segment (e.g., 1024 sampling points). Inside the onboard processing unit, through fixed-point arithmetic and hardware logic multiplexing, the streaming feature extraction engine can calculate preset signal integrity feature parameters with nanosecond-level latency, such as real-time calculation of jitter and eye height within each window. Compared to traditional methods that transmit all raw data to a host computer for batch processing, this onboard real-time processing significantly reduces data processing latency.

[0049] The process then proceeds to the feature vector generation step. Signal integrity feature parameters calculated by the streaming feature extraction engine, such as jitter, eye height, and rise time, are encapsulated into a structured feature vector in real time by the feature vector encapsulation module. To ensure data traceability and integrity, this structured feature vector is also appended with a timestamp, sampling configuration information, and an integrity checksum. For example, a structured feature vector containing dozens of parameters may only be a few hundred bytes, while its corresponding original waveform data may be several megabytes.

[0050] Finally, there is the selective upload step. The trigger and condition judgment module in the onboard processing unit automatically performs tests and judgments based on the generated structured feature vector. In the default mode, if all signal integrity parameters (e.g., jitter value, eye height) in the structured feature vector are within the preset acceptable threshold range, the test is considered passed. In this case, only this compact structured feature vector is uploaded to the host computer through the feature channel of the host computer interface module. After receiving these feature vectors, the host computer can quickly record and statistically analyze the test results without processing massive amounts of raw data. This method significantly reduces the amount of data transmission, avoids bandwidth bottlenecks, and reduces the storage and computing burden on the host computer.

[0051] If preset backtracking conditions are met, the system switches to backtracking mode. For example, if the trigger and condition judgment module detects that the jitter parameter in the structured feature vector exceeds a preset threshold (e.g., more than 10 picoseconds), or if the host computer issues a backtracking command requesting detailed analysis of the signal for a specific time period, the system will activate backtracking mode. In backtracking mode, the onboard processing unit compresses the raw waveform data stream corresponding to the abnormal situation and then uploads it to the host computer through the raw data channel of the host computer interface module. After receiving the compressed raw waveform data stream, the host computer can perform more in-depth fault diagnosis and waveform analysis, such as drawing detailed eye diagrams or performing spectrum analysis.

[0052] Using the above method, the ATE board achieves real-time streaming processing and feature extraction of the raw waveform data stream on its onboard processing unit. It uploads compact, structured feature vectors only under most normal conditions, significantly reducing data transmission volume and latency. The compressed raw waveform data stream is only uploaded when an anomaly occurs or when explicitly requested by the host computer. This effectively solves the problems of bandwidth bottlenecks, high transmission latency, and high storage and computational overhead on the host computer caused by massive data transmission in traditional testing, improving testing efficiency and reducing testing costs.

[0053] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for real-time waveform feature vector extraction for semiconductor testing, characterized in that, Includes the following steps: Configuration steps: Configure a streaming feature extraction engine in the onboard processing unit of the ATE board to receive the raw waveform data stream acquired by the analog-to-digital converter in the ATE board; Streaming acquisition and extraction steps: Perform real-time streaming processing on the original waveform data stream and calculate at least one signal integrity feature parameter; Feature vector generation step: Encapsulate the extracted signal integrity feature parameters into a structured feature vector; Selective upload step: Automatic testing and judgment are performed based on the structured feature vector. In the default mode, only the structured feature vector is uploaded to the host computer. If the preset backtracking conditions are met, the system switches to backtracking mode and uploads the original waveform data stream after compression.

2. The real-time waveform feature vector extraction method for semiconductor testing according to claim 1, characterized in that: In the streaming acquisition and extraction steps, the streaming processing adopts a sliding window or point-by-point processing method, and achieves nanosecond-level latency through fixed-point arithmetic and hardware logic multiplexing.

3. The real-time waveform feature vector extraction method for semiconductor testing according to claim 1, characterized in that: The structured feature vector is also accompanied by a timestamp, sampling configuration information, and integrity check code.

4. The real-time waveform feature vector extraction method for semiconductor testing according to claim 1, characterized in that: In the selective upload step, the backtracking condition is that a parameter in the structured feature vector exceeds a preset threshold, or a backtracking instruction is received from the host computer.

5. The real-time waveform feature vector extraction method for semiconductor testing according to claim 1, characterized in that: The signal integrity characteristic parameters include one or more of the following: basic statistics, time-domain characteristics, high-speed serial signal characteristics, and abnormal event flags.

6. A real-time waveform feature vector extraction system for semiconductor testing, used to implement the real-time waveform feature vector extraction method for semiconductor testing as described in any one of claims 1-5, characterized in that, include: The host computer is used to send out test configuration parameters, receive structured feature vectors, and make test judgments. ATE board, which integrates onboard processing unit and analog-to-digital converter; The streaming feature extraction engine, feature vector encapsulation module, and host computer interface module are deployed in the onboard processing unit. The streaming feature extraction engine is used to perform real-time analysis on the raw waveform data stream output by the analog-to-digital converter and extract at least one signal integrity feature parameter. The feature vector encapsulation module is used to encapsulate the extracted signal integrity feature parameters into structured feature vectors; The host computer interface module is used to upload the structured feature vector or the compressed original waveform data stream to the host computer.

7. The real-time waveform feature vector extraction system for semiconductor testing according to claim 6, characterized in that: The streaming feature extraction engine includes parallel basic statistics units, time-domain feature units, high-speed serial signal feature units, and abnormal event flag units, which are used to calculate basic statistics, time-domain features, high-speed serial signal features, and abnormal event flags, respectively.

8. The real-time waveform feature vector extraction system for semiconductor testing according to claim 6, characterized in that: The onboard processing unit is also equipped with a trigger and condition judgment module, which is used to monitor whether the feature value exceeds the preset threshold, or to receive instructions from the host computer to decide whether to start the original waveform data stream backtracking mode.

9. The real-time waveform feature vector extraction system for semiconductor testing according to claim 6, characterized in that: The onboard processing unit is a dedicated processor or a programmable logic device.

10. The real-time waveform feature vector extraction system for semiconductor testing according to claim 6, characterized in that: The host computer interface module includes independent feature channels and raw data channels, which are used to transmit structured feature vectors and compressed raw waveform data streams, respectively.

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