An ai processor-oriented parameterized computing storage collaborative ip synthesis method and system

Abstract

The application relates to the technical field of electronic design automation, and specifically provides a parameterized calculation storage collaborative IP synthesis method and system for an AI processor, aiming to solve the problem that the synthesis tool in the prior art lacks the recognition and optimization capability of the overall structure of calculation + storage. The application first converts an RTL description file into a data flow graph, then identifies the structure level subgraph in the data flow graph and extracts parameters according to an AI calculation template graph set, searches for a calculation storage collaborative optimization IP instance matched with the subgraph in an IP library according to the parameters, and replaces the subgraph in the data flow graph with the optimization IP instance. The application can not only realize the recognition and optimization of the overall calculation + storage of the AI processor, and avoid the decline of the comprehensive PPA quality caused by the separate optimization of calculation and storage. Moreover, compared with the gate level unit-by-unit reconstruction mode in the prior art, only matching and calling need to be performed in the IP library in the application, so that the running time is shorter, and the synthesis efficiency is higher.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation (EDA) technology, specifically relating to a parametric computing and storage collaborative IP synthesis method and system for AI processors, applicable to the front-end synthesis process of deep learning accelerators, neural network processors and dedicated AI chips. Background Technology

[0002] like Figure 5 As shown, in current mainstream logic synthesis tools, the synthesis process typically includes: RTL parsing, arithmetic unit identification (multipliers, adders, etc.), memory structure identification (registers, RAM, etc.), technology mapping, timing optimization, and area or power optimization. During the synthesis process, arithmetic units and memory units are usually identified and optimized independently; the arithmetic structure is mapped to standard cells or DesignWare-type arithmetic IP (an arithmetic operation hardware module), and the memory structure is inferred to be RAM or a register array.

[0003] However, in modern AI processor architectures, the compute array and local storage are laid out in a coordinated manner, and timing-critical paths often span both storage and compute units. When existing logic synthesis tools process AI processor architectures, they fail to recognize the overall "compute + storage" structure because they separate and optimize compute and storage units. This disrupts the original data flow coordination within the AI ​​processor architecture, and arithmetic structure reconstruction is required in each synthesis process, resulting in excessively long synthesis times and low synthesis efficiency. Summary of the Invention

[0004] This invention provides a parameterized computing and storage collaborative IP synthesis method and system for AI processors, aiming to solve the problem that existing synthesis tools lack the ability to identify and optimize the overall computing and storage structure.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a parameterized computation-storage collaborative IP synthesis method for AI processors, comprising the following steps:

[0007] S100: Convert the input AI processor's RTL description file into a data flow graph;

[0008] S200. Based on the AI ​​computing template graph set, perform structural-level recognition on the data flow graph to obtain the identified subgraphs and the mapping relationship between the subgraphs and the AI ​​computing template graph set;

[0009] S300. Extract the parameter vector of the subgraph based on the mapping relationship;

[0010] S400. Based on the parameter vector, perform a search in the IP database to retrieve a computation-storage collaborative optimization IP instance that matches the subgraph;

[0011] S500: Replace the subgraph with the matching optimized IP instance, and integrate the optimized IP instance into the data flow graph to obtain the optimized data flow graph of RTL;

[0012] S600. Perform a synthesis process on the optimized data flow graph and output an optimized gate-level netlist.

[0013] A further solution: In step S200, the subgraphs that are structurally isomorphic to the AI ​​computation template graph set in the data flow graph are identified sequentially using topological signature pre-screening and VF2 subgraph isomorphism algorithm; the mapping relationship is a mapping table from the AI ​​computation template graph set to the nodes and / or edges of the subgraphs.

[0014] Based on the above scheme, the data flow graph is first filtered using topological signature pre-screening to quickly eliminate subgraphs in the data flow graph that do not clearly match the AI ​​computation template graph set, thus obtaining a candidate subgraph set. This allows the VF2 subgraph isomorphism algorithm to be used for further identification, and only the candidate subgraph set needs to be searched for identification. This can significantly reduce the computational overhead of the VF2 subgraph isomorphism algorithm and thus improve the overall identification efficiency.

[0015] A further solution: In step S300, the parameter vector of the subgraph includes:

[0016] P={W_in, W_weight, kernel_size, channel, buffer_depth, parallel_degree, reuse_factor};

[0017] Wherein, P represents the parameter vector of the subgraph; W_in represents the input data bit width; W_weight represents the weight data bit width; kernel_size represents the convolution kernel size; channel represents the number of parallel multipliers; buffer_depth represents the local storage capacity; parallel_degree represents the degree of parallelism, the number of computational units executed simultaneously in the hardware; and reuse_factor represents the number of times data is reused.

[0018] A further solution: Before performing step S400, an IP library is first constructed; the steps for constructing the IP library include:

[0019] L1. Construct a structural-level collaborative macro architecture for computing and storage;

[0020] L2. Introduce variable parameters to replace the fixed-size units in the computation-storage collaborative macro architecture with parameter expressions to obtain a parameterized macro generation model that can generate instances of arbitrary size.

[0021] L3. By defining the range of values ​​for the parameters in the parameterized macro generation model, several sets of parameter vectors are obtained;

[0022] L4. Perform collaborative layout optimization on each set of parameter vectors;

[0023] L5. Extract PPA features from each optimized set of parameter vectors to obtain several optimized IP instances that correspond one-to-one with several sets of optimized parameter vectors.

[0024] L6. Store several optimized IP instances in a structure-level IP library in the form of an index to complete the construction of the IP library.

[0025] Based on the above scheme, the IP library is first constructed so that it can be searched later. In addition, all the optimized IP instances stored in the IP library are generated through collaborative layout optimization of computing units and storage units, rather than simple arithmetic unit splicing. Therefore, the data flow graph integrating the optimized IP instances maintains the consistency of data reuse paths and physical structure.

[0026] A further solution: In step S400, the optimized IP instance that matches the subgraph is retrieved from the IP database by means of exact matching or approximate matching.

[0027] Based on the above scheme, the present invention sets two matching methods: exact matching and approximate matching, which not only ensures the sub-matching... Figure 1 It can definitely match optimized IP instances in the IP library that coordinate computing and storage, which also reflects the flexibility of reusing optimized IP instances.

[0028] A further solution: The principle followed by the precise matching method is as follows:

[0029] If the parameter vector of the subgraph is equivalent to the i-th parameter vector in the IP library, then the i-th optimized IP instance in the IP library is selected as the optimized IP instance that matches the subgraph.

[0030] Based on the above scheme, the optimized IP instance matched by the precise matching method is equivalent to the parameter vector of the subgraph, is structurally isomorphic, and has the highest matching accuracy.

[0031] A further approach: The principle followed by the approximate matching method is as follows:

[0032] The cost function of each optimized IP instance in the IP library is calculated based on PPA features, and the optimized IP instance with the smallest cost function is selected as the optimized IP instance that matches the subgraph.

[0033] Based on the above scheme, the approximate matching can be used when precise matching is not possible. By calculating the cost function of each optimized IP instance, the deviation of each optimized IP instance from the subgraph in terms of PPA (area, timing, and power consumption) is measured, thereby selecting the structural-level preferred IP instance that is closest to the subgraph and achieving optimal performance selection.

[0034] A further solution: In step S500, the process of replacing the subgraph with a matching optimized IP instance includes:

[0035] S501, Remove the subgraph from the data flow graph;

[0036] S502, Insert the node of the optimized IP instance at the removal location;

[0037] S503. Based on the mapping relationship, establish the corresponding connection relationship between the removed subgraph boundary port and the optimized IP instance port, integrate the optimized IP instance into the data flow graph, and obtain the optimized data flow graph.

[0038] Based on the above scheme, step S503 ensures that the optimized IP instance can receive and output data, and can communicate normally with external circuits, thereby enabling the optimized data flow graph to operate normally.

[0039] A further solution: In step S600, the integration process includes technology mapping, timing optimization, and area and power consumption optimization.

[0040] Secondly, the present invention provides a parameterized computation-memory collaborative IP synthesis system for AI processors, characterized in that it is used to execute a parameterized computation-memory collaborative IP synthesis method for AI processors as described in any of the first aspects; the system includes:

[0041] The integrated front end receives the RTL description file and AI computing template graph set from the AI ​​processor; it converts the RTL description file into a data flow graph; based on the AI ​​computing template graph set, it performs structural-level recognition on the data flow graph to obtain the identified subgraphs and the mapping relationship between the subgraphs and the AI ​​computing template graph set; it extracts the parameter vectors of the identified subgraphs and outputs them.

[0042] IP library server, used to build IP library;

[0043] The parameter matching engine is connected to both the integrated front-end and the IP library server. Based on the parameter vector of the subgraph output by the integrated front-end, it searches the IP library to retrieve and output the computation-storage co-optimized IP instance that matches the subgraph.

[0044] A netlist generator is connected to both the synthesis front-end and the parameter matching engine. It replaces the subgraph with the optimized IP instance output by the parameter matching engine and integrates the optimized IP instance into the data flow graph to obtain an optimized data flow graph for RTL. It performs a synthesis process on the optimized data flow graph and outputs an optimized gate-level netlist.

[0045] The beneficial effects of this invention are as follows:

[0046] In this invention, by calling and replacing computation-storage collaborative optimization IP instances at the structural level rather than the arithmetic unit level, the computation-storage collaboration within the optimized IP instances is preserved. This not only enables the invention to identify and optimize the overall computation and storage in the AI ​​processor, avoiding a decline in overall PPA quality caused by separately optimizing computation and storage, but also, compared to the gate-level unit-by-unit reconstruction method in existing technologies, this invention only requires matching and calling within the IP library, resulting in shorter runtime and higher overall efficiency. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a flowchart illustrating a parameterized computation-storage collaborative IP synthesis method for AI processors according to the present invention.

[0049] Figure 2 This is a schematic diagram of the process for constructing the IP library in this invention;

[0050] Figure 3 This is a schematic diagram of the process for retrieving optimized IP instances that match the subgraph in this invention;

[0051] Figure 4 This is a flowchart illustrating the process of calling the optimized IP instance in step S500 of the present invention;

[0052] Figure 5 This is a flowchart illustrating the process of performing synthesis operations using existing logic synthesis tools. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the protection scope of the present invention.

[0054] Example 1:

[0055] like Figure 1 As shown, this embodiment provides a parameterized computation-storage collaborative IP synthesis method for AI processors, including the following steps:

[0056] S100: Convert the input AI processor's RTL description file into a data flow graph; where RTL (Register-Transfer Level) is an abstraction level and design method used to describe digital circuits.

[0057] S200. Based on the AI ​​computing template graph set, perform structural-level recognition on the data flow graph to obtain the identified subgraphs and the mapping relationship between the subgraphs and the AI ​​computing template graph set;

[0058] S300. Extract the parameter vector of the subgraph based on the mapping relationship;

[0059] S400. Based on the parameter vector, a search is performed in the IP library to retrieve a computation-storage co-optimization IP instance that matches the subgraph; where IP refers to a reusable circuit or functional module design.

[0060] S500: Replace the subgraph with the matching optimized IP instance, and integrate the optimized IP instance into the data flow graph to obtain the optimized data flow graph of RTL;

[0061] S600. Perform a synthesis process on the optimized data flow graph and output an optimized gate-level netlist.

[0062] It should be noted that steps S100-S600 are all executed in a computer system.

[0063] The AI ​​computing template graph set includes convolution templates, attention mechanism templates, and pooling templates, etc. Therefore, when performing structure-level recognition on the data flow graph based on the AI ​​computing template graph set, the identified subgraphs may not be a single one, but may be multiple. For example, they may include convolution structure subgraphs that are isomorphic to the convolution template in the AI ​​computing template graph set, attention mechanism structure subgraphs that are isomorphic to the attention mechanism template, or pooling structure subgraphs that are isomorphic to the pooling template.

[0064] For each identified subgraph, an optimized AI instance is matched, and the matched optimized IP instance replaces the corresponding subgraph.

[0065] The following is a detailed explanation of each step in Example 1:

[0066] A more specific example of step S100 is as follows: step S100 completes the transformation from hardware description to computational dependency structure, which is an abstract expression of the computation path; the expression of the data flow graph is:

[0067] G = (V, E);

[0068] Wherein, G represents a data flow graph; V represents an operation node (e.g., multiplication, addition, register, RAM, etc.); and E represents a signal-dependent edge.

[0069] A more specific example of step S200 is as follows: In step S200, the subgraphs in the data flow graph G that are structurally isomorphic to the AI ​​computing template graph set are identified sequentially using topological signature pre-screening and VF2 subgraph isomorphism algorithm; the mapping relationship is a mapping table from the AI ​​computing template graph set to the nodes and / or edges of the subgraphs.

[0070] Specifically, the process of pre-screening based on topological signatures is as follows: the data flow graph is divided into regions at the structural level, a topological signature is calculated for each region, and compared with the set of AI calculation template graphs to quickly eliminate regions that do not match obviously, and the remaining regions are candidate subgraphs.

[0071] The VF2 subgraph isomorphism algorithm identifies and judges each candidate subgraph, mapping nodes in the AI ​​computation template graph set to nodes in the candidate subgraph while maintaining edge consistency. A successful mapping indicates that the subgraph has been successfully identified.

[0072] Taking the convolution template T_conv in the AI ​​computation template graph set T as an example:

[0073] Convolutional template T_conv={sliding window cache structure multi-multiplication node addition tree accumulation register};

[0074] The sliding window cache structure, multi-multiplication nodes, addition tree, and accumulation register are all structural components of the convolution template.

[0075] First, a pre-screening process based on topological signatures is used to quickly eliminate obviously mismatched regions in the data flow graph. (For example, if the convolution template requires "at least 8 multiplication nodes + 1 addition tree structure", then any region in the data flow graph with fewer than 8 multiplications can be skipped.) Then, the VF2 subgraph isomorphism algorithm is used to map nodes and edges, thereby identifying subgraphs isomorphic to the convolution template.

[0076] Find G' G, such that G' T_conv;

[0077] Wherein, G' represents the identified subgraph; The subset symbol; The expression indicates isomorphism; that is, finding a subgraph G' in the data flow graph G such that the subgraph G' is isomorphic to the convolution template T_conv.

[0078] A more specific example of step S300 is: determining the computation type corresponding to the subgraph based on the mapping relationship, and selecting corresponding parameter extraction rules based on different computation types to extract parameter vectors from the subgraph. The parameter vectors of the subgraph G' include:

[0079] P={W_in, W_weight, kernel_size, channel, buffer_depth, parallel_degree, reuse_factor};

[0080] Wherein, P represents the parameter vector of the subgraph; W_in represents the input data bit width; W_weight represents the weight data bit width; kernel_size represents the convolution kernel size; channel represents the number of parallel multipliers; buffer_depth represents the local storage capacity; parallel_degree represents the degree of parallelism, the number of computational units executed simultaneously in the hardware; and reuse_factor represents the number of times data is reused.

[0081] The W_in, W_weight, channel, and reuse_factor can all be obtained through the mapping table of nodes and / or edges from the AI ​​calculation template graph set T to the subgraph G'.

[0082] The kernel_size is obtained (extraction rule) as follows: kernel_size = sqrt(#weight_edges); where sqrt represents the square root function; weight_edges represents the set of edges connecting the weight input nodes to the multiplication nodes in the subgraph G', which can be obtained from the mapping table of edges from the AI ​​computation template graph set T to the subgraph G'; # is a counting symbol, representing the total number of elements in the edge set weight_edges.

[0083] The method (extraction rule) for obtaining buffer_depth is: buffer_depth = max(FIFO_depth); where max represents the maximum value; FIFO_depth represents the set of depths of all first-in-first-out buffer units (FIFOs) in the subgraph G', which can be obtained from the synthesis tool report, in which the synthesis tool will list the depth of each FIFO.

[0084] The method (extraction rule) for obtaining the parallel_degree is as follows: parallel_degree = #mul_nodes; where mul_nodes represents the set of all nodes that perform multiplication operations in the subgraph G', which can be obtained from the mapping table of nodes from the AI ​​computation template graph set T to the subgraph G'; and # is a counting symbol, representing the total number of elements in the node set mul_nodes.

[0085] Based on the above solutions, such as Figure 2 As shown, before performing step S400, an IP library is first constructed; the steps for constructing the IP library include:

[0086] L1. Construct a structure-level computation-storage collaborative macro architecture (e.g., convolutional macros, attention mechanism macros, etc.).

[0087] L2. Introduce variable parameters to replace the fixed-size units in the computation-storage collaborative macro architecture with parameter expressions to obtain a parameterized macro generation model that can generate instances of arbitrary size.

[0088] L3. By defining the range of values ​​for the parameters in the parameterized macro generation model, several sets of parameter vectors are obtained;

[0089] L4. Perform collaborative layout optimization on each set of parameter vectors;

[0090] L5. Extract PPA features from each optimized set of parameter vectors to obtain several optimized IP instances that correspond one-to-one with several sets of optimized parameter vectors.

[0091] L6. Store several optimized IP instances in a structure-level IP library in the form of an index to complete the construction of the IP library.

[0092] Furthermore, a more specific example of step L1 is as follows: taking a convolutional macro as an example, the structure of the convolutional macro includes a multiplication array, an addition tree, an accumulation register structure, a local weight cache, an input sliding window cache, and a data multiplexing control unit.

[0093] These structures are abstracted and represented as a structure graph: Macro = (V_compute, V_memory, E_dataflow); where Macro represents the macro architecture; V_compute represents the set of computing units; V_memory represents the set of local storage units; and E_dataflow represents data dependency edges.

[0094] A more specific example of step L2 is as follows: First, the introduced variable parameters are defined as a parameter vector: P={W_in, W_weight, K, C, D, S, R}; where W_in represents the input bit width; W_weight represents the weight bit width; K represents the convolution kernel size; C represents the number of parallel channels (number of multipliers); D represents the local cache depth; S represents the stride; and R represents the data reuse factor.

[0095] Next, the fixed-size units in the computation-storage collaborative macro-architecture are replaced with parametric expressions. For example, the number of multipliers N_mul is replaced with the parametric expression C; the number of weights N_weight is replaced with the parametric expression C. The sliding window buffer size Buffer_size is replaced with a parameter expression. .

[0096] A more specific example of step L3 is as follows: Based on process limitations and application scope, define the range of parameter values, for example: K∈{1, 3, 5, 7}; C∈{8, 16, 32, 64}; W_in∈{8, 16}; thus obtaining 32 (4×4×2=32) sets of parameter vectors.

[0097] A more specific example of step L4 is: performing collaborative layout optimization includes: generating the corresponding RTL structure based on each set of parameter vectors, performing synthesis, performing local layout optimization, and coordinating the placement of computing units and cache units.

[0098] For a more specific example of step L5, the expression for extracting PPA features (Area, Delay, and Power) is:

[0099] Area = f(Netlist);

[0100] Delay = MaxPath(Netlist);

[0101] Power=EstimatePower(Netlist);

[0102] Wherein, Netlist represents the circuit's connection relationships and component list; f represents the mapping function; MaxPath represents the path from input to output where the sum of the delays of all gates is the largest; and EstimatePower represents the power consumption estimation function.

[0103] Obtain several optimized IP instances that correspond one-to-one with several sets of optimized parameter vectors:

[0104] IP_i={P_i, Area_i, Delay_i, Power_i}; where i represents the index number, i=1…n.

[0105] In a more specific example of step L6, the expression for the IP library is:

[0106] Library= {IP_1, IP_2, IP_3… IP_n}.

[0107] Based on the above solutions, such as Figure 3 As shown, step S400 retrieves the optimized IP instance that matches the subgraph from the IP database by means of exact matching or approximate matching.

[0108] More preferably, in the IP library, each optimized IP instance also includes a gate-level netlist, expressed as:

[0109] IP_i={ParamVector P_i, Netlist_i, Area_i, Delay_i, Power_i};

[0110] Wherein, IP_i represents the i-th parameterized compute-storage co-optimized IP instance; ParamVector represents the compute and storage organization characteristics of the optimized IP instance at the structural level; P_i represents the parameter vector corresponding to the i-th optimized IP instance; Netlist_i represents the optimized gate-level netlist or structural-level netlist corresponding to the i-th optimized IP instance; Area_i represents the pre-evaluated area value of the i-th optimized IP instance under the target process library; Delay_i represents the critical path delay value of the i-th optimized IP instance; and Power_i represents the estimated power consumption value of the i-th optimized IP instance under specified operating conditions.

[0111] Of course, in addition to storing the optimized IP instances in the IP library in the form of a gate-level netlist, the Youhu AIP instances can also be stored in the IP library in the form of soft IPs (RTL source code) or physical macro units (GDS hard cores).

[0112] In addition, the IP library search space can be limited according to the mapping relationship of the subgraph, thereby narrowing the search range of the IP library.

[0113] Matching Method 1: The principle followed by the exact matching method is as follows:

[0114] If the parameter vector of the subgraph is equivalent to the i-th parameter vector in the IP library, then the i-th optimized IP instance in the IP library is selected as the optimized IP instance that matches the subgraph.

[0115] When the optimized IP instance cannot be matched using matching method 1, matching method 2 can be used for approximate matching. The principle followed by the approximate matching method is as follows:

[0116] The cost function of each optimized IP instance in the IP library is calculated based on PPA features, and the optimized IP instance with the smallest cost function is selected as the optimized IP instance that matches the subgraph.

[0117] Specifically, the formula used to calculate the cost function is as follows:

[0118] ΔArea=| Area_est - Area_i |;

[0119] ΔDelay=| Delay_est - Delay_i |;

[0120] ΔPower=| Power_est - Power_i |;

[0121] Cost_i = α·ΔArea + β·ΔDelay+ γ·ΔPower;

[0122] IP *= argmin(Cost_i);

[0123] Wherein, | represents a positive number; Area_est represents the design target area value estimated based on the identified subgraph, and ΔArea represents the difference between the design target area value and the area of ​​the i-th IP optimization instance; Delay_est represents the design target delay value estimated based on the identified subgraph, and ΔDelay represents the difference between the design target delay value and the delay of the i-th IP optimization instance; Power_est represents the design target power consumption value estimated based on the identified subgraph, and ΔPower represents the difference between the design target power consumption value and the power consumption of the i-th IP optimization instance; α represents the area weighting coefficient, β represents the delay weighting coefficient, and γ represents the power consumption weighting coefficient, and satisfies α+β+γ=1; Cost_i represents the comprehensive (PPA including area, timing, and power consumption) deviation value of the i-th IP optimization instance relative to the design target; argmin represents taking the minimum value; and IP* represents the optimized IP instance that best matches the subgraph.

[0124] Based on the above scheme, when an optimal IP instance cannot be matched through exact matching, in addition to calculating the cost function through approximate matching, the following three alternative schemes can also be used to match the best optimized IP instance.

[0125] Alternative Solution 1: Predict the optimal IP instance that best matches the subgraph using a machine learning model: Construct a prediction model, input parameter vectors and design constraint information into the prediction model, and the optimal IP instance that best matches the subgraph can be output.

[0126] Alternative Solution 2: When the parameter vector of the subgraph falls between two adjacent optimized IP instances in the IP library, a new parameter is generated based on the parameters of the two optimized IP instances, which is the optimized IP instance that best matches the subgraph.

[0127] Alternative Solution 3: By calculating the cost function, the optimized IP instance with the smallest cost function is selected as the baseline IP. Based on the constraint information of the target design, the baseline IP is locally optimized, and finally, an optimized IP instance matching the subgraph is generated.

[0128] like Figure 4As shown, a more specific example of step S500 is as follows: In step S500, the process of replacing the subgraph with the matching optimized IP instance includes:

[0129] S501, Remove the subgraph from the data flow graph;

[0130] S502, Insert the node of the optimized IP instance at the removal location;

[0131] S503. Based on the mapping relationship, establish the corresponding connection relationship between the removed subgraph boundary ports and the optimized IP instance ports, integrate the optimized IP instance into the data flow graph, that is, map the external connection ports of the removed subgraph to the connection ports of the optimized IP instance one by one, and obtain the optimized data flow graph.

[0132] Preferably, the mapping relationship is Original_Port[k] → IP_Port[j], which represents the Kth external connection port in the subgraph to be removed and the jth connection port in the replaced optimized IP instance.

[0133] The Kth external connection port in the removed subgraph can be an input port, an output port, a control port, a clock port, or a reset port.

[0134] A more specific example of step S600 is as follows: In step S600, the integration process includes technology mapping, timing optimization, and area and power consumption optimization.

[0135] It should be noted that during the comprehensive process, the optimized IP instance is marked with dont_touch = true to prevent it from being disassembled again.

[0136] The technology mapping, timing optimization, and area / power optimization operations in step S600 can refer to the technology mapping, timing optimization, and area / power optimization operations performed by traditional logic synthesis tools in the prior art.

[0137] Example 2:

[0138] This embodiment provides a parameterized computation-store collaborative IP synthesis system for AI processors, characterized in that it is used to execute the parameterized computation-store collaborative IP synthesis method for AI processors described in Embodiment 1; the system includes:

[0139] The integrated front end receives the RTL description file and AI computing template graph set from the AI ​​processor; it converts the RTL description file into a data flow graph; based on the AI ​​computing template graph set, it performs structural-level recognition on the data flow graph to obtain the identified subgraphs and the mapping relationship between the subgraphs and the AI ​​computing template graph set; it extracts the parameter vectors of the identified subgraphs and outputs them.

[0140] IP library server, used to build IP library;

[0141] The parameter matching engine is connected to both the integrated front-end and the IP library server. Based on the parameter vector of the subgraph output by the integrated front-end, it searches the IP library to retrieve and output the computation-storage co-optimized IP instance that matches the subgraph.

[0142] A netlist generator is connected to both the synthesis front-end and the parameter matching engine. It replaces the subgraph with the optimized IP instance output by the parameter matching engine and integrates the optimized IP instance into the data flow graph to obtain an optimized data flow graph for RTL. It performs a synthesis process on the optimized data flow graph and outputs an optimized gate-level netlist.

[0143] This invention is not limited to the above-described optional embodiments. Anyone can derive other various forms of products under the guidance of this invention. However, regardless of any changes made in their shape or structure, any technical solution that falls within the scope of the claims of this invention shall be protected by this invention.

Claims

1. A parameterized computation-storage collaborative IP synthesis method for AI processors, characterized in that, Includes the following steps: S100: Convert the input AI processor's RTL description file into a data flow graph; S200. Based on the AI ​​computing template graph set, perform structural-level recognition on the data flow graph to obtain the identified subgraphs and the mapping relationship between the subgraphs and the AI ​​computing template graph set; S300. Extract the parameter vector of the subgraph based on the mapping relationship; S400. Based on the parameter vector, perform a search in the IP database to retrieve a computation-storage collaborative optimization IP instance that matches the subgraph; S500: Replace the subgraph with the matching optimized IP instance, and integrate the optimized IP instance into the data flow graph to obtain the optimized data flow graph of RTL; S600. Perform a synthesis process on the optimized data flow graph and output an optimized gate-level netlist.

2. The parameterized computation-storage collaborative IP synthesis method for AI processors according to claim 1, characterized in that, In step S200, the subgraphs in the data flow graph that are structurally isomorphic to the AI ​​computation template graph set are identified sequentially using topological signature pre-screening and VF2 subgraph isomorphism algorithm; the mapping relationship is a mapping table from the AI ​​computation template graph set to the nodes and / or edges of the subgraphs.

3. The parameterized computation-storage collaborative IP synthesis method for AI processors according to claim 1, characterized in that, In step S300, the parameter vector of the subgraph includes: P={W_in, W_weight, kernel_size, channel, buffer_depth, parallel_degree,reuse_factor}; Wherein, P represents the parameter vector of the subgraph; W_in represents the input data bit width; W_weight represents the weight data bit width; kernel_size represents the convolution kernel size; channel represents the number of parallel multipliers; buffer_depth represents the local storage capacity; parallel_degree represents the degree of parallelism, the number of computational units executed simultaneously in the hardware; and reuse_factor represents the number of times data is reused.

4. The parameterized computation-storage collaborative IP synthesis method for AI processors according to claim 1, characterized in that, Before performing step S400, the IP library is built first; The steps for constructing the IP library include: L1. Construct a structural-level collaborative macro architecture for computing and storage; L2. Introduce variable parameters to replace the fixed-size units in the computation-storage collaborative macro architecture with parameter expressions to obtain a parameterized macro generation model that can generate instances of arbitrary size. L3. By defining the range of values ​​for the parameters in the parameterized macro generation model, several sets of parameter vectors are obtained; L4. Perform collaborative layout optimization on each set of parameter vectors; L5. Extract PPA features from each optimized set of parameter vectors to obtain several optimized IP instances that correspond one-to-one with several sets of optimized parameter vectors. L6. Store several optimized IP instances in a structure-level IP library in the form of an index to complete the construction of the IP library.

5. A parameterized computation-storage collaborative IP synthesis method for AI processors according to claim 4, characterized in that, In step S400, the optimized IP instance that matches the subgraph is retrieved from the IP database by means of exact matching or approximate matching.

6. The parameterized computation-storage collaborative IP synthesis method for AI processors according to claim 5, characterized in that, The principle followed by the exact matching method is as follows: If the parameter vector of the subgraph is equivalent to the i-th parameter vector in the IP library, then the i-th optimized IP instance in the IP library is selected as the optimized IP instance that matches the subgraph.

7. A parameterized computation-storage collaborative IP synthesis method for AI processors according to claim 5, characterized in that, The principle followed by the approximate matching method is as follows: The cost function of each optimized IP instance in the IP library is calculated based on PPA features, and the optimized IP instance with the smallest cost function is selected as the optimized IP instance that matches the subgraph.

8. The parameterized computation-storage collaborative IP synthesis method for AI processors according to claim 1, characterized in that, In step S500, the process of replacing the subgraph with the matching optimized IP instance includes: S501, Remove the subgraph from the data flow graph; S502, Insert the node of the optimized IP instance at the removal location; S503. Based on the mapping relationship, establish the corresponding connection relationship between the removed subgraph boundary port and the optimized IP instance port, integrate the optimized IP instance into the data flow graph, and obtain the optimized data flow graph.

9. A parameterized computation-storage collaborative IP synthesis method for AI processors according to claim 1, characterized in that, In step S600, the integration process includes technology mapping, timing optimization, and area and power consumption optimization.

10. A parameterized computing-storage collaborative IP integration system for AI processors, characterized in that, The system is used to execute a parameterized computation-memory co-synthesis IP method for AI processors as described in any one of claims 1-9; the system includes: The integrated front end receives the RTL description file and AI computing template graph set from the AI ​​processor; it converts the RTL description file into a data flow graph; based on the AI ​​computing template graph set, it performs structural-level recognition on the data flow graph to obtain the identified subgraphs and the mapping relationship between the subgraphs and the AI ​​computing template graph set; it extracts the parameter vectors of the identified subgraphs and outputs them. IP library server, used to build IP library; The parameter matching engine is connected to both the integrated front-end and the IP library server. Based on the parameter vector of the subgraph output by the integrated front-end, it searches the IP library to retrieve and output the computation-storage co-optimized IP instance that matches the subgraph. A netlist generator is connected to both the synthesis front-end and the parameter matching engine. It replaces the subgraph with the optimized IP instance output by the parameter matching engine and integrates the optimized IP instance into the data flow graph to obtain an optimized data flow graph for RTL. It performs a synthesis process on the optimized data flow graph and outputs an optimized gate-level netlist.

Images