Method for constructing a double-gate reconfigurable field effect transistor process design kit

Abstract

The application discloses a double-gate reconfigurable field effect transistor process design kit construction method, and belongs to the field of integrated circuit process design kit expansion, reconfigurable device modeling and physical verification. In view of the fact that existing open source PDK mainly faces traditional CMOS devices and is difficult to support circuit design, layout drawing and post-layout verification of double-gate RFET, the application provides a process design kit construction method for double-gate RFET. The method comprises the following steps: constructing a four-terminal RFET compact model and packaging the four-terminal RFET compact model into a SPICE subcircuit; establishing a schematic symbol, a layout unit and parameter configuration; extending LVS device identification rules to identify four-port RFET devices containing a source, a drain, a control gate and a polarity gate; constructing a parasitic parameter extraction file and integrating the parasitic parameter extraction file into a layout verification process; and finally, performing post-layout simulation verification on an RFET inverter and reconfigurable NAND and NOR logic. The application realizes a complete design closed loop of double-gate RFET from a model, a schematic, a layout, DRC / LVS, PEX and reverse label simulation.

Description

Technical Field

[0002] This invention belongs to the field of integrated circuit process design kit (PDK) extension, reconfigurable transistor circuit implementation and physical verification, and specifically relates to a method for constructing a dual-gate reconfigurable field-effect transistor process design kit compatible with ASAP7. Background Technology

[0004] Reconfigurable field-effect transistors (RFETs) achieve dynamic switching of device polarity through electrical bias, enabling multiple logic functions to be implemented within the same device structure. They hold promise for logic simplification, area reduction, and function reuse. Compared to traditional CMOS devices that rely on fixed source / drain doping polarities, RFETs typically employ a Schottky barrier structure formed by metal / intrinsic semiconductor / metal, and use independent polarity gates and control gates to regulate carrier type and conduction capability.

[0005] Existing research on RFETs largely focuses on device mechanisms, TCAD simulation, and schematic-level circuit verification. While some work has demonstrated the functional advantages of RFETs in reconfigurable logic, their circuit implementation often remains at the level of ideal device models or pre-simulation, lacking a complete design flow covering layout drawing, physical verification, parasitic extraction, and post-layout scaling simulation. Meanwhile, existing predictive PDKs, such as ASAP7, ASAP5, FreePDK15, and GT3, are primarily geared towards traditional CMOS, FinFET, or GAAFET devices and do not natively support RFET devices with dual-gate, four-port characteristics.

[0006] Because RFETs possess characteristics such as near-symmetrical source-drain, independent dual-gate bias, and programmable polarity, directly applying traditional CMOS PDK and LVS / PEX processes will make it difficult to correctly identify the control gate and polarity gate ports, establish parasitic parameter extraction rules that match the device structure, and complete reliable post-layout evaluation in a standard EDA environment. Therefore, it is necessary to propose a process design kit construction method for dual-gate RFETs to support their standardized implementation in standard cells and reconfigurable logic. Summary of the Invention

[0007] The purpose of this invention is to address the problem that existing open-source PDKs cannot support a complete closed loop from schematic to layout to post-simulation for dual-gate RFETs. This invention proposes a method for constructing a dual-gate reconfigurable field-effect transistor (RFT) process design kit compatible with ASAP7. While retaining the basic ASAP7 settings, this method establishes device models, schematic and layout libraries, LVS identification rules, and parasitic extraction processes suitable for RFETs, enabling post-layout functional and timing verification of dual-gate RFET logic circuits.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: A method for constructing a dual-gate reconfigurable field-effect transistor process design kit includes the following steps: Step 1: Construct a compact model of a dual-gate reconfigurable field-effect transistor (RFET). The RFET includes at least four ports: source (S), drain (D), control gate (CG), and polar gate (PG). The polar gate (PG) is used to modulate the source-drain Schottky barrier to achieve device polarity switching, and the control gate (CG) is used to regulate channel conduction and drive current. Step 2: Encapsulate the compact model into a SPICE sub-circuit compatible with the circuit simulator, establish the corresponding schematic symbols, parameterized attribute configurations and layout units, and form an extension module for the dual-gate reconfigurable field-effect transistor process design kit; Step 3: On the layout hierarchy, routing layer definition and basic verification environment provided by the open source process design kit, call the design extension module described in Step 2 to complete the layout design of the target logic unit; Step 4: Expand the device identification rules in the layout verification process to identify the four ports: source, drain, control gate, and polarity gate, and complete the layout and schematic verification. Figure 1 Consistency verification; Step 5: Construct the interconnect technology file corresponding to the dual-gate reconfigurable field-effect transistor structure and integrate it into the parasitic parameter extraction process to extract the coupling parasitic parameters between device ports and the interconnect parasitic parameters; Step 6: Based on the layout obtained in Step 3, the layout verification results obtained in Step 4, and the parasitic parameter extraction results obtained in Step 5, perform post-layout simulation verification on the target logic circuit.

[0009] Furthermore, the compact model described in step 1 adopts a behavior model based on artificial neural networks. By training the current-voltage and capacitance-voltage characteristics of the dual-gate RFET under different gate bias and device size conditions, a compact model that can simultaneously characterize IV and CV characteristics is obtained.

[0010] Furthermore, the training data of the artificial neural network comes from TCAD device simulation, and the training input includes at least the control gate bias voltage, polarity gate bias voltage and device geometry, and the training output includes at least the device leakage current and parasitic capacitance parameters between the device and the port.

[0011] Furthermore, the SPICE sub-circuit described in step 2 adopts a four-port definition, with the port order being source (S), drain (D), control gate (CG), and polarity gate (PG), to maintain consistency with the layout and schematic. Figure 1 The port correspondence between the consistency test results and the parasitic parameter extraction netlist is consistent.

[0012] Furthermore, in step 3, the layout design of the target logic cell is carried out according to the standard cell height of 7.5T. Each RFET device adopts a two-fin structure to reserve independent wiring paths for the control gate and polarity gate within the limited cell height. The RFET devices configured as p-type equivalent and n-type equivalent are symmetrically arranged in the layout, and dummy fins are set at the cell boundaries to maintain fin density uniformity and layout manufacturability.

[0013] Furthermore, the extended device identification rules described in step 4 include: setting identification layers corresponding to the control gate and polarity gate respectively in the layout, and in the layout and schematic diagram... Figure 1 The consistency check rule file maps the identification layer to control gate ports and polarity gate ports, respectively.

[0014] Furthermore, the interconnect technology document mentioned in step 5 is established based on the front-end cross-sectional structure of the dual-gate reconfigurable field-effect transistor, and includes at least descriptions of the active region, dual-gate structure, local interconnect structure, and conductor and dielectric layers of the contact vias, thereby supporting the extraction of parasitic coupling parameters between the control gate and the polar gate, as well as between the dual gate and the source and drain.

[0015] Furthermore, the target logic circuit in step 6 includes at least an RFET inverter and reconfigurable NAND and NOR logic units; wherein, the reconfigurable NAND and NOR logic units switch between NAND and NOR functions without changing the circuit topology by applying a selection signal SEL to the polarity gate. When the selection signal SEL is in the first logic state, the corresponding RFET is configured with the first conduction polarity to implement NAND logic; when the selection signal SEL is in the second logic state, the corresponding RFET is configured with the second conduction polarity to implement NOR logic.

[0016] A process design kit for a dual-gate reconfigurable field-effect transistor constructed using the above method includes an RFET compact model library, a schematic symbol library, a layout library, a parametric attribute configuration file, and layout and schematic diagrams. Figure 1It includes consistency check and identification rules, parasitic parameter extraction rules, and a back-annotation netlist interface for post-layout simulation. It can also complete schematic design, layout implementation, design rule checking, and layout-schematic conversion of dual-gate reconfigurable field-effect transistor circuits within a standard EDA environment. Figure 1 Consistency checks, parasitic parameter extraction, post-layout functional verification, and timing simulation.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects: (1) For the first time, a dual-gate RFET was systematically introduced in an open PDK framework compatible with ASAP7, which opened up the entire process of device model, schematic diagram, layout, LVS, PEX and post-simulation. (2) The accuracy of layout verification after RFET is improved by identifying four-terminal devices and extracting parasitic dual-gate coupling; (3) It can realize the standardized implementation and performance evaluation of reconfigurable logic units in the standard EDA environment, providing a foundation for the subsequent RFET standard cell library and complex system design. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the dual-gate RFET structure involved in the present invention, which shows the relative positions and functions of the source S, drain D, control gate CG, and polar gate PG; Figure 2 This is a schematic diagram of the artificial neural network structure used for compact modeling of RFET in this invention; Figure 3 This is a schematic diagram of the RFET inverter in the ASAP7 7.5T standard cell architecture of the present invention; Figure 4 This is a schematic diagram of the cross-section and connection relationship of the RFET front-end used for parasitic extraction in this invention; Figure 5 This is a schematic diagram of the reconfigurable NAND and NOR logic units in this invention, wherein (a) is a schematic diagram and (b) is a layout diagram.

[0020] Figure 6 This is a comparison of the transient waveforms from the pre-simulation and post-layout reverse-annotation simulation of the RFET inverter in this invention. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0023] The construction method of the present invention includes: First, a four-port compact model is established for a dual-gate RFET. The device includes a source (S), a drain (D), a control gate (CG), and a polarity gate (PG). The polarity gate modulates the Schottky barrier at the source-drain contact to select the device's conduction polarity, and the control gate controls the channel current. The model employs a behavioral modeling approach based on artificial neural networks, learning the IV and CV characteristics under different bias and size conditions from TCAD simulation data, and encapsulating them into sub-circuits that can be used by circuit simulators such as HSPICE.

[0024] Secondly, schematic symbols, parameterized attribute files, and layout views corresponding to the four-terminal RFETs are created in the PDK to ensure compatibility with the existing hierarchical cell structure of ASAP7. To accommodate the requirement of independent dual-gate routing, a 7.5T standard cell architecture is preferred, and the fin number, pin positions, and local interconnection methods of the RFET cells are redefined.

[0025] Secondly, in terms of physical verification, the original ASAP7 design rule inspection framework remains unchanged, inheriting its basic design rules such as gate pitch, gate length, and diffusion isolation; at the same time, the LVS rule is extended, and the automatic identification of four-terminal RFET devices and netlist generation are realized by combining the geometric relationship between the gate and the active region in the layout with the control gate identification layer and the polarity gate identification layer. The preferred port order is defined as S, D, CG, PG.

[0026] Furthermore, in terms of parasitic parameter extraction, an interconnect technology file (ITF) consistent with the front-end cross-section of the RFET is constructed, incorporating the conductor / dielectric information of the active region, dual-gate structure, contact holes, local interconnects, and metal layers into the model. This enables the extraction of grid-to-ground, grid-to-grid, and dual-gate coupling parasites in the parasitic extraction tool, and outputs an RC netlist for post-layout back-indexing simulation.

[0027] Finally, the circuits represented by RFET inverters and reconfigurable NAND and NOR cells were used for verification. The propagation delay and functional waveforms were compared under ideal pre-simulation and parasitic back-scale post-simulation conditions to verify that the RFET-ASAP7 extended PDK can achieve correct post-layout functional evaluation.

[0028] Example 1: Construction of an expansion module for a dual-gate reconfigurable field-effect transistor process design kit This embodiment proposes a method for constructing an extended module of a process design kit for dual-gate reconfigurable field-effect transistors. The overall method includes four parts: device modeling, schematic and layout cell establishment, physical verification process extension, and parasitic parameter extraction, thereby forming a complete closed loop from schematic design and layout implementation to post-layout back-annotation simulation.

[0029] In a preferred embodiment, the method is implemented based on an existing open-source process design kit, preferably extended based on the basic layout environment, hierarchical definition, and verification process of the ASAP7 open-source process design kit.

[0030] 1. RFET device model construction like Figure 1 As shown, the RFET in this embodiment adopts a stacked nanosheet channel structure, comprising three laterally arranged semiconductor channels, with the source and drain regions forming a Schottky barrier using metal contacts. The control gate CG is used to adjust the channel conduction capability, and the polar gate PG is used to adjust the barrier height, thereby realizing the switching between the equivalent n-type or p-type operating modes of the device.

[0031] To accurately describe the nonlinear characteristics of the device in circuit simulation, this embodiment preferably uses an artificial neural network to build a compact model. For example... Figure 2 As shown, the neural network is trained using parameters such as control gate bias, polarity gate bias, and device geometry as inputs, and the device's current-voltage and capacitance-voltage characteristics as output targets. The training data is generated by TCAD simulation, covering IV and CV characteristics under different control gate bias, polarity gate bias, and device size conditions. After training, the model is encapsulated as a SPICE-compatible subcircuit and integrated into the design environment as an HSPICE view.

[0032] 2. Establishment of schematic symbols and layout units In the schematic design environment, a four-terminal device symbol is created for the RFET, with the ports defined as S, D, CG, and PG, and the corresponding CDF parameters are configured to support model calls and simulation attribute transfer.

[0033] In the layout implementation, this embodiment establishes RFET layout cells on the basic layout environment provided by existing open-source process design kits. In a preferred embodiment, the basic layout environment adopts the ASAP7 standard cell architecture, so the layout cells can be designed according to the 7.5-rail standard cell height of ASAP7. Considering the requirement for independent routing of dual gates, compared with the three-fin configuration commonly found in traditional ASAP7 libraries, this embodiment adopts a two-fin RFET structure, providing independent lead-out paths for the control gate and polarity gate within a limited cell height.

[0034] like Figure 3The diagram shows a layout of an RFET inverter in a standard cell architecture. RFET devices configured for p-type and n-type equivalent operation are symmetrically arranged in the layout, with dummy fins added to the cell edges to maintain consistent fin density. The diagram illustrates the layout of the dual-gate RFET devices within the cell, the relationship between the local interconnect layers and source / drain connections, and the routing of power and signal terminals. In a preferred embodiment, the cell boundaries, power rail locations, and routing constraints can inherit the existing specifications of the ASAP7 open-source process design kit, thereby completing the physical implementation of the dual-gate RFET logic cell without changing the base layer definitions and routing rules.

[0035] 3. Physical verification process expansion This embodiment, without disrupting the existing design rule checking framework of the open-source process design kit, adopts its basic design rules and extends the layout and principle for the four-terminal structure of the dual-gate RFET. Figure 1 Consistency check process. In a preferred embodiment, the existing open-source process design suite is ASAP7. Therefore, based on the original design rule check framework of ASAP7, only the identification rules for dual-gate RFET related devices can be extended without rebuilding the complete basic rule system.

[0036] Specifically, in terms of layout and principles Figure 1 During the consistency check, the device body is determined by detecting the overlap between the gate pattern and the active region. Then, combined with the control gate identification layer and the polarity gate identification layer, the dual gates are mapped as CG ports and PG ports, respectively. The source and drain are extracted according to the layout connection relationship, and finally a four-terminal device netlist with the port order S, D, CG, PG is generated. This method ensures the consistency of the schematic, layout, and subsequent parasitic extraction netlist.

[0037] 4. Parasitic parameter extraction and post-map back-indexing To support post-layout evaluation of dual-gate RFETs, this embodiment constructs an ITF file that matches the front-end cross-section of the RFET. This ITF not only describes the conductor and dielectric properties of the conventional active region, contact layer, and metal interconnects, but also considers the coupling paths associated with the control gate and polarity gate, enabling parasitic extraction tools to output parasitic information such as grid-to-ground, grid-to-grid, and inter-gate coupling capacitance.

[0038] like Figure 4 The diagram shows the RFET front-end cross-section and interconnections used for parasitic parameter extraction, illustrating the relative positions of the active region, dual-gate structure, local interconnect structures, and contact vias. An RC netlist suitable for circuit simulation can be generated using the parasitic parameter extraction process, and this RC netlist can be back-indexed into the target logic circuit for post-layout transient response and propagation delay verification.

[0039] In a preferred embodiment, the parasitic parameter extraction process can work in conjunction with the existing back-end interconnect layer definition and parasitic extraction environment of the ASAP7 open-source process design kit, thereby achieving compatible extensions for the addition of front-end structures to dual-gate RFETs.

[0040] Example 2: Implementation of Reconfigurable Logic Units Utilizing the polarity programmable feature of RFET devices, this embodiment implements a reconfigurable NAND and NOR logic cell. For example... Figure 5 As shown in (a), the logic unit adopts a fixed transistor connection topology at the schematic level. By applying a selection signal SEL to the polarity gate, the conduction polarity of the device can be changed without altering the transistor topology. When SEL is in the first logic state, the target RFET is configured with an equivalent polarity, and the entire network implements NAND logic; when SEL is in the second logic state, the target RFET is configured with another equivalent polarity, and the entire network implements NOR logic.

[0041] like Figure 5 As shown in (b), the corresponding layout structure, while maintaining basic consistency in cell boundaries and routing rules, achieves the same functionality as... Figure 5 (a) Corresponding reconfigurable logical layout. Figure 5 (b) illustrates the device array, dual-gate leads, and selection signal introduction method. In a preferred embodiment, the layout can inherit the ASAP7 standard cell row height, power rail constraints, and metal interconnect layer usage. Compared to the traditional approach that requires separate design of NAND and NOR cells, this embodiment enables logic function switching within the same layout structure, thereby improving logic density and functional reconfigurability.

[0042] Example 3: Post-layout Functionality and Latency Verification To verify the effectiveness of the dual-gate reconfigurable field-effect transistor design kit construction method proposed in this invention, this embodiment selects an RFET inverter as the test circuit and compares its pre-simulation and post-layout simulation.

[0043] The pre-simulation uses a compact RFET schematic-level netlist generated based on a neural network, while the post-simulation introduces an RC parasitic network extracted from the layout under the same excitation conditions. For example... Figure 6 As shown, simulation results indicate that, under ideal conditions, the inverter's rise propagation delay t PLH Approximately 25.6 ps, decreasing propagation delay t PHL Approximately 23.2 ps; after the parasitic parameters of the backscalar, t PLH Increased to approximately 69.0 ps, ​​t PHLThe latency increased to approximately 56.4 ps. Although the latency increased significantly due to interconnect parasitic capacitance and RC effects, the circuit logic function remained correct, indicating that the method proposed in this invention can not only complete the modeling, schematic design, and layout implementation of dual-gate RFET devices, but also support the layout of the target logic circuit. Figure 1 Consistency verification, parasitic parameter extraction, and post-layout functionality and latency verification.

[0044] In a preferred embodiment, the aforementioned layout implementation, parasitic extraction, and post-layout verification processes can be completed on the basic environment provided by the ASAP7 open-source process design kit, thereby verifying the adaptability of the method described in this invention to existing open-source process design platforms.

Claims

1. A method for constructing a process design kit for a dual-gate reconfigurable field-effect transistor, characterized in that, Includes the following steps: Step 1: Construct a compact model of a dual-gate reconfigurable field-effect transistor (RFET). The RFET includes at least four ports: source (S), drain (D), control gate (CG), and polar gate (PG). The polar gate (PG) is used to modulate the source-drain Schottky barrier to achieve device polarity switching, and the control gate (CG) is used to regulate channel conduction and drive current. Step 2: Encapsulate the compact model into a SPICE sub-circuit compatible with the circuit simulator, establish the corresponding schematic symbols, parameterized attribute configurations and layout units, and form an extension module for the dual-gate reconfigurable field-effect transistor process design kit; Step 3: On the layout hierarchy, routing layer definition and basic verification environment provided by the open source process design kit, call the design extension module described in Step 2 to complete the layout design of the target logic unit; Step 4: Expand the device identification rules in the layout verification process to identify the four ports: source, drain, control gate, and polarity gate, and complete the consistency verification between the layout and the schematic. Step 5: Construct the interconnect technology file corresponding to the dual-gate reconfigurable field-effect transistor structure and integrate it into the parasitic parameter extraction process to extract the coupling parasitic parameters between device ports and the interconnect parasitic parameters; Step 6: Based on the layout obtained in Step 3, the layout verification results obtained in Step 4, and the parasitic parameter extraction results obtained in Step 5, perform post-layout simulation verification on the target logic circuit.

2. The construction method according to claim 1, characterized in that, The compact model described in step 1 adopts a behavior model based on artificial neural networks. By training the current-voltage and capacitance-voltage characteristics of the dual-gate RFET under different gate bias and device size conditions, a compact model that can simultaneously characterize IV and CV characteristics is obtained.

3. The construction method according to claim 2, characterized in that, The artificial neural network is trained using TCAD device simulation data. The training input includes at least the control gate bias voltage, polarity gate bias voltage, and device geometry. The training output includes at least the device leakage current and parasitic capacitance parameters between the device and the port.

4. The construction method according to claim 1, characterized in that, The SPICE sub-circuit described in step 2 adopts a four-port definition method, with the port order being source S, drain D, control gate CG, and polarity gate PG, in order to maintain consistency with the port correspondence between the layout and schematic consistency check results and the parasitic parameter extraction netlist.

5. The construction method according to claim 1, characterized in that, The layout design of the target logic cell in step 3 is carried out by designing the RFET layout of the target logic cell according to the standard cell height of 7.5T. Each RFET device adopts a two-fin structure to reserve independent wiring paths for the control gate and polarity gate within the limited cell height. Among them, the RFET devices configured as p-type equivalent and n-type equivalent are symmetrically arranged in the layout, and dummy fins are set at the cell boundaries to maintain fin density uniformity and layout manufacturability.

6. The construction method according to claim 1, characterized in that, The extended device identification rules in step 4 include: setting identification layers corresponding to control gates and polar gates respectively in the layout, and mapping the identification layers to control gate ports and polar gate ports respectively in the layout and schematic consistency check rule file.

7. The construction method according to claim 1, characterized in that, The interconnect technology document mentioned in step 5 is established based on the front-end cross-sectional structure of the dual-gate reconfigurable field-effect transistor. It includes at least descriptions of the active region, dual-gate structure, local interconnect structure, and the conductor and dielectric layers of the contact vias, thereby supporting the extraction of parasitic coupling parameters between the control gate and the polar gate, as well as between the dual gate and the source and drain.

8. The construction method according to claim 1, characterized in that, The target logic circuit described in step 6 includes at least an RFET inverter and reconfigurable NAND and NOR logic units. The reconfigurable NAND and NOR logic units switch between NAND and NOR functions without changing the circuit topology by applying a selection signal SEL to the polarity gate. When the selection signal SEL is in the first logic state, the corresponding RFET is configured with the first polarity to implement NAND logic; when the selection signal SEL is in the second logic state, the corresponding RFET is configured with the second polarity to implement NOR logic.

9. A process design kit for a dual-gate reconfigurable field-effect transistor constructed according to any one of claims 1 to 8, characterized in that, The process design suite includes an RFET compact model library, a schematic symbol library, a layout library, a parametric attribute configuration file, layout and schematic consistency check and identification rules, parasitic parameter extraction rules, and a back-annotation netlist interface for post-layout simulation. It can complete schematic design, layout implementation, design rule checking, layout and schematic consistency check, parasitic parameter extraction, and post-layout functional verification and timing simulation of dual-gate reconfigurable field-effect transistor circuits in a standard EDA environment.

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