A convolutional neural network accelerator with storage-computing cooperation
By using a co-designed in-memory computing convolutional neural network accelerator, the problems of separation between computing and storage and bandwidth limitations have been solved, achieving efficient acceleration of convolutional neural networks and improving computing throughput and energy efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-02-12
- Publication Date
- 2026-06-05
AI Technical Summary
Existing convolutional neural network processors suffer from problems such as separation of computation and storage, low efficiency of convolution operations, and limited on-chip memory bandwidth, resulting in high memory access overhead, low throughput, and poor energy efficiency.
Design a memory-computation co-operation convolutional neural network accelerator. Through the collaborative design of configuration unit, control unit, convolutional computation unit, vector computation unit, unified on-chip storage unit and arbitration unit, achieve tight coupling between computation and storage, and support parallel execution and high bandwidth access.
It improves computational throughput and storage bandwidth utilization, reduces data migration overhead, achieves efficient acceleration of convolutional neural networks, and reduces power consumption.
Smart Images
Figure CN122154791A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of humanoid robot technology, and in particular to a memory-computation collaborative convolutional neural network accelerator. Background Technology
[0002] Convolutional neural networks (CNNs) have been widely used in computer vision, object detection, semantic segmentation, and intelligent perception due to their excellent feature extraction capabilities. Their core computational modes include multi-channel convolution operations, channel-by-channel / point-by-point operations, and the generation and propagation of activation values between layers. The execution efficiency of these computational modes is a key factor determining the overall performance and energy efficiency of CNNs.
[0003] In practical hardware acceleration design, modern convolutional neural networks (CNNs) exhibit several significant characteristics to meet higher task requirements: a substantial increase in network depth, a large scale of both spatial resolution and channel number of feature maps, and an exponential increase in both the total number of model parameters and the amount of intermediate activation data. These characteristics collectively lead to extremely high computational density and memory access requirements for CNNs, making on-chip / off-chip memory access, data reuse efficiency, and data flow between computation and storage the main bottlenecks restricting accelerator performance and energy efficiency, constituting the main computational and storage overhead in the process of CNN hardware acceleration.
[0004] Existing neural network processors generally suffer from the following technical problems when performing convolutional neural network operations, which severely limit the speedup effect: 1. Separation of computation and storage: Convolution operation is characterized by high data reuse but frequent access. The computation unit and storage unit of the existing processor are separated, which leads to frequent data movement between on-chip and off-chip storage. This process not only consumes a lot of storage bandwidth, but also significantly increases memory access latency and dynamic power consumption, becoming the main bottleneck restricting the improvement of overall performance and energy efficiency. 2. Inefficient Convolution Operations: Existing processors typically do not directly support convolution operations. Instead, they convert convolution into matrix multiplication using methods such as im2col. This implementation requires data unrolling and rearranging of the input feature map, introducing additional data copying and storage access overhead. This not only further increases storage bandwidth pressure but also disrupts data locality, leading to decreased cache and on-chip storage utilization, thus limiting the performance and energy efficiency of convolution computations. 3. Limited on-chip memory bandwidth: The on-chip memory structure of existing processors usually adopts a design with limited ports and a small number of memory banks. When multiple computing units initiate read and write requests at the same time, memory access conflicts are likely to occur. At this time, access requests need to be processed through arbitration or serialization, which leads to a decrease in effective memory bandwidth. Computing units are forced to wait for memory access to be completed, thereby limiting the throughput of the overall system.
[0005] Therefore, there is an urgent need for a convolutional neural network accelerator architecture that can achieve close collaboration between computation and storage on-chip, support parallel execution of convolutional and vector computations, and have high-bandwidth storage access capabilities, in order to solve the above-mentioned problems in the existing technology and achieve high throughput and low power consumption hardware acceleration of convolutional neural networks. Summary of the Invention
[0006] The purpose of this invention is to overcome the problems of the prior art and provide a memory-computation co-processing convolutional neural network accelerator. This accelerator addresses the technical issues of existing neural network processors, such as the separation of computation and storage, low efficiency of convolution operations, and high memory access overhead, low throughput, and poor energy efficiency due to limited on-chip memory bandwidth. By co-designing the convolution computation unit, vector computation unit, and unified on-chip memory unit, and optimizing the functions of the configuration unit, control unit, and arbitration unit, the invention reduces data migration overhead, improves computational throughput, enhances memory bandwidth utilization and computational resource utilization, and achieves efficient acceleration for various convolutional neural network models.
[0007] The above objectives are achieved through the following technical solutions: A memory-computation co-processing convolutional neural network accelerator includes a configuration unit, a control unit, a convolution computation unit, a vector computation unit, a unified on-chip storage unit, and an arbitration unit. The configuration unit is connected to the control unit, the control unit is connected to the convolution computation unit, the vector computation unit, and the unified on-chip storage unit, the convolution computation unit and the vector computation unit are both connected to the unified on-chip storage unit, and the arbitration unit is connected to the unified on-chip storage unit, the convolution computation unit, and the vector computation unit.
[0008] In this embodiment, the configuration unit is used to configure the accelerator operating parameters. The accelerator operating parameters include the data precision used for convolution and vector calculations, the model structure parameters of the convolutional neural network, and the storage access parameters. The model structure parameters include the convolution kernel size, channel size, feature map size, and number of network layers. The configuration unit can receive configuration instructions from the host computer or external control module during the system startup phase or operation, and write the configuration parameters into the control unit or unified on-chip storage unit.
[0009] The control unit is used to acquire and transmit accelerator primitives, and to control and schedule the execution process of the convolution computation unit, vector computation unit, and unified on-chip storage unit according to the primitives. The control unit adopts a primitive-based scheduling mechanism. Each primitive describes a convolution computation, vector computation, or data transfer operation. The primitive has a 256-bit structure, with the lower 16 bits being the primitive encoding and the remaining bits being the data precision, model structure parameters, and the storage address of the unified on-chip storage unit at runtime. The control unit supports the convolution computation unit and vector computation unit to work in parallel and access the unified on-chip storage unit simultaneously, and can update the primitive pointers according to the execution status feedback of each computation unit, realizing the pipelined execution of computation and data operations.
[0010] The convolutional computation unit is used to perform convolutional operations of the convolutional neural network. It is constructed using a static data stream output method and includes an address generation unit, an input buffer module, a weight buffer module, and a multiply-accumulate array composed of multiple parallel processing units. The multiply-accumulate array has a size of 8*32. The input data type of the processing unit is INT8, and the output data type is INT32. In addition to a register for accumulating convolution results, each processing unit is also equipped with an additional set of registers to simultaneously store two sets of output feature map data and to alternately update the two sets of output feature map data at different computation stages. The address generation unit of the convolutional computation unit is used to generate enable signals, write enable signals, and corresponding access addresses for the unified on-chip storage unit according to the computation process, and to generate control signals for the input buffer module and the weight buffer module. The multiply-accumulate array is used to perform multiply-accumulate operations on the input feature map data and weight data output by the input buffer module and the weight buffer module, and to write the operation results back to the unified on-chip storage unit.
[0011] The vector computing unit is used to implement vector pointwise and reduction operations, including an address generation unit, an input cache module, an output cache module, a parallel adder array, a comparator array, and a pooling unit. Specifically, it is used to implement activation operations, pooling operations, and residual join operations. The vector computing unit supports a single instruction multiple data stream processing mode with data-level parallel computing, and its parallelism is matched with the read and write bandwidth of the unified on-chip memory unit to achieve high throughput operation.
[0012] The unified on-chip storage unit is used to store and transmit input data, weight data, and intermediate calculation results during convolution and vector calculations. It adopts a multi-storage design, consisting of a multi-storage random access memory, a crossbar switch, and the arbitration unit. It is configured with multiple ports that can be read and written in parallel, including read ports, write ports, and read-write ports, to realize the unified storage and transmission of input data, weight data, and intermediate calculation results, and to support tightly coupled access of the convolution and vector calculation units.
[0013] The arbitration unit is used to resolve conflicts when various computing units access the same on-chip storage unit. It sets priority rules for each type of port and defines the priority of ports of the same type. When multiple computing units or ports access the same random access memory at the same time, causing an access conflict, the arbitration unit responds to the access request of the port with the highest priority according to the priority rules, transmits the request signal, address and data to the corresponding random access memory, and returns the response signal and data to the port.
[0014] The accelerator of this invention can be deployed in application-specific integrated circuits or programmable logic devices to adapt to and accelerate convolutional neural network models with different numbers of layers, different kernel sizes and different channel scales. Furthermore, through the tight coupling design of the computing unit and the unified on-chip storage unit, the data transfer between on-chip storage and off-chip storage is reduced, thereby achieving high energy efficiency and low power consumption convolutional neural network computing.
[0015] This invention also discloses a method for operating the above-mentioned in-memory computation co-operational convolutional neural network accelerator, comprising the following steps: Step S1: The host computer configures the operating parameters of the accelerator's configuration unit via PCIe. The operating parameters include data precision, convolution kernel size, channel size, vector operation mode, and storage access method. The accelerator primitives used to describe convolution calculation, vector calculation, and data transfer operations are preset into the unified on-chip storage unit. The control unit initializes the primitive pointers and reads the primitive information from the unified on-chip storage unit according to the primitive order to determine the executable status of the corresponding computing unit. Step S2: When the control unit detects that the convolution computation primitive can be emitted, it sends a start signal to the convolution computation unit; under the control of the internal address generation unit, the convolution computation unit reads the input feature map data and weight data from the unified on-chip memory unit, performs convolution operation through the parallel multiply-accumulate array, and writes the convolution computation result back to the unified on-chip memory unit. Step S3: When the control unit detects that the vector computation primitive can be emitted, it sends a start signal to the vector computation unit; under the control of the internal address generation unit, the vector computation unit reads the data to be processed from the unified on-chip memory unit. The data to be processed may come from the output of the convolution computation unit. It uses a parallel adder array or comparator array to perform element-wise operations or reduction operations, including activation operations, pooling operations or residual concatenation operations, and writes the calculation results back to the unified on-chip memory unit to provide data for the execution of the next primitive. Step S4: After completing the corresponding primitive operation, each computing unit feeds back the execution status information to the control unit; the control unit updates the primitive pointer according to the feedback result and schedules the execution of the next primitive, realizing the pipelined and parallel execution of convolution calculation, vector calculation and data transfer operations.
[0016] The present invention provides a memory-computation co-operation convolutional neural network accelerator, which achieves tight coupling between computation and storage through the collaborative design of configuration control of convolution vector computation and unified on-chip storage arbitration unit, improves computational efficiency by directly executing convolution operations without data transformation, achieves high-bandwidth and low-conflict access to storage through multiple storage banks and priority arbitration mechanism, and achieves high-throughput and low-power convolutional neural network acceleration through parallel pipelined scheduling. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structural connections of a memory-computation collaborative convolutional neural network accelerator according to the present invention. The diagram shows the interconnection relationships between the configuration unit, unified on-chip storage unit, arbitration unit, control unit, convolutional computation unit, and vector computation unit. Figure 2 This is a diagram illustrating the primitive fields of a memory-computation collaborative convolutional neural network accelerator as described in this invention; Figure 3 This is a framework diagram of the convolutional computation unit of a memory-computation collaborative convolutional neural network accelerator according to the present invention; Figure 4 This is a framework diagram of the vector computation unit of a memory-computation collaborative convolutional neural network accelerator according to the present invention. Detailed Implementation
[0018] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] This solution provides a memory-computation co-processing convolutional neural network accelerator, such as... Figure 1 As shown, it includes a configuration unit, a control unit, a convolution calculation unit, a vector calculation unit, a unified on-chip storage unit, and an arbitration unit. The configuration unit is connected to the control unit, and the control unit is connected to the convolution calculation unit, the vector calculation unit, and the unified on-chip storage unit. The convolution calculation unit and the vector calculation unit are both connected to the unified on-chip storage unit. The arbitration unit is connected to the unified on-chip storage unit, the convolution calculation unit, and the vector calculation unit. Each unit achieves tight coupling and collaborative work through the above connection relationship, eliminating the defects of separation between computing and storage at the architecture level.
[0020] In this embodiment, the configuration unit is used to receive configuration instructions transmitted by the host computer via PCIe and configure the operating parameters of the accelerator. The operating parameters include the data precision (such as INT8, INT32) used for convolution and vector calculations, the model structure parameters of the convolutional neural network, and storage access parameters. The model structure parameters include the convolution kernel size, channel size, feature map size, and number of network layers. The configuration unit writes the configured operating parameters into the control unit or the unified on-chip storage unit to provide basic parameter support for the operation of the accelerator, enabling the accelerator to adapt to convolutional neural network models with different numbers of layers, different convolution kernel sizes, and different channel sizes.
[0021] The control unit is the scheduling core of the accelerator, employing a primitive-based scheduling mechanism. It retrieves and emits accelerator primitives from the unified on-chip memory unit, and performs unified control and scheduling of the execution processes of the convolution computation unit, vector computation unit, and unified on-chip memory unit based on these primitives. Figure 2 As shown, each primitive has a 256-bit structure. The lower 16 bits are the primitive encoding, and the remaining bits are the data precision, model structure parameters, and the storage address of the unified on-chip storage unit during runtime. Each primitive uniquely describes a convolution calculation, vector calculation, or data transfer operation. After the control unit initializes the primitive pointer, it reads the primitives in sequence and determines the executable status of the convolution calculation unit and the vector calculation unit. It supports the parallel operation of the two calculation units and simultaneous access to the unified on-chip storage unit. Based on the execution status feedback after each calculation unit completes its operation, it can update the primitive pointer in real time and schedule the execution of the next primitive, realizing the pipelining and parallel execution of convolution calculation, vector calculation, and data transfer operations.
[0022] like Figure 3 As shown, the convolution computation unit is constructed using a static data stream output method and is the core unit for performing convolution operations. It includes an address generation unit (AGU), an input buffer module (Ifmap Buffer), a weight buffer module (Weight Buffer), and a multiply-accumulate array (MAC) composed of multiple parallel processing units (PEs). In this embodiment, the size of the multiply-accumulate array (MAC) is 832, which means it contains 832 parallel processing units (PEs). The input data type of each processing unit (PE) is INT8, and the output data type is INT32. It can directly perform convolution operations in the form of multiply-accumulate without the need for convolution conversion through methods such as im2col, thus fundamentally eliminating the additional overhead caused by data unrolling and rearrangement.
[0023] Each processing unit (PE) is equipped with a register for accumulating convolution results, and an additional set of registers to simultaneously store two sets of output feature map (Ofmap) data. During convolution calculation, the two sets of output feature map data are updated alternately, enabling parallel or interleaved execution of multiple convolution calculations. This significantly improves the reuse rate of input feature maps, reduces redundant data readings, and thus improves the throughput of convolution calculations. The address generation unit (AGU) of the convolution calculation unit generates enable signals, write enable signals, and corresponding access addresses for the unified on-chip storage unit in real time according to the convolution calculation process. It also generates control signals for the input buffer module Ifmap Buffer and the weight buffer module Weight Buffer, enabling accurate and efficient reading of input feature map data and weight data from the unified on-chip storage unit to the buffer modules. The multiply-accumulate array (MAC) performs multiply-accumulate operations on the input feature map data and weight data output from the input buffer module Ifmap Buffer and the weight buffer module Weight Buffer. After completing the convolution operation, the operation result is written back to the unified on-chip storage unit.
[0024] like Figure 4 As shown, the vector computation unit is used to implement vector pointwise and reduction operations, specifically including activation operation, pooling operation and residual join operation. It consists of address generation unit AGU, input cache module, output cache module, parallel adder array ADD, comparator array Compare and pooling unit Pooling. The vector computation unit supports data-level parallel computing in single instruction multiple data stream (SIMD) processing mode, and its parallelism is precisely matched with the read and write bandwidth of the unified on-chip memory unit, avoiding idle computing unit or bandwidth waste, and achieving high throughput operation.
[0025] During residual join operations, the control unit sends residual join primitives to the vector computation unit. The address generation unit (AGU) generates initial data addresses for two input vectors and control signals. Input data is read from the unified on-chip memory unit into the input buffer module. The parallel adder array (ADD) performs element-wise addition on the input data and stores the results in the output buffer module. The address generation unit (AGU) then writes the results to the corresponding location in the unified on-chip memory unit according to the target address. The control unit repeats the above steps according to the state machine and the primitive termination condition to complete the residual join operation. During activation and pooling operations, the comparator array (Compare) and the pooling unit (Pooling) work together to complete the corresponding operations, and the results are also written back to the unified on-chip memory unit.
[0026] The unified on-chip storage unit is the unified data storage core of the accelerator, used to store and transfer input data, weight data, and all intermediate calculation results during convolution and vector calculations. It adopts a multi-bank design, consisting of Multibank RAM (Multi-bank Random Access Memory), crossbar switches, and arbitration units. It is configured with multiple ports that can be read and written in parallel, including read ports, write ports, and read-write ports. Through the design of multiple storage banks and multiple parallel ports, the overall read and write bandwidth is significantly improved, meeting the parallel memory access requirements of the convolution and vector calculation units, and supporting tightly coupled access between the two calculation units, reducing the movement of data between on-chip and off-chip storage.
[0027] The arbitration unit is used to resolve conflicts when various computing units access the same on-chip memory. It sets priority rules for three types of ports: read ports, write ports, and read-write ports, and defines the priority of ports of the same type. When convolution computing units and vector computing units access the same on-chip memory simultaneously, or when multiple ports access the same Multibank RAM simultaneously, causing an access conflict, the arbitration unit selects the access request according to the preset priority rules. It only responds to the access request of the port with the highest priority, transmits the signal, address, and data of the request to the corresponding Multibank RAM, and returns a response signal and data to the port. This makes the access request of the higher-priority computing unit effective, eliminates the drawbacks of serialized memory access processing, and improves the effective storage bandwidth.
[0028] The accelerator in this embodiment can be deployed on an application-specific integrated circuit or a programmable logic device, and its operation method includes the following steps: Step S1: The host computer configures the operating parameters of the accelerator's configuration unit via PCIe. The configured parameters include data precision, convolution kernel size, channel size, vector operation mode, and storage access method. The accelerator primitives used to describe convolution calculation, vector calculation, and data transfer operations are pre-loaded into the unified on-chip storage unit. The control unit initializes the primitive pointers and reads the primitive information from the unified on-chip storage unit according to the primitive order to determine the executable status of the convolution calculation unit and the vector calculation unit. Step S2: When the control unit detects that the convolution calculation primitive can be emitted, it sends a start signal to the convolution calculation unit; under the control of the internal address generation unit AGU, the convolution calculation unit reads the input feature map data and weight data from the unified on-chip storage unit, inputs them to the multiply-accumulate array MAC to perform convolution operation, and writes the convolution calculation result back to the unified on-chip storage unit in a timely manner. Step S3: When the control unit detects that the vector computation primitive can be emitted, it sends a start signal to the vector computation unit. Under the control of the internal address generation unit AGU, the vector computation unit reads the data to be processed from the unified on-chip memory unit. The data to be processed can come directly from the output result of the convolution computation unit. The parallel adder array ADD or comparator array Compare is used to perform element-wise operations or reduction operations, such as activation operations, pooling operations or residual connection operations, and the calculation results are written back to the unified on-chip memory unit to provide data support for the execution of the next primitive. Step S4: After completing the corresponding primitive operation, the convolution calculation unit and the vector calculation unit respectively report the execution status information to the control unit; the control unit updates the primitive pointer in real time according to the feedback results of each calculation unit and schedules the execution of the next primitive. This process is repeated to realize the pipelined and parallel execution of convolution calculation, vector calculation and data transfer operations.
[0029] The in-memory computing co-operational convolutional neural network accelerator in this embodiment, through the above-described structural design and operation method, achieves parallel execution of convolutional computation and vector computation while ensuring functional correctness. This reduces data movement between computing units and storage units, improves the resource utilization of convolutional computation and vector computation, and enhances the bandwidth utilization efficiency of the unified on-chip storage unit, thereby achieving high-throughput, low-power convolutional neural network accelerated computation.
[0030] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A memory-computation co-processing convolutional neural network accelerator, characterized in that, It includes a configuration unit, a control unit, a convolution calculation unit, a vector calculation unit, a unified on-chip storage unit, and an arbitration unit; the configuration unit is connected to the control unit, the control unit is connected to the convolution calculation unit, the vector calculation unit, and the unified on-chip storage unit respectively, the convolution calculation unit and the vector calculation unit are both connected to the unified on-chip storage unit, and the arbitration unit is connected to the unified on-chip storage unit, the convolution calculation unit, and the vector calculation unit; The configuration unit is used to configure the accelerator operating parameters; The control unit is used to acquire and transmit accelerator primitives, and to schedule each unit to perform operations according to the primitives; The convolution computation unit is used to perform convolution operations in a convolutional neural network; The vector calculation unit is used to perform vector pointwise and reduction operations; The unified on-chip storage unit is used to store and transmit input data, weight data, and intermediate calculation results during convolution and vector calculation processes; The arbitration unit is used to resolve conflicts between computing units accessing a unified on-chip storage unit.
2. The in-memory computing co-operational convolutional neural network accelerator according to claim 1, characterized in that, The accelerator operating parameters configured by the configuration unit include the data precision used for convolution and vector computation, the model structure parameters of the convolutional neural network, and the storage access parameters. The model structure parameters include the convolution kernel size, channel size, feature map size, and number of network layers.
3. The in-memory computing co-operational convolutional neural network accelerator according to claim 1, characterized in that, The control unit employs a primitive-based scheduling mechanism. Each primitive describes a convolution calculation, vector calculation, or data transfer operation. The primitive has a 256-bit structure, with the lower 16 bits representing the primitive encoding and the remaining bits representing data precision, model structure parameters, and the storage address of the unified on-chip storage unit during runtime. The control unit supports the convolution calculation unit and the vector calculation unit to work in parallel and access the unified on-chip storage unit simultaneously. It can also update the primitive pointer based on the execution status feedback of each calculation unit, thereby realizing the pipelined execution of computation and data operations.
4. The in-memory computing co-operational convolutional neural network accelerator according to claim 1, characterized in that, The convolutional computation unit is constructed using a static output data stream approach, including an address generation unit, an input buffer module, a weight buffer module, and a multiply-accumulate array composed of multiple parallel processing units. The size of the multiply-accumulate array is 8*32. The input data type of the processing unit is INT8, and the output data type is INT32. In addition to a register for accumulating the convolutional result, each processing unit is also equipped with an additional set of registers to simultaneously store two sets of output feature map data and to alternately update the two sets of output feature map data at different computation stages.
5. The in-memory computation co-operational convolutional neural network accelerator according to claim 4, characterized in that, The address generation unit of the convolution calculation unit is used to generate an enable signal, a write enable signal and a corresponding access address for the unified on-chip storage unit according to the calculation process, and at the same time generate control signals for the input buffer module and the weight buffer module; the multiply-accumulate array is used to perform multiply-accumulate operations on the input feature map data and weight data output by the input buffer module and the weight buffer module, and write the operation result back to the unified on-chip storage unit.
6. The in-memory computing co-operational convolutional neural network accelerator according to claim 1, characterized in that, The vector computing unit includes an address generation unit, an input cache module, an output cache module, a parallel adder array, a comparator array, and a pooling unit, used to implement activation operations, pooling operations, and residual join operations; the vector computing unit supports a single instruction multiple data stream processing mode with data-level parallel computing, and its parallelism matches the read and write bandwidth of the unified on-chip memory unit.
7. The in-memory computing co-operational convolutional neural network accelerator according to claim 1, characterized in that, The unified on-chip storage unit adopts a multi-bank design, consisting of a multi-bank random access memory, a crossbar switch, and the arbitration unit. It is configured with multiple ports that can be read and written in parallel, including read ports, write ports, and read-write ports, which are used to realize the unified storage and transmission of input data, weight data, and intermediate calculation results, and support tight-coupled access of the convolution calculation unit and the vector calculation unit.
8. The in-memory computing co-operational convolutional neural network accelerator according to claim 7, characterized in that, The arbitration unit sets priority rules for each type of port and defines the priority of ports of the same type. When multiple computing units or ports access the same random access memory at the same time, causing an access conflict, the arbitration unit responds to the access request of the port with the highest priority according to the priority rules, transmits the request signal, address and data to the corresponding random access memory, and returns the response signal and data to the port.
9. The in-memory computing co-operational convolutional neural network accelerator according to claim 1, characterized in that, The accelerator can be deployed in application-specific integrated circuits or programmable logic devices to adapt to and accelerate convolutional neural network models with different numbers of layers, different kernel sizes, and different channel scales.
10. A memory-computation co-operational convolutional neural network accelerator according to any one of claims 1-9, characterized in that, The convolutional computation unit and the vector computation unit are tightly coupled with the unified on-chip storage unit to reduce the movement of data between on-chip storage and off-chip storage, thereby achieving high-efficiency and low-power convolutional neural network computation.