Scan driver and electronic device including the same

Abstract

A scan driver and an electronic device including the same are provided. The scan driver includes a stage configured to output a scan signal, wherein an nth stage among the stages includes a voltage charging part connected to a first power line and a second power line and configured to transfer a voltage of the first power line to a first output control node in response to a first carry signal from an (n-1)th stage among the stages, and configured to transfer a voltage of the second power line to the first output control node in response to a voltage of a second output control node, a voltage reset part including a transistor connected in series between the first output control node and a third power line and configured to reset the voltage of the first output control node, and a scan signal output part configured to output one or more of the scan signals in response to the voltage of the second output control node.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0177337, filed on December 3, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Various embodiments of this disclosure relate to a scan driver and an electronic device including the scan driver. Background Technology

[0003] With the development of information technology, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various display devices, such as liquid crystal displays, organic light-emitting diode displays, and plasma displays, has increased.

[0004] The display device includes a display panel, a scan driver, and a data driver. The display panel includes pixels. The scan driver sequentially applies scan signals to scan lines connected to rows of pixels. The data driver applies data signals to data lines connected to columns of pixels. For example, the scan driver can select pixels to which data voltage will be supplied. The scan driver can be constructed as a shift register to sequentially provide on-level scan signals on a scan-line basis.

[0005] The above description is intended only to provide background art for understanding the technical spirit of this disclosure and should not be construed as prior art known to those skilled in the art constituting this disclosure. Summary of the Invention

[0006] Various embodiments of this disclosure relate to a scan driver with improved reliability and an electronic device including the scan driver. For example, the scan driver may include multiple stages, and a first output control node (or CQS (Common Qnode Switch) node) of each of the multiple stages may be charged to a high voltage level and may be reset based on the voltage of a second node (or QB node) of the current stage and the voltage of a second node of the next stage. Therefore, the operation of the scan driver can be simplified, and the scan driver can have improved reliability.

[0007] A scan driver according to one or more embodiments of the present disclosure includes a stage configured to output a scan signal, wherein the nth stage (n is an integer greater than 1) includes: a voltage charging section connected to a first power line and a second power line and configured to transmit a voltage of the first power line to a first output control node in response to a first carry signal from the (n-1)th stage, and configured to transmit a voltage of the second power line to the first output control node in response to a voltage of the second output control node; a voltage reset section including a transistor connected in series between the first output control node and a third power line and configured to reset the voltage of the first output control node; and a scan signal output section configured to output one or more scan signals in response to a voltage of the second output control node.

[0008] The voltage charging section may include: a first transistor connected between a first power line and a first output control node, and having a gate electrode connected to a first carry line configured to receive a first carry signal; a second transistor connected between a second power line and the first output control node, and having a gate electrode connected to the second output control node; and a first capacitor connected between the first power line and the first output control node.

[0009] The series-connected transistors may include: a third transistor connected between the first output control node and the third power line, and having a gate electrode connected to a second node of the nth stage; and a fourth transistor connected between the third transistor and the third power line, and having a gate electrode connected to a second node of the (n+1)th stage in the stage, wherein the third transistor and the fourth transistor are configured to turn on in response to the voltage of the second node of the nth stage and the voltage of the second node of the (n+1)th stage, respectively, such that the first output control node has the voltage of the third power line.

[0010] One of the scan signal output sections can be connected to the scan clock line and can be configured to output the signal of the scan clock line as a scan signal according to the voltage of the second output control node.

[0011] One of the scan signal output sections may include: a fifth transistor connected between the first node and the third node, and having a gate electrode connected to the first output control node; a second capacitor connected between the third node and the second output control node; a sixth transistor connected between the scan clock line and the scan line, and having a gate electrode connected to the third node; and a seventh transistor connected between the scan line and the third power line, and having a gate electrode connected to the second node of the nth stage.

[0012] The nth stage may also include an eighth transistor configured to transmit a boost clock signal to a second output control node in response to the voltage of the first node, so as to boost the voltage of the third node through a second capacitor.

[0013] The nth stage may also include: a boost controller configured to transmit a boost clock signal to a second output control node in response to the voltage of the first node, and to increase the voltage of the first node according to the boost clock signal.

[0014] The nth stage may include: an eighth transistor connected between the boost clock line and the second output control node, and having a gate electrode connected to the first node; a third capacitor connected between the gate electrode of the eighth transistor and the second output control node; and a ninth transistor connected between the second output control node and the fourth power line, and having a gate electrode connected to the second node.

[0015] The nth stage may further include: a carry signal output section connected between the carry clock line and the fourth power line, configured to output the carry clock line signal as the second carry signal in response to the voltage of the first node, and configured to output the voltage of the fourth power line as the second carry signal in response to the voltage of the second node.

[0016] A scan driver according to one or more embodiments of the present disclosure includes stages configured to output scan signals, wherein the nth stage includes: a first transistor having a first electrode connected to a first power line, a second electrode connected to a first output control node, and a gate electrode connected to a first carry line, the first carry line being connected to the (n-1)th stage; a second transistor having a first electrode connected to a second power line, a second electrode connected to a first output control node, and a gate electrode connected to a second output control node; a first capacitor connected between the first power line and the first output control node; a transistor connected in series between the first output control node and a third power line; and a scan signal output portion configured to output one or more scan signals in response to a voltage of the second output control node, wherein n is an integer greater than 1.

[0017] The voltage of the first electric field line can be higher than the voltage of the second electric field line.

[0018] The nth stage may further include: a tenth transistor having a first electrode connected to a carry clock line, a second electrode connected to a second carry line, and a gate electrode connected to a first node, the second carry line being connected to the (n-1)th and (n+1)th stages in the stage; and an eleventh transistor having a first electrode connected to a second carry line, a second electrode connected to a fourth power line, and a gate electrode connected to a second node.

[0019] The series-connected transistors may include: a third transistor connected between the first output control node and the third power line, and having a gate electrode connected to a second node of the nth stage; and a fourth transistor connected between the third transistor and the third power line, and having a gate electrode connected to a second node of the (n+1)th stage, wherein the third transistor and the fourth transistor are configured to turn on in response to the voltage of the second node of the nth stage and the voltage of the second node of the (n+1)th stage, respectively, such that the voltage of the first output control node has the voltage of the third power line.

[0020] One of the scan signal output sections may include: a fifth transistor connected between the first node and the third node, and having a gate electrode connected to the first output control node; a second capacitor connected between the third node and the second output control node; a sixth transistor connected between the scan clock line and the scan line, and having a gate electrode connected to the third node; and a seventh transistor connected between the scan line and the third power line, and having a gate electrode connected to the second node of the nth stage.

[0021] An electronic device including a scan driver according to one or more embodiments of the present disclosure includes: a display panel including scan lines and pixels connected to the scan lines; a processor configured to provide input image data; a controller configured to receive the input image data from the processor and configured to drive the display panel; and a scan driver configured to supply scan signals to the display panel and including a stage configured to output scan signals to the scan lines, the nth stage including: a voltage charging portion connected to a first power line and a second power line and configured to transmit a voltage of the first power line to a first output control node in response to a first carry signal from the (n-1)th stage, and configured to transmit a voltage of the second power line to the first output control node in response to a voltage of the second output control node; a voltage reset portion including a transistor connected in series between the first output control node and a third power line and configured to reset the voltage of the first output control node; and a scan signal output portion configured to output one or more scan signals in response to a voltage of the second output control node, wherein n is an integer greater than 1.

[0022] The voltage of the first output control node can be configured to fluctuate via one of the first carry signal of the (n-1)th stage, the voltage of the second output control node, and the voltage of the second node of the (n+1)th stage.

[0023] The voltage of the first power line can be configured to be applied as the voltage of the first output control node, and the voltage of the second power line can be configured to be applied as the voltage of the first output control node in response to the voltage of the second output control node.

[0024] The voltage of the first output control node can be configured to have the voltage of the third power line in response to the voltage of the second node of the nth stage and the voltage of the second node of the (n+1)th stage in the stage.

[0025] The nth stage can be configured to transmit a boost clock signal to the second output control node in response to the voltage of the first node, and can be configured to increase the voltage of the first node according to the boost clock signal transmitted to the second output control node.

[0026] The third node can be configured to be electrically isolated from the first node based on the voltage of the first node and the voltage of the first output control node. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating one or more embodiments of a display device.

[0028] Figure 2 yes Figure 1 A schematic diagram of the equivalent circuit of one or more embodiments of one of the sub-pixels.

[0029] Figure 3 It is shown that it includes Figure 1 A block diagram of one or more embodiments of a scan driver in a display device.

[0030] Figure 4 It is shown that it includes Figure 3 A block diagram of one or more embodiments of a level in a scan driver.

[0031] Figure 5 yes Figure 4 A schematic diagram of the equivalent circuit of one or more embodiments of the level.

[0032] Figure 6 and Figure 7 It is shown Figure 5 Timing diagrams of one or more embodiments of the level of operation.

[0033] Figure 8 This is a schematic block diagram illustrating one or more embodiments of an electronic device including a scan driver according to one or more embodiments of the present disclosure. Detailed Implementation

[0034] Aspects of some embodiments of this disclosure and their implementation methods can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for those skilled in the art to fully understand aspects of this disclosure, may be omitted. Throughout the drawings and written description, unless otherwise stated, the same reference numerals, symbols, or combinations thereof indicate the same elements, and therefore their repeated description may be omitted.

[0035] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of "can," "may," or "may not" corresponds to one or more embodiments of this disclosure.

[0036] Those skilled in the art will understand that, in view of the completeness of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or in combination with each other, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently or in combination with each other in any suitable manner.

[0037] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operably, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, it can be directly formed on, directly on, directly connected to, or directly incorporated into the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into the other component, layer, region, or assembly, such that one or more intermediary components, intermediary layers, intermediary regions, or intermediary assemblies may exist. Furthermore, this can uniformly refer to direct or indirect incorporation or connection, as well as integral or non-integral incorporation or connection.

[0038] For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, it can be directly electrically connected or directly bonded to said other layer, region, and / or component, or one or more intermediary layers, intermediary regions, or intermediary components may exist. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on" means that one component is directly connected to or directly bonded to another component or directly on another component, without any intermediate components.

[0039] Similarly, other expressions describing relationships between components can be interpreted in a similar way, such as "between," "directly between," or "adjacent to" and "directly adjacent to." It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or intervening layers.

[0040] For the purposes of this disclosure, when expressions such as “at least one of…” or “any one of…” or “one or more of…” follow a list of elements, they modify the entire list of elements, not the individual elements listed. For example, “at least one of X, Y, and Z” and “at least one of the groups consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of…”, “multiple…”, “one of…”, and other prepositional phrases before / after a list of elements modify the entire list, not the individual elements listed. When “C to D” is stated, unless otherwise specified, it means C or greater and D or less.

[0041] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, section, or part from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, first assembly, first region, first layer, or first part described below may be referred to as a second element, second assembly, second region, second layer, or second part. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For brevity, the terms “first,” “second,” etc., may respectively mean “first category (or first group),” “second category (or second group),” etc.

[0042] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms, and the plural forms are intended to include the singular forms. It will also be understood that when the terms “comprising,” “including,” “having,” “owning,” and variations thereof are used in this specification, they specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0043] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0044] As used herein, the terms “basically,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “basically” can include a range of + / - 5% of the corresponding value. As used herein, “about” or “approximately” includes the stated value and indicates an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “is the same” can mean “is substantially the same.” In other words, the expression “is the same” can include a range acceptable to one of ordinary skill in the art. Other expressions may also be derived from those that omit “basically.”

[0045] In some embodiments, known structures and devices may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wire connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. Furthermore, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Additionally, in some embodiments, blocks, units, and / or modules may be physically separated into two or more interactive individual blocks, units, and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, without departing from the scope of this disclosure, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or the context (background) of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0047] Figure 1 This is a block diagram illustrating one or more embodiments of a display device DD.

[0048] Reference Figure 1 The display device DD may include a display panel DP, a controller 110, a scan driver 120, and a data driver 130.

[0049] The display panel DP may include sub-pixels SP. Sub-pixels SP may be connected to scan driver 120 via first scan line SL1 to p-th scan line SLp (p is an integer greater than 1). Sub-pixels SP may be connected to data driver 130 via first data line DL1 to q-th data line DLq (q is an integer greater than 1).

[0050] Subpixels (SPs) can generate light of two or more colors. For example, each subpixel SP can generate light of colors such as red, green, blue, cyan, magenta, and yellow.

[0051] Two or more sub-pixels SP can form a single pixel PXL. For example, pixel PXL can include, for example, Figure 1 The three sub-pixels SP are shown in the diagram. Thus, pixel PXL can emit light of various colors and brightnesses based on the combination of light emitted from the sub-pixels SP included therein.

[0052] The controller 110 can control the overall operation of the display device DD. The controller 110 can receive input image data IMG and corresponding control signal CTRL from an external source. The controller 110 can provide scan control signal SCS and data control signal DCS in response to the control signal CTRL.

[0053] The controller 110 can convert the input image data IMG into a format suitable for a display device DD or a display panel DP, and can output image data DATA. In an embodiment, the controller 110 can align the input image data IMG to a format suitable for sub-pixels SP in rows, and output image data DATA.

[0054] Scan driver 120 can be connected to sub-pixels SP arranged in the row direction via first scan lines SL1 to p-th scan lines SLp. Scan driver 120 can output scan signals to first scan lines SL1 to p-th scan lines SLp in response to scan control signal SCS. In an embodiment, scan control signal SCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, etc.

[0055] The scan driver 120 may be arranged on one side of the display panel DP. However, the embodiments are not limited to this. For example, the scan driver 120 may be separated into two or more physically and / or logically separated drivers, and such drivers may be positioned on one side of the display panel DP and on the opposite side of the display panel DP, respectively. Thus, the scan driver 120 may be positioned around the display panel DP in various forms depending on the embodiment.

[0056] Data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to q-th data lines DLq. Data driver 130 can receive image data DATA and data control signal DCS from controller 110. Data driver 130 can operate in response to data control signal DCS. In an embodiment, data control signal DCS may include source start signal, source shift clock, source output enable signal, etc.

[0057] The data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the qth data lines DLq. When a scan signal is applied to each of the first scan lines SL1 to the pth scan line SLp, the data signal corresponding to the image data DATA can be applied to the first data lines DL1 to the qth data lines DLq. Therefore, the sub-pixel SP can generate light corresponding to the data signal, and the display panel DP can display the image.

[0058] In an embodiment, scan driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit devices.

[0059] Components of the data driver 130 and the controller 110 may be mounted on a single integrated circuit. In one or more embodiments, the data driver 130 and the controller 110 may be included in a driver integrated circuit (DIC). In this case, the data driver 130 and the controller 110 may be functionally different components within a single driver integrated circuit (DIC).

[0060] Figure 2 yes Figure 1 A schematic diagram of the equivalent circuit of one or more embodiments of one of the sub-pixels SP.

[0061] exist Figure 2 The example shown is a sub-pixel SPij arranged in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to p) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to q).

[0062] Reference Figure 2Subpixel SPij may include subpixel circuit SPC and light-emitting device LD.

[0063] The light-emitting device (LD) can be connected between a first driving power node VDDN and a second driving power node VSSN. The first driving power node VDDN can receive a first driving voltage. The second driving power node VSSN can receive a second driving voltage. The first driving voltage can have a higher voltage level than the second driving voltage.

[0064] A light-emitting device (LD) can be connected between an anode (AE) and a cathode (CE). The anode (AE) can be connected to a first driving power node (VDDN) via a sub-pixel circuit (SPC). For example, the anode (AE) can be connected to the first driving power node (VDDN) via one or more transistors included in the sub-pixel circuit (SPC). The cathode (CE) can be connected to a second driving power node (VSSN). The LD can be configured to emit light in response to a current flowing from the anode (AE) to the cathode (CE).

[0065] Sub-pixel circuits (SPCs) can be connected to Figure 1 The first scan line SL1 to the p-th scan line SLp, and connected to the i-th scan line SLi. Figure 1 The first data line DL1 to the qth data line DLq includes the j-th data line DLj. In response to a scan signal received via the i-th scan line SLi, the sub-pixel circuit SPC can control the light-emitting device LD to emit light based on the data signal received via the j-th data line DLj. For the above operation, the sub-pixel circuit SPC may include circuit devices such as transistors and one or more capacitors.

[0066] The transistors in the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors in the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, the transistors in the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon, polycrystalline silicon, oxide semiconductors, etc.

[0067] Reference Figure 2 The gate electrode of the first transistor M1 can be connected to the i-th scan line SLi, the first electrode can be connected to the j-th data line DLj, and the second electrode can be connected to one electrode (or node Na) of the storage capacitor Cst. The first transistor M1 can be referred to as the scan transistor.

[0068] The gate electrode of the second transistor M2 can be connected to the second electrode of the first transistor M1, the first electrode can be connected to the first driving power node VDDN, and the second electrode can be connected to the anode AE ​​of the light-emitting device LD. The second transistor M2 can be referred to as the driving transistor.

[0069] One electrode of the storage capacitor Cst can be connected to the gate electrode of the second transistor M2, and the other electrode can be connected to the first drive power node VDDN.

[0070] The anode AE ​​of the light-emitting device LD can be connected to the second electrode of the second transistor M2, and the cathode CE can be connected to the second drive power node VSSN.

[0071] According to one or more embodiments, when a scan signal with a conduction level (here, low level) is applied through the i-th scan line SLi, the first transistor M1 can be turned on. At this time, the data voltage applied to the j-th data line DLj can be stored in the storage capacitor Cst.

[0072] The driving current corresponding to the voltage difference between the electrodes of the storage capacitor Cst can flow between the first and second electrodes of the second transistor M2. Therefore, the light-emitting device LD can emit light with a brightness corresponding to the data voltage.

[0073] Then, when a scan signal with a cutoff level (here, high level) is applied through the i-th scan line SLi, the first transistor M1 can be turned off, and the j-th data line DLj can be electrically isolated from one electrode of the storage capacitor Cst. Therefore, even when the data voltage of the j-th data line DLj fluctuates, the voltage on one electrode of the storage capacitor Cst can remain stable.

[0074] The embodiments of this disclosure can be applied not only to Figure 2 The sub-pixel SPij shown can also be applied to sub-pixels having another sub-pixel circuit according to the prior art.

[0075] Figure 3 It is shown that it includes Figure 1 Block diagram of one or more embodiments of the scan driver 120 in the display device DD.

[0076] Reference Figure 3 The scan driver 120 may include multiple levels ST1 to ST(n+1) (or scan levels). Levels ST1 to ST(n+1) may correspond to or be connected to... Figure 1 The first scan line SL1 to the p-th scan line SLp.

[0077] Levels ST1 to ST(n+1) can be connected to the first scan clock line SKL1 to the sixth scan clock line SKL6 (see...) Figure 5 ), carry clock line CKL (see) Figure 5 ) and boost clock line BKL (see Figure 5The first scan clock line SKL1 to the sixth scan clock line SKL6, the carry clock line CKL, and the boost clock line BKL can be supplied with input signals for stages ST1 to ST(n+1).

[0078] The first scan clock signals SCK1 to the sixth scan clock signals SCK6 can be applied to stages ST1 to ST(n+1) respectively via the first scan clock line SKL1 to the sixth scan clock line SKL6. One of the carry clock signals CRK1 and CRK2 can be applied to stages ST1 to ST(n+1) via the carry clock line CKL. For example, the first carry clock signal CRK1 can be applied to odd-numbered stages via the carry clock line CKL. The second carry clock signal CRK2 can be applied to even-numbered stages via the carry clock line CKL. One of the boost clock signals BCK1 and BCK2 can be applied to stages ST1 to ST(n+1) via the boost clock line BKL. For example, the first boost clock signal BCK1 can be applied to odd-numbered stages via the boost clock line BKL. The second boost clock signal BCK2 can be applied to even-numbered stages via the boost clock line BKL.

[0079] Levels ST1 to ST(n+1) can be respectively connected via the first electric line PL1 (see...) Figure 5 ), second power line PL2 (see Figure 5 ), third power line PL3 (see Figure 5 ) and the fourth power line PL4 (see Figure 5 The device receives a first power voltage VGH1, a second power voltage VGH2, a third power voltage VGL1, and a fourth power voltage VGL2. These voltages can be supplied from a power source located external to the scan driver 120. In an embodiment, the first power voltage VGH1 may have a higher voltage level than the second power voltage VGH2, and the third power voltage VGL1 may have a lower voltage level than the second power voltage VGH2. The fourth power voltage VGL2 may have a lower voltage level than the third power voltage VGL1. For example, the first power voltage VGH1 may be approximately 25V, the second power voltage VGH2 may be approximately 15V, the third power voltage VGL1 may be approximately -5V, and the fourth power voltage VGL2 may be approximately -9V. However, the embodiment is not limited to these.

[0080] Each of stages ST1 to ST(n+1) can be connected to the previous and subsequent stages via carry lines. The second node QB[n] of each of stages ST1 to ST(n+1) (see...) Figure 5 It can be connected to the previous stage.

[0081] The first stage ST1 can receive the scan start signal FLM (or start pulse) as the carry signal of the previous stage. The first stage ST1 can receive the carry signal CR[2] of the second stage ST2. The first stage ST1 can receive the voltage QBV[2] of the second node of the second stage ST2. The first stage ST1 can output the carry signal CR[1] and the first scan signal SC1[1] to the sixth scan signal SC6[1] generated by the first stage ST1.

[0082] The second stage ST2 can receive the carry signal CR[1] from the first stage ST1 and the carry signal CR[3] from the third stage ST3. The second stage ST2 can receive the voltage QBV[3] of the second node of the third stage ST3. The second stage ST2 can output the carry signal CR[2] and the first scan signal SC1[2] to the sixth scan signal SC6[2] generated by the second stage ST2. The second stage ST2 can output the voltage QBV[2] of the second node.

[0083] The (n-1)th stage ST(n-1) can receive the carry signal CR[n-2] from the previous stage and the carry signal CR[n] from the nth stage STn. The (n-1)th stage ST(n-1) can receive the voltage QBV[n] of the second node of the nth stage STn. The (n-1)th stage ST(n-1) can output the carry signal CR[n-1] and the first scan signal SC1[n-1] to the sixth scan signal SC6[n-1] generated by the (n-1)th stage ST(n-1). The (n-1)th stage ST(n-1) can output the voltage QBV[n-1] of the second node.

[0084] The nth stage STn can receive the carry signal CR[n-1] from the (n-1)th stage ST(n-1) and the carry signal CR[n+1] from the (n+1)th stage ST(n+1). The nth stage STn can receive the voltage QBV[n+1] of the second node of the (n+1)th stage ST(n+1). The nth stage STn can output the carry signal CR[n] generated by the nth stage STn and the first scan signal SC1[n] to the sixth scan signal SC6[n]. The nth stage STn can output the voltage QBV[n] of the second node.

[0085] The (n+1)th stage ST(n+1) can receive the carry signal CR[n] from the nth stage STn and the carry signal CR[n+2] from subsequent stages. The (n+1)th stage ST(n+1) can also receive the voltage QBV[n+2] of the second node from subsequent stages. The (n+1)th stage ST(n+1) can output the carry signal CR[n+1] generated by the (n+1)th stage ST(n+1) and the first scan signal SC1[n+1] to the sixth scan signal SC6[n+1]. The (n+1)th stage ST(n+1) can also output the voltage QBV[n+1] of the second node.

[0086] For example, when stage (n+1) is the last stage, stage (n+1) may not receive carry signals from subsequent stages or voltage from the second node. When stage (n+1) is the last stage, a dummy stage can be added to provide carry signals from subsequent stages and voltage from the second node.

[0087] Figure 4 It is shown that it includes Figure 3 A block diagram of one or more embodiments of level STn in the scan driver 120.

[0088] Figure 4 The nth level STn is shown (where n is a positive integer less than p). Since the first level ST1 to the (n+1)th level ST(n+1) are basically the same or similar to each other, the nth level STn will be described by example for clarity and conciseness.

[0089] Reference Figure 3 and Figure 4 The nth stage STn may include the first scan clock input terminal SCIN1 to the sixth scan clock input terminal SCIN6, the second node input terminal QBIN, the carry clock input terminal CRIN, the boost clock input terminal BIN, the first power input terminal VI1 to the fourth power input terminal VI4, the first carry input terminal CRIN1 and the second carry input terminal CRIN2, and the first output terminal OUT1 to the eighth output terminal OUT8.

[0090] The first scan clock input terminals SCIN1 to the sixth scan clock input terminal SCIN6 can receive inputs applied to the first scan clock line SKL1 (see...). Figure 5 ) to the sixth scan clock line SKL6 (see Figure 5 The first scan clock signal SCK1 to the sixth scan clock signal SCK6. For example, the first scan clock input terminal SCIN1 can be connected to the first scan clock line SKL1 and can receive the first scan clock signal SCK1.

[0091] The second node input terminal QBIN can receive the voltage QBV[n+1] of the second node of the (n+1)th stage ST(n+1). For example, the second node input terminal QBIN can be connected to the second node of the (n+1)th stage ST(n+1) and can receive the voltage QBV[n+1] of the second node of the (n+1)th stage ST(n+1). The voltage QBV[n+1] provided to the second node input terminal QBIN can be delayed and can have a voltage greater than that of the second node QB[n] of the nth stage STn (see [link to relevant documentation]). Figure 5 The voltage QBV[n] of stage n+1 is delayed by phase. Stage n+1 ST(n+1) can be a subsequent stage whose voltage is applied later than stage n STn.

[0092] The carry clock input terminal CRIN can receive the carry clock applied to the carry clock line CKL (see...). Figure 5 The carry clock input terminal CRIN of each of the odd-numbered stages can be connected to the carry clock line CKL and can receive the first carry clock signal CRK1. The carry clock input terminal CRIN of each of the even-numbered stages can be connected to the carry clock line CKL and can receive the second carry clock signal CRK2.

[0093] The boost clock input terminal BIN can receive the clock signal applied to the boost clock line BKL (see...). Figure 5 The boost clock input terminal BIN of each of the odd-numbered stages can be connected to the boost clock line BKL and can receive the first boost clock signal BCK1. The boost clock input terminal BIN of each of the even-numbered stages can be connected to the boost clock line BKL and can receive the second boost clock signal BCK2.

[0094] The first power input terminal VI1 can be connected to the first power line PL1 and can receive the first power voltage VGH1. The second power input terminal VI2 can be connected to the second power line PL2 and can receive the second power voltage VGH2. The third power input terminal VI3 can be connected to the third power line PL3 and can receive the third power voltage VGL1. The fourth power input terminal VI4 can be connected to the fourth power line PL4 and can receive the fourth power voltage VGL2.

[0095] The first carry input terminal CRIN1 and the second carry input terminal CRIN2 can respectively receive inputs applied to the (n-1)th carry line CRL[n-1] (see...). Figure 5The carry signals CR[n-1] and CR[n+1] of the (n-1)th stage ST(n-1) and the (n+1)th stage ST(n+1) can have a phase difference. For example, the first carry input terminal CRIN1 can be connected to the carry line CRL[n-1] of the (n-1)th stage ST(n-1) and can receive the carry signal CR[n-1] of the (n-1)th stage ST(n-1). The (n-1)th stage ST(n-1) can be the previous stage of the nth stage STn. The second carry input terminal CRIN2 can be connected to the carry line CRL[n+1] of the (n+1)th stage ST(n+1) and can receive the carry signal CR[n+1] of the (n+1)th stage ST(n+1). The (n+1)th level ST(n+1) can be a successor level to the nth level STn.

[0096] The first output terminal OUT1 to the sixth output terminal OUT6 are connected to the first scan line SL1[n] (see...) Figure 5 ) to the sixth scan line SL6[n] (see Figure 5 It can output the first scan signal SC1[n] to the sixth scan signal SC6[n]. For example, the first output terminal OUT1 is connected to the first scan line SL1[n] and can output the first scan signal SC1[n].

[0097] The seventh output terminal OUT7 is connected to the carry line CRL[n] of the nth stage STn (see...). Figure 5 The carry signal CR[n] of the nth stage STn can be output from the seventh output terminal OUT7. The carry signal CR[n] of the nth stage STn can be provided to the (n-1)th stage ST(n-1) and the (n+1)th stage ST(n+1). The carry signal CR[n] of the nth stage STn output from the seventh output terminal OUT7 can be a signal synchronized with the first carry clock signal CRK1 provided to the carry clock input terminal CRIN during the drive period.

[0098] The eighth output terminal OUT8 is connected to the second node QB[n] of the nth stage STn, and can output the potential or voltage QBV[n] of the second node QB[n] of the nth stage STn. The voltage QBV[n] of the second node QB[n] of the nth stage STn output from the eighth output terminal OUT8 can be supplied to the (n-1)th stage ST(n-1).

[0099] Figure 5 yes Figure 4 A schematic diagram of the equivalent circuit of one or more embodiments of the STn stage.

[0100] Reference Figure 3 , Figure 4 and Figure 5 The nth stage STn (where n is a natural number greater than 1) may include a voltage charging section SST1, a voltage reset section SST2, a scan signal output section SST3, a carry signal output section SST4, a boost controller SST5, a first node controller SST6, and a second node controller SST7. For clarity and brevity, the nth stage STn is described as an example, but the remaining stages can be configured similarly to the nth stage STn.

[0101] In an embodiment, the transistor included in the nth stage STn may be an oxide semiconductor transistor. The transistor may have a semiconductor layer comprising an oxide semiconductor.

[0102] The voltage charging section SST1 can control the voltage of the first output control node CQS[n] in response to the carry signal CR[n-1] supplied to the (n-1)th stage ST(n-1) of the first carry input terminal CRIN1. However, the first stage ST1 can receive the scan start signal FLM instead of the carry signal from the previous stage. The first stage ST1 can control the voltage of the first output control node of the first stage ST1 in response to the scan start signal FLM.

[0103] The voltage of the first output control node CQS[n] can be the voltage used to control the output of the first scan signal SC1[n] to the sixth scan signal SC6[n]. For example, the voltage of the first output control node CQS[n] can be the voltage used to control the pull-up of the first scan signal SC1[n] to the sixth scan signal SC6[n].

[0104] The voltage charging section SST1 is connected to the first power line PL1 and can provide the first power voltage VGH1 of the first power line PL1 to the first output control node CQS[n] in response to the (n-1)th carry signal CR[n-1]. For example, the voltage charging section SST1 can use the on-state voltage of the (n-1)th carry signal CR[n-1] to charge the voltage of the first output control node CQS[n].

[0105] The voltage input section SST1 can control the voltage of the first output control node CQS[n] in response to the voltage of the second output control node BCR[n]. The voltage input section SST1 is connected to the second power line PL2 and can supply the second power voltage VGH2 of the second power line PL2 to the first output control node CQS[n] in response to the voltage of the second output control node BCR[n]. For example, the voltage input section SST1 can use the on-state voltage of the second output control node BCR[n] to maintain the voltage of the first output control node CQS[n].

[0106] The voltage charging section SST1 may include a first transistor TR1 connected between the first power line PL1 and the first output control node CQS[n]. The first transistor TR1 may have a first electrode connected to the first power line PL1, a second electrode connected to the first output control node CQS[n], and a gate electrode connected to the (n-1)th carry line CRL[n-1]. The gate electrode of the first transistor TR1 may be connected to the (n-1)th carry line CRL[n-1] which is input with the (n-1)th level ST(n-1) carry signal CR[n-1].

[0107] The voltage charging section SST1 may include a second transistor TR2 connected between the second power line PL2 and the first output control node CQS[n]. The second transistor TR2 may have a first electrode connected to the second power line PL2, a second electrode connected to the first output control node CQS[n], and a gate electrode connected to the second output control node BCR[n]. The gate electrode of the second transistor TR2 may be connected to the second output control node BCR[n], which is input with a first boost clock signal BCK1 in response to the voltage of the first node CQS[n]. Figure 5 In the diagram, the first boost clock signal BCK1 is shown as input to the boost controller SST5, but a second boost clock signal BCK2 can be input according to the stage (see...). Figure 3 The voltage charging section SST1 may include a first capacitor C1 connected between the first power line PL1 and the first output control node CQS[n].

[0108] According to one or more embodiments, before applying the second power voltage VGH2, a first power voltage VGH1 can be applied to the first output control node CQS[n] in response to the carry signal CR[n-1] of the (n-1)th stage ST(n-1). Therefore, the first output control node CQS[n] can be charged with a first power voltage VGH1 that is higher than the second power voltage VGH2. Based on the first power voltage VGH1 transmitted to the first output control node CQS[n], the fifth transistor TR5 can be stably turned on, thus the voltage of the first node CQ[n] can be effectively transmitted to the third node Q[n]. This indicates that the voltage of the third node Q[n] is controlled with high reliability. Therefore, as described below, the sixth transistor TR6 outputs a scan signal in response to the voltage of the third node Q[n], thereby enabling control of the scan signal with improved reliability.

[0109] The voltage reset section SST2 can control the voltage of the first output control node CQS[n] in response to the voltage of the second node QB[n] of the nth stage (or the current stage) and the voltage of the second node QB[n+1] of the (n+1)th stage (or the next stage). According to one or more embodiments, the voltage reset section SST2 can provide the third power voltage VGL1 of the third power line PL3 to the first output control node CQS[n] in response to the voltage of the second node QB[n] of the nth stage and the voltage of the second node QB[n+1] of the (n+1)th stage. For example, the voltage reset section SST2 can discharge, thereby resetting the voltage of the first output control node CQS[n].

[0110] The voltage reset section SST2 may include a plurality of transistors connected in series between the first output control node CQS[n] and the third power line PL3. In one or more embodiments, the voltage reset section SST2 may include a third transistor TR3 and a fourth transistor TR4 connected in series between the first output control node CQS[n] and the third power line PL3.

[0111] The third transistor TR3 can be connected between the first output control node CQS[n] and the fourth transistor TR4. The gate electrode of the third transistor TR3 can be connected to the second node QB[n] of the nth stage. The third transistor TR3 may include a third transistor TR3_1 and a third transistor TR3_2 connected in series. The gate electrodes of the third transistor TR3_1 and the third transistor TR3_2 can be connected together to the second node QB[n] of the nth stage. However, the embodiments are not limited to this. For example, the third transistor TR3 can be a single transistor, and the gate electrode of the third transistor TR3 as a single transistor can be connected to the second node QB[n].

[0112] The fourth transistor TR4 can be connected between the third transistor TR3 and the third power line PL3. The gate electrode of the fourth transistor TR4 can be connected to the second node QB[n+1] of the (n+1)th stage.

[0113] In the voltage reset section SST2, when both the second node QB[n] of the nth stage and the second node QB[n+1] of the (n+1)th stage have on-state voltages, the third transistor TR3 and the fourth transistor TR4 can be turned on. Therefore, the voltage of the first output control node CQS[n] can be reset by discharging the voltage of the first output control node CQS[n] to the third power voltage VGL1 of the third power line PL3. Furthermore, when at least one of the second node QB[n] of the nth stage and the second node QB[n+1] of the (n+1)th stage has a cutoff voltage, the voltage reset section SST2 can maintain the voltage of the first output control node CQS[n] without current leakage.

[0114] The scan signal output section SST3 may include a first scan signal output section SST3_1 to a sixth scan signal output section SST3_6. The scan signal output section SST3 may output scan signals SC1[n] to SC6[n] in response to the voltage of the first output control node CQS[n].

[0115] The first scan signal output section SST3_1 can be connected to the first scan clock line SKL1 and the first scan line SL1[n]. For example, the first scan signal output section SST3_1 can output the first scan clock signal SCK1 of the first scan clock line SKL1 as the first scan signal SC1[n] in response to the voltage of the first output control node CQS[n] and the voltage of the first node CQ[n].

[0116] The first scan signal output section SST3_1 may include a fifth transistor TR5, a sixth transistor TR6, and a second capacitor C2. Furthermore, the first scan signal output section SST3_1 may include a seventh transistor TR7.

[0117] The fifth transistor TR5 can be connected between the first node CQ[n] and the third node Q[n]. The gate electrode of the fifth transistor TR5 can be connected to the first output control node CQS[n]. The fifth transistor TR5 can provide a turn-on voltage to the sixth transistor TR6 in response to the voltage of the first output control node CQS[n]. The fifth transistor TR5 can also provide the voltage of the first node CQ[n] to the gate electrode of the sixth transistor TR6 in response to the voltage of the first output control node CQS[n]. For example, the fifth transistor TR5 can be used as a pull-up buffer.

[0118] The first node CQ[n] can receive a first power voltage VGH1, which is higher than the second power voltage VGH2, via the thirteenth transistor TR13, based on the carry signal CR[n-1]. Furthermore, the voltage charging section SST1 can transmit the first power voltage VGH1 to the first output control node CQS[n] in response to the carry signal CR[n-1] of the (n-1)th stage ST(n-1). Based on the first power voltage VGH1 transmitted to the first output control node CQS[n], the fifth transistor TR5 can be stably turned on. Therefore, the relatively high voltage of the first node CQ[n] can be stably transmitted to the third node Q[n] via the fifth transistor TR5.

[0119] Furthermore, because the fifth transistor TR5 is positioned between the first node CQ[n] and the third node Q[n], the voltage of the first node CQ[n] is unaffected by the outputs of the first scan signal SC1[n] to the sixth scan signal SC6[n]. Therefore, the first node CQ[n] and the first output control node CQS[n] can be controlled to the desired voltage level, and the first scan signal SC1[n] to the sixth scan signal SC6[n] can be output at the desired voltage level in the desired timing. For example, the first scan signal SC1[n] to the sixth scan signal SC6[n] can have the same voltage level. For example, the time taken for the voltage rise and fall of each scan signal can be the same for each other. Therefore, the deviation between the first scan signal SC1[n] to the sixth scan signal SC6[n] can be negligible, or can be minimal or extremely small, thus preventing or mitigating the effects of the display panel DP (see [link to relevant documentation]). Figure 1 The horizontal line defect is caused by the brightness difference between pixel rows.

[0120] The sixth transistor TR6 can be connected between the first scan clock line SKL1 and the first scan line SL1[n]. The gate electrode of the sixth transistor TR6 can be connected to the third node Q[n]. The sixth transistor TR6 can output the first scan signal SC1[n] corresponding to the first scan clock signal SCK1 to the first scan line SL1[n] in response to the voltage of the third node Q[n].

[0121] The second capacitor C2 can be connected between the third node Q[n] and the second output control node BCR[n]. The second capacitor C2 can be a boost capacitor. When the fifth transistor TR5 is in the off state, the voltage rise of the second output control node BCR[n] can increase the voltage of the third node Q[n] through the coupling of the second capacitor C2. Therefore, the sixth transistor TR6 can remain stably on for a period of time (e.g., a predetermined period of time).

[0122] The seventh transistor TR7 can be connected between the first scan line SL1[n] and the third power line PL3. The gate electrode of the seventh transistor TR7 can be connected to the second node QB[n]. The seventh transistor TR7 can provide a turn-on voltage to the sixth transistor TR6 in response to the voltage of the second node QB[n]. The seventh transistor TR7 can output the third power voltage VGL1 of the third power line PL3 to the first scan line SL1[n] in response to the voltage of the second node QB[n].

[0123] Each of the second scan signal output sections SST3_2 to the sixth scan signal output section SST3_6 can be configured similarly to the first scan signal output section SST3_1. Repeated descriptions are omitted.

[0124] The carry signal output section SST4 can be connected between the carry clock line CKL and the fourth power line PL4. In response to the voltage of the first node CQ[n], the carry signal output section SST4 can output the first carry clock signal CRK1 of the carry clock line CKL to the carry line CRL[n] of the nth stage STn. In response to the voltage of the second node QB[n], the carry signal output section SST4 can output the fourth power voltage VGL2 of the fourth power line PL4 to the carry line CRL[n] of the nth stage STn.

[0125] The carry signal output section SST4 may include the tenth transistor TR10 and the eleventh transistor TR11.

[0126] The tenth transistor TR10 may have a first electrode connected to the carry clock line CKL, a second electrode connected to the carry line CRL[n], and a gate electrode connected to the first node CQ[n]. The tenth transistor TR10 may provide a first carry clock signal CRK1 to the carry line CRL[n] in response to the voltage of the first node CQ[n]. However, although in Figure 5 The diagram shows the provision of a first carry clock signal CRK1, but a second carry clock signal CRK2 can be provided depending on the stage (see [link]). Figure 3 ).

[0127] The eleventh transistor TR11 may have a first electrode connected to the carry line CRL[n], a second electrode connected to the fourth power line PL4, and a gate electrode connected to the second node QB[n]. The eleventh transistor TR11 may supply the fourth power voltage VGL2 to the carry line CRL[n] in response to the voltage at the second node QB[n]. The carry line CRL[n] connected to the tenth transistor TR10 and the eleventh transistor TR11 may be connected to the (n-1)th stage ST(n-1) and the (n+1)th stage ST(n+1).

[0128] The boost controller SST5 can transmit a first boost clock signal BCK1 to the second output control node BCR[n] in response to the voltage of the first node CQ[n]. The first boost clock signal BCK1 transmitted to the second output control node BCR[n] can turn off the second transistor TR2 to float the first output control node CQS[n]. The first boost clock signal BCK1 transmitted to the second output control node BCR[n] can raise the voltage level of the first node CQ[n] through coupling with the third capacitor C3. Furthermore, the first boost clock signal BCK1 transmitted to the second output control node BCR[n] can raise the voltage level of the third node Q[n] through coupling with the second capacitor C2. However, the capacitance of the third capacitor C3, which raises the voltage level of the first node CQ[n], can be relatively large compared to the capacitance of the second capacitor C2, which raises the voltage level of the third node Q[n].

[0129] The boost controller SST5 may include an eighth transistor TR8 and a third capacitor C3. Additionally, the boost controller SST5 may include a ninth transistor TR9.

[0130] The eighth transistor TR8 can be connected between the boost clock line BKL and the second output control node BCR[n]. The gate electrode of the eighth transistor TR8 can be connected to the first node CQ[n].

[0131] The ninth transistor TR9 can be connected between the second output control node BCR[n] and the fourth power line PL4. The gate electrode of the ninth transistor TR9 can be connected to the second node QB[n].

[0132] The third capacitor C3 can be connected between the first node CQ[n] and the second output control node BCR[n]. The third capacitor C3 can also be connected between the gate electrode of the eighth transistor TR8 and the second output control node BCR[n]. The third capacitor C3 can be a boost capacitor. When the first boost clock signal BCK1 is transmitted to the second output control node BCR[n] via the eighth transistor TR8, the voltage rise of the second output control node BCR[n] can increase the voltage of the first node CQ[n] through the coupling of the third capacitor C3. The voltage of the first node CQ[n] can be transmitted to the third node Q[n] via the fifth transistor TR5 to increase the voltage of the third node Q[n].

[0133] The first node controller SST6 can control the voltage of the first node CQ[n] in response to the carry signal CR[n-1] of the (n-1)th stage ST(n-1) and the carry signal CR[n+1] of the (n+1)th stage ST(n+1).

[0134] The first node controller SST6 may include a twelfth transistor TR12 connected between the first power line PL1 and the (n-1)th carry line CRL[n-1], and a thirteenth transistor TR13 connected between the first power line PL1 and the first node CQ[n]. The gate electrodes of the twelfth transistor TR12 and the thirteenth transistor TR13 may be connected to the (n-1)th carry line CRL[n-1]. For example, the thirteenth transistor TR13 may provide a first power voltage VGH1 to the first node CQ[n] in response to the carry signal CR[n-1] of the (n-1)th stage ST(n-1).

[0135] The first node controller SST6 may further include a fourteenth transistor TR14 and a fifteenth transistor TR15 connected between the fourth power line PL4 and the first node CQ[n]. The gate electrode of the fourteenth transistor TR14 may be connected to the (n+1)th carry line CRL[n+1]. The fourteenth transistor TR14 may include a 14_1 transistor TR14_1 and a 14_2 transistor TR14_2 connected in series. The gate electrodes of the 14_1 transistor TR14_1 and the 14_2 transistor TR14_2 may be connected together to the (n+1)th carry line CRL[n+1]. For example, the fourteenth transistor TR14 may provide the fourth power voltage VGL2 to the first node CQ[n] in response to the carry signal CR[n+1] of the (n+1)th stage ST(n+1).

[0136] The gate electrode of the fifteenth transistor TR15 can be connected to the second node QB[n]. The fifteenth transistor TR15 may include a 15_1 transistor TR15_1 and a 15_2 transistor TR15_2 connected in series. The gate electrodes of the 15_1 transistor TR15_1 and the 15_2 transistor TR15_2 can be connected together to the second node QB[n]. For example, the fifteenth transistor TR15 can provide a fourth power voltage VGL2 to the first node CQ[n] in response to the voltage of the second node QB[n].

[0137] The second node controller SST7 can control the voltage of the second node QB[n] in response to the second power voltage VGH2 of the second power line PL2 and the voltage of the first node CQ[n].

[0138] The second node controller SST7 may include a sixteenth transistor TR16 and a seventeenth transistor TR17 connected between the second power line PL2 and the third power line PL3. The gate electrode of the sixteenth transistor TR16 may be connected to the second power line PL2. The sixteenth transistor TR16 may include a 16_1 transistor TR16_1 and a 16_2 transistor TR16_2 connected in series. The gate electrodes of the 16_1 transistor TR16_1 and the 16_2 transistor TR16_2 may be commonly connected to the second power line PL2. For example, the sixteenth transistor TR16 may provide a second power voltage VGH2 to the first voltage node N1 in response to the second power voltage VGH2 on the second power line PL2. The gate electrode of the seventeenth transistor TR17 may be connected to the first node CQ[n]. For example, the seventeenth transistor TR17 may provide a third power voltage VGL1 to the first voltage node N1 in response to the voltage of the first node CQ[n].

[0139] The second node controller SST7 may further include an eighteenth transistor TR18 and a nineteenth transistor TR19 connected between the second power line PL2 and the fourth power line PL4. The gate electrode of the eighteenth transistor TR18 may be connected to the first voltage node N1. For example, the eighteenth transistor TR18 may provide a second power voltage VGH2 to the second node QB[n] in response to the voltage of the first voltage node N1. The gate electrode of the nineteenth transistor TR19 may be connected to the first node CQ[n]. For example, the nineteenth transistor TR19 may provide a fourth power voltage VGL2 to the second node QB[n] in response to the voltage of the first node CQ[n].

[0140] The second node controller SST7 can control the voltage of the first node CQ[n] and the voltage of the second node QB[n]. For example, the second node controller SST7 can control the voltage of the first node CQ[n] and the voltage of the second node QB[n] to be out of phase with each other.

[0141] Figure 6 and Figure 7 It is shown Figure 5 Timing diagrams of one or more embodiments of the level of operation.

[0142] Figures 5 to 7The signals applied to the boost clock line BKL, carry clock line CKL, carry lines CRL[n-1] to CRL[n+1] (n-1th carry line), first node CQ[n], first output control node CQS[n], third node Q[n], second node QB[n] of the nth stage STn, second node QB[n+1] of the (n+1th stage ST(n+1)), first scan clock lines SKL1 to SKL6, and first scan lines SL1[n] to SL6[n]. The operation of the nth stage STn during the display period is described below. For clarity and brevity, the operation of the nth stage STn is described as an example, but the operation of the remaining stages can be similar to that of the nth stage STn.

[0143] At the first time point t1, the (n-1)th carry signal CR[n-1] on the (n-1)th carry line CRL[n-1] can transition to a high-level voltage. The thirteenth transistor TR13 can turn on in response to the (n-1)th carry signal CR[n-1], and a first power voltage VGH1 can be transmitted to the first node CQ[n]. Therefore, the voltage CQV[n] of the first node CQ[n] can have a first voltage level V1. For example, the first voltage level V1 can be approximately, but not limited to, 25V.

[0144] The first transistor TR1 can be turned on in response to the (n-1)th carry signal CR[n-1], and the first power voltage VGH1 can be transmitted to the first output control node CQS[n]. Therefore, the voltage CQSV[n] of the first output control node CQS[n] can have a first voltage level V1'.

[0145] The fifth transistor TR5 can be turned on in response to the voltage CQSV[n] of the first output control node CQS[n], and the voltage of the first node CQ[n] can be transferred to the third node Q[n]. Therefore, the voltage QV[n] of the third node Q[n] can change to the first voltage level V1''. Figure 6 For clarity and brevity, only the voltage QV[n] of the third node Q[n] of one of the first scan signal output sections SST3_1 to the sixth scan signal output section SST3_6 is shown, and the voltages of the third node Q[n] of the remaining scan signal output sections are omitted. For example, in Figure 6 The voltage QV[n] of the third node Q[n] of the first scan signal output section SST3_1 is shown in the figure.

[0146] When the first power voltage VGH1 is transmitted to the first node CQ[n], the nineteenth transistor TR19 can be turned on. Through the turned-on nineteenth transistor TR19, the fourth power voltage VGL2 can be transmitted to the second node QB[n]. The voltage QBV[n] of the second node QB[n] can change to a low level in response to the fourth power voltage VGL2. The third transistor TR3 can be turned off in response to the voltage QBV[n] of the second node QB[n], and the first output control node CQS[n] can be electrically isolated from the third power voltage VGL1.

[0147] At the second time point t2, the first boost clock signal BCK1 applied to the boost clock line BKL can transition to a high-level voltage. The eighth transistor TR8 turns on in response to the voltage CQV[n] of the first node CQ[n], allowing the high-level first boost clock signal BCK1 to be transmitted to the second output control node BCR[n] through the conducting eighth transistor TR8. The high-level voltage applied to the second output control node BCR[n] can increase the voltage CQV[n] of the first node CQ[n] through the third capacitor C3 connected between the second output control node BCR[n] and the first node CQ[n]. Therefore, at the second time point t2, the voltage CQV[n] of the first node CQ[n] can have a second voltage level V2 that is approximately twice as high as the first voltage level V1. The high-level voltage applied to the second output control node BCR[n] can increase the voltage QV[n] of the third node Q[n] through the second capacitor C2 connected between the second output control node BCR[n] and the third node Q[n]. Therefore, at the second time point t2, the voltage QV[n] of the third node Q[n] can have a fourth voltage level V4 that is about twice as high as the first voltage level V1''.

[0148] At a second time point t2, the second transistor TR2 can be turned on in response to the voltage of the second output control node BCR[n]. Through the turned-on second transistor TR2, the second power voltage VGH2 can be transmitted to the first output control node CQS[n]. The voltage CQSV[n] of the first output control node CQS[n] can drop from the first power voltage VGH1 to the second power voltage VGH2. For example, the voltage CQSV[n] of the first output control node CQS[n] can be changed to a third voltage level V3. The third voltage level V3 can be approximately, but is not limited to, 15V. The voltage CQSV[n] of the first output control node CQS[n] can be applied to the gate electrode of the fifth transistor TR5 connected between the first node CQ[n] and the third node Q[n]. For example, the fifth transistor TR5 can be turned off when the third voltage level V3 is applied to the gate electrode, and the fifth transistor TR5 can be turned off when a second voltage level V2, which is higher than the third voltage level V3, is applied to the source electrode. In other words, when the fifth transistor TR5 is turned off, the first node CQ[n] and the third node Q[n] can be electrically isolated. As a result, the deviation between the first scan signal SC1[n] and the sixth scan signal SC6[n] described below can be avoided.

[0149] At the second time point t2, the (n-1)th carry signal CR[n-1] can transition to a low-level voltage. Because the first output control node CQS[n] is connected to the first power line PL1 through the first capacitor C1, the voltage CQSV[n] of the first output control node CQS[n] can be maintained even if the first transistor TR1 is turned off.

[0150] At the third time point t3, the first carry clock signal CRK1 of the carry clock line CKL can transition to a high-level voltage. Because the tenth transistor TR10 is turned on in response to the voltage CQV[n] of the first node CQ[n], the high-level first carry clock signal CRK1 can be transmitted to the nth carry line CRL[n]. Therefore, at the third time point t3, the first carry clock signal CRK1 is output to the nth carry line CRL[n], and thus the nth carry signal CR[n] can have a high-level voltage.

[0151] At the third time point t3, the first carry clock signal CRK1, which is at the level applied to the nth carry line CRL[n], can increase the voltage CQV[n] of the first node CQ[n] through the tenth transistor TR10 connected between the nth carry line CRL[n] and the first node CQ[n]. Therefore, at the third time point t3, the voltage CQV[n] of the first node CQ[n] can have a higher voltage level than the second voltage level V2.

[0152] At the third time point t3, the voltage QBV[n+1] applied from the second node QB[n+1] of the (n+1)th stage ST(n+1) can have a low level voltage. The fourth transistor TR4 can be turned off in response to the voltage QBV[n+1], and the first output control node CQS[n] can be electrically isolated from the third power voltage VGL1.

[0153] At the fourth time point t4, the first carry clock signal CRK1 on the carry clock line CKL can transition to a low-level voltage. Therefore, at the fourth time point t4, the nth carry signal CR[n] can have a low-level voltage.

[0154] At the fifth time point t5, the first boost clock signal BCK1 applied to the boost clock line BKL can transition to a low-level voltage. The (n+1)th carry signal CR[n+1] applied to the (n+1)th carry line CRL[n+1] can have a high-level voltage. The fourteenth transistor TR14 can turn on in response to the (n+1)th carry signal CR[n+1], and the fourth power voltage VGL2 can be transmitted to the first node CQ[n]. Therefore, the voltage CQV[n] of the first node CQ[n] and the voltage QV[n] of the third node Q[n] can be reduced.

[0155] According to one or more embodiments, during a first time period P1 from the second time point t2 to the fifth time point t5, the first boost clock signal BCK1 may have a high-level voltage. The first time period P1 may be a period in which the fifth transistor TR5 is turned off when the voltage CQSV[n] of the first output control node CQS[n] is lower than the voltage CQV[n] of the first node CQ[n]. Furthermore, the first time period P1 may be a period in which the sixth transistor TR6 is turned on in response to the voltage QV[n] of the third node Q[n]. The voltage QV[n] of the third node Q[n] may be the voltage of the second output control node BCR[n] transmitted through the second capacitor C2.

[0156] Reference Figure 5 and Figure 7The first scan clock signals SCK1 to the sixth scan clock signals SCK6, applied to the first scan clock line SKL1 to the sixth scan clock line SKL6, can be pulses with low-level voltages and high-level voltages. The phase of the second scan clock signal SCK2 can be delayed from the first scan clock signal SCK1. The high-level voltage of the second scan clock signal SCK2 can have a phase delayed from the high-level voltage of the first scan clock signal SCK1, but can partially overlap with the high-level voltage of the first scan clock signal SCK1. The phase of the third scan clock signal SCK3 can be delayed from the second scan clock signal SCK2. The high-level voltage of the third scan clock signal SCK3 can have a phase delayed from the high-level voltage of the second scan clock signal SCK2, but can partially overlap with the high-level voltage of the second scan clock signal SCK2. The phase of the fourth scan clock signal SCK4 can be delayed from the third scan clock signal SCK3. The high-level voltage of the fourth scan clock signal SCK4 can have a phase delayed from the high-level voltage of the third scan clock signal SCK3, but can partially overlap with the high-level voltage of the third scan clock signal SCK3. The phase of the fifth scan clock signal SCK5 can be delayed from the fourth scan clock signal SCK4. The high-level voltage of the fifth scan clock signal SCK5 can have a phase delayed from the high-level voltage of the fourth scan clock signal SCK4, but can partially overlap with the high-level voltage of the fourth scan clock signal SCK4. The phase of the sixth scan clock signal SCK6 can be delayed from the fifth scan clock signal SCK5. The high-level voltage of the sixth scan clock signal SCK6 can have a phase delayed from the high-level voltage of the fifth scan clock signal SCK5, but can partially overlap with the high-level voltage of the fifth scan clock signal SCK5.

[0157] During the first time period P1, the voltage QV[n] of the third node Q[n] can have a fourth voltage level V4 (see Figure 6 Thus, the sixth transistor TR6 of the first scan signal output section SST3_1 to the sixth scan signal output section SST3_6 can be turned on according to the voltage of the third node Q[n] of the first scan signal output section SST3_1 to the sixth scan signal output section SST3_6. Therefore, the first scan clock signal SCK1 to the sixth scan clock signal SCK6 can be output to the first scan line SL1[n] to the sixth scan line SL6[n] as the first scan signal SC1[n] to the sixth scan signal SC6[n]. According to the first scan clock signal SCK1 to the sixth scan clock signal SCK6, each of the first scan signal SC1[n] to the sixth scan signal SC6[n] can have a phase delayed from the previous scan signal, but can partially overlap with the previous scan signal.

[0158] During the first time period P1, whenever each scan clock signal is output as a scan signal, the voltage of the third node Q[n] in the corresponding scan signal output section will unintentionally fluctuate. For example, due to the coupling of parasitic capacitors that can be formed between the drain and gate electrodes of the sixth transistor TR6, or due to the coupling of parasitic capacitors that can be formed between the source and gate electrodes of the sixth transistor TR6, the voltage of the scan signal will affect the voltage of the third node Q[n]. Therefore, in one or more embodiments, the first pulse PS1 will appear at the voltage of the third node Q[n] of the first scan signal output section SST3_1 (for example, the first pulse PS1 will appear simultaneously with the first scan clock signal SCK1 and the first scan signal SC1[n].

[0159] On the other hand, since the first node CQ[n] is connected to the third node Q[n] via the fifth transistor TR5, the first node CQ[n] can have a relatively stable voltage when the scan clock signal of the corresponding scan signal output section is output as a scan signal. Therefore, even if the voltage of the third node Q[n] of one of the first scan signal output sections SST3_1 to the sixth scan signal output section SST3_6 fluctuates due to the output of the scan signal, the voltage of the third node Q[n] of the other scan signal output sections can receive the stable voltage of the first node CQ[n]. As described above, the output of each scan signal can not affect the output of the other scan signal. Therefore, the first scan signal SC1[n] to the sixth scan signal SC6[n] can be output at the desired voltage level in the desired timing. For example, the first scan signal SC1[n] to the sixth scan signal SC6[n] can have the same voltage level. For example, the time taken for the voltage rise and fall of each scan signal can be the same for each other. Therefore, the deviation between the first scan signal SC1[n] and the sixth scan signal SC6[n] can be avoided, thus preventing or mitigating the deviation caused by the display panel DP (see...). Figure 1 The horizontal line defect is caused by the brightness difference between pixel rows.

[0160] Refer again Figure 6 At the sixth time point t6, the first boost clock signal BCK1 applied to the boost clock line BKL can be switched to a high level voltage. The (n+1)th carry signal CR[n+1] applied to the (n+1)th carry line CRL[n+1] can be switched to a low level voltage.

[0161] At time point t7, the voltage QBV[n+1] applied from the second node QB[n+1] of stage n+1 ST(n+1) can be converted to a high-level voltage. The voltage QBV[n] applied to the second node QB[n] of stage n STn can be a high-level voltage from time point t5. The third transistor TR3 can be turned on in response to the voltage QBV[n] of the second node QB[n], and the fourth transistor TR4 can be turned on in response to the voltage QBV[n+1] of the second node QB[n+1] of stage n+1 ST(n+1). The period after time point t7 can be defined as the second period P2. In the second period P2, the voltage CQSV[n] of the first output control node CQS[n] can be discharged to the third power voltage VGL1 via the turned-on third transistor TR3 and fourth transistor TR4. The voltage CQSV[n] of the first output control node CQS[n] can have the third power voltage VGL1. Since the voltage CQSV[n] of the first output control node CQS[n] has a third power voltage VGL1, degradation of the transistors connected to the first output control node CQS[n] can be prevented or mitigated. For example, degradation of the fifth transistor TR5 can be prevented or mitigated.

[0162] Figure 8 This is a schematic block diagram illustrating one or more embodiments of an electronic device 1000 including a scan driver 1142 according to one or more embodiments of the present disclosure.

[0163] Reference Figure 8 The electronic device 1000 of one or more embodiments of this disclosure can output various information via the display module 1140. When the processor 1110 executes an application stored in the memory 1120, the display module 1140 can provide application information to the user through the display panel 1141.

[0164] Processor 1110 can acquire external input via input module 1130 or sensor module 1161 and execute the application corresponding to the external input. For example, when a user selects the camera icon (or camera application icon) displayed on display panel 1141, processor 1110 acquires user input via input sensor 1161-2 and activates camera module 1171. Processor 1110 can then transmit image data corresponding to the captured image acquired by camera module 1171 to display module 1140. Display module 1140 can display the image corresponding to the captured image via display panel 1141.

[0165] As another example, when performing personal information authentication in display module 1140, fingerprint sensor 1161-1 can acquire input fingerprint information as input data. Processor 1110 can compare the input data acquired by fingerprint sensor 1161-1 with authentication data stored in memory 1120 and execute the application based on the comparison result. Display module 1140 can display information executed according to the application logic via display panel 1141. Fingerprint sensor 1161-1 can be arranged to acquire fingerprint information over the entire area of ​​display module 1140 (or display panel 1141).

[0166] As another example, when a music stream icon is selected to be displayed on display module 1140, processor 1110 can acquire user input via input sensor 1161-2 and activate the music stream application stored in memory 1120. When a music playback command is input to the music stream application, processor 1110 can activate sound output module 1163 to provide the user with sound information corresponding to the music playback command.

[0167] The operation of the electronic device 1000 has been briefly described above. The components of the electronic device 1000 will be described in detail below. Some of the components of the electronic device 1000 described below can be integrated and configured as a single component, or a single component can be configured as two or more separate components.

[0168] Electronic device 1000 can communicate with external electronic device 2000 via a network (e.g., a near-field communication network or a far-field communication network). According to one or more embodiments, electronic device 1000 may include a processor 1110, a memory 1120, an input module 1130, a display module 1140, a power module 1150, an embedded module 1160, and an external module 1170. According to one or more embodiments, at least one of the above-described components of electronic device 1000 may be omitted, or one or more other components may be added. According to one or more embodiments, some of the above-described components (e.g., sensor module 1161, antenna module 1162, or audio output module 1163) may be integrated into another component (e.g., display module 1140).

[0169] Processor 1110 can execute software to control one or more other components (e.g., hardware or software components) connected to electronic device 1000, and can perform various data processing or operations. According to one or more embodiments, as at least part of data processing or operations, processor 1110 can store commands or data received from another component (e.g., input module 1130, sensor module 1161, or communication module 1173) in volatile memory 1121, process commands or data stored in volatile memory 1121, and store result data in non-volatile memory 1122.

[0170] Processor 1110 may include a main processor 1111 and an auxiliary processor 1112. Main processor 1111 may include one or more of a central processing unit (CPU) 1111-1 and an application processor (AP). Main processor 1111 may also include one or more of a graphics processing unit (GPU) 1111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 1111 may also include a neural processing unit (NPU) 1111-3. NPU 1111-3 is a processor specifically designed to process artificial intelligence models, which can be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural network may be one or a combination of two or more of the following: deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), restricted Boltzmann machine (RBM), deep belief network (DBN), bidirectional recurrent deep neural network (BRDNN), deep Q-network, but is not limited to the foregoing examples. In addition to hardware architecture, the artificial intelligence model may also include software architecture, or typically includes software architecture. Two or more of the aforementioned processing units and processors may be implemented in an integrated component (e.g., a single chip), or all may be implemented in independent components (e.g., multiple chips).

[0171] The auxiliary processor 1112 may include a controller 1112-1. The controller 1112-1 may include interface conversion circuitry and timing control circuitry. For example, the controller 1112-1 may include... Figure 1 The controller 110 shown is shown. Controller 1112-1 can receive image signals from the main processor 1111, convert the data format of the image signals to meet the interface specifications of the display module 1140, and output image data. Controller 1112-1 can output various control signals suitable for driving the display module 1140.

[0172] In one or more embodiments, the auxiliary processor 1112 may further include a data conversion circuit 1112-2, a gamma correction circuit 1112-3, a rendering circuit 1112-4, a touch control circuit, etc. The data conversion circuit 1112-2 may receive image data from the controller 1112-1 and, according to the characteristics of the electronic device 1000 or user settings, compensate the image data to display the image at the desired brightness, or convert the image data to reduce power consumption or compensate for image retention.

[0173] The gamma correction circuit 1112-3 can convert image data, gamma reference voltage, etc., so that the image displayed on the electronic device 1000 has the desired gamma characteristics. The rendering circuit 1112-4 can receive image data from the controller 1112-1 and render the image data taking into account the pixel arrangement and other factors applied to the display panel 1141 of the electronic device 1000.

[0174] The touch control circuit can supply touch signals to the input sensor 1161-2 and receive sensing signals from the input sensor 1161-2 in response to the touch signals.

[0175] At least one of the data conversion circuit 1112-2, gamma correction circuit 1112-3, rendering circuit 1112-4, and touch control circuit can be integrated into another component (e.g., the main processor 1111 or the controller 1112-1). At least one of the data conversion circuit 1112-2, gamma correction circuit 1112-3, and rendering circuit 1112-4 can be integrated into the source driver 1143, which will be described below.

[0176] The memory 1120 may store various data used by at least one component of the electronic device 1000 (e.g., processor 1110 or sensor module 1161), as well as input or output data of commands associated therewith. Furthermore, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include at least one of volatile memory 1121 and non-volatile memory 1122.

[0177] The input module 1130 can receive commands or data from outside the electronic device 1000 (such as from a user or external electronic device 2000) for use by components of the electronic device 1000 (e.g., processor 1110, sensor module 1161, or voice output module 1163).

[0178] Input module 1130 may include a first input module 1131 and a second input module 1132. A user inputs commands or data to the first input module 1131, and an external electronic device 2000 inputs commands or data to the second input module 1132. The first input module 1131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or a pen (e.g., a passive or active pen). The second input module 1132 may support a specified protocol that allows wired or wireless connection to the external electronic device 2000. According to one or more embodiments, the second input module 1132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 1132 may include a connector (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)) that can be physically connected to the external electronic device 2000.

[0179] Display module 1140 can visually provide information to the user. Display module 1140 may include display panel 1141, scan driver 1142, and source driver 1143. Display module 1140 may also include a window, chassis, and bracket for protecting display panel 1141.

[0180] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel. The type of display panel 1141 is not particularly limited. The display panel 1141 may be rigid or flexible, such as rollable or foldable. The display module 1140 may also include supports, brackets, heat dissipation layers, etc., that support the display panel 1141.

[0181] Display panel 1141 can receive image data from auxiliary processor 1112 and display the image while controlling the amount of current supplied from first drive power node VDDN to second drive power node VSSN via pixel PXL in response to the image data. Display panel 1141 can correspond to Figure 1 The display panel DP shown is shown.

[0182] The scan driver 1142 can be mounted as a driver chip on the display panel 1141. Alternatively, the scan driver 1142 can be integrated into the display panel 1141. For example, the scan driver 1142 may include an amorphous silicon TFT gate driver circuit (ASG), a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) embedded in the display panel 1141. The scan driver 1142 can receive control signals from the controller 1112-1 and output scan signals to the display panel 1141 in response to the control signals. The scan driver 1142 may include... Figure 1 The scan driver 120 shown.

[0183] The display module 1140 may also include a transmitter driver. The transmitter driver can output a transmitter control signal to the display panel 1141 in response to a control signal received from the controller 1112-1. The transmitter driver may be formed separately from the scan driver 1142, or it may be integrated into the scan driver 1142.

[0184] The source driver 1143 can receive control signals from the controller 1112-1, convert image data into analog voltages (e.g., data signals) in response to the control signals, and output the data signals to the display panel 1141. The source driver 1143 may include... Figure 1 The data drive 130 shown is shown.

[0185] The source driver 1143 can be integrated into another component (e.g., controller 1112-1). The functions of the interface conversion circuit and timing control circuit of the controller 1112-1 can be integrated into the source driver 1143.

[0186] The display module 1140 may also include a voltage generation circuit 1144. The voltage generation circuit 1144 can output various voltages required to drive the display panel 1141.

[0187] In one or more embodiments, the source driver 1143 can convert the data corresponding to the red (R), green (G) and blue (B) colors included in the image data received from the processor 1110 into red data signals (or data voltages), green data signals (or data voltages), and blue data signals (or data voltages), respectively, and can provide the data signals to a plurality of pixel columns included in the display panel 1141 during a horizontal time period.

[0188] Power module 1150 can supply power to components of electronic device 1000. Power module 1150 may include a battery charged with electrical voltage. Examples of batteries may include non-rechargeable primary batteries, rechargeable secondary batteries, or fuel cells. Power module 1150 may include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the modules described above and below. Power module 1150 may include wireless power transmitting / receiving elements electrically connected to the battery. The wireless power transmitting / receiving elements may include multiple antenna radiators in the form of coils. Voltage generation circuitry 1144 may be integrated into power module 1150.

[0189] The electronic device 1000 may also include an embedded module 1160 and an external module 1170. The embedded module 1160 may include a sensor module 1161, an antenna module 1162, and a sound output module 1163. The external module 1170 may include a camera module 1171, an optical module 1172, and a communication module 1173.

[0190] Sensor module 1161 can sense input from the user's body or from the pen of the first input module 1131, and generate an electrical signal or data value corresponding to the input. Sensor module 1161 may include at least one of fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3.

[0191] The fingerprint sensor 1161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 1161-1 may include an optical or capacitive fingerprint sensor.

[0192] Input sensor 1161-2 can generate data values ​​corresponding to the coordinate information of user's body input or pen input. Input sensor 1161-2 can generate the amount of capacitance change caused by input as a data value. Input sensor 1161-2 can sense input from a passive pen, or send data to and receive data from an active pen.

[0193] Input sensor 1161-2 can measure biosignals such as blood pressure, water content, or body fat. For example, when a user touches a part of their body with the sensor layer or sensing panel and does not move for a certain period of time, input sensor 1161-2 can sense biosignals based on changes in the electric field caused by the part of the body and output the information desired by the user to display module 1140.

[0194] The digitizer 1161-3 can generate data values ​​corresponding to the coordinate information input by the pen. The digitizer 1161-3 can generate electromagnetic changes as data values ​​based on the input. The digitizer 1161-3 can sense input from a passive pen, or send data to and receive data from an active pen.

[0195] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be implemented as a sensor layer formed on the display panel 1141 by a continuous process. At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be positioned above the display panel 1141, and one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 (e.g., the digitizer 1161-3) can be positioned below the display panel 1141.

[0196] Two or more of the fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3 can be formed and integrated into a single sensing panel using the same process. When integrated into a single sensing panel, the sensing panel can be positioned between the display panel 1141 and a window located above the display panel 1141. According to one or more embodiments, the sensing panel can be positioned on the window, and the position of the sensing panel is not particularly limited.

[0197] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be embedded in the display panel 1141. For example, at least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be formed simultaneously by a process for forming devices (e.g., light-emitting devices, transistors, etc.) included in the display panel 1141.

[0198] Furthermore, sensor module 1161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 1000. Sensor module 1161 may also include, for example, gesture sensors, gyroscope sensors, atmospheric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0199] Antenna module 1162 may include one or more antennas for externally transmitting or receiving signals or power. According to one or more embodiments, antenna module 1162 may transmit signals to or receive signals from external electronic device 2000 via antennas suitable for communication methods. The antenna pattern of antenna module 1162 may be integrated into a component of display module 1140 (e.g., display panel 1141) or input sensors 1161-2.

[0200] The sound output module 1163 is a device for outputting sound signals to the outside of the electronic device 1000, and may include, for example, a speaker for general purposes such as multimedia playback or recording playback, and a receiver specifically for receiving telephone calls. According to one or more embodiments, the receiver may be integrally formed with the speaker or formed separately from the speaker. The sound output pattern of the sound output module 1163 may be integrated into the display module 1140.

[0201] Camera module 1171 can capture still images and movie videos. According to one or more embodiments, camera module 1171 may include one or more lenses, image sensors, or image signal processors. Camera module 1171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, the user's line of sight, etc.

[0202] The light module 1172 can provide light. The light module 1172 may include a light-emitting diode or a xenon lamp. The light module 1172 can operate together with the camera module 1171, or it can operate independently.

[0203] Communication module 1173 can support the establishment of a wired or wireless communication channel between electronic device 1000 and external electronic device 2000, and support communication through the established communication channel. Communication module 1173 may include one or both of a wireless communication module (such as a cellular communication module, a near-field communication module, or a Global Navigation Satellite System (GNSS) communication module) and a wired communication module (such as a local area network (LAN) communication module or a power line communication module). Communication module 1173 can communicate via a local area network (such as Bluetooth). ® Bluetooth ® Bluetooth Sig, Inc., Kirkland, Washington (a registered trademark of Bluetooth Sig, Inc.) and Wi-Fi ® Direct connection (Wi-Fi) ® The communication module 1173 (a registered trademark of the non-profit Wi-Fi Alliance, the Infrared Data Association (IrDA), or a long-range communication network (such as a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN))) communicates with an external electronic device 2000. The various types of communication modules 1173 described above can be implemented as a single chip or as separate chips.

[0204] Input module 1130, sensor module 1161, camera module 1171, etc. can be used in conjunction with processor 1110 to control the operation of display module 1140.

[0205] The processor 1110 can output commands or data to the display module 1140, the sound output module 1163, the camera module 1171, or the optical module 1172 based on the input data received from the input module 1130. For example, the processor 1110 can generate image data and output the image data to the display module 1140 in response to input data applied by a mouse, active pen, etc., or it can generate command data and output the command data to the camera module 1171 or the optical module 1172 in response to input data. When no input data is received from the input module 1130, the processor 1110 can switch the operating mode of the electronic device 1000 to a low-power mode or a sleep mode to reduce the power consumed by the electronic device 1000.

[0206] Processor 1110 can output commands or data to display module 1140, sound output module 1163, camera module 1171, or optical module 1172 based on sensing data received from sensor module 1161. For example, processor 1110 can compare authentication data sensed by fingerprint sensor 1161-1 with authentication data stored in memory 1120, and then execute an application based on the comparison result. Processor 1110 can execute commands or output corresponding image data to display module 1140 based on sensing data sensed by input sensor 1161-2 or digitizer 1161-3. When sensor module 1161 includes a temperature sensor, processor 1110 can receive temperature data for the measured temperature from sensor module 1161, and also perform brightness correction, etc., on image data based on the temperature data.

[0207] Processor 1110 can receive measurement data from camera module 1171 regarding the presence or absence of a user, the user's position, and the user's gaze. Processor 1110 can also correct the brightness of image data based on the measurement data. For example, when processor 1110 determines the presence or absence of a user based on input from camera module 1171, processor 1110 can output its brightness-corrected image data to display module 1140 via data conversion circuit 1112-2 or gamma correction circuit 1112-3.

[0208] Some of the aforementioned components can be connected to each other via peripheral communication methods (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or ultrapath interconnect (UPI) link) and can exchange signals (e.g., commands or data). Processor 1110 can communicate with display module 1140 through a mutually agreed interface; for example, one of the aforementioned communication methods can be used, but the communication methods are not limited to these.

[0209] In the scan driver and display device including the scan driver according to embodiments of the present disclosure, the scan driver may include multiple stages, and by charging and maintaining the common Q-node switch (CQS) node of each stage at a high voltage level, deviation of the scan signal can be reduced. Therefore, horizontal line defects caused by brightness differences between pixel rows in the display device can be prevented or mitigated. Furthermore, transistor degradation can be prevented or mitigated by resetting the first output control node (or common Q-node switch (CQS) node) of each stage via the voltage of the second node (or QB node) of the current stage and the voltage of the QB node of the next stage.

[0210] Although some embodiments and applications have been described herein, other embodiments and variations can be derived from the above description. Therefore, the concept of this disclosure is not limited to these embodiments, but extends to the claims of the illustrated patent, various obvious variations and equivalents.

[0211] According to some embodiments of this disclosure, a scan driver with improved reliability, a display device including the scan driver, and an electronic device including the scan driver are provided.

[0212] The embodiments disclosed herein are not limited to the foregoing aspects, and many more aspects are included in this specification.

Claims

1. A scan driver, the scan driver comprising a stage configured to output a scan signal, wherein, The nth level in the hierarchy includes: The voltage charging section is connected to a first power line and a second power line, and is configured to: transmit the voltage of the first power line to a first output control node in response to a first carry signal from the (n-1)th stage; and transmit the voltage of the second power line to the first output control node in response to the voltage of the second output control node. The voltage reset section includes a transistor connected in series between the first output control node and the third power line, and is configured to reset the voltage of the first output control node; and The scan signal output section is configured to output one or more scan signals in response to the voltage of the second output control node. Where n is an integer greater than 1.

2. The scan driver according to claim 1, wherein, The voltage charging section includes: A first transistor is connected between the first power line and the first output control node, and has a gate electrode connected to a first carry line configured to receive the first carry signal. A second transistor is connected between the second power line and the first output control node, and has a gate electrode connected to the second output control node; and A first capacitor is connected between the first power line and the first output control node.

3. The scan driver according to claim 1, wherein, The transistors connected in series include: A third transistor is connected between the first output control node and the third power line, and has a gate electrode connected to the second node of the nth stage; and A fourth transistor is connected between the third transistor and the third electric field line, and has a gate electrode connected to the second node of the (n+1)th stage in the stage. The third transistor and the fourth transistor are configured to turn on in response to the voltage of the second node of the nth stage and the voltage of the second node of the (n+1)th stage, respectively, such that the first output control node has the voltage of the third power line.

4. The scan driver according to claim 1, wherein, One of the scan signal output sections is connected to the scan clock line and is configured to output a signal from the scan clock line as one of the scan signals according to the voltage of the second output control node.

5. The scan driver according to claim 1, wherein, One of the scan signal output sections includes: The fifth transistor is connected between the first node and the third node and has a gate electrode connected to the first output control node; A second capacitor is connected between the third node and the second output control node; A sixth transistor, connected between the scan clock line and the scan line, and having a gate electrode connected to the third node; and The seventh transistor is connected between the scan line and the third power line, and has a gate electrode connected to the second node of the nth stage.

6. The scan driver according to claim 5, wherein, The nth stage further includes an eighth transistor configured to transmit a boost clock signal to the second output control node in response to the voltage of the first node, so as to boost the voltage of the third node through the second capacitor.

7. The scan driver according to claim 1, wherein, The nth stage further includes a boost controller configured to transmit a boost clock signal to the second output control node in response to the voltage of the first node, and to increase the voltage of the first node according to the boost clock signal.

8. The scan driver according to claim 1, wherein, The nth level includes: The eighth transistor is connected between the boost clock line and the second output control node, and has a gate electrode connected to the first node; A third capacitor is connected between the gate electrode of the eighth transistor and the second output control node; and The ninth transistor is connected between the second output control node and the fourth power line, and has a gate electrode connected to the second node.

9. The scan driver according to claim 1, wherein, The nth stage further includes: a carry signal output section connected between the carry clock line and the fourth power line, configured to output the signal of the carry clock line as a second carry signal in response to the voltage of the first node, and configured to output the voltage of the fourth power line as the second carry signal in response to the voltage of the second node.

10. A scan driver, the scan driver comprising stages configured to output a scan signal, the nth stage comprising: The first transistor has a first electrode connected to a first power line, a second electrode connected to a first output control node, and a gate electrode connected to a first carry line, the first carry line being connected to the (n-1)th stage in the stage; The second transistor has a first electrode connected to a second power line, a second electrode connected to the first output control node, and a gate electrode connected to the second output control node; A first capacitor is connected between the first power line and the first output control node; A transistor connected in series between the first output control node and the third power line; as well as The scan signal output section is configured to output one or more scan signals in response to the voltage of the second output control node. Where n is an integer greater than 1.

11. The scan driver according to claim 10, wherein, The voltage of the first electric field line is higher than the voltage of the second electric field line.

12. The scan driver according to claim 10, wherein, The nth level also includes: The tenth transistor has a first electrode connected to a carry clock line, a second electrode connected to a second carry line, and a gate electrode connected to a first node, the second carry line being connected to the (n-1)th and (n+1)th stages in the stage; and The eleventh transistor has a first electrode connected to the second carry line, a second electrode connected to the fourth power line, and a gate electrode connected to the second node.

13. The scan driver according to claim 10, wherein, The transistors connected in series include: A third transistor is connected between the first output control node and the third power line, and has a gate electrode connected to the second node of the nth stage; and A fourth transistor is connected between the third transistor and the third electric field line, and has a gate electrode connected to the second node of the (n+1)th stage in the stage. The third transistor and the fourth transistor are configured to turn on in response to the voltage of the second node of the nth stage and the voltage of the second node of the (n+1)th stage, respectively, such that the voltage of the first output control node has the voltage of the third electric field line.

14. The scan driver according to claim 10, wherein, One of the scan signal output sections includes: The fifth transistor is connected between the first node and the third node and has a gate electrode connected to the first output control node; A second capacitor is connected between the third node and the second output control node; A sixth transistor, connected between the scan clock line and the scan line, and having a gate electrode connected to the third node; and The seventh transistor is connected between the scan line and the third power line, and has a gate electrode connected to the second node of the nth stage.

15. An electronic device, the electronic device comprising: A display panel includes scan lines and pixels connected to the scan lines; The processor is configured to provide input image data; The controller is configured to receive the input image data from the processor and is configured to drive the display panel; as well as A scan driver, configured to supply a scan signal to the display panel, and including stages configured to output the scan signal to the scan lines, wherein the nth stage comprises: The voltage charging section is connected to the first power line and the second power line, and is configured to transmit the voltage of the first power line to the first output control node in response to a first carry signal from the (n-1)th stage, and is configured to transmit the voltage of the second power line to the first output control node in response to the voltage of the second output control node. The voltage reset section includes a transistor connected in series between the first output control node and the third power line, and is configured to reset the voltage of the first output control node; and The scan signal output section is configured to output one or more scan signals in response to the voltage of the second output control node. Where n is an integer greater than 1.

16. The electronic device according to claim 15, wherein, The voltage of the first output control node is configured to fluctuate via one of the first carry signal of the (n-1)th stage, the voltage of the second output control node, and the voltage of the second node of the (n+1)th stage.

17. The electronic device according to claim 15, wherein, The voltage of the first power line is configured to be applied as the voltage of the first output control node, and the voltage of the second power line is configured to be applied as the voltage of the first output control node in response to the voltage of the second output control node.

18. The electronic device according to claim 15, wherein, The voltage of the first output control node is configured to have the voltage of the third electric field line in response to the voltage of the second node of the nth stage and the voltage of the second node of the (n+1)th stage in the stage.

19. The electronic device according to claim 15, wherein, The nth stage is configured to transmit a boost clock signal to the second output control node in response to the voltage of the first node, and is configured to increase the voltage of the first node according to the boost clock signal transmitted to the second output control node.

20. The electronic device according to claim 15, wherein, The third node is configured to be electrically isolated from the first node based on the voltage of the first node and the voltage of the first output control node.

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