Restarting circuit, timing control system and display device

Abstract

Embodiments of the present application disclose a restart circuit, a timing control system and a display device. The restart circuit comprises a comparison circuit and a switch circuit. A first input end of the comparison circuit is connected to a first output end of a power management chip of the display device to input a first voltage. A second input end of the comparison circuit is connected to a source driver of the display device to input a second voltage. The switch circuit is connected to an output end of the comparison circuit, a second output end of the power management chip and a reset end of a timing controller of the display device. When the timing controller loads a code to start the display device, if the first voltage is greater than the second voltage, the comparison circuit controls the switch circuit to be connected or disconnected between the second output end of the power management chip and the reset end of the timing controller to output a reset signal to the reset end of the timing controller. The timing controller is restarted based on the reset signal. Manual intervention of the display device during the start-up process is avoided, and the efficiency and reliability of the start-up of the display device are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a restart circuit, a timing control system, and a display device. Background Technology

[0002] During the power-on process, the timing controller sends training sequence data to the source driver. Once the source driver successfully receives and parses the training sequence data, it sends a lock signal back to the timing controller to notify it that it can begin transmitting real image data. However, if the training process continues to fail, the display screen will go black, requiring manual power-on / off to reload the initialization code until the display device powers on normally. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this application provides a restart circuit, a timing control system, and a display device, aiming to solve the technical problem that requires manual power-on when the screen is black, thereby improving the efficiency and reliability of the display device's power-on process.

[0004] To address the aforementioned problems, in a first aspect, this application provides a restart circuit applied to a display device, the restart circuit comprising:

[0005] The comparator circuit has a first input terminal connected to the first output terminal of the power management chip of the display device to input a first voltage, and a second input terminal connected to the source driver of the display device to input a second voltage. The switching circuit is connected to the output of the comparator circuit, the second output of the power management chip, and the reset terminal of the timing controller of the display device, respectively. When the timing controller loads code to start the display device, if the first voltage is greater than the second voltage, the comparator circuit controls the connection or disconnection between the second output terminal of the power management chip and the reset terminal of the timing controller, so as to output a reset signal to the reset terminal of the timing controller, and the timing controller restarts based on the reset signal.

[0006] In one embodiment, the comparator circuit includes an operational amplifier and a filter circuit; The first input terminal of the operational amplifier is connected to the first output terminal of the power management chip, the second input terminal of the operational amplifier is connected to the first terminal of the filter circuit, the output terminal of the operational amplifier is connected to the switching circuit, the second terminal of the filter circuit is connected to the source driver, and the third terminal of the filter circuit is grounded.

[0007] In one embodiment, the filter circuit includes a first resistor and a first capacitor; One end of the first resistor is connected to the source driver, and the other end of the first resistor is connected to the second input terminal of the operational amplifier and one end of the first capacitor, respectively. The other end of the first capacitor is grounded.

[0008] In one embodiment, the switching circuit includes a first switch, a voltage divider circuit, and a second switch; Among them, the control terminal of the first switch is connected to the output terminal of the comparator circuit, the first terminal of the first switch is connected to the first terminal of the voltage divider circuit, and the second terminal of the first switch is grounded. The second terminal of the voltage divider circuit is connected to the control terminal of the second switch, and the third terminal of the voltage divider circuit and the first terminal of the second switch are both connected to the second output terminal of the power management chip. The second terminal of the second switch is connected to the reset terminal of the timing controller and grounded; When the timing controller loads code to start the display device, if the first voltage is greater than the second voltage, the first and second terminals of the first switch are disconnected, the first and second terminals of the second switch are disconnected, and the timing controller restarts.

[0009] In one embodiment, the voltage divider circuit includes a second resistor and a third resistor; One end of the second resistor is connected to the second output terminal of the power management chip, the other end of the second resistor is connected to the control terminal of the second switch and one end of the third resistor, and the other end of the third resistor is connected to the first terminal of the first switch.

[0010] In one embodiment, the first voltage is configured as the power supply voltage of the display panel of the display device; or / and, The second output terminal of the power management chip is connected to the power supply terminal of the timing controller to provide power supply voltage to the timing controller.

[0011] In one embodiment, the feedback terminal of the source driver is connected to a timing controller to output a lock signal in the form of a second voltage to the timing controller.

[0012] In one embodiment, when the timing controller loads code to start the display device, the timing controller is configured to output training sequence data to the source driver, and the source driver is configured to output a lock signal to the timing controller based on the training sequence data.

[0013] Secondly, this application also provides a timing control system, which includes a timing controller and a restart circuit provided in the first aspect.

[0014] Thirdly, this application also provides a display device, which includes a display panel, a power management system, and a timing control system provided in the second aspect.

[0015] The restart circuit provided in this application includes a comparator circuit and a switch circuit. The first input terminal of the comparator circuit is connected to the first output terminal of the power management chip of the display device to input a first voltage, and the second input terminal of the comparator circuit is connected to the source driver of the display device to input a second voltage. The switch circuit is connected to the output terminal of the comparator circuit, the second output terminal of the power management chip, and the reset terminal of the timing controller of the display device. When the timing controller loads code to start the display device, if the first voltage is greater than the second voltage, the comparator circuit controls the connection or disconnection between the second output terminal of the power management chip and the reset terminal of the timing controller to output a reset signal to the reset terminal of the timing controller. The timing controller restarts based on the reset signal, thereby solving the problem of needing to manually turn the device on and off, avoiding manual intervention during the power-on process, and improving the efficiency and reliability of the power-on process of the display device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic block diagram of the restart circuit provided in an embodiment of this application; Figure 2 A circuit diagram of the charging circuit provided in an embodiment of this application; Figure 3 A first timing diagram for powering on a display device provided in an embodiment of this application; Figure 4 A second timing diagram for powering on a display device provided in an embodiment of this application; Figure 5 A third timing diagram for powering on a display device provided in an embodiment of this application; Figure 6 A schematic block diagram of a timing control system provided in an embodiment of this application; Figure 7 A schematic block diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0020] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0021] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0022] Furthermore, in this application, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication between two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific implementation.

[0023] In related technologies, during the power-on process of a display device, the timing controller (TCON) is responsible for loading initialization code to coordinate system operation.

[0024] like Figure 3 As shown, during normal operation, the display device performs power-on initialization. The power supply signal VIN changes from low to high at time t0, and the timing controller enters free run mode. The timing controller's reset signal RESET changes from low to high at time t1, and then the timing controller (Source Driver) sends training sequence data to the source driver. When the source driver successfully receives and parses the training sequence data at time t2, the lock signal LOCK fed back by the source driver to the timing controller changes from low to high to notify the timing controller that it can start transmitting real image data. The timing controller can then continue sending screen data, and the display device successfully displays the image.

[0025] However, when the training process continues to fail, such as Figure 4 As shown, the LOCK signal fed back from the source driver to the timing controller will remain at a low level, and the screen of the display device will be black. The main reason for this is that the timing controller has a configuration error during the code loading stage, which requires manual power-on and power-off operations to force a restart of the timing controller, reload the code and try to configure it until training is successful. This not only increases the complexity of operation and reduces the user experience, but may also cause unnecessary downtime of the device in critical application scenarios, affecting the overall operating efficiency.

[0026] To address the aforementioned technical problems, this application provides a restart circuit, a timing control system, and a display device. The restart circuit includes a comparator circuit and a switching circuit. The first input terminal of the comparator circuit is connected to the first output terminal of the power management chip of the display device to input a first voltage. The second input terminal of the comparator circuit is connected to the source driver of the display device to input a second voltage. The switching circuit is connected to the output terminal of the comparator circuit, the second output terminal of the power management chip, and the reset terminal of the timing controller of the display device. When the timing controller loads code to start the display device, if the first voltage is greater than the second voltage, the comparator circuit controls the connection or disconnection between the second output terminal of the power management chip and the reset terminal of the timing controller, thereby inputting a reset signal at the reset terminal of the timing controller. The timing controller restarts based on the reset signal, avoiding manual intervention during the power-on process and improving the efficiency and reliability of the display device's power-on.

[0027] Please see Figure 1 , Figure 1 This is a schematic block diagram of the restart circuit 110 provided in an embodiment of this application. Figure 1 As shown, this application provides a restart circuit 110, which is applied to a display device 10. The restart circuit 110 includes: The comparator circuit 111 has a first input terminal connected to the first output terminal of the power management chip 210 of the display device 10 to input a first voltage, and a second input terminal connected to the source driver 300 of the display device 10 to input a second voltage. The switching circuit 112 is connected to the output terminal of the comparator circuit 111, the second output terminal of the power management chip 210, and the reset terminal of the timing controller 120 of the display device 10, respectively. When the timing controller 120 loads code to start the display device 10, if the first voltage is greater than the second voltage, the comparison circuit 111 controls the connection or disconnection between the second output terminal of the power management chip 210 and the reset terminal of the timing controller 120, so as to output a reset signal to the reset terminal of the timing controller 120, and the timing controller 120 restarts based on the reset signal.

[0028] In this embodiment, the restart circuit 110 is used to automatically trigger the timing controller 120 to restart when it is detected that the screen of the display device 10 will turn black during the startup process of the display device 10. The timing controller reloads the initialization code until the display device 10 is powered on normally.

[0029] Display device 10 is an electronic device that integrates components such as display panel 400, power management system 200, and timing control system 100, such as a television, monitor, smartphone, or tablet computer.

[0030] The power management chip 210 is responsible for managing the power supply inside the display device 10, including generating and distributing various operating voltages, and may provide a reference voltage or supply voltage.

[0031] The source driver 300 is connected to the timing controller 120 to receive training sequence data from the timing controller 120. When the display device 10 is started, the source driver 300 may train with the timing controller 120 to establish communication.

[0032] The timing controller 120 is one of the core control units of the display device 10. It is responsible for generating various timing signals, controlling the data transmission and display refresh of the display panel 400, and loading startup code to configure the entire display system.

[0033] The comparator circuit 111 is used to compare the magnitudes of two input voltages and output a corresponding control signal based on the comparison result.

[0034] The switching circuit 112 controls the conduction or disconnection of a specific path in the circuit according to the received control signal, thereby realizing the transmission or blocking of the signal.

[0035] The first voltage can be understood as the reference voltage input at the first input terminal of the comparator circuit. It can be input from the first output terminal of the power management chip 210 to the first input terminal of the comparator circuit 111, and compared with the second voltage input by the source driver 300 in the comparator circuit 111 to determine whether the source driver 300 has successfully received and parsed the training sequence data, and then determine whether to input a reset signal to the timing controller 120 to restart the timing controller 120.

[0036] The second voltage can be understood as the feedback made by the source driver 300 after the timing controller 120 sends the training sequence data to the source driver 300. It can also be understood as the lock signal LOCK output by the source driver 300 to the timing controller 120. The level change of the lock signal LOCK can characterize whether the source driver 300 has successfully received and parsed the training sequence data.

[0037] When a reset signal is applied to the reset terminal of the timing controller 120, it triggers the timing controller 120 to stop its current operation and restart the startup program. The reset signal can be either a high-level signal or a low-level signal; this application specifically uses a low-level reset signal to restart the timing controller. It should be noted that the type of reset signal can be selected according to the actual application, and this application does not impose any specific limitations.

[0038] Specifically, the restart circuit 110 provided in this application can improve the startup reliability and user experience of the display device 10. The restart circuit 110 can be implemented as an independent module on the motherboard of the display device 10, or integrated into the existing chipset of the display device 10, such as the power management chip 210 or the timing controller 120.

[0039] The restart circuit 110 includes a comparator circuit 111 and a switch circuit 112. The first input terminal of the comparator circuit 111 is connected to the first output terminal of the power management chip 210 of the display device 10 to receive and input a first voltage. The first voltage can be a reference voltage, such as one provided by a reference voltage source inside the power management chip 210. Alternatively, the first voltage can be the power supply voltage of the display panel 400 of the display device 10, such as VDD or VCC. The second input terminal of the comparator circuit 111 is connected to the source driver 300 of the display device 10 to receive and input a second voltage. The second voltage is typically a lock signal (LOCK) output by the source driver 300 during training with the timing controller 120; its level reflects the success or failure of the training. For example, when training is successful, the second voltage may be pulled high; when training fails, the second voltage may remain low.

[0040] The switching circuit 112 is connected to the output terminal of the comparator circuit 111, the second output terminal of the power management chip 210, and the reset terminal of the timing controller 120 of the display device 10. The function of the switching circuit 112 is to control the connection state between the second output terminal of the power management chip 210 and the reset terminal of the timing controller 120 based on the output result of the comparator circuit 111, thereby determining whether to output a reset signal to the reset terminal of the timing controller 120.

[0041] The switching circuit 112 can be composed of one or more transistors, such as a bipolar junction transistor (BJT), also known as a triode. The on or off state of the triode can be controlled by the output signal of the comparator circuit 111.

[0042] The second output of the power management chip 210 can be a power supply voltage output, such as VDDIO, which provides the operating voltage for the timing controller 120.

[0043] When the timing controller 120 of the display device 10 loads code to start the display device 10, the restart circuit 110 begins to operate. If the comparator circuit 111 detects that the first voltage is greater than the second voltage, it can be determined that the training process between the timing controller 120 and the source driver 300 has failed to complete successfully. At this time, the comparator circuit 111 will output a control signal to the switching circuit 112 to connect or disconnect the second output terminal of the control power management chip 210 from the reset terminal of the timing controller 120, thereby restarting the timing controller 120.

[0044] For example, when the first voltage is greater than the second voltage, the switching circuit 112 can be configured to pull the reset terminal of the timing controller 120 low, thereby outputting a low-level signal that can trigger the reset function to the reset terminal of the timing controller 120. Then, after receiving the low-level reset signal, the timing controller 120 restarts, reloads the startup code, and attempts to configure and train again.

[0045] In this application, when training failure is detected, i.e., when the first voltage is greater than the second voltage, a reset signal can be automatically generated and output to the reset terminal of the timing controller 120, thereby triggering the timing controller 120 to automatically restart, reload the code and complete the configuration. This effectively solves the problem that the timing controller 120 needs to be manually turned on and off in the traditional solution to reconfigure it, improves the startup efficiency and user experience of the display device 10, avoids the black screen phenomenon caused by training failure, and restores normal display without manual intervention.

[0046] For example, such as Figure 5 As shown, when the training process continues to fail, the lock signal LOCK fed back from the source driver 300 to the timing controller 120 will remain at a low level. At this time, the comparator circuit 111 can compare the power supply voltage VDD (first voltage) of the display panel 400 with the lock signal LOCK (second voltage). If the first voltage is greater than the second voltage, it can be determined that the training process between the timing controller 120 and the source driver 300 has failed to be completed successfully. At this time, the comparator circuit 111 will output a control signal to the switch circuit 112, so that the reset signal of the reset terminal of the timing controller 120 changes from a high level signal to a low level signal, so that the timing controller 120 restarts, reloads the startup code, and attempts to configure and train again.

[0047] In some embodiments, such as Figure 2As shown, the comparator circuit 111 includes an operational amplifier OP1 and a filter circuit; wherein, the first input terminal 1 of the operational amplifier OP1 is connected to the first output terminal of the power management chip 210, the second input terminal 2 of the operational amplifier OP1 is connected to the first terminal of the filter circuit, the output terminal 3 of the operational amplifier OP1 is connected to the switching circuit 112, the second terminal of the filter circuit is connected to the source driver 300, and the third terminal of the filter circuit is grounded.

[0048] In this embodiment, the first input terminal 1 of operational amplifier OP1 is directly connected to the first output terminal of power management chip 210 to receive a stable first voltage as a comparison reference. The second input terminal 2 of operational amplifier OP1 is connected to the first terminal of filter circuit to receive the filtered second voltage. The output terminal 3 of operational amplifier OP1 is connected to switch circuit 112 to transmit the comparison result to switch circuit 112 as a signal to control the switching circuit 112 to turn on and off. Simultaneously, operational amplifier OP1 also has a first power supply terminal 4 and a second power supply terminal 5. The first power supply terminal 4 is connected to the second output terminal of power management chip 210, and the second power supply terminal 5 is grounded (GND).

[0049] In some embodiments, such as Figure 2 As shown, the filter circuit includes a first resistor R1 and a first capacitor C1; one end of the first resistor R1 is connected to the source driver 300, the other end of the first resistor R1 is connected to the second input terminal 2 of the operational amplifier OP1 and one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

[0050] In this embodiment, the filtering circuit can use an RC filter structure composed of a first resistor R1 and a first capacitor C1. Through the first resistor R1, the second voltage output by the source driver 300 can be initially impedance matched and signal attenuated, which helps to suppress high-frequency noise. The first capacitor C1 can filter out the high-frequency noise components in the second voltage, so that the second input terminal 2 of the operational amplifier OP1 receives a more stable second voltage. This allows the operational amplifier OP1 to more accurately determine the relationship between the first voltage and the second voltage, avoiding misjudgments caused by signal fluctuations or noise. This accurately triggers the precise restart of the timing controller 120, thereby achieving automatic recovery of the display device 10 without manual power on / off, significantly improving the stability of the system and the user experience.

[0051] In some embodiments, such as Figure 2As shown, the switching circuit 112 includes a first switch Q1, a voltage divider circuit, and a second switch Q2. The control terminal of the first switch Q1 is connected to the output terminal of the comparator circuit 111, the first terminal of the first switch Q1 is connected to the first terminal of the voltage divider circuit, and the second terminal of the first switch Q1 is grounded to GND. The second terminal of the voltage divider circuit is connected to the control terminal of the second switch Q2, and the third terminal of the voltage divider circuit and the first terminal of the second switch Q2 are both connected to the second output terminal of the power management chip 210. The second terminal of the second switch Q2 is connected to the reset terminal of the timing controller 120 and grounded to GND. When the timing controller 120 loads code to start the display device 10, if the first voltage is greater than the second voltage, the first and second terminals of the first switch Q1 are disconnected, the first and second terminals of the second switch Q2 are disconnected, and the timing controller 120 restarts.

[0052] In this embodiment, the first switch Q1 can be turned on or off according to the control signal output by the comparator circuit 111. If the first switch Q1 is turned on, the voltage divider circuit divides the voltage output by the second output terminal of the power management chip 210, and at the same time, the second switch Q2 is turned on, and the reset terminal of the timing controller 120 receives a high-level signal. At this time, the timing controller 120 does not restart. If the first switch Q1 is turned off, the voltage divider circuit stops dividing the voltage output by the second output terminal of the power management chip 210, and at the same time, the second switch Q2 is turned off, and the reset terminal of the timing controller 120 receives a low-level signal. At this time, the timing controller 120 restarts.

[0053] It should be noted that the on or off state of the first switch Q1 can be determined by the control signal output by the comparator circuit 111. The first switch Q1 can be implemented in various forms. For example, it can be a field-effect transistor (such as a MOSFET), with its gate as the control terminal and its source and drain as the first and second terminals; or it can be a bipolar transistor (such as a BJT), with its base as the control terminal and its collector and emitter as the first and second terminals. Additionally, a resistor R4 is provided between the control terminal of the first switch Q1 and the output terminal 3 of the operational amplifier OP1.

[0054] The voltage divider circuit can provide a precisely set control voltage to ensure that the second switch Q2 can be accurately turned on or off under specific conditions.

[0055] The second switch Q2 controls the level of the reset terminal of the timing controller 120 based on the control voltage output from the voltage divider circuit, ensuring that a reset signal is not output under specific conditions. The on or off state of the second switch Q2 can be determined by the signal output from the second terminal of the voltage divider circuit. Simultaneously, the second terminal of the second switch Q2 is also grounded to GND through resistor R5.

[0056] It should be noted that the first switch Q1 and the second switch Q2 can be selected according to the actual application, and this application does not impose any specific restrictions.

[0057] In this application, by setting a first switch Q1, a voltage divider circuit, and a second switch Q2 in the switching circuit 112, when the comparator circuit 111 detects that the first voltage is greater than the second voltage, its output signal directly drives the first switch Q1 to open. Since the second terminal of the first switch Q1 is connected to the reset terminal of the timing controller 120 and grounded to GND, the conduction of the first switch Q1 can quickly pull the reset terminal of the timing controller 120 down to the ground potential, thereby directly triggering the timing controller 120 to restart.

[0058] Simultaneously, the opening of the first switch Q1 also changes the voltage distribution of the voltage divider circuit, causing the control voltage output by the voltage divider circuit to open the second switch Q2. Since the first terminal of the second switch Q2 is connected to the second output terminal of the power management chip 210, the opening of the second switch Q2 effectively isolates the second output terminal of the power management chip 210 from the reset terminal of the timing controller 120, avoiding interference of the output voltage of the power management chip 210 on the reset signal, ensuring the purity and effectiveness of the reset signal, and realizing fast, accurate and automatic control of the reset signal of the timing controller 120 without manual intervention, significantly improving the recovery efficiency and system stability of the display device 10 when startup fails.

[0059] For example, when the timing controller 120 of the display device 10 loads code to start the display device 10, the restart circuit 110 starts working. If the comparator circuit 111 detects that the first voltage is less than the second voltage, it can be determined that the training process between the timing controller 120 and the source driver 300 has been successfully completed. At this time, the comparator circuit 111 outputs a control signal to control the first switch Q1 to turn on, the voltage divider circuit divides the voltage output from the second output terminal of the power management chip 210, and at the same time, the second switch Q2 turns on, the reset terminal of the timing controller 120 inputs a high-level signal, and thus the timing controller 120 does not restart. If the comparator circuit 111 detects that the first voltage is greater than the second voltage, it can be determined that the training process between the timing controller 120 and the source driver 300 has not been successfully completed. At this time, the comparator circuit 111 outputs a control signal to control the first switch Q1 to turn off, the voltage divider circuit stops dividing the voltage output from the second output terminal of the power management chip 210, and at the same time, the second switch Q2 turns off, the reset terminal of the timing controller 120 inputs a low-level signal, and thus the timing controller 120 restarts.

[0060] In some embodiments, such as Figure 2As shown, the voltage divider circuit includes a second resistor R2 and a third resistor R3; one end of the second resistor R2 is connected to the second output terminal of the power management chip 210, the other end of the second resistor R2 is connected to the control terminal of the second switch Q2 and one end of the third resistor R3, and the other end of the third resistor R3 is connected to the first terminal of the first switch Q1.

[0061] In this application, one end of the second resistor R2 is connected to the second output terminal of the power management chip 210, providing a stable input voltage source for the voltage divider circuit. The other end of the second resistor R2 is connected to the control terminal of the second switch Q2 and one end of the third resistor R3, so that the voltage after voltage division can directly and effectively control the conduction state of the second switch Q2. The other end of the third resistor R3 is connected to the first terminal of the first switch Q1, and combined with the grounding characteristics of the first switch Q1, provides a stable reference ground for the voltage divider circuit.

[0062] When the first voltage is greater than the second voltage, the first switch Q1 is opened, and its first terminal is pulled low. At this time, the voltage divider circuit can accurately divide the voltage of the second output terminal of the power management chip 210 according to the ratio of the second resistor R2 and the third resistor R3, and output a specific control voltage to the control terminal of the second switch Q2, thereby ensuring that the reset terminal of the timing controller 120 is pulled low (through the grounding effect of the first switch Q1), realizing the restart of the timing controller 120. This avoids false triggering or missed triggering caused by inaccurate voltage control, significantly improving the reliability and stability of the restart circuit 110, so that the display device 10 can automatically and accurately restart when the timing controller 120 is configured abnormally, without manual intervention, thereby improving the user experience.

[0063] In some embodiments, the first voltage is configured as the power supply voltage of the display panel 400 of the display device 10; the second output terminal of the power management chip 210 is connected to the power supply terminal of the timing controller 120 to provide power supply voltage to the timing controller 120.

[0064] Specifically, the first voltage is the voltage received at the first input terminal of the comparator circuit 111, and the power supply voltage is the voltage that provides operating power to the display panel 400. The power supply voltage can be the analog power supply voltage AVDD of the display panel 400, or it can be the power supply voltage VDD of the display panel 400, for example, 0.9V. By configuring the first voltage to be the power supply voltage of the display panel 400, this application ensures that the comparator circuit 111 receives a reliable signal that directly reflects the operating state of the display panel 400, thereby improving the accuracy of the comparator circuit 111's judgment and avoiding misjudgments caused by unclear voltage sources.

[0065] The second output terminal of the power management chip 210 is an output port that provides power to the power management chip 210, while the power supply terminal of the timing controller 120 is a pin that receives the operating voltage required for the timing controller 120 to operate normally. The second output terminal of the power management chip 210 can directly output a stable DC voltage, such as 2.5V or 1.8V, as the main power supply voltage VDDIO of the timing controller 120, which can ensure that the timing controller 120 receives a stable power supply during normal operation and restart.

[0066] In some embodiments, such as Figure 2 As shown, the feedback terminal of the source driver 300 is connected to the timing controller 120 to output a lock signal in the form of a second voltage to the timing controller 120.

[0067] In this embodiment, the feedback terminal of the source driver 300 is connected to the timing controller 120, enabling it to transmit a lock signal LOCK in real time to the timing controller 120 in the form of a second voltage. The second voltage output to the timing controller 120 can be understood as the lock signal LOCK output by the source driver 300, which indicates whether the training between the source driver 300 and the timing controller 120 has been successful. When training is successful, the lock signal LOCK may be high; when training fails, the lock signal LOCK may be low.

[0068] Specifically, this application provides real-time training status information to the timing controller 120 by outputting a second voltage. This allows the timing controller 120 to determine whether the source driver 300 has successfully completed the initialization and training process based on the received second voltage. When the training between the source driver 300 and the timing controller 120 fails, the timing controller 120 can immediately detect the abnormal state of the second voltage and respond more intelligently. This effectively reduces the black screen time caused by training failure and reduces the need for manual intervention, further optimizing the automatic restart function.

[0069] In some embodiments, when the timing controller 120 loads code to start the display device 10, the timing controller 120 is configured to output training sequence data to the source driver 300, and the source driver 300 is configured to output a lock signal LOCK to the timing controller 120 based on the training sequence data.

[0070] In this embodiment, the training sequence data includes, but is not limited to, grayscale test patterns, color stripes, or specific timing signal sequences. The timing controller 120 sends the training sequence data to the source driver 300. After receiving the training sequence data, the source driver 300 processes it according to its internal logic and outputs a corresponding signal, namely the lock signal LOCK, to the timing controller 120.

[0071] Furthermore, after receiving and processing the training sequence data sent by the timing controller 120, the source driver 300 generates a lock signal LOCK, i.e., a second voltage, based on its internal state or processing result. The lock signal LOCK can reflect the response of the source driver 300 to the training sequence data, such as its internal register state, the integrity of data processing, or the health of its output drive capability.

[0072] In this application, when the timing controller 120 loads code to start the display device 10, the timing controller 120 actively outputs training sequence data to the source driver 300, and the source driver 300 outputs a lock signal LOCK to the timing controller 120 based on the training sequence data. When training fails, the restart circuit 110 can trigger the timing controller 120 to reset in time according to the lock signal LOCK, causing the timing controller 120 to reload the code and perform configuration, avoiding black screen or display abnormality caused by training failure. The system can be automatically restored without manual intervention, which significantly improves the startup reliability of the display device 10 and the user experience.

[0073] In some embodiments, such as Figure 6 As shown, this application also provides a timing control system 100, which includes a timing controller 120 and a restart circuit 110 provided in this application.

[0074] Specifically, this application combines the timing controller 120 with the restart circuit 110 in a specific way, thereby automatically triggering the timing controller 120 to restart when the first voltage is detected to be greater than the second voltage, achieving the effect of reloading the code and completing the correct configuration without manual intervention.

[0075] In some embodiments, such as Figure 7 As shown, this application also provides a display device 10, which includes a display panel 400, a power management system 200, and a timing control system 100 provided in this application.

[0076] In this application, the power management system 200 is a system for managing and regulating power supply, providing a stable and efficient power supply to the display device 10. The power management system 200 may consist of a power management integrated circuit, a voltage regulator, a power converter, and corresponding control logic. The main function of the power management system 200 is to ensure that a stable voltage and current meeting requirements are provided to loads such as the display panel 400.

[0077] The power management chip 210 can provide a stable and reliable power supply for the display panel 400, and can realize power conversion, voltage regulation, current limiting, power timing control and various protection functions. The power management module can be a PMIC (Power Management IC).

[0078] Display panel 400 may be a liquid crystal display panel. It should be noted that this application does not limit the type of display panel 400. Specifically, the liquid crystal display panel mentioned in this application may be a horizontal electric field type liquid crystal display panel, such as a fringe field switching (FFS) type liquid crystal display panel or an in-plane switching (In... Plane Switching (IPS) type liquid crystal display panels can also be vertical electric field type liquid crystal display panels, such as twisted nematic (TN) type liquid crystal display panels, multi-domain vertical alignment (Multi... Domain Vertical Alignment (MVA) type liquid crystal display panel.

[0079] Furthermore, the display panel 400 mentioned in this application can be used in mobile phones, tablets, desktop computers, laptops, e-readers, handheld computers, electronic display screens, laptops, and Ultra Mobile Personal Computers (Ultra). Mobile Personal Computers (UMPCs), netbooks, cellular phones, Personal Digital Assistants (PDAs), Augmented Reality (AR) / Virtual Reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0080] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A restart circuit, characterized in that, The restart circuit, applied to a display device, includes: A comparator circuit, wherein the first input terminal of the comparator circuit is connected to the first output terminal of the power management chip of the display device to input a first voltage, and the second input terminal of the comparator circuit is connected to the source driver of the display device to input a second voltage; A switching circuit is connected to the output terminal of the comparator circuit, the second output terminal of the power management chip, and the reset terminal of the timing controller of the display device, respectively. When the timing controller loads code to start the display device, if the first voltage is greater than the second voltage, the comparator circuit controls the connection or disconnection between the second output terminal of the power management chip and the reset terminal of the timing controller to output a reset signal to the reset terminal of the timing controller, and the timing controller restarts based on the reset signal.

2. The restart circuit according to claim 1, characterized in that, The comparator circuit includes an operational amplifier and a filter circuit; The first input terminal of the operational amplifier is connected to the first output terminal of the power management chip, the second input terminal of the operational amplifier is connected to the first terminal of the filter circuit, the output terminal of the operational amplifier is connected to the switching circuit, the second terminal of the filter circuit is connected to the source driver, and the third terminal of the filter circuit is grounded.

3. The restart circuit according to claim 2, characterized in that, The filter circuit includes a first resistor and a first capacitor; Wherein, one end of the first resistor is connected to the source driver, the other end of the first resistor is connected to the second input terminal of the operational amplifier and one end of the first capacitor, and the other end of the first capacitor is grounded.

4. The restart circuit according to claim 1, characterized in that, The switching circuit includes a first switch, a voltage divider circuit, and a second switch. Wherein, the control terminal of the first switch is connected to the output terminal of the comparator circuit, the first terminal of the first switch is connected to the first terminal of the voltage divider circuit, and the second terminal of the first switch is grounded. The second terminal of the voltage divider circuit is connected to the control terminal of the second switch, and the third terminal of the voltage divider circuit and the first terminal of the second switch are both connected to the second output terminal of the power management chip. The second terminal of the second switch is connected to the reset terminal of the timing controller and grounded; When the timing controller loads code to start the display device, if the first voltage is greater than the second voltage, the first and second terminals of the first switch are disconnected, the first and second terminals of the second switch are disconnected, and the timing controller restarts.

5. The restart circuit according to claim 4, characterized in that, The voltage divider circuit includes a second resistor and a third resistor; Wherein, one end of the second resistor is connected to the second output terminal of the power management chip, the other end of the second resistor is connected to the control terminal of the second switch and one end of the third resistor, and the other end of the third resistor is connected to the first terminal of the first switch.

6. The restart circuit according to any one of claims 1-5, characterized in that, The first voltage is configured as the power supply voltage of the display panel of the display device; or / and, The second output terminal of the power management chip is connected to the power supply terminal of the timing controller to provide power supply voltage to the timing controller.

7. The restart circuit according to any one of claims 1-5, characterized in that, The feedback terminal of the source driver is connected to the timing controller to output a lock signal in the form of the second voltage to the timing controller.

8. The restart circuit according to claim 7, characterized in that, When the timing controller loads code to start the display device, the timing controller is configured to output training sequence data to the source driver, and the source driver is configured to output the lock signal to the timing controller based on the training sequence data.

9. A timing control system, characterized in that, It includes a timing controller and a restart circuit as described in any one of claims 1-8.

10. A display device, characterized in that, It includes a display panel, a power management system, and the timing control system as described in claim 9.

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