Pixel circuit and display device

Abstract

A pixel circuit and a display device are provided. The pixel circuit includes a first light emitting diode and a second light emitting diode, a driving transistor connected between a first node and a third node to control a driving current flowing through the first light emitting diode and the second light emitting diode, a first mode selection unit connected between the first node and a first power supply line supplying a first power supply voltage and configured to operate according to a mode signal, and a second mode selection unit connected between the third node and the first light emitting diode and the second light emitting diode and configured to operate according to the mode signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0178596, filed on December 4, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device capable of achieving high pixels per inch (PPI) and high resolution. Background Technology

[0004] Display devices are typically used as screens for a wide range of electronic devices, such as mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), ultra-mobile PCs (UMPCs), mobile phones, smartphones, tablet PCs (personal computers), electronic tablets, wearable devices, watch phones, portable information devices, navigation systems, vehicle control displays, televisions, laptops, and monitors.

[0005] Recently, research and development are underway on display devices that can achieve maximum screen size by reducing the bezel area where no image is displayed, while using the same size display panel. Summary of the Invention

[0006] The purpose of this disclosure is to provide a display device capable of achieving high pixels per inch (PPI) and high resolution.

[0007] Another objective of this disclosure is to provide a display device with a minimized border area.

[0008] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0009] According to one aspect of this disclosure, a pixel circuit includes: a first light-emitting diode (LED) and a second LED; a driving transistor connected between a first node and a third node to control driving current flowing through the first LED and the second LED; a first mode selection unit connected between the first node and a first power line supplying a first power supply voltage and configured to operate according to a mode signal; and a second mode selection unit connected between the third node and the first LED and the second LED and configured to operate according to the mode signal.

[0010] According to other aspects of this disclosure, a display device includes: a substrate including an effective region having a plurality of sub-pixels and an ineffective region surrounding the effective region; and a gate driver disposed in the ineffective region, wherein each of the plurality of sub-pixels includes: a first light-emitting diode and a second light-emitting diode; a driving transistor connected between a first node and a third node; a first transistor connected between the third node and a second node corresponding to the gate electrode of the driving transistor; a second transistor connected between a data line to which a data signal is applied and the first node; a third transistor connected between a first power line supplying a first power supply voltage and the first node to operate according to a first mode signal; and a fourth transistor connected between the first power line and the first node to operate according to a second mode. Signal operation; a fifth transistor connected between the driving transistor and the first light-emitting diode to operate according to the first mode signal; a sixth transistor connected between the driving transistor and the second light-emitting diode to operate according to the second mode signal; a seventh transistor connected between a second power supply line supplying a second power supply voltage and the first node; an eighth transistor connected between a third power supply line supplying a third power supply voltage and a fourth node corresponding to the first electrode of the first light-emitting diode; a ninth transistor connected between the third power supply line and a fifth node corresponding to the first electrode of the second light-emitting diode; a tenth transistor connected between a fourth power supply line supplying a fourth power supply voltage and the second node; and a storage capacitor connected between the first power supply line and the second node.

[0011] Further details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0012] According to this disclosure, a display device is provided that achieves high pixels per inch (PPI) and high resolution by reducing the number of wirings.

[0013] According to this disclosure, a display device is provided that minimizes the bezel area by reducing the gate driver.

[0014] The effects of this disclosure are not limited to those illustrated above, and this application includes many more effects. Attached Figure Description

[0015] The above and other aspects, features, and other advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This is a block diagram of a display device according to an exemplary embodiment of the present disclosure;

[0017] Figure 2 This is a block diagram of a gate driver for a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 3 This is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 4 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 5A and Figure 5B It is used for explanation Figure 4 Waveform diagram of the sub-pixel circuit;

[0021] Figure 6 This is a circuit diagram of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure;

[0022] Figure 7 This is a plan view of the sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure;

[0023] Figure 8 yes Figure 7 Circuit diagram of the sub-pixel;

[0024] Figure 9 This is a plan view of the sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure; and

[0025] Figure 10 yes Figure 9 The circuit diagram of the sub-pixel. Detailed Implementation

[0026] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure.

[0027] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the application, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “constituting” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Any reference to the singular may include the plural unless otherwise expressly stated.

[0028] The component is interpreted to include the normal tolerance range, even if not explicitly stated.

[0029] When using terms such as “above,” “over,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be placed between the two parts, unless these terms are used with the terms “immediately following” or “directly.”

[0030] When interpreting temporal relationships, terms such as “after,” “below,” “following,” or “before” may include non-continuous cases, unless terms such as “immediately” or “directly” are used.

[0031] Various components are described using terms such as "first," "second," etc., but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical scope of this disclosure, a first component mentioned herein can be a second component.

[0032] When describing the components of this disclosure, terms such as first, second, A, B, (a), or (b) may be used. These terms are intended only to distinguish one component from other components, and the nature, order, sequence, or number of the corresponding components are not limited by these terms.

[0033] When a component is described as “connected,” “joined,” “engaged,” or “attached” to another component, it should be understood that the component may be directly connected, joined, engaged, or attached to the other component, but unless otherwise expressly stated, it may also be indirectly connected, joined, engaged, or attached to the other component where other components are inserted in between.

[0034] When a component or layer is described as “contacting” or “overlapping” another component or layer, the component or layer may directly contact or overlap the other component or layer, but unless otherwise expressly stated, it should be understood that it may also indirectly contact or overlap the other component or layer in the presence of other components inserted in between.

[0035] The term "at least one" should be understood to include all combinations of one or more of the related components. For example, "at least one of the first component, the second component, and the third component" means not only the first component, the second component, or the third component, but also includes all combinations of two or more of the first component, the second component, and the third component.

[0036] The terms “first direction,” “second direction,” “third direction,” “X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted merely as geometric relationships that are perpendicular to each other, but can represent a broader range of directions within the scope of the configuration of this disclosure that can function.

[0037] The features of the various embodiments in this disclosure can be combined or associated with each other in part or in whole, and various technical linkages and operations can be performed. Each embodiment can be implemented independently or can be implemented together in an associated relationship.

[0038] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0040] The display device 100 according to the exemplary embodiments of this disclosure can be applied to an electroluminescent display device. The electroluminescent display device may be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0041] Reference Figure 1 The display device 100 may include a display panel PN, a data driver DD, a gate driver GD, and a timing controller TC.

[0042] The display panel PN can generate an image to be provided to the user. For example, the display panel PN can generate and display an image to be provided to the user through pixels PX in which multiple sub-pixel circuits are provided.

[0043] The data driver DD, gate driver GD, and timing controller TC can provide signals for operating each pixel PX via signal lines. For example, the signal lines may include the data line DL and the gate line GL.

[0044] The data line DL is disposed in the column direction and may include multiple wirings connected to a pixel PX disposed in the column direction, and the gate line GL is disposed in the row direction and may include multiple wirings connected to a pixel PX disposed in the row direction.

[0045] In some cases, the display device 100 may further include a power supply unit. In this case, a power supply voltage for the operation of the pixel PX can be supplied via a power line that PN connects the power supply unit and the display panel. For example, the power supply unit can supply a high-level drive voltage, a low-level drive voltage, and an initialization voltage to the pixel PX. The high-level drive voltage, low-level drive voltage, and initialization voltage can be constant voltages at predetermined levels. Furthermore, the power supply unit can supply power supply voltages to the data driver DD and the gate driver GD. The data driver DD and the gate driver GD can be driven based on the power supply voltage supplied from the power supply unit.

[0046] For example, the data driver DD applies a data signal to each pixel PX via the data line DL. The gate driver GD applies a gate signal to each pixel PX via the gate line GL. The power supply unit supplies power voltage to each pixel PX via the power supply line.

[0047] The timing controller TC controls the data driver DD and the gate driver GD. For example, the timing controller TC rearranges externally input digital video data according to the resolution of the display panel PN to supply the digital video data to the data driver DD.

[0048] The data driver DD converts digital video data input from the timing controller TD into analog data voltage based on data control signals, and supplies the converted analog data voltage to multiple data lines DL.

[0049] A gate driver (GD) can generate scan signals and mode signals based on a gate control signal. The gate driver (GD) may include a scan driver and a mode signal driver. The scan driver generates scan signals in a row-sequential manner to drive at least one or more scan lines connected to each pixel row, thereby supplying scan signals to the scan lines. The mode signal driver generates mode signals in a row-sequential manner to drive at least one or more mode signal lines connected to each pixel row, thereby supplying mode signals to the mode signal lines.

[0050] According to an exemplary embodiment, the gate driver GD can be disposed in the display panel PN as an in-panel gate driver (GIP). For example, the gate driver GD can be divided into multiple circuits disposed on at least two side surfaces of the display panel PN.

[0051] The display panel PN may include an active area and an inactive area surrounding the active area.

[0052] The effective area of ​​the display panel PN may include multiple pixels PX disposed in the row and column directions. Pixels PX may be disposed in the intersection area of ​​multiple data lines DL and multiple gate lines GL.

[0053] A pixel PX may include multiple sub-pixels that emit different colors of light. For example, a pixel PX may use three sub-pixels to achieve blue, red, and green. However, this is not the case; in some cases, a pixel PX may further include sub-pixels for further achieving a specific color (e.g., white).

[0054] In a pixel PX, the area that realizes blue can be called a blue subpixel, the area that realizes red can be called a red subpixel, and the area that realizes green can be called a green subpixel.

[0055] Each of the plurality of sub-pixels may include a first light-emitting diode and a second light-emitting diode that emit light of the same color, a first lens that refracts light from the first light-emitting diode to a predetermined direction, and a second lens that refracts light from the second light-emitting diode to a predetermined direction. Therefore, the first lens and the second lens can limit the viewing angle of each of the plurality of sub-pixels.

[0056] The following will refer to Figure 3 Describe the first lens and the second lens in detail.

[0057] An inactive region may be set along the outer periphery of the active region. Various components for driving multiple sub-pixels disposed in pixel PX may be set in the inactive region. For example, at least a portion of signal lines for transmitting signals, power lines for applying power, and gate drivers GD may be set in the inactive region. The inactive region may be referred to as a border region.

[0058] Figure 2 This is a block diagram of a gate driver for a display device according to an exemplary embodiment of the present disclosure. Figure 2 For ease of description, only the gate driver GD for one pixel row is shown in the diagram.

[0059] Reference Figure 2 The gate driver GD is symmetrically disposed in the inactive region NA on both sides of the active region AA to supply scan signals and mode signals to multiple pixels PX.

[0060] Each gate driver GD may include a first scan driver SC1(n), a second scan driver SC2(n), a third scan driver SC3(n), a fourth scan driver SC4(n), a first mode driver MC1(n), and a second mode driver MC2(n). Each of the first scan driver SC1(n), the second scan driver SC2(n), the third scan driver SC3(n), the fourth scan driver SC4(n), the first mode driver MC1(n), and the second mode driver MC2(n) may include multiple stages.

[0061] In each gate driver GD, the second scan driver SC2(n), the first scan driver SC1(n), the third scan driver SC3(n), the fourth scan driver SC4(n), the second mode driver MC2(n), and the first mode driver MC1(n) can be arranged in this order from positions adjacent to the active region AA. However, it is not limited to this and can be changed according to the design.

[0062] The first scan driver SC1(n) can output the first scan signal through the first scan line SL1. Figure 4 The second scan driver SC2(n) can output the second scan signal through the second scan line SL2. Figure 4 The third scan driver SC3(n) can output the third scan signal through the third scan line SL3. Figure 4 The fourth scan driver SC4(n) can output the fourth scan signal through the fourth scan line SL4. Figure 4 The SCAN4(n)). The first mode driver MC1(n) can output the first mode signal through the first mode line ML1 ( Figure 4 The second-mode driver MC2(n) can output the second-mode signal via the second-mode line ML2. Figure 4 P(n)).

[0063] One of the scan drivers SC1(n), SC2(n), SC3(n), and SC4(n) can be configured via a shift register circuit, and the remaining scan drivers, as well as the first mode driver MC1(n) and the second mode driver MC2(n), can be configured via an edge trigger circuit. For example, the second scan driver SC2(n) can be configured via a shift register circuit, and the first scan driver SC1(n), third scan driver SC3(n), fourth scan driver SC4(n), first mode driver MC1(n), and second mode driver MC2(n) can be configured via an edge trigger circuit. However, this is not a limitation and can be varied depending on the design.

[0064] The first scan signal SCAN1(n) can be used as a signal to drive the transistors (e.g., compensation transistors) included in the sub-pixel circuit. The second scan signal SCAN2(n) can be used as a signal to drive the transistors (e.g., data supply transistors) included in the sub-pixel circuit. The third scan signal SCAN3(n) can be used as a signal to drive the transistors (e.g., bias transistors) included in the sub-pixel circuit. The fourth scan signal SCAN4(n) can be used as a signal to drive the transistors (e.g., initialization transistors) included in the sub-pixel circuit. The first mode signal S(n) and the second mode signal P(n) can be used as signals to drive the transistors (e.g., light-emitting control transistors) included in the sub-pixel circuit. For example, when the first mode signal S(n) and the second mode signal P(n) are used to control the light-emitting control transistors of a pixel, multiple light-emitting diodes can selectively emit light.

[0065] Figure 3 This is a plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 3 The plane of pixel region PA is shown when three sub-pixels are set in pixel region PA.

[0066] Reference Figure 3 The pixel region PA may include a blue sub-pixel region BPA for blue, a red sub-pixel region RPA for red, and a green sub-pixel region GPA for green. According to an exemplary embodiment, the blue sub-pixel region BPA may correspond to a first sub-pixel, the red sub-pixel region RPA may correspond to a second sub-pixel, and the green sub-pixel region GPA may correspond to a third sub-pixel. Sub-pixel circuitry may correspond to each sub-pixel. A corresponding sub-pixel circuit may be provided in each sub-pixel.

[0067] The pixel region PA may include a first lens region BWE, RWE and GWE that provides different viewing angles, and a second lens region BNE, RNE and GNE.

[0068] A first light-emitting diode (LED) can be disposed in the first lens areas BWE, RWE, and GWE. Figure 4 The first light-emitting diode (ED1) and first lenses BWR, RWR, and GWR are provided in each pixel region PA. The first lenses BWR, RWR, and GWR can be disposed on the first lens regions BWE, RWE, and GWE of each pixel region PA. For example, light generated by the first light-emitting diode ED1 in each pixel region PA can be emitted through the first lenses BWR, RWR, and GWR of the pixel region PA. The first lenses BWR, RWR, and GWR can have shapes that do not restrict light in at least one direction. The first lenses BWR, RWR, and GWR can provide a viewing angle with a first value. For example, the flat shape of the first lenses BWR, RWR, and GWR in each pixel region PA can have a strip shape extending along a first direction.

[0069] In this scenario, the direction of light travel emitted from the first lens regions BWE, RWE, and GWE of the pixel region PA is not restricted to the first direction. For example, content (or images) provided through the first lens regions BWE, RWE, and GWE of the pixel region PA can be shared with people in the vicinity of the user in the first direction. When content is provided through the first lens regions BWE, RWE, and GWE, and the content is provided at a viewing angle range with a first value that is wider than the viewing angle range with a second value provided by the second lens regions BNE, RNE, and GNE, this can be referred to as the first mode or wide field-of-view mode.

[0070] A second light-emitting diode (LED) can be installed in the second lens regions BNE, RNE, and GNE. Figure 4 The second light-emitting diode (ED2) and the second lenses BNR, RNR, and GNR are located on the second lens regions BNE, RNE, and GNE of each pixel region PA. Light generated by the second light-emitting diode ED2 in each pixel region PA can be emitted through the second lenses BNR, RNR, and GNR of the pixel region PA. The direction of light travel through the second lenses BNR, RNR, and GNR can be restricted to a first direction and / or a second direction. The second lenses BNR, RNR, and GNR can provide a viewing angle with a second value. For example, the flat shape of the second lenses BNR, RNR, and GNR located in the pixel region PA can be circular.

[0071] In this configuration, the direction of light travel emitted from the second lens regions BNE, RNE, and GNE of each pixel region PA can be restricted to a first direction and a second direction. For example, the content provided by the second lens regions BNE, RNE, and GNE of pixel region PA may not be shared by people around the user. When content is provided through the second lens regions BNE, RNE, and GNE, and at a second field of view that is narrower than the first lens regions BWE, RWE, and GWE (which have a first value), this can be referred to as a second mode or narrow field-of-view mode.

[0072] In the first lens areas BWE, RWE, and GWE of the pixel area PA, a first lens BWR, RWR, or GWR and a first light-emitting diode can be provided. Figure 4 The first light-emitting diode (ED1). A second light-emitting diode (ED1) can be disposed in the second lens regions BNE, RNE, and GNE of the pixel region PA. Figure 4 The second light-emitting diode (ED2) and multiple second lenses (BNR, RNR, GNR).

[0073] Figure 4This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 4 An example of a subpixel circuit is shown that can be applied to a subpixel circuit of a display device according to an exemplary embodiment of the present disclosure.

[0074] Reference Figure 4 The sub-pixel circuit controls the drive current flowing through the first light-emitting diode ED1 and the second light-emitting diode ED2 to drive them. The sub-pixel circuit may include a drive transistor DT, first transistors T1 through T10, and a storage capacitor Cst. Each of transistors DT and T1 through T10 may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be a source electrode, and the other may be a drain electrode.

[0075] Each of transistors DT and T1 through T10 can be a P-type thin-film transistor or an N-type thin-film transistor. Figure 4 In the exemplary embodiment, the first transistor T1 and the tenth transistor T10 are described as N-type thin-film transistors, and the remaining transistors DT, T2 to T9 are P-type thin-film transistors. However, this is not a limitation; according to the exemplary embodiment, all or some of transistors DT and T1 to T10 may be either P-type or N-type thin-film transistors. Furthermore, the N-type thin-film transistor may be an oxide thin-film transistor, and the P-type thin-film transistor may be a polycrystalline silicon thin-film transistor.

[0076] The following example illustrates that the first transistor T1 and the tenth transistor T10 are N-type thin-film transistors, and the remaining transistors DT, T2 to T9 are P-type thin-film transistors. Therefore, a high voltage is applied to the first transistor T1 and the tenth transistor T10 to turn them on, and a low voltage is applied to the remaining transistors DT, T2 to T9 to turn them on.

[0077] According to the example, the first transistor T1 constituting the sub-pixel circuit can be used as a compensation unit, the second transistor T2 can be used as a data supply unit, the third transistor T3 and the fourth transistor T4 can be used as a first mode selection unit. The fifth transistor T5 and the sixth transistor T6 can be used as a second mode selection unit, the seventh transistor T7 can be used as a bias unit, and the eighth transistor T8, the tenth transistor T9 and the tenth transistor T10 can be used as an initialization unit.

[0078] The first light-emitting diode ED1 and the second light-emitting diode ED2 may each include an anode electrode and a cathode electrode. For example, the anode electrode of the first light-emitting diode ED1 may be connected to a fourth node N4, and the cathode electrode may be connected to a low-potential driving voltage VSS. For example, the anode electrode of the second light-emitting diode ED2 may be connected to a fifth node N5, and the cathode electrode may be connected to a low-potential driving voltage VSS.

[0079] The driving transistor DT may include a first electrode connected to a first node N1, a second electrode connected to a third node N3, and a gate electrode connected to a second node N2. The driving transistor DT may supply driving current to the first light-emitting diode ED1 and the second light-emitting diode ED2 based on the voltage of the second node N2 (or the data voltage stored in the storage capacitor Cst described below).

[0080] The first transistor T1 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode for receiving a first scan signal Scan1(n). The first transistor T1 is turned on in response to the first scan signal Scan1(n), and a diode is connected between the second node N2 and the third node N3 to sample the threshold voltage Vth of the driving transistor DT.

[0081] The storage capacitor Cst can be connected between the second node N2 and the first power line VDDL to which the first power supply voltage VDD is applied. For example, the first power supply voltage VDD can be a high-potential drive voltage, and the first power line VDDL can be a high-potential drive voltage line. The storage capacitor Cst can store or retain the supplied high-potential drive voltage VDD.

[0082] The second transistor T2 may include a first electrode connected to the data line DL, a second electrode connected to the first node N1, and a gate electrode for receiving the second scan signal SCAN2(n). The second transistor T2 may be turned on in response to the second scan signal SCAN2(n) and transmit the data voltage VDATA to the first node N1.

[0083] The third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be connected between the high-potential drive voltage line VDDL and the first light-emitting diode ED1 and the second light-emitting diode ED2, and form a current movement path through which the drive current Id generated by the drive transistor DT moves.

[0084] The third transistor T3 may include a first electrode connected to the high-potential drive voltage line VDDL to receive the high-potential drive voltage VDD, a second electrode connected to the first node N1, and a gate electrode connected to the first mode signal line ML1 to receive the first mode signal S(n).

[0085] The fourth transistor T4 may include a first electrode connected to the high-potential drive voltage line VDDL to receive the high-potential drive voltage VDD, a second electrode connected to the first node N1, and a gate electrode connected to the second mode signal line ML2 to receive the second mode signal P(n).

[0086] When driven in the first mode, the fifth transistor T5 can form a current path between the driving transistor DT and the first light-emitting diode ED1. The fifth transistor T5 may include a first electrode connected to the third node N3, a second electrode connected to the fourth node N4, and a gate electrode connected to the first mode signal line ML1 to receive the first mode signal S(n). At this time, the fourth node N4 can be connected to the anode electrode of the first light-emitting diode ED1.

[0087] The fifth transistor T5 can be turned on or off by the first mode signal S(n). Therefore, the fifth transistor T5 can form a current path between the third node N3 and the first light-emitting diode ED1 in response to a low level of the first mode signal S(n), which is the on level. That is, the fifth transistor T5 can form a current path between the driving transistor DT and the first light-emitting diode ED1 in response to a low level of the first mode signal S(n). Therefore, the fifth transistor T5 can be referred to as the first light-emitting control transistor that controls the light emission of the first light-emitting diode ED1.

[0088] That is, the third transistor T3 and the fifth transistor T5 are turned on in response to the first mode signal S(n). In this case, the drive current Id is supplied to the first light-emitting diode ED1, and the first light-emitting diode ED1 can emit light with a brightness corresponding to the drive current Id.

[0089] When driven in the second mode, the sixth transistor T6 can form a current path between the driving transistor DT and the second light-emitting diode ED2. The sixth transistor T6 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5, and a gate electrode connected to the second mode signal line ML2 to receive the second mode signal P(n). At this time, the fifth node N5 can be connected to the anode electrode of the second light-emitting diode ED2.

[0090] The sixth transistor T6 can be turned on or off by the second mode signal P(n). Therefore, the sixth transistor T6 can form a current path between the third node N3 and the second light-emitting diode ED2 in response to a low level of the second mode signal P(n), which is the on-state level. That is, the sixth transistor T6 can form a current path between the driving transistor DT and the second light-emitting diode ED2 in response to a low level of the second mode signal P(n). Therefore, the sixth transistor T6 can be referred to as the second light-emitting control transistor that controls the light emission of the second light-emitting diode ED2.

[0091] That is, the fourth transistor T4 and the sixth transistor T6 are turned on in response to the second mode signal P(n). In this case, the drive current Id is supplied to the second light-emitting diode ED2, and the second light-emitting diode ED2 can emit light with a brightness corresponding to the drive current Id.

[0092] The seventh transistor T7 may include a first electrode connected to a second power supply line VOBSL to which a second power supply voltage VOBS is applied, a second electrode connected to a first node N1, and a gate electrode for receiving a third scan signal SCAN3(n). For example, the second power supply voltage VOBS may be a bias voltage, and the second power supply line VOBSL may be a bias voltage line.

[0093] The eighth transistor T8 may include a first electrode connected to a third power supply line VARL to which a third power supply voltage VAR is applied, a second electrode connected to a fourth node N4, and a gate electrode for receiving a third scan signal SCAN3(n). For example, the third power supply voltage VAR may be a first initialization voltage, and the third power supply line VARL may be a first initialization voltage line.

[0094] The ninth transistor T9 may include a first electrode connected to a third power supply line VARL to which a third power supply voltage VAR is applied, a second electrode connected to a fifth node N5, and a gate electrode for receiving a third scan signal SCAN3(n). For example, the third power supply voltage VAR may be a first initialization voltage, and the third power supply line VARL may be a first initialization voltage line.

[0095] Before (or after) the first LED ED1 and the second LED ED2 emit light, the eighth transistor T8 and the ninth transistor T9 are turned on in response to the third scan signal SCAN3(n). Furthermore, the eighth transistor T8 and the ninth transistor T9 can use a first initialization voltage VAR to initialize the anode electrodes (or pixel electrodes) of the first LED ED1 and the second LED ED2. The first LED ED1 and the second LED ED2 may include parasitic capacitors formed between the anode and cathode electrodes. These parasitic capacitors are charged simultaneously with the emission of light from the first LED ED1 and the second LED ED2, allowing the anodes of the first LED ED1 and the second LED ED2 to have a certain voltage. Therefore, the first initialization voltage VAR is applied to the anode electrodes of the first LED ED1 and the second LED ED2 through the eighth transistor T8 and the ninth transistor T9 to initialize the amount of charge accumulated in the first LED ED1 and the second LED ED2.

[0096] In this exemplary embodiment, the gate electrodes of the eighth transistor T8 and the ninth transistor T9 are configured to jointly receive the third scan signal SCAN3(n). However, this disclosure is not limited thereto, and the gate electrodes of the eighth transistor T8 and the ninth transistor T9 may be configured to receive independently controlled separate scan signals.

[0097] The tenth transistor T10 may include a first electrode connected to a fourth power supply line VINIL to which a fourth power supply voltage VINI is applied, a second electrode connected to a second node N2, and a gate electrode receiving a fourth scan signal SCAN4(n). For example, the fourth power supply voltage VINI may be a second initialization voltage, and the fourth power supply line VINIL may be a second initialization voltage line.

[0098] The tenth transistor T10 is turned on in response to the fourth scan signal SCAN4(n), and the gate electrode of the driving transistor DT can be initialized using the second initialization voltage VINI. Unnecessary charge may remain in the gate electrode of the driving transistor DT due to the high-potential driving voltage VDD stored in the storage capacitor Cst. Therefore, the second initialization voltage VINI is applied to the gate electrode of the driving transistor DT through the tenth transistor T10 to initialize the remaining charge.

[0099] Figure 5A and Figure 5B It is used for explanation Figure 4 Waveform diagram of the sub-pixel circuit. Figure 5A and Figure 5B This diagram illustrates the operation of the scan signal and mode signal during the refresh period in the sub-pixel circuit. Figure 5A This is a diagram used to illustrate the operation of the first mode. Figure 5B This is a diagram used to illustrate the operation of the second mode.

[0100] The display device according to the exemplary embodiments of this disclosure can operate as a variable refresh rate (VRR) mode display device. In VRR mode, pixels are driven at a constant frequency, and when high-speed driving is required, the refresh rate in which the data voltage VDATA is updated is increased to operate the pixels. Furthermore, when it is necessary to reduce power consumption or when low-speed driving is required, the refresh rate is decreased to operate the pixels.

[0101] Each of the multiple pixels PX can be driven for one second through a combination of refresh and hold periods. In this disclosure, a set is defined as a combination of a refresh period in which the data voltage VDATA is updated and a hold period in which the data voltage VDATA is not updated, repeated for one second. A set period can be a period in which the combination of refresh and hold periods is repeated.

[0102] When driving pixels at a refresh rate of 120Hz, pixels can be driven using only refresh periods. That is, a refresh period can be driven 120 times per second. A refresh period is 1 / 120 = 8.33ms, and a group of refresh periods is also 8.33ms.

[0103] When driving pixels at a refresh rate of 60Hz, refresh and hold periods can be driven alternately. That is, the refresh and hold periods can each be driven alternately 60 times within 1 second. One refresh period and one hold period is 0.5 / 60 = 8.33ms, and one set of periods is 16.66ms.

[0104] When driving pixels at a refresh rate of 1Hz, a frame can be driven by one refresh period and 119 hold periods following the refresh period. Alternatively, when driving pixels at a refresh rate of 1Hz, a frame can be driven by multiple refresh periods and multiple hold periods. In this case, one refresh period and one hold period is 1 / 120 = 8.33ms, and one set of periods is 1s.

[0105] During the refresh period, a new data voltage VDATA is charged to apply to the drive transistor DT, and during the hold period, the data voltage VDATA from the previous frame is retained and used as is. Furthermore, the process of applying the new data voltage VDATA to the drive transistor DT during the hold period is omitted, making the hold period also known as the skip period.

[0106] During the refresh period, each of the multiple pixels PX can initialize the voltage that is being charged or held in the sub-pixel circuit. Specifically, during the refresh period, each of the multiple pixels PX can eliminate the effects of the data voltage VDATA and the high-potential drive voltage VDD stored in the previous frame. Therefore, during the hold period, each of the multiple pixels PX can display an image corresponding to the new data voltage VDATA.

[0107] Each of the multiple pixels PX can provide a drive current corresponding to the data voltage VDATA to the first light-emitting diode ED1 or the second light-emitting diode ED2 to display an image, and maintain the first light-emitting diode ED1 or the second light-emitting diode ED2 in the on state during the hold period.

[0108] Reference Figure 5A and Figure 5BThe difference between the driving signals in the first mode and the second mode lies in the first mode signal S(n) and the second mode signal P(n). In the first mode, only the first LED ED1 can emit light, and in the second mode, only the second LED ED2 can emit light. In the first mode, to allow only the first LED ED1 to emit light, the second mode signal P(n) can be output as a high level (cutoff level) to control the emission of the second LED ED2. In the second mode, to allow only the second LED ED2 to emit light, the first mode signal S(n) can be output as a high level (cutoff level) to control the emission of the first LED ED1.

[0109] Reference Figure 5A and Figure 5B In the first and second modes, the refresh period may be operable to include at least one bias interval Tobs1 and Tobs2, an initialization interval Ti, a sampling interval Ts and an emission interval Te, but this is only an exemplary implementation and is not necessarily limited to this order.

[0110] Reference Figure 5A During the refresh period, the pixel circuit can be operated to include at least one bias interval Tobs1 and Tobs2.

[0111] At least one bias interval, Tobs1 and Tobs2, is the interval when performing the on-bias stress operation OBS with applied bias voltage VOBS.

[0112] In the first bias interval Tobs1 and the second bias interval Tobs2, the first mode control signal S(n) and the second mode control signal P(n) are high voltages, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are off. The first scan signal SCAN1(n) is high voltage, and the first transistor T1 is on. The second scan signal SCAN2(n) is high voltage, the fourth scan signal SCAN4(n) is low voltage, and the second transistor T2 and the tenth transistor T10 are off. The third scan signal SCAN3(n) is input as low voltage, and the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are on. When the seventh transistor T7 is on, the bias voltage VOBS is applied to the first electrode of the drive transistor DT connected to the first node N1.

[0113] Here, a bias voltage VOBS is supplied to the third node N3, which serves as the second electrode of the driving transistor DT. Therefore, the charging time or charging delay of the voltages at the fourth node N4 and the fifth node N5, which serve as the anode electrodes of the first LED ED1 and the second LED ED2, during the light-emitting period can be reduced. At this time, the driving transistor DT maintains a stronger saturation state.

[0114] For example, the higher the bias voltage VOBS, the higher the voltage at the third node N3, which serves as the drain electrode of the driving transistor DT, and the lower the gate-source voltage or drain-source voltage of the driving transistor DT. Therefore, it is desirable that the bias voltage VOBS is at least higher than the data voltage VDATA.

[0115] At this point, the magnitude of the drive current Id through the drive transistor DT can be reduced, and under positive bias stress, the stress on the drive transistor DT can be reduced to address the charging delay of the voltage at the third node N3. In other words, the on-bias stress operation OBS is performed before sampling the threshold voltage Vth of the drive transistor DT to mitigate the hysteresis of the drive transistor DT.

[0116] Therefore, in at least one bias interval Tobs1 and Tobs2, the conduction bias stress operation OBS can be defined as the operation of directly applying an appropriate bias voltage to the driving transistor DT during the non-light-emitting period.

[0117] Furthermore, when the eighth transistor T8 and the ninth transistor T9 are turned on in at least one bias interval Tobs1 and Tobs2, the anode electrode (or pixel electrode) of the first light-emitting diode ED1 connected to the fourth node N4 and the anode electrode (or pixel electrode) of the second light-emitting diode ED2 connected to the fifth node N5 are initialized with the first initialization voltage VAR.

[0118] However, the gate electrodes of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be configured to receive independently controlled separate scan signals. That is, during the bias interval, it is not necessary to simultaneously apply bias voltages to the first electrode of the driving transistor DT and the anode electrodes of the first light-emitting diode ED1 and the second light-emitting diode ED2.

[0119] Reference Figure 5A During the refresh period, the sub-pixel circuit is operable to include an initialization interval Ti. The initialization interval Ti is the interval in which the voltage of the gate electrode of the driving transistor DT is initialized.

[0120] The first scan signal SCAN1(n), the second scan signal SCAN2(n), the third scan signal SCAN3(n), the fourth scan signal SCAN4(n), the first mode signal S(n), and the second mode signal P(n) are at high voltage, and the first transistor T1 and the tenth transistor T10 are turned on. The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off. When the first transistor T1 and the tenth transistor T10 are turned on, the gate electrode and the second electrode of the drive transistor DT connected to the second node N2 are initialized with the second initialization voltage VINI.

[0121] Reference Figure 5A During the refresh period, the sub-pixel circuit can operate to include a sampling interval Ts. The sampling interval Ts is the interval in which the threshold voltage Vth of the driving transistor DT is sampled.

[0122] The first scan signal SCAN1(n), the third signal SCAN3(n), the first mode signal S(n), and the second mode signal P(n) are at high voltages, while the second scan signal SCAN2(n) and the fourth scan signal SCAN4(n) are at low voltages. Therefore, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are off, the first transistor T1 remains on, and the second transistor T2 is on. That is, the second transistor T2 is on to apply the data voltage VDATA to the driving transistor DT, and the diode of the first transistor T1 is connected between the second node N2 and the third node N3 to sample the threshold voltage Vth of the driving transistor DT.

[0123] Reference Figure 5A During the refresh period, the sub-pixel circuit is operable to include a light-emitting region Te. The light-emitting region Te is the region in which the sampled threshold voltage Vth is canceled and the drive current corresponding to the sampled data voltage causes the first light-emitting diode ED1 to emit light.

[0124] The first mode signal S(n) is at a low voltage, and the third transistor T3 and the fifth transistor T5 are turned on.

[0125] Since the third transistor T3 is turned on, the high-potential drive voltage VDD is applied through the third transistor T3 to the first electrode of the drive transistor DT connected to the first node N1. The drive current Id is applied from the drive transistor DT to the first light-emitting diode ED1 due to the turned-on fifth transistor T5. At this time, the threshold voltage Vth of the drive transistor DT is compensated independently of the value of the threshold voltage Vth, causing the first light-emitting diode ED1 to operate based on the drive current Id corresponding to the sampled data voltage. Therefore, in the first mode, the drive current Id is applied only to the first light-emitting diode ED1, causing only the first light-emitting diode ED1 to emit light.

[0126] Reference Figure 5B In the second mode, during the refresh period, the remaining intervals except for the light-emitting interval Te operate in the same manner, and therefore their description will be omitted. During the refresh period, the sub-pixel circuit can operate to include the light-emitting interval Te. The light-emitting interval Te is the interval in which the sampled threshold voltage Vth is canceled and the drive current corresponding to the sampled data voltage causes the second light-emitting diode ED2 to emit light.

[0127] The second mode signal P(n) is at a low voltage, and the fourth transistor T4 and the sixth transistor T6 are turned on.

[0128] Since the fourth transistor T4 is turned on, the high-potential drive voltage VDD is applied through the fourth transistor T4 to the first electrode of the drive transistor DT connected to the first node N1. The drive current Id is applied from the drive transistor DT to the second light-emitting diode ED2 due to the turned-on sixth transistor T6. Therefore, in the second mode, the drive current Id is applied only to the second light-emitting diode ED2, causing only the second light-emitting diode ED2 to emit light.

[0129] To drive the sub-pixel circuitry, display devices in related technologies require numerous wirings to apply drive signals and drive power. Specifically, to control multiple light-emitting control transistors, each of these transistors requires a light-emitting control signal line to apply a light-emitting control signal, thus increasing the wiring density within the pixel. Therefore, the problem is that this limits the achievement of high pixels per inch (PPI) and high resolution.

[0130] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, a high pixel per inch (PPI) and high resolution can be achieved. Specifically, the third transistor T3 and the fourth transistor T4 are connected between the high-potential drive voltage line VDDL, to which a high-potential drive voltage VDD is applied, and the source electrode of the drive transistor DT. The fifth transistor T5 is connected between the drain electrode of the drive transistor DT and the first light-emitting diode ED1, and the sixth transistor T6 is connected between the drain electrode of the drive transistor DT and the second light-emitting diode ED2. The third transistor T3 and the fifth transistor T5 operate according to the first mode signal S(n), and the fourth transistor T4 and the sixth transistor T6 operate according to the second mode signal P(n) to cause the first light-emitting diode ED1 and the second light-emitting diode ED2 to emit light. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the first light-emitting diode ED1 or the second light-emitting diode ED2 is controlled to emit light only by the first mode signal S(n) and the second mode signal P(n) according to the mode selection, without the need for a separate light-emitting control signal. Therefore, the number of wirings in the subpixels is reduced, thereby lowering the line density in the pixel circuitry and increasing the pixels per inch (PPI) and resolution.

[0131] In display devices of related technologies, in order to operate the sub-pixel circuits driving the pixels, first scan signals to fourth scan signals and first light emission signals to third light emission signals are required. Therefore, in order to supply the driving signals, first scan drivers to fourth scan drivers and first light emission drivers to third light emission drivers are required. Consequently, in order to accommodate the first scan drivers to fourth scan drivers and the first light emission drivers to third light emission drivers, there is a problem of increased area of ​​the ineffective region of the display panel.

[0132] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the bezel area can be minimized. Specifically, the sub-pixel circuit includes a light-emitting transistor that operates only with a first mode signal S(n) and a second mode signal P(n) to reduce the drive signal used to drive the sub-pixel circuit. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the drive signal used to drive the sub-pixel circuit is reduced, thereby reducing the gate driver that generates the drive signal, making it possible to minimize the area of ​​the ineffective region where the gate driver is disposed and to minimize the bezel area.

[0133] Figure 6 This is a circuit diagram of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure. Figure 6 Is with Figure 4 The circuit diagram for the same sub-pixel. Except for the boost capacitor Cbst, Figure 6 With Figure 4The sub-pixel circuits have the same configuration, so redundant descriptions will be omitted.

[0134] Reference Figure 6 In another exemplary embodiment of the present disclosure, the sub-pixel circuit of the display device 200 may further include a boost capacitor Cbst.

[0135] The boost capacitor Cbst can be connected between the second scan signal line to which the second scan signal SCAN2(n) is applied and the gate electrode of the driving transistor DT. For example, the first electrode of the boost capacitor Cbst can be connected to the second scan signal line to which the second scan signal SCAN2(n) is applied, and the gate electrode of the second transistor T2 and the second electrode of the boost capacitor Cbst can be connected to the gate electrode of the driving transistor DT.

[0136] Therefore, the second scan signal SCAN2(n) stored in the boost capacitor Cbst can be applied to the gate electrode of the driving transistor DT. That is, the voltage of the gate electrode of the driving transistor DT can change as much as the voltage change of the second scan signal SCAN2(n).

[0137] Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, the first light-emitting diode ED1 or the second light-emitting diode ED2 can be controlled to emit light only through the first mode signal S(n) and the second mode signal P(n) according to the mode selection, without the need for a separate light emission control signal. This reduces the number of wires provided in the sub-pixel circuit, thereby reducing the line density in the pixel circuit and improving the pixels per inch (PPI) and resolution.

[0138] Therefore, in another exemplary embodiment of the display device 200 according to the present disclosure, the driving signal for driving the sub-pixel circuit is reduced, thereby reducing the gate driver that generates the driving signal, so that the area of ​​the ineffective region in which the gate driver is disposed can be minimized and the border area can be minimized.

[0139] In a display device 200 according to another exemplary embodiment of the present disclosure, a boost capacitor Cbst is connected between a second scan signal line to which a second scan signal SCAN2(n) is applied and the gate electrode of a driving transistor DT. Therefore, the voltage applied to the gate electrode of the driving transistor DT can be changed by the voltage level of the second scan signal SCAN2(n). Thus, in the display device 200 according to another exemplary embodiment of the present disclosure, the voltage applied to the gate electrode of the driving transistor DT can change as quickly as the voltage level of the second scan signal SCAN2(n). Therefore, when the color is changed to black, the color can be changed faster and more accurately.

[0140] Figure 7 This is a plan view of the sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure. Figure 8 yes Figure 7 The circuit diagram of the sub-pixel. Figure 7 It is a diagram used to illustrate two pixels that are set to be adjacent in the column direction. Figure 8 This is a diagram used to illustrate two sub-pixel circuits that are set up to be adjacent in the column direction.

[0141] For ease of description, the horizontal direction on the plane is called the second direction (or row direction), and the vertical direction (or orthogonal direction) on the plane is called the first direction (or column direction).

[0142] Reference Figure 7 In the pixel region of the display device 300 according to another exemplary embodiment of the present disclosure, a plurality of data lines DL, at least one first power line VDDL and at least one third power line VARL may be provided in a first direction.

[0143] For example, three data lines DL can be provided in the first direction, respectively connected to the red sub-pixel SPC1, the green sub-pixel and the blue sub-pixel, and a high-potential drive voltage line VDDL and a third power supply line VARL can be provided in the first direction.

[0144] Within a pixel region, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, a second power line VOBSL, a third power line VARL_R, VARL_GB, a fourth power line VINIL, a first mode line ML1, and a second mode line ML2 can be configured in the second direction. For example, the third scan line SL3 can be configured on a different layer than the second power line VOBSL to overlap. The fourth scan line SL4 and the fourth power line VINIL can be configured on different layers to overlap each other. For example, the first mode line ML1 and the second mode line ML2 can be configured to be adjacent to each other. For example, the third power line VARL_R, which supplies the third power voltage to the red sub-pixel, and the third power line VARL_GB, which supplies the third power voltage to the blue and green sub-pixels, can be configured on different layers to overlap each other, but are not limited to this.

[0145] Reference Figure 7 and Figure 8Subpixels arranged adjacent to each other in the first direction can be symmetrically arranged. For example, the first subpixel SPC1 can be arranged above the third power lines VARL_R and VARL_GB, and the second subpixel SPC2 can be arranged below the third power lines VARL_R and VARL_GB. In this case, the driving transistor DT, the first transistors T1 to T10, and the storage capacitor Cst constituting the first subpixel SPC1 can be arranged symmetrically with respect to the third power lines VARL_R and VARL_GB to the driving transistor DT, the first transistors T1 to T10, and the storage capacitor Cst constituting the second subpixel SPC2.

[0146] The first sub-pixel SPC1 and the second sub-pixel SPC2 can share the third power lines VARL_R and VARL_GB. For example, the first sub-pixel SPC1 and the second sub-pixel SPC2 can be red sub-pixels and can be connected to the third power line VARL_R that supplies the third power supply voltage to the red sub-pixels. For example, the eighth transistor T8 and the ninth transistor T9 of each of the first sub-pixel SPC1 and the second sub-pixel SPC2 can be connected to the third power line VARL_R.

[0147] Therefore, in a display device 300 according to another exemplary embodiment of the present disclosure, the first light-emitting diode ED1 or the second light-emitting diode ED2 can be controlled to emit light only through the first mode signal S(n) and the second mode signal P(n) according to the mode selection, without the need for a separate light emission control signal. This reduces the number of wirings provided in the sub-pixels, thereby reducing the line density in the pixel circuitry and improving pixels per inch (PPI) and resolution.

[0148] In another exemplary embodiment of the display device 300 according to the present disclosure, the driving signal for driving the sub-pixel circuit is reduced, thereby reducing the gate driver that generates the driving signal, so that the area of ​​the ineffective region in which the gate driver is disposed can be minimized and the border area can be minimized.

[0149] In display devices of the related technology, a third power line VARL_R and VARL_GB are provided in each sub-pixel, and the third power line VARL_R and VARL_GB are connected for each sub-pixel. The problem is that the number of wires provided in the sub-pixels of the effective area AA increases.

[0150] In another exemplary embodiment of the display device 300 according to the present disclosure, first sub-pixels SPC1 and second sub-pixels SPC2, arranged adjacent to each other in a first direction, are configured symmetrically with respect to third power lines VARL_R and VARL_GB. First sub-pixels SPC1 and second sub-pixels SPC2 share the third power lines VARL_R and VARL_GB. First sub-pixels SPC1 and second sub-pixels SPC2 are connected to the third power lines VARL_R and VARL_GB. Therefore, in another exemplary embodiment of the display device 300 according to the present disclosure, first sub-pixels SPC1 and second sub-pixels SPC2, arranged adjacent to each other in a first direction, are connected to share the third power lines VARL_R and VARL_GB. This reduces the number of wirings provided in the sub-pixels, thereby reducing the line density in the pixel circuitry, increasing design freedom, and improving pixels per inch (PPI) and resolution.

[0151] Figure 9 This is a plan view of the sub-pixels of a display device according to yet another exemplary embodiment of the present disclosure. Figure 10 yes Figure 9 The circuit diagram of the sub-pixel. Figure 9 It is a diagram used to illustrate two pixels that are set to be adjacent in the column direction. Figure 10 This is a diagram used to illustrate two sub-pixel circuits that are set up to be adjacent in the column direction.

[0152] Reference Figure 9 In the pixel region of a display device 400 according to another exemplary embodiment of the present disclosure, a plurality of data lines DL, at least one first power line VDDL, and at least one third power line VARL may be provided in a first direction.

[0153] For example, three data lines DL can be provided in the first direction, respectively connected to the red sub-pixel SPC1, the green sub-pixel and the blue sub-pixel, and a high-potential drive voltage line VDDL and a third power supply line VARL can be provided in the first direction.

[0154] Within a pixel region, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, a second power line VOBSL, third power lines VARL_R and VARL_GB, a fourth power line VINIL, a first mode line ML1, and a second mode line ML2 can be configured in the second direction. For example, the third scan line SL3 and the second power line VOBSL can be configured on different layers to overlap. For example, the first mode line ML1 and the second mode line ML2 can be configured to be adjacent to each other. For example, the third power line VARL_R, which supplies the third power voltage to the red sub-pixel, and the third power line VARL_GB, which supplies the third power voltage to the blue and green sub-pixels, can be configured on different layers to overlap. For example, the fourth scan line SL4 and the fourth power line VINIL can be configured on different layers to overlap, but are not limited to this.

[0155] Reference Figure 9 and Figure 10 Subpixels arranged adjacent to each other in the first direction can be symmetrically arranged. For example, with respect to the fourth power line VINIL, the first subpixel SPC1 can be arranged above the fourth power line VINIL, and the second subpixel SPC2 can be arranged below the fourth power line VINIL. In this case, the driving transistor DT, the first transistor T1 to the tenth transistor T10, and the storage capacitor Cst constituting the first subpixel SPC1 can be arranged symmetrically with respect to the fourth power line VINIL to the driving transistor DT, the first transistor T1 to the tenth transistor T10, and the storage capacitor Cst constituting the second subpixel SPC2.

[0156] The first sub-pixel SPC1 and the second sub-pixel SPC2 may share the fourth power line VINIL. For example, the first sub-pixel SPC1 and the second sub-pixel SPC2 may be red sub-pixels and may be connected to the fourth power line VINIL, which supplies the fourth power supply voltage VINI. For example, the tenth transistor T10 of each of the first sub-pixel SPC1 and the second sub-pixel SPC2 may be connected to the fourth power line VINIL.

[0157] Therefore, in a display device 400 according to another exemplary embodiment of the present disclosure, the first light-emitting diode ED1 or the second light-emitting diode ED2 can be controlled to emit light only through the first mode signal S(n) and the second mode signal P(n) according to the mode selection, without having a separate light emission control signal. This reduces the number of wires provided in the pixel circuit, thereby reducing the line density in the pixel circuit and increasing the pixels per inch (PPI) and resolution.

[0158] In another exemplary embodiment of the display device 400 according to the present disclosure, the driving signal for driving the sub-pixel circuit is reduced, thereby reducing the gate driver that generates the driving signal, so that the area of ​​the ineffective region in which the gate driver is disposed can be minimized and the border region can be minimized.

[0159] In display devices of the related technology, a fourth power line VINIL is provided in each sub-pixel, and the fourth power line VINIL is connected for each sub-pixel. The problem is that the number of wires provided in the sub-pixels of the effective area AA increases.

[0160] In another exemplary embodiment of the display device 400 according to the present disclosure, first sub-pixels SPC1 and second sub-pixels SPC2, arranged adjacent to each other in a first direction, are configured symmetrically with respect to a fourth power line VINIL. The first sub-pixels SPC1 and second sub-pixels SPC2 share the fourth power line VINIL. The first sub-pixels SPC1 and second sub-pixels SPC2 are connected to the fourth power line VINIL. Therefore, in another exemplary embodiment of the display device 400 according to the present disclosure, the first sub-pixels SPC1 and second sub-pixels SPC2, arranged adjacent to each other in a first direction, are connected to share a single fourth power line VINIL. This reduces the number of wirings provided in the sub-pixels, thereby reducing the line density in the pixel circuitry, increasing design freedom, and improving pixels per inch (PPI) and resolution.

[0161] Exemplary embodiments of this disclosure may also be described as follows:

[0162] According to an aspect of this disclosure, a pixel circuit includes: a first light-emitting diode (LED) and a second LED; a driving transistor connected between a first node and a third node to control driving current flowing through the first LED and the second LED; a first mode selection unit connected between the first node and a first power line supplying a first power supply voltage and configured to operate according to a mode signal; and a second mode selection unit connected between the third node and the first LED and the second LED and configured to operate according to the mode signal.

[0163] The first mode selection unit may include: a third transistor connected between the first power line supplying the first power supply voltage and the first node to operate according to a first mode signal among the mode signals; and a fourth transistor connected between the first power line and the first node to operate according to a second mode signal among the mode signals.

[0164] The second mode selection unit may include: a fifth transistor connected between the driving transistor and the first light-emitting diode to operate according to the first mode signal; and a sixth transistor connected between the driving transistor and the second light-emitting diode to operate according to the second mode signal.

[0165] The pixel circuit may further include: a first transistor connected between the third node and a second node corresponding to the gate electrode of the driving transistor; a second transistor connected between a data line to which a data signal is applied and the first node; a seventh transistor connected between a second power line supplying a second power supply voltage and the first node; an eighth transistor connected between a third power line supplying a third power supply voltage and a fourth node corresponding to the first electrode of the first light-emitting diode; a ninth transistor connected between the third power line and a fifth node corresponding to the first electrode of the second light-emitting diode; a tenth transistor connected between a fourth power line supplying a fourth power supply voltage and the second node; and a storage capacitor connected between the first power line and the second node.

[0166] The driving transistor may include a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to the second node. The first transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode for receiving a first scan signal. The second transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode for receiving a second scan signal. The third transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode for receiving a first mode signal. The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode for receiving the second mode signal. The fifth transistor includes a first electrode connected to the third node, a second electrode connected to the third node, a second electrode connected to the third node, and a gate electrode for receiving a second scan signal. The sixth transistor includes a second electrode of the node and a gate electrode for receiving the first mode signal; the seventh transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a gate electrode for receiving the third scan signal; the eighth transistor includes a first electrode connected to the third power line, a second electrode connected to the fourth node, and a gate electrode for receiving the third scan signal; the ninth transistor includes a first electrode connected to the third power line, a second electrode connected to the fifth node, and a gate electrode for receiving the third scan signal; and the tenth transistor includes a first electrode connected to the fourth power line, a second electrode connected to the second node, and a gate electrode for receiving the fourth scan signal.

[0167] The first transistor and the tenth transistor are N-type oxide transistors, and the driving transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor can be P-type low-temperature polycrystalline silicon (LTPS) transistors.

[0168] The first LED can emit light when the third transistor and the fifth transistor are turned on in response to the first mode signal, and the second LED can emit light when the fourth transistor and the sixth transistor are turned on in response to the second mode signal.

[0169] The pixel circuit may further include a boost capacitor connected between a second scan signal line to which a second scan signal is applied and the gate electrode of the driving transistor.

[0170] The first LED and the second LED can emit light of the same color.

[0171] The first power supply voltage can be a high-potential driving voltage, the second power supply voltage can be a bias voltage, the third power supply voltage can be a first initialization voltage, and the fourth power supply voltage can be a second initialization voltage.

[0172] According to other aspects of this disclosure, a display device includes: a substrate including an effective region having a plurality of sub-pixels and an ineffective region surrounding the effective region; and a gate driver disposed in the ineffective region, wherein each of the plurality of sub-pixels includes: a first light-emitting diode and a second light-emitting diode; a driving transistor connected between a first node and a third node; a first transistor connected between the third node and a second node corresponding to the gate electrode of the driving transistor; a second transistor connected between a data line to which a data signal is applied and the first node; a third transistor connected between a first power line supplying a first power supply voltage and the first node to operate according to a first mode signal; and a fourth transistor connected between the first power line and the first node to operate according to a second mode. Signal operation; a fifth transistor connected between the driving transistor and the first light-emitting diode to operate according to the first mode signal; a sixth transistor connected between the driving transistor and the second light-emitting diode to operate according to the second mode signal; a seventh transistor connected between a second power supply line supplying a second power supply voltage and the first node; an eighth transistor connected between a third power supply line supplying a third power supply voltage and a fourth node corresponding to the first electrode of the first light-emitting diode; a ninth transistor connected between the third power supply line and a fifth node corresponding to the first electrode of the second light-emitting diode; a tenth transistor connected between a fourth power supply line supplying a fourth power supply voltage and the second node; and a storage capacitor connected between the first power supply line and the second node.

[0173] The gate driver may include: a first scan driver that supplies a first scan signal to the plurality of sub-pixels; a second scan driver that supplies a second scan signal to the plurality of sub-pixels; a third scan driver that supplies a third scan signal to the plurality of sub-pixels; a fourth scan driver that supplies a fourth scan signal to the plurality of sub-pixels; a first mode signal driver that supplies the first mode signal; and a second mode signal driver that supplies the second mode signal.

[0174] Each of the plurality of sub-pixels may include: a first lens configured to overlap with the light-emitting area of ​​the first light-emitting diode and provide a viewing angle having a first value; and a second lens configured to overlap with the light-emitting area of ​​the second light-emitting diode and provide a viewing angle having a second value, the viewing angle having the second value being smaller than the viewing angle having the first value.

[0175] Each of the plurality of sub-pixels can be selectively driven in a first mode and a second mode. In the first mode, the first light-emitting diode can emit light such that the first lens outputs light from the first light-emitting diode at a viewing angle having the first value, and in the second mode, the second light-emitting diode can emit light such that the second lens outputs light from the second light-emitting diode at a viewing angle having the second value.

[0176] The first transistor and the tenth transistor are N-type oxide transistors, and the driving transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor can be P-type low-temperature polycrystalline silicon (LTPS) transistors.

[0177] Each of the plurality of sub-pixels may further include a boost capacitor connected between a second scan signal line to which a second scan signal is applied and the gate electrode of the driving transistor.

[0178] In each of the plurality of sub-pixels, the driving transistor may include a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to the second node. The first transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode for receiving a first scan signal. The second transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode for receiving a second scan signal. The third transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode for receiving the first mode signal. The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode for receiving the second mode signal. The fifth transistor includes a first electrode connected to the third node, a second electrode connected to the third node, and a gate electrode for receiving the second mode signal. The fourth transistor includes a second electrode of the fourth node and a gate electrode for receiving the first mode signal; the sixth transistor includes a first electrode connected to the third node, a second electrode connected to the fifth node, and a gate electrode for receiving the second mode signal; the seventh transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a gate electrode for receiving the third scan signal; the eighth transistor includes a first electrode connected to the third power line, a second electrode connected to the fourth node, and a gate electrode for receiving the third scan signal; the ninth transistor includes a first electrode connected to the third power line, a second electrode connected to the fifth node, and a gate electrode for receiving the third scan signal; and the tenth transistor includes a first electrode connected to the fourth power line, a second electrode connected to the second node, and a gate electrode for receiving the fourth scan signal.

[0179] Among the plurality of sub-pixels, multiple sub-pixels that are adjacent in the column direction are configured to share the third power line.

[0180] Among the plurality of sub-pixels, multiple sub-pixels that are adjacent in the column direction are configured to share the fourth power line.

[0181] The first LED and the second LED can emit light of the same color.

[0182] The first power supply voltage can be a high-potential driving voltage, the second power supply voltage can be a bias voltage, the third power supply voltage can be a first initialization voltage, and the fourth power supply voltage can be a second initialization voltage.

[0183] The first lens may have a strip-shaped flat shape, and the second lens may have a circular flat shape.

[0184] The direction of light passing through the first lens may not be restricted to the first direction, while the direction of light passing through the second lens may be restricted to the first direction.

[0185] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A pixel circuit, comprising: First light-emitting diode and second light-emitting diode; A driving transistor is connected between a first node and a third node to control the driving current flowing through the first light-emitting diode and the second light-emitting diode; A first mode selection unit is connected between the first node and a first power line supplying a first power supply voltage and is configured to operate according to a mode signal. as well as A second mode selection unit is connected between the third node and the first and second light-emitting diodes and configured to operate according to the mode signal.

2. The pixel circuit according to claim 1, wherein the first mode selection unit comprises: A third transistor is connected between the first power line supplying the first power supply voltage and the first node to operate according to a first mode signal among the mode signals. and A fourth transistor is connected between the first power line and the first node to operate according to a second mode signal among the mode signals.

3. The pixel circuit according to claim 2, wherein the second mode selection unit comprises: A fifth transistor is connected between the driving transistor and the first light-emitting diode to operate according to the first mode signal; and A sixth transistor is connected between the driving transistor and the second light-emitting diode to operate according to the second mode signal.

4. The pixel circuit according to claim 3, further comprising: A first transistor is connected between the third node and a second node corresponding to the gate electrode of the driving transistor; The second transistor is connected between the data line to which the data signal is applied and the first node; A seventh transistor is connected between the second power supply line supplying the second power supply voltage and the first node; The eighth transistor is connected between the third power supply line supplying the third power supply voltage and the fourth node corresponding to the first electrode of the first light-emitting diode. A ninth transistor, the ninth transistor being connected between the third power line and the fifth node corresponding to the first electrode of the second light-emitting diode; The tenth transistor is connected between the fourth power supply line supplying the fourth power supply voltage and the second node; and A storage capacitor is connected between the first power line and the second node.

5. The pixel circuit of claim 4, wherein the driving transistor includes a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to the second node. The first transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode for receiving a first scan signal. The second transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode for receiving a second scan signal. The third transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode for receiving the first mode signal. The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode for receiving the second mode signal. The fifth transistor includes a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode for receiving the first mode signal. The sixth transistor includes a first electrode connected to the third node, a second electrode connected to the fifth node, and a gate electrode for receiving the second mode signal. The seventh transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a gate electrode for receiving a third scan signal. The eighth transistor includes a first electrode connected to the third power line, a second electrode connected to the fourth node, and a gate electrode for receiving the third scan signal. The ninth transistor includes a first electrode connected to the third power line, a second electrode connected to the fifth node, and a gate electrode for receiving the third scan signal. The tenth transistor includes a first electrode connected to the fourth power line, a second electrode connected to the second node, and a gate electrode for receiving the fourth scan signal.

6. The pixel circuit according to claim 4, wherein the first transistor and the tenth transistor are N-type oxide transistors, and the driving transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type low-temperature polycrystalline silicon (LTPS) transistors.

7. The pixel circuit of claim 4, wherein the first light-emitting diode emits light when the third transistor and the fifth transistor are turned on in response to the first mode signal, and the second light-emitting diode emits light when the fourth transistor and the sixth transistor are turned on in response to the second mode signal.

8. The pixel circuit according to claim 4, further comprising: A boost capacitor is connected between the second scan signal line to which the second scan signal is applied and the gate electrode of the driving transistor.

9. The pixel circuit according to claim 1, wherein the first light-emitting diode and the second light-emitting diode emit light of the same color.

10. The pixel circuit according to claim 4, wherein the first power supply voltage is a high-potential driving voltage, the second power supply voltage is a bias voltage, the third power supply voltage is a first initialization voltage, and the fourth power supply voltage is a second initialization voltage.

11. A display device, comprising: A substrate, the substrate including an effective region having a plurality of sub-pixels and an ineffective region surrounding the effective region; as well as A gate driver, wherein the gate driver is disposed in the inactive region. Each of the plurality of sub-pixels includes: First light-emitting diode and second light-emitting diode; A driving transistor, wherein the driving transistor is connected between the first node and the third node; A first transistor is connected between the third node and a second node corresponding to the gate electrode of the driving transistor; The second transistor is connected between the data line to which the data signal is applied and the first node; A third transistor is connected between a first power line supplying a first power supply voltage and the first node to operate according to a first mode signal; A fourth transistor is connected between the first power line and the first node to operate according to a second mode signal; A fifth transistor is connected between the driving transistor and the first light-emitting diode to operate according to the first mode signal; A sixth transistor is connected between the driving transistor and the second light-emitting diode to operate according to the second mode signal; A seventh transistor is connected between the second power supply line supplying the second power supply voltage and the first node; The eighth transistor is connected between the third power supply line supplying the third power supply voltage and the fourth node corresponding to the first electrode of the first light-emitting diode. A ninth transistor, the ninth transistor being connected between the third power line and the fifth node corresponding to the first electrode of the second light-emitting diode; The tenth transistor is connected between the fourth power line supplying the fourth power supply voltage and the second node; and A storage capacitor is connected between the first power line and the second node.

12. The display device according to claim 11, wherein the gate driver comprises: A first scan signal is supplied to a first scan driver of the plurality of sub-pixels; The second scan signal is supplied to the second scan driver of the plurality of sub-pixels; The third scan signal is supplied to the third scan driver of multiple sub-pixels; The fourth scan signal is supplied to the fourth scan driver of multiple sub-pixels; A first-mode signal driver that supplies the first-mode signal; and A second-mode signal driver that supplies the second-mode signal.

13. The display device of claim 11, wherein each of the plurality of sub-pixels comprises: A first lens is configured to overlap with the light-emitting area of ​​the first light-emitting diode and provide a viewing angle having a first value; and A second lens is configured to overlap with the light-emitting area of ​​the second light-emitting diode and provide a viewing angle with a second value, the viewing angle with the second value being smaller than the viewing angle with the first value.

14. The display device of claim 13, wherein each of the plurality of sub-pixels is selectively driven in a first mode and a second mode, wherein in the first mode, the first light-emitting diode emits light such that the first lens outputs light from the first light-emitting diode at a viewing angle having the first value, and in the second mode, the second light-emitting diode emits light such that the second lens outputs light from the second light-emitting diode at a viewing angle having the second value.

15. The display device of claim 11, wherein the first transistor and the tenth transistor are N-type oxide transistors, and the driving transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type low-temperature polycrystalline silicon (LTPS) transistors.

16. The display device of claim 11, wherein each of the plurality of sub-pixels further comprises a boost capacitor connected between a second scan signal line to which a second scan signal is applied and the gate electrode of the driving transistor.

17. The display device of claim 11, wherein in each of the plurality of sub-pixels, the driving transistor includes a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to the second node. The first transistor includes a first electrode connected to a second node, a second electrode connected to a third node, and a gate electrode that receives a first scan signal. The second transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode for receiving a second scan signal. The third transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode for receiving the first mode signal. The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode for receiving the second mode signal. The fifth transistor includes a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode for receiving the first mode signal. The sixth transistor includes a first electrode connected to the third node, a second electrode connected to the fifth node, and a gate electrode for receiving the second mode signal. The seventh transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a gate electrode for receiving a third scan signal. The eighth transistor includes a first electrode connected to the third power line, a second electrode connected to the fourth node, and a gate electrode for receiving the third scan signal. The ninth transistor includes a first electrode connected to the third power line, a second electrode connected to the fifth node, and a gate electrode for receiving the third scan signal. The tenth transistor includes a first electrode connected to the fourth power line, a second electrode connected to the second node, and a gate electrode for receiving the fourth scan signal.

18. The display device of claim 11, wherein a plurality of sub-pixels are configured such that adjacent sub-pixels in the column direction share the third power line.

19. The display device of claim 11, wherein a plurality of sub-pixels are configured such that adjacent sub-pixels in the column direction share the fourth power line.

20. The display device according to claim 11, wherein the first light-emitting diode and the second light-emitting diode emit light of the same color.

21. The display device according to claim 11, wherein the first power supply voltage is a high-potential driving voltage, the second power supply voltage is a bias voltage, the third power supply voltage is a first initialization voltage, and the fourth power supply voltage is a second initialization voltage.

22. The display device according to claim 13, wherein the flat shape of the first lens has a strip shape, and the flat shape of the second lens has a circular shape.

23. The display device of claim 13, wherein the direction of travel of light passing through the first lens is not restricted to the first direction, and the direction of travel of light passing through the second lens is restricted to the first direction.

Images