Systems and methods to drive pixels with optimized power and area

Abstract

The system of the present invention reduces the size of a display system or device into which a display, such as an LED display, such as a micro-LED display and an OLED display, or a LCoS display, is integrated or included and / or improves the efficiency of such a display system or device. Embodiments of the present disclosure include, but are not limited to, the following displays: in which at least two pixels are four pixels including two green pixels, one blue pixel, and one red pixel, and in which a pixel logic circuit maintains the red pixel in an on state while driving the two green pixels and the blue pixel according to a field sequential color (FSC) pixel driving process or method.

Description

[0001] This invention application is a divisional application of patent application No. 202180078179.0 entitled "System and method for driving pixels with optimized power and area", filed on November 23, 2021, with international application number PCT / US2021 / 060477, and entered the Chinese national phase on May 19, 2023. Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 117,240, filed November 23, 2020, entitled “SYSTEM AND METHOD FOR DRIVING APIXEL WITH OPTIMIZED POWER AND AREA,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to displays, such as liquid crystal on silicon (LCoS) displays, light-emitting diode (LED) displays (including micro-LED displays and OLED displays), and microdisplays (e.g., LCoS or LED displays). More specifically, the present invention relates to displays operating according to field sequential driving technology. Background Technology

[0004] A typical augmented reality (AR) headset consists of a device worn on the face or around the head. To generate AR images, the headset must house many components, such as two displays, optical components (e.g., an optical engine), and a power supply. Therefore, AR headsets can be bulky and cumbersome. In mobile systems such as AR and head-mounted systems, LCoS or micro-LED type displays are commonly used. When manufacturing such systems, the size, weight, and battery life of the displays used are important so that the system or device can be worn comfortably for as long as possible before needing to be recharged.

[0005] LED displays typically driven by TFT arrays can be used in AR systems such as head-mounted displays and are relatively inexpensive. However, TFTs have high resistance and thus consume a lot of power. Therefore, driving large currents with such TFTs can also be challenging. Moreover, shrinking TFTs to the optimal size for microdisplays is challenging because they use a geometry larger than transistors fabricated on silicon wafers. While LCoS microdisplays made with silicon backplanes allow logic and memory to be located below the pixels, such devices operate in a color sequential manner, which involves sequentially repeating the same pixels and mirrors for the red, green, and blue fields. When driving LEDs, multiple panels (one for each color) may be required, potentially tripling the size of the subsystem, or a spatial color arrangement of multiple LEDs of different colors on a single panel may be involved. However, these options often result in display or display system sizes that are not optimal for AR systems or devices. The displays according to the present invention, such as liquid crystal on silicon (LCoS) displays, light-emitting diode (LED) displays (including micro-LED displays and OLED displays), and microdisplays (e.g., LCoS or LED displays), can be used in applications including but not limited to: projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices, such as headsets or other near-eye devices or systems. Summary of the Invention

[0006] One aspect of the invention may involve, for example, driving a main pixel by driving sub-pixels in a field-sequential and / or hybrid mode, such that a single pixel driving circuit, including a pixel logic circuitry system (e.g., a pixel control logic circuitry system), is used to drive at least two sub-pixels or LED / LED pixels (e.g., micro-LEDs). Thus, no driving circuitry or separate driving circuitry system is required for each sub-pixel or LED / LED pixel (e.g., micro-LED). In an exemplary aspect of the invention, one or more pixels of the main pixel may be always on during a frame or color subframe, while driving one or more other pixels (e.g., sub-pixels, LEDs, or micro-LEDs) according to field-sequential operation. In an exemplary aspect of the invention, the display is a multi-color display, such as a multi-color micro-LED display, which includes a main pixel having a plurality of colored LEDs as sub-pixels (wherein the color of one of these LEDs may be different from the color of another LED). In an exemplary aspect of the invention, the display is an LCoS display driven by field-sequential color operation.

[0007] Comparative examples of displays might require a separate set of driving circuitry for each sub-pixel within a main pixel (e.g., for each of the sets of red, green, and blue sub-pixel LEDs). Exemplary aspects of the invention reuse driving circuitry (e.g., pixel circuitry, pixel control circuitry, pixel logic circuitry, or pixel control logic circuitry) over time, reducing the number of copies of such circuitry required to drive the display according to the invention. Therefore, the display according to the invention has a reduced main pixel size, and thus a reduced overall size. The microLED display according to the invention is an alternative to other types of displays and provides a compact form factor and high optical engine efficiency due to the elimination of the need for an external illumination source. In the example of the microLED display according to the invention, only the source pixels are illuminated, in contrast to, for example, an LCoS display, in which the entire display is illuminated regardless of whether the image content requires it.

[0008] Exemplary aspects of the present invention reduce the size of display systems or devices that integrate or include displays according to the invention (e.g., LED displays, such as micro-LED displays and OLED displays) and / or improve the efficiency of such display systems or devices. Examples of circuit systems according to the invention allow for small-sized displays while providing sufficient resolution and brightness to the pixels of the display using a reasonable amount of power. Displays including circuit systems according to the invention have a low battery volume for providing power to the display and its associated circuitry. Displays including circuit systems according to the invention also result in low weight for the display and its associated circuitry. Displays according to the invention offer advantages when used in applications including, but not limited to, projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices, such as headsets or other near-eye devices or systems. Attached Figure Description

[0009] The present disclosure is illustrated and described herein with reference to the accompanying drawings, in which similar reference numerals are appropriately used to denote similar system components, and in the drawings:

[0010] Figure 1 Exemplary display systems according to various aspects of this disclosure are shown;

[0011] Figures 2A to 3B Exemplary multicolor subpixels in a main pixel system are shown respectively according to various aspects of this disclosure;

[0012] Figures 4 to 7Block diagrams of exemplary pixel circuit systems according to the present invention are shown respectively;

[0013] Figures 8 to 10 Details of an exemplary pixel circuit system according to the present invention are shown respectively;

[0014] Figures 11 to 14 Exemplary duty cycles for the color components according to the present invention are shown respectively; and

[0015] Figure 15 Details of an exemplary pixel circuit system according to the present invention are shown. Detailed Implementation

[0016] Detailed embodiments are disclosed herein as needed. It must be understood that the disclosed embodiments are merely examples of various alternative forms. As used herein, the term "exemplary" is widely used to refer to embodiments used as illustrations, samples, models, or patterns. The drawings are not necessarily drawn to scale, and some features may be enlarged or reduced to show details of specific components. In other instances, well-known components, systems, materials, or methods known to those skilled in the art have not been described in detail to avoid obscuring the content of this disclosure. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as a basis for the claims and as a representative basis for teaching those skilled in the art.

[0017] Reference Figure 1 The present disclosure provides a block diagram of exemplary aspects of a display system 100 in the context of the environment. As shown, the display system 100 may include a graphics processing unit 102 electrically coupled to a digital drive unit 104, and an optical engine 106 electrically and / or optically coupled to the digital drive unit 104.

[0018] The graphics processing device 102 transmits image data and / or control data to the digital drive device 104. The graphics processing device 102 typically includes a processor or associated with the processor, as well as other components known to those skilled in the art. The processor may be internal or external to the graphics processing device 102. In an exemplary aspect of this disclosure, the processor may execute software modules, programs, or instructions of the graphics processing device 102. Storage devices (e.g., memory devices or storage areas) may also be internal or external to the graphics processing device 102.

[0019] The digital drive unit 104 receives data from the graphics processing unit 102, analyzes the data in the resolver 108, and arranges the received data (e.g., image data) before transmitting it to the optical engine 106. The resolver 108 separates and / or identifies image data and command data, and routes information (e.g., based on the received data) to the light source control module 110, the formatter module 113, and the bias voltage control module 112. The light source control module 110 is used only when the display is an LCoS display.

[0020] The light source control module 110 converts received commands into timed control inputs. The bias voltage control module 112 converts received commands into voltages, and the formatter module 113 converts image data into binary formatted data (e.g., a "bit plane"), which is used to drive the state of pixels in the display 120 after the bit plane has been stored in memory 114 (which serves as a staging area and may also store control data). The digital drive device 104 may be a component of, for example, a computing system, a head-mounted device, and / or other devices utilizing LCoS or micro-LED (uLED) displays.

[0021] In an exemplary aspect of this disclosure, the optical engine 106 includes components of a spatial light modulator or display 120, as well as all other means that may be necessary to complete the display system 100, as is known to those skilled in the art. In other exemplary aspects of this disclosure, the display 120 itself may be located external to the optical engine 106. If an LCoS display is used, the optical engine 106 may be used to include a light source 116, which is controlled to illuminate the spatial light modulator 120 using electromagnetic radiation (e.g., light) intensity and on / off timing provided by the light source control module 110. The display 120 includes a pixel array 126 comprising a two-dimensional array of main pixels 128 arranged in a series of rows and columns indicated by dashed lines. Figure 1 In the original display, only one primary pixel 128 is highlighted, and only two rows and two columns are shown. However, in a practical implementation, the pixel array 126 can contain thousands or more rows and columns, allowing for up to a million or more primary pixels 128 to be displayed on the display 120.

[0022] In an LCoS display, a spatial light modulator 120 includes a display front panel 122, such as a liquid crystal (LC) cell, which modulates reflected or transmitted light under the influence of or according to electrical inputs from or based on pixel circuitry systems located beneath pixel elements (e.g., pixel electrodes or conductive metal elements, such as reflective metal mirrors) of pixels 128 in a two-dimensional pixel array 126. The two-dimensional pixel array 126 resides in, is coupled to, and / or is integrated with a backplane integrated circuit 124. The backplane integrated circuit 124 also includes pixel circuitry systems, such as pixel array driving logic 125, which provides image data and / or control data connected to a pixel array distributed in rows or columns of pixels, depending on the data's functionality. In an LED display (e.g., a microLED display), the spatial light modulator 120 includes a display front panel 122, such as an LED array (e.g., microLEDs), which modulates reflected or transmitted light under the influence of or based on electrical inputs from pixel elements (e.g., LEDs and microLEDs, see...) of pixels 128 in a two-dimensional pixel array 126. Figures 2A to 2B The pixel array 126 resides in, is coupled to, and / or is integrated with the backplane integrated circuit 124, under the influence of or according to the electrical inputs of the pixel circuit system below. Pixels 128 in the backplane are coupled to or electrically connected to the front panel and modulate reflected light according to a binary pattern provided by the memory 114. In an exemplary aspect of the invention, pixel 128 may include pixel elements (e.g., pixel electrodes or conductive and reflective metal elements, such as reflective metal mirrors, or light-emitting structures such as LEDs and microLEDs), pixel circuit systems (e.g., pixel control or drive circuit systems), and driver devices (e.g., current or voltage driver devices or systems). In an exemplary aspect of the invention, the pixel control or drive circuit system includes pixel logic or logic functions. In a microLED display, the LED array is light-emitting, and the backplane modulates the drive current to the LEDs of each pixel according to the binary pattern provided by the memory 114 to illuminate or de-illuminate them.

[0023] As described in the following figures, the pixel or pixel unit 128 includes, is integrated into, or is electrically coupled to Figures 2A to 6 The memory elements (e.g., static random access memory (SRAM) elements) and the pixel circuit system / pixel driving circuit system according to the present invention (e.g., Figures 2A to 6The pixel circuitry / pixel driver circuitry repeatedly loads the memory elements of the pixels according to the binary pattern provided by memory 114, thereby creating time-dependent pixel states and generating grayscale values ​​(illuminance) at each pixel. In the case of an LCoS display, the pixel circuitry / pixel driver circuitry is used to convert the lower voltage output from the memory elements into a higher voltage required to perform electro-optic modulation in the front panel 122. In the case of a microLED display, the pixel driver (which is included in the pixel circuitry / pixel driver circuitry) is a current source that converts the binary output into a controlled current, wherein the controlled current changes over time to be on or off.

[0024] Optical components 118 within optical engine 106 may include beam splitters, polarizers (or polarization beam splitters), lenses, and waveguides, and are used to route light from light source 116 to spatial light modulator 120, and then transmit the resulting modulated image to the user's eye.

[0025] Figure 2A and Figure 2B An exemplary layout of the main pixel 200 according to the present invention is shown, along with a schematic reproduction of the main pixel 200. The main pixel 200 can be... Figure 1 The pixel 128 shown is the same. For example... Figure 2A As shown, the main pixel 200 includes four sub-pixels 201 to 204. Figure 2B In the example shown, the sub-pixels 201 to 204 constituting the main pixel 200 include LEDs 211 to 214, respectively; however, in other examples, the sub-pixels 201 to 204 may be based on other emitting devices and / or on reflective materials or devices, such as digital micromirror devices (DMDs).

[0026] In an exemplary aspect of the invention, in the main pixel 200, one or more LEDs 211 to 214 may be different in color from the other LEDs 211 to 214. LEDs according to the invention include micro-LEDs, OLEDs, quantum dots, etc. In an exemplary aspect of the invention, such as Figure 2BAs shown, there are two green LEDs 212 and 213, one blue LED 211, and one red LED 214. However, those skilled in the art will understand that each LED of the main pixel 200 can be any color or combination of colors. In an exemplary aspect of the invention, the emitting area (i.e., where the emitting area corresponds to the physical size of the region emitting light) of one or more LEDs 211 to 214 of the main pixel 200 can have a different size than the other LEDs 211 to 214. In an exemplary aspect of the invention, LEDs can have varying sizes to compensate for differences in electro-optical conversion efficiency between LEDs of different colors, perceptual differences in the human visual system (e.g., different sensitivities to different colors), etc. In an exemplary aspect of the invention, as Figure 2A As shown, green (G) subpixels 212 and 213 have the same size and shape, red (R) subpixels 204 and blue (B) subpixels 201 have the same shape, and the size of red subpixel 204 is larger than the size of blue subpixel 201. Those skilled in the art will understand that the size, shape, number, and color of each subpixel 201 to 204 of the main pixel 200 may differ from one or more other subpixels 201 to 204. For the implementation of subpixels 201 to 204 based on the LCoS architecture, LEDs 211 to 214 can alternatively be represented by metal mirrors driven by circuit components (e.g., capacitive devices) operating based on the voltage gap between electrodes.

[0027] like Figure 2A As shown, subpixels 201 to 204 are arranged according to a Bayer-type pattern. Since the eye responds most strongly to green when discerning details, the number of green pixels or subpixels included in the main pixel 200 according to the invention determines the effective resolution of the display including the main pixel 200 according to the invention.

[0028] In another exemplary aspect of the invention, a single green LED sub-pixel may be used. Figure 3A and Figure 3B An exemplary layout of the main pixel 300 according to the present invention is shown, along with a schematic reproduction of the main pixel 300. The main pixel 300 can be... Figure 1 The pixel 128 shown is the same. For example... Figure 3A As shown, the main pixel 300 includes three sub-pixels 301 to 303. Figure 3BIn the example shown, sub-pixels 301 to 303 constituting the main pixel 300 respectively include LEDs 311 to 313; however, in other examples, sub-pixels 301 to 303 may be based on other emitting devices and / or on reflective materials or devices, such as micromirrors. In an exemplary aspect of the invention, one or more LEDs of the main pixel 300 311 to 313 may be different in color from the other LEDs of LEDs 311 to 313. LEDs according to the invention include microLEDs, OLEDs, quantum dots, etc. Figure 3B As shown, there is a green LED 312, a blue LED 311, and a red LED 313. However, those skilled in the art will understand that each LED of the main pixel 300 can be any color or combination of colors. In an exemplary aspect of the invention, the emitting area (wherein the emitting area corresponds to the physical size of the region emitting light) of one or more LEDs 311 to 313 of the main pixel 300 can have a different size than the other LEDs 311 to 313. In an exemplary aspect of the invention, LEDs can have varying sizes to compensate for differences in electro-optical conversion efficiency between LEDs of different colors, perceptual differences in the human visual system, etc. In an exemplary aspect of the invention, as Figure 3A As shown, green (G) subpixel 302 and blue (B) subpixel 301 have the same size and shape, while red (R) subpixel 303 is larger than green subpixel 302 and blue subpixel 301 and has a different shape. Those skilled in the art will understand that the size, shape, number, and color of each subpixel 301 to 303 of the main pixel 300 may differ from one or more other subpixels 301 to 303. For an LCoS architecture-based implementation of subpixels 301 to 303, LEDs 311 to 313 can alternatively be represented by metal mirrors driven by circuit components (e.g., capacitive devices) operating based on a voltage gap between electrodes.

[0029] Compared to main pixel 200, main pixel 300 may have a lower effective resolution due to the reduced number of green subpixels. However, because red LEDs may have reduced efficiency, main pixel 300 can more easily achieve a specific brightness with better efficiency and / or more easily achieve white balance by utilizing a larger red component. This disclosure is not limited to main pixels comprising only three or four subpixels, and in other exemplary aspects of this disclosure, a main pixel may comprise five or more subpixels.

[0030] In an exemplary aspect of the invention, a mapping software module is provided in the form of software or display integrated circuit (IC) hardware. This mapping software module maps an original image containing color information (e.g., R, G, B pixel color information) onto a physical arrangement of sub-pixels within a main pixel, such that the color information is distributed among sub-pixels 201 to 204 or 301 to 303 in such a way that the amount of color output by sub-pixels 201 to 204 or 301 to 303 corresponds to, is equal to, or is substantially equal to the amount of color represented by the color information input to the software, software module, and / or hardware (e.g., display driver software and / or hardware) associated with the display. The software may be stored in memory associated with any component of the display device (e.g., such as...). Figure 1 As shown, it is stored in the graphics processing device 102, the digital drive device 104, the display device 120, etc.

[0031] Figure 4 A pixel circuit system 400 according to an exemplary aspect of the present invention is shown, which may correspond to a method for driving. Figure 2A and Figure 2B An example of the circuitry system for the main pixel 200 is shown. The pixel circuitry system 400 can be... Figure 1 An example of at least a portion of the array driver logic 125 is shown. In exemplary aspects of the invention, such as... Figure 4 As shown, all LEDs in the main pixel can share a common cathode terminal, and the anode of each LED is driven by a separate LED driver. In another exemplary aspect of the invention, all LEDs in the pixel share a common anode, and the cathode of each LED is driven by a separate LED driver.

[0032] The pixel circuit system 400 receives the following as inputs: image data DATA, power supply voltage Vpix, and a row write input ROW indicating the timing of the row selection for the main pixel, for G1 / G2 / B sub-pixels (e.g., for...). Figure 2A The time-varying value GGB_TVV of subpixels 201 to 203, for red subpixels (e.g., for... Figure 2A The time-varying value R_TVV of sub-pixel 204, and sub-pixel-specific enable inputs R_ena, B_ena, G1_ena, and G2_ena indicating the timing of sub-pixel driving; and output current waveforms at nodes PB, PG1, PG2, and PR to drive the corresponding sub-pixels (e.g., via...). Figure 2B The corresponding nodes PB, PG1, PG2, and PR shown drive LEDs 211 to 214. (This can be achieved from...) Figure 1The digital driving device 104 shown receives input (e.g., from bias voltage control module 112 and / or memory 114) and can send output to sub-pixel LEDs (e.g., such as...). Figure 2B (As shown).

[0033] Figure 5 A pixel circuit system 500 according to the present invention is shown, and may correspond to a driving method. Figures 2A to 2B An example of the circuit system for the main pixel 200 is shown. The pixel circuit system 500 can be... Figure 1 An example of at least a portion of the array driver logic 125 is shown. In exemplary aspects of the invention, such as... Figure 5 As shown, all LEDs in the main pixel can share a common cathode terminal, and the anode of each LED is driven by a separate LED driver. In another exemplary aspect of the invention, all LEDs in the pixel share a common anode, and the cathode of each LED is driven by a separate LED driver.

[0034] The pixel circuit system 500 receives the following as inputs: image data DATA, power supply voltage Vpix, and a row write input ROW indicating the timing of the row selection for the main pixel, for R / G1 / G2 / B sub-pixels (e.g., for...). Figure 2A The time-varying value RGGB_TVV of sub-pixels 201 to 204, and sub-pixel-specific enable inputs R_ena, B_ena, G1_ena, and G2_ena indicating the timing of sub-pixel driving; and output current waveforms at nodes PB, PG1, PG2, and PR to drive the corresponding sub-pixels (e.g., via...). Figure 2B The corresponding nodes PB, PG1, PG2, and PR shown drive LEDs 211 to 214. (This can be achieved from...) Figure 1 The digital driving device 104 shown receives input (e.g., from bias voltage control module 112 and / or memory 114) and can send output to sub-pixel LEDs (e.g., such as...). Figure 2B (As shown).

[0035] In accordance with the present invention, Figures 4 to 5 In the example of the pixel circuit system shown, each master pixel (i.e., a set of one or more sub-pixels, such as...) Figure 2A The main pixel 200 includes or is associated with the following: each LED used for driving the main pixel (e.g., for...). Figure 2B Current sources 421 to 424 for each of LEDs 211 to 214 Figure 4 ) or current source 521 to 524 ( Figure 5(e.g., a current source driver device such as a transistor or a combination of a resistor and a transistor), and at least one storage device (e.g., a memory device) together with pixel logic (e.g., pixel control logic) that stores the desired or predetermined brightness levels of one or more LEDs and activates and deactivates the current at the desired or predetermined time, such that the LEDs are driven in response to the stored brightness level values ​​according to a pulse width modulation (PWM) operating mode (i.e., where the drive waveform oscillates between zero and a set value, and the brightness is determined by multiplying the drive current by the proportion of time the drive waveform is at the set value) or other series of pulses with variable width or number. Figure 4 The image shows two pixel logic and storage devices 411 and 412. Figure 5 The diagram shows a pixel logic and storage device 511. In the comparative example, four sets of pixel logic and storage devices would be needed to drive four sub-pixels; therefore, pixel circuit system 400 and pixel circuit system 500 require fewer circuit systems to drive the same number of sub-pixels. Although Figure 4 and Figure 5 A pixel circuit system corresponding to a main pixel having LEDs driven by current sources 421 to 424 or 521 to 524 is shown. However, in an implementation of the main pixel based on an LCoS architecture, voltage sources can be used instead of current sources 421 to 424 or 521 to 524. Pixel circuit system 500 can occupy a smaller area compared to pixel circuit system 400. Conversely, pixel circuit system 400 can provide a larger usable duty cycle and / or a lower required peak current compared to pixel circuit system 500.

[0036] Figure 6 A pixel circuit system 600 according to the present invention is shown, and may correspond to a method for driving. Figures 3A to 3B The example shown is of the circuitry system for the main pixel 300. The pixel circuitry system 600 can be... Figure 1 An example of at least a portion of the array driver logic 125 shown. In an exemplary aspect of the invention, as... Figure 6 As shown, all LEDs in the main pixel can share a common cathode terminal, and the anode of each LED is driven by a separate LED driver. In another exemplary aspect of the invention, all LEDs in the pixel share a common anode, and the cathode of each LED is driven by a separate LED driver.

[0037] The pixel circuit system 600 receives the following as inputs: image data DATA, power supply voltage Vpix, a row write input ROW indicating the timing of the row selection of the main pixel, and inputs for G / B sub-pixels (e.g., for G / B sub-pixels). Figure 3A The time-varying value GB_TVV of subpixels 301 and 302, for red subpixels (e.g., for...). Figure 3A The time-varying value R_TVV of sub-pixel 303, and sub-pixel-specific enable inputs R_ena, B_ena, and G_ena indicating the timing of sub-pixel driving; and output current waveforms at nodes PB, PG, and PR to drive the corresponding sub-pixels (e.g., via...). Figure 3B The corresponding nodes PB, PG, and PR shown are used to drive LEDs 301 to 303. (This can be achieved from...) Figure 1 The digital driving device 104 shown receives input (e.g., from bias voltage control module 112 and / or memory 114) and can send output to sub-pixel LEDs (e.g., such as...). Figure 3B (As shown).

[0038] Figure 7 A pixel circuit system 700 according to the present invention is shown, and may correspond to a driving method. Figure 3A and Figure 3B The example shown is of the circuit system of the main pixel 300. The pixel circuit system 700 can be... Figure 1 An example of at least a portion of the array driver logic 125 shown. In an exemplary aspect of the invention, as... Figure 7 As shown, all LEDs in the main pixel can share a common cathode terminal, and the anode of each LED is driven by a separate LED driver. In another exemplary aspect of the invention, all LEDs in the pixel share a common anode, and the cathode of each LED is driven by a separate LED driver.

[0039] The pixel circuit system 700 receives the following as inputs: image data DATA, power supply voltage Vpix, a row write input ROW indicating the timing of the row selection of the main pixel, and inputs for R / G / B sub-pixels (e.g., for R / G / B sub-pixels). Figure 3A The time-varying value RGB_TVV of sub-pixels 301 to 303, and the sub-pixel-specific enable inputs R_ena, B_ena, and G_ena indicating the timing of the sub-pixel being driven; and output current waveforms at nodes PB, PG, and PR to drive the corresponding sub-pixels (e.g., via...). Figure 3B The corresponding nodes PB, PG, and PR shown are used to drive LEDs 301 to 303. (This can be achieved from...) Figure 1 The digital driving device 104 shown receives input (e.g., from bias voltage control module 112 and / or memory 114) and can send output to sub-pixel LEDs (e.g., such as...). Figure 3B (As shown).

[0040] In accordance with the present invention, Figures 6 to 7 In the example of the pixel circuit system shown, each main pixel (i.e., a set of one or more sub-pixels, such as...) Figure 3AThe main pixel 300 includes or is associated with the following: each LED used for driving the main pixel (e.g., for...). Figure 3B Current sources 621 to 623 for each of LEDs 311 to 313 Figure 6 ) or current source 721 to 723 ( Figure 7 (e.g., a current source driver device such as a transistor or a combination of a resistor and a transistor), and at least one storage device (e.g., a memory device) together with pixel logic (e.g., pixel control logic) that stores the desired or predetermined brightness levels of one or more LEDs and activates and deactivates currents at desired or predetermined times, such that the LEDs are driven in response to the stored brightness level values ​​according to a pulse width modulation (PWM) operating mode or other series of pulses with variable width (where width refers to duration and corresponds to different brightness levels) or number. Figure 6 The image shows two pixel logic and storage devices 611 and 612. Figure 7 In the example shown, only one pixel logic and storage device 711 is illustrated. In the comparative example, three sets of pixel logic and storage devices would be required to drive three sub-pixels; therefore, pixel circuit system 600 and pixel circuit system 700 require fewer circuitry to drive the same number of sub-pixels. Although Figure 6 and Figure 7 A pixel circuit system corresponding to a main pixel having LEDs driven by current sources 621 to 623 or 721 to 723 is shown. However, in an implementation of the main pixel based on an LCoS architecture, voltage sources can be used instead of current sources 621 to 623 or 721 to 723. Pixel circuit system 700 can occupy a smaller area compared to pixel circuit system 600. Conversely, pixel circuit system 600 can provide a larger usable duty cycle and / or a lower required peak current compared to pixel circuit system 700.

[0041] In an exemplary aspect of the invention, although in Figures 4 to 7 They are shown together, but the memory devices (e.g., memory devices) and pixel logic circuit system components in pixel logic and memory circuits 411 / 412, 511, 611 / 612 or 711 may be electrically coupled separate components / devices / systems (e.g., such as...). Figures 8 to 10 As shown below, which will be described in more detail below.

[0042] In an exemplary aspect of the invention, Figures 4 to 7 The current sources 421 to 424, 521 to 524, 621 to 623, or 721 to 723 shown are used as driving elements to drive Figures 2A to 3BThe operation of LEDs 211 to 214 or LEDs 311 to 313 shown is due to their ability to convert current into light in a substantially linear manner. This contrasts with voltage-driven sources, which can produce undesirable variations in light output due to variations in, for example, the resistance of LEDs 211 to 214 or LEDs 311 to 314, their contacts, and the power delivery network of the common cathode and driver power supply. In an exemplary aspect of the invention, when the display 120 is an LCoS display, a voltage source can be used to drive the pixels / pixel elements / LED / LED pixels. The reference to "pixel" is a reference to pixels of any type of display, such as LCoS pixels or LED / LED pixels.

[0043] In an exemplary aspect of the invention, a pixel memory (e.g., Figures 8 to 10 The pixel memories 811, 911, 913, 1011 and / or shown are Figures 4 to 7 The pixel logic and memory components of storage devices 411, 412, 511, 611, 612, or 711 shown are loaded with data (e.g., image data, which may include video data), such as values ​​(e.g., values ​​between 0 and 255 including end values ​​for a pixel with an 8-bit color depth, or values ​​between 0 and 1023 including end values ​​for a pixel with a 10-bit color depth). In an exemplary aspect of the invention, those skilled in the art will understand that the bit depth and the values ​​representing said bit depth can vary.

[0044] In an exemplary aspect of the invention, such as Figures 8 to 10 As shown, data (e.g., image data) is loaded into pixel memories 811, 911, 913, and / or 1011 by placing the data to be written on the data bus (labeled "DATA" in the figure) and applying voltage or current pulses as ROW-WRITE inputs. These ROW-WRITE inputs are input to pixel logic circuitry systems 812, 912, and / or 1012, which determine when to write the data (e.g., DATA) to the pixel memory of at least one sub-pixel. In implementations where the sub-pixels of the top and bottom rows are driven separately (e.g., as...), Figure 9 As required, the pixel memory can be loaded with image data DATA0 or DATA1 and provided with ROWWRITE0 input or ROWWRITE1 input. In an exemplary aspect of the invention, the display (e.g., Figure 1 The display 120 includes an array of pixel elements such as LEDs or mirrors (e.g., Figure 1The primary pixels 128), and the ROW-WRITE input determines when to write data simultaneously for all primary pixels 128 in the row of the pixel array 126.

[0045] During a given color of an LED being valid for a period of time (e.g., a frame or a subframe), which may be the entire duration of a video / image frame or a subset thereof (i.e., referred to as a subframe (e.g., a color subframe)), data stored in pixel memories 811, 911, 913 and / or 1011 (e.g., image data DATA [n:0], which corresponds to values, such as color values ​​and are represented by multi-bit binary values) is input to pixel logic circuitry systems 812, 912 and / or 1012. In an exemplary aspect of the invention, one or more time-varying values ​​(e.g., digital values ​​that change over time, such as digital data patterns or multi-bit count values ​​represented by voltage pulses) identified by reference numerals R_TVV and C_TVV data or R_TVV and C_TVV are input to pixel logic circuit systems 812, 912 and / or 1012 (e.g., LED pixel control logic circuit systems), where R represents a time-varying value for red, C represents a time-varying value for a combination of green (G) and blue (B), and logic functions (e.g., comparison, summation, OR, AND) combine the time-varying values ​​with image / video data (e.g., luminance data corresponding to color values) and generate an output that controls an LED / sub-pixel via drivers 820, 921, 922 and / or 1020 (e.g., current or voltage driver devices). For example, in an exemplary aspect of the invention, a master clock is coupled to a pixel logic circuit system, and during each cycle, the master clock causes a color-specific time-varying count value (e.g., R_TVV and C_TVV data or R_TVV and C_TVV) to increment over a period of time (e.g., within a frame or subframe), and such a count value is input to pixel logic circuit systems 812, 912 and / or 1012 and used to control when to activate a current control device using stored data (e.g., image / video data, such as luminance data) received by pixel logic circuit systems 812, 912 and / or 1012 to achieve or reach, for example, a desired or predetermined color, intensity or luminance of a corresponding LED / LED pixel in an LED / LED pixel. In an exemplary aspect of the invention, data stored in pixel memories 811, 911, 913, and / or 1011 is logically combined with incoming multi-bit count values ​​or digital data patterns on inputs / data / values ​​R_TVV and C_TVV, and logic functions (e.g., comparison, summation, OR, AND) determine, for each cycle of the master clock controlling the advancement or change of the R_TVV and C_TVV inputs / data / values, whether the current control driven by this logic is set high or low. For example, in an exemplary aspect of the invention, the master clock can advance the count from 0 to 256. The end result is digital modulation of the LED output over time. In embodiments of the invention, as... Figure 4 As shown, two pixel logic and storage devices 411 and 412 are used to control the four LEDs of the main pixel. For example, one pixel logic and storage device 411 controls the green (G1 and G2) and blue LED / LED pixels, while the other pixel logic and storage device 412 controls the red LED / LED pixel. In addition to the count value, enable inputs R_ena, G1_ena, G2_ena, and B_ena can also be used to activate one LED driver at a time, so that the modulation function is applied to only some of the LEDs at a time. In another exemplary aspect of the invention, as... Figure 6 As shown, two pixel logic and storage devices 611 and 612 are used to control the three LEDs of the main pixel. For example, one pixel logic and storage device 611 controls the green and blue LEDs / LED pixels, while the other pixel logic and storage device 612 controls the red LED / LED pixel. In addition to the count value, enable inputs R_ena, G_ena, and B_ena can also be used to activate one LED driver at a time, so that the modulation function is applied to only some LEDs at a time.

[0046] In an exemplary aspect of the invention, such as Figure 5 As shown, all pixels / LEDs (e.g., the three colors of a main pixel are represented by one or more LEDs or varying colors) can be driven by a single pixel logic and memory device 511. The number of such pixel logic circuits / memory areas required is determined by the desired duty cycle.

[0047] Figures 8 to 10 An exemplary pixel circuit system of the present invention is illustrated, which includes logical operations of a pixel logic circuit system (i.e., logical operations of the pixel). Specifically, Figure 8 It shows Figure 4 An example where the pixel logic and storage devices 411 and 412 are separated; Figure 9 It shows Figure 5 An example in which the pixel logic and storage device 511 components are separated; and Figure 10 It shows Figure 6 Pixel logic and storage devices 611 and 612 or Figure 7 An example where the pixel logic and storage device 711 components are separated.

[0048] exist Figure 8In the pixel logic and storage device, the following are received as inputs: image data DATA [n:0], a row write input ROW-WRITE indicating the timing of row selection of the main pixel, a time-varying value TVV [n:0], a calculation input COMPUTE indicating the timing of calculations performed by logic function 812 and latch 813, and sub-pixel-specific enable inputs (e.g., R_ena, B_ena, G1_ena, and G2_ena); and outputs a voltage or current waveform to drive the pixel. Pixel driver 820 (e.g., Figures 4 to 7 A current source (or a voltage source in an LCoS implementation) is operatively connected to pixel memory 811, logic function 812, and latch 813. Logic function 812 can store the desired or predetermined brightness level of one or more sub-pixels and activate and deactivate current (or change voltage) at desired or predetermined times, such that the sub-pixels are driven according to a PWM operating mode or other control in response to the stored brightness level value (e.g., stored in pixel memory 811).

[0049] exist Figure 9 In this process, sub-pixels in different rows within the main pixel can be driven individually. The pixel logic and storage device receives the following as inputs: top row image data DATA0[n:0] and bottom row image data DATA1[n:0], top row write inputs ROWWRITE0 and bottom row write inputs ROWWRITE1 indicating the timing of the selection of the top row and bottom row sub-pixels of the main pixel, time-varying value TVV[n:0], calculation input COMPUTE indicating the timing of the calculation performed by logic function 912 and latches 914 / 915, and sub-pixel-specific enable inputs R_ena, B_ena, G1_ena, and G2_ena indicating the timing of the driving of the sub-pixel; and outputs a voltage or current waveform to drive the pixel. Therefore, the first pixel driver 921 (e.g., corresponding to Figures 4 to 7 The current source of the top row sub-pixels within the main pixel, or, in an LCoS implementation, a voltage source, is operatively connected to the first pixel memory 911, logic function 912, and first latch 914. Logic function 912 can output a voltage or current waveform representing a desired or predetermined brightness level for one or more sub-pixels in the top row, and activate and deactivate the current (or change the voltage) at a desired or predetermined time, such that the sub-pixels are driven according to a PWM operating mode or other control in response to a stored brightness level value (e.g., stored in the first pixel memory 911). The second pixel driver 922 (e.g., corresponding to...) Figures 4 to 7The current source of the bottom row sub-pixels within the main pixel (or, in an LCoS implementation, a voltage source) is operatively connected to the second pixel memory 913, logic function 912, and second latch 915. Logic function 912 can output a voltage or current waveform representing a desired or predetermined brightness level of one or more sub-pixels in the bottom row, and activate and deactivate the current (or change the voltage) at a desired or predetermined time, such that the sub-pixels are driven according to a PWM function or other control in response to a stored brightness level value (e.g., stored in the second pixel memory 913).

[0050] In an exemplary aspect of the invention, such as Figure 9 As shown, the logic function elements / components / devices of the pixel logic circuit system are shared between two adjacent main pixels and used in a time-multiplexed manner, such that the calculations performed by the logic function elements / components / devices of the pixel logic circuit system alternately cycle between each main pixel or LED pixel.

[0051] exist Figure 10 In the pixel logic and storage device, the following are received as inputs: image data DATA [n:0], a row write input ROW-WRITE indicating the timing of row selection of the main pixel, a time-varying value TVV [n:0], a calculation input COMPUTE indicating the timing of calculations performed by logic function 1012 and latch 1013, and sub-pixel-specific enable inputs R_ena, B_ena, and G_ena indicating the timing of driving sub-pixels; and outputs a voltage or current waveform to drive the pixel, pixel driver 1020 (e.g., Figures 4 to 7 A current source (or a voltage source in an LCoS implementation) is operatively connected to pixel memory 1011, logic function 1012, and latch 1013. Logic function 1012 can store the desired or predetermined brightness level of one or more sub-pixels and activate and deactivate current (or change voltage) at desired or predetermined times, such that the sub-pixels are driven according to a PWM operating mode or other control in response to the stored brightness level values ​​(e.g., stored in pixel memory 1011). However, Figure 10 Examples are similar to Figure 8 The example is for cases where the main pixel consists of only three sub-pixels (R, G, B) instead of four sub-pixels (R, G1, G2, B).

[0052] In an exemplary aspect of the invention, pixel memories 811, 911, 913, and / or 1011 are loaded by presenting data values ​​on an input data bus and loading the data values ​​into a memory using a ROW-WRITE (or ROW-WRITE0 / ROW-WRITE1) input (e.g., a voltage input or a voltage pulse input). The pixel / LED / LED pixels of the invention emit or reflect light in intensity corresponding to the loaded data value based on a count value (e.g., data or a changing digital pattern, such as a linear count or a one-hot encoded value, e.g., a data stream where only one value is always high), which is transmitted via a bus carrying a time-varying voltage value (e.g., an RGGB_TVV bus or a TVV value) to the pixel logic circuitry (e.g., in…). Figures 4 to 7 The pixel logic and the pixel logic circuit system shown and included in the memory area (see ) logic functions / pixel logic circuit system / components / parts / devices (see Figures 8 to 10 The logic function / pixel logic circuit system performs combinational logic (e.g., logic combinations (e.g., AND, OR, XOR, or equivalent functions)) of the stored data value and the incoming TVV value to produce a logical result, which is passed to a latch (which may be the last of a plurality and electrically coupled to the pixel driver) that outputs data to the pixel driver, and such data controls the pixel driver (e.g., which may be the last of a plurality and is a current source or current source device in the case of an LED or microLED display, and a voltage source / voltage source device in the case of an LCoS or liquid crystal (LCD) display or microdisplay). In an exemplary aspect of the invention, the logic function / pixel logic circuit system performs a comparison logic function. For example, in an exemplary aspect of the invention, when the display is a microLED display, the pixel driver may be a current source, or when the display is an LCoS display, the pixel driver may be a voltage level shifter. In an exemplary aspect of the invention, the value of TVV is periodically (e.g., whenever the value of TVV changes) updated based on activation of the COMPUTE input created by logic in a backplane outside the pixel array. Figures 8 to 10 The latch. In an exemplary aspect of the invention, the COMPUTE input can also be used to control pixel control processing / activities in the logic functional elements / components / devices of the pixel logic circuit system, and to reduce its power dissipation by stopping and starting internal activities, so that energy is used only when needed.

[0053] Figures 11 to 14 Compared to the frame length, this shows the maximum duty cycle of the color corresponding to each LED (e.g., each colored LED) of the main pixel. For example, in Figures 11 to 14The maximum range of duty cycles is shown, which is the length of a full video frame. Figure 11 It can correspond to the Figure 4 and Figure 8 The maximum duty cycle of the sub-pixel driven by the pixel driving circuit system shown; Figure 12 It can correspond to the Figure 5 and Figure 9 The maximum duty cycle of the sub-pixel driven by the pixel driving circuit system shown; Figure 13 It can correspond to the Figure 6 and Figure 10 The pixel driving circuit system shown represents the maximum duty cycle of the sub-pixels driven by the system; and Figure 14 It can correspond to the Figure 7 and Figure 10 The pixel driving circuit system shown represents the maximum duty cycle of the sub-pixels driven. However, those skilled in the art will understand that the duty cycle / duty cycle length can vary. Furthermore, for illustrative purposes, in Figures 11 to 14 The lengths of the frames shown in each example are different, but in actual implementation, the lengths of the frames can be the same or different from each other.

[0054] In the first example (in) Figure 11 As shown in the diagram, a larger duty cycle is used for red LEDs due to their lower efficiency. The relative brightness of the LED / LED pixel is determined by multiplying the amount of time each individual LED is on by its drive current for each maximum possible duty cycle. Figure 4 As shown, the memory (in pixel logic and storage device 412) coupled to the circuitry driving the red LED (e.g., current source 424) is loaded with a value once at the start of a full frame, while the memory (in pixel logic and storage device 411) coupled to the circuitry driving the two green LEDs and one blue LED (e.g., current sources 422, 423, and 421, respectively) is loaded with a value once at the start of the corresponding color subframe, thus enabling the reuse of the circuitry (i.e., using the pixel logic circuitry to drive color subframes individually, for example, at different times, without needing a separate pixel logic circuitry for each pixel or LED pixel). Therefore, as Figure 11 As shown, the red LED is driven in parallel with the green and blue LEDs for the entire frame, while the green and blue LEDs are each driven in field-sequence mode for one-third of the frame. In other words, subpixels are driven in a hybrid manner between full-time-on and field-sequence operation.

[0055] In accordance with the corresponding Figure 5 Examples of pixel circuit system structures, such as Figure 12 As shown, an image or video frame is divided into four time periods, during which each sub-pixel is independently activated, turned on, deactivated, or loaded based on data (e.g., image data or video data). Therefore, as... Figure 12 As shown, each LED is driven in a field-sequence manner up to a quarter frame. This process, which involves four time periods, also reduces the amount of circuitry required to drive pixels (e.g., micro-LED pixels or LCoS pixels), but at the cost of requiring higher current and operating at a faster clock rate during the red period.

[0056] In accordance with the corresponding Figure 6 In the example of the pixel circuit system structure, a larger duty cycle is used for the red LED due to its lower efficiency. The relative brightness of the LED / LED pixel is determined by the amount of time each individual LED is turned on, using each maximum possible duty cycle. Figure 6 As shown, the memory (in pixel logic and storage device 612) coupled to the circuitry driving the red LED (e.g., current source 623) is loaded with a value once at the start of a full frame, while the memory (in pixel logic and storage device 611) coupled to the circuitry driving a green LED and a blue LED (e.g., current sources 622 and 621, respectively) is loaded with a value once at the start of the corresponding color subframe, thus enabling the reuse of the circuitry (i.e., using the pixel logic circuitry to drive color subframes individually, for example, at different times, without needing a separate pixel logic circuitry for each pixel or LED pixel). Therefore, as Figure 13 As shown, the red LED is driven in parallel with the green and blue LEDs throughout the entire frame, while the green and blue LEDs are each driven in a field-sequential manner for one-third of the frame. In other words, for the three-subpixel main pixel, the subpixel is driven in a hybrid manner between full-time on and field-sequential operation.

[0057] In accordance with the corresponding Figure 7 Examples of pixel circuit system structures, such as Figure 14 As shown, an image or video frame is divided into three time periods, thereby allowing each sub-pixel to be independently activated, turned on, deactivated, or loaded based on data (e.g., image data or video data) during one of these three time periods. Therefore, as... Figure 14 As shown, each LED is driven in a field-sequence manner up to one-third of a frame. This process, which involves three time periods, also reduces the amount of circuitry required to drive pixels (e.g., micro-LED pixels or LCoS pixels), but at the cost of requiring higher current and operating at a faster clock rate during the red period.

[0058] Some examples of the pixel circuitry systems according to the invention provide for driving sub-pixels in a field-sequential manner or in a hybrid manner between always-on and field-sequential operation. This makes it possible to reuse the pixel circuitry system (e.g., pixel driving or control circuitry systems over time) and reduces the number of copies of such circuitry required. Consequently, the size of the main pixel is reduced, and thus the size of the entire display including such a main pixel is also reduced.

[0059] Although Figure 11 and Figure 13 The above description illustrates an implementation where the red subpixel has a longer maximum duty cycle than other color subpixels, but this disclosure is not limited thereto. In exemplary aspects of the invention, one or more other color subpixels may be driven for a longer time than the red subpixel. Furthermore, as stated above, this disclosure is not limited to the use of red, blue, and green primary pixels, but can be applied to other colors or combinations of colors.

[0060] exist Figures 11 to 14 In each image, the brightness of a subpixel is determined by its duty cycle relative to the maximum duty cycle within the frame. For example, a subpixel with a relative duty cycle of 50% will be illuminated in 50% of its assigned subframe and will be at medium brightness. To minimize energy-consuming signal transitions, single-pulse PWM can be implemented; that is, one pulse per color frame. This can be achieved using a global N-bit counting bus and comparators, as will be discussed below. Figure 15 To describe in more detail: Subpixels can be loaded with data values ​​(e.g., DAC codes or grayscale values) to trigger a pulse transition at the point within the subframe where the DAC code equals the bus counter. For example, in a subpixel with 8-bit color depth and a 50% duty cycle, the subpixel can be loaded with a DAC code of 128, which will cause the corresponding LED to be turned on midway through the subframe (when the counter has a value of 128).

[0061] Silicon backplanes used with existing LCoS designs can be adapted for use with microLED displays. However, in some implementations, such a backplane may only be used to drive monochrome LEDs, and therefore multiple display panels are required to achieve full color. If such a backplane is applied to a multicolor LED process, the resolution will be reduced or the size will have to be increased because three to four (3 to 4) pixel circuits are needed to drive three to four (3 to 4) LEDs that constitute the main pixel (i.e., the full-color pixel composed of sub-pixels of each color). In an exemplary aspect of the invention, by utilizing a reduced pixel circuit system, a complex pixel logic circuit system can be located under each pixel.

[0062] The pixel circuitry system according to the invention achieves a smaller display size without sacrificing power or speed. Unlike LCoS displays, LED displays (e.g., microLED displays) according to the invention illuminate only active pixels, i.e., “on” pixels (e.g., LEDs or microLEDs), rather than utilizing an external lighting source that illuminates the entire display (e.g., an LCoS display).

[0063] As described above, in one example of the logic function according to this disclosure, a comparator can be used to implement the PWM according to this disclosure. Digital comparator circuitry can occupy a significant area. The display size can be further reduced by using digital comparator circuitry in a time-multiplexed manner between adjacent pixels or groups of pixels (e.g., between multiple subpixels within a main pixel, between groups of subpixels within a main pixel, and / or between groups of main pixels). Timing can be synchronized with a global bus so that each subpixel or pixel is evaluated during a portion of the global counting cycle.

[0064] In an exemplary aspect of the invention, such as Figure 15 As shown, the logic circuit system includes a comparator that is shared among multiple sub-pixels and operates in a time-sequential manner among columns of sub-pixels within the main pixel. Figure 15 The logic circuit system receives the following as inputs: image data Data0 for the first column of sub-pixels in the main pixel, image data Datal for the second column of sub-pixels in the main pixel, row selection input Row0 for the first row of sub-pixels in the main pixel, row selection input Rowl for the second row of sub-pixels in the main pixel, four sub-pixel memory selection inputs Pxl_selxy (where x represents the x position of the corresponding sub-pixel in the main pixel, y represents the y position of the corresponding sub-pixel in the main pixel, and at the top left sub-pixel, both x and y are 0), four sub-pixel latch selection outputs Pxl_gsetxyselxy (where x represents the x position of the corresponding sub-pixel in the main pixel, y represents the y position of the corresponding sub-pixel in the main pixel, and at the top left sub-pixel, both x and y are 0), and a global timer / counter G[7:0]. Figure 15 The logic circuit system outputs four pixel driving waveforms (e.g., time-varying voltage values) drvxy (where x represents the x position of the corresponding sub-pixel within the main pixel, y represents the y position of the corresponding sub-pixel within the main pixel, and at the top left sub-pixel, both x and y are 0).

[0065] Figure 15The logic circuit system includes four sub-pixel memory circuits 1501 to 1504, two multiplexers 1511 to 1512, logic function 1520 (in some implementations, this may be combinational logic circuitry such as a digital comparator circuit), and four sub-pixel latches 1531 to 1534. The logic circuit system may also include a demultiplexer between logic function 1520 and the four sub-pixel latches 1531 to 1534. Figure 15 In this context, "subpixel (x,y)" refers to the subpixel located at position (x,y) within the main pixel, where (0,0) indicates the subpixel at the top left corner of the main pixel.

[0066] Figure 15 The components in can correspond to Figures 4 to 7 The pixel driving and storage devices 411, 412, 511, 611, 612 and / or 711 are shown. For example, sub-pixel memory circuits 1501 to 1504 may correspond to... Figures 8 to 10 The pixel memories 811, 911, 913 and / or 1011 shown; multiplexers 1511 to 1512; and logic function 1520 can correspond to Figures 8 to 10 The logic functions 812, 912 and / or 1012 shown are illustrated; and the sub-pixel latches 1531 to 1534 can correspond to Figures 8 to 10 The latches 813, 914, 915, and / or 1013 are shown. Subpixel memory circuits 1501 to 1504 can each be implemented as an N-bit memory circuit corresponding to the color depth of the subpixel. For example, subpixel memory circuits 1501 to 1504 can be 8-bit SRAM circuits.

[0067] Figure 15An example of four sub-pixels arranged in a 2×2 array within a main pixel is shown. Sub-pixel memories 1501 and 1502 (corresponding to the left column of sub-pixels) are loaded by presenting the data value data0 on the input data bus and loading the data value into memory using Row0 or Row1 input according to the row where the sub-pixel is located. Sub-pixel memories 1503 and 1504 (corresponding to the right column of sub-pixels) are loaded by presenting the data value data1 on the input data bus and loading the data value into memory using Row0 or Row1 input according to the row where the sub-pixel is located. The outputs of subpixel memories 1501 to 1502 and 1503 to 1504 are multiplexed together by multiplexers 1511 and 1512, respectively, and output as 8-bit data signals DATA[7:0] on a common bus based on pixel selection inputs Px1_sel00, Px1_sel10, Px1_sel01, and Px1_sel11, which are selected from the inputs of the respective subpixel memories 1501 to 1504. Logic function 1520 receives both the data value DATA[7:0] and the 8-bit global counter value G[7:0]. The output of logic function 1520 toggles at the point when the data signal equals the global counter value. This output is provided to subpixel latches 1531 to 1534. Then, subpixel latches 1531 to 1534 store the signals or values ​​of the operational outputs of the corresponding output selection waveforms Px1_gsel00, Px1_gsel10, Px1_gsel01, and Px1_gsel11. The output from each subpixel latch is provided as needed to the corresponding pixel driver drv00, drv10, drv01, or drv11.

[0068] The subject matter described herein can be implemented in digital electronic circuit systems including the structural devices disclosed in this specification and their structural equivalents or combinations thereof.

[0069] Furthermore, the present invention can also be implemented through the following embodiments:

[0070] 1. A display system having a pixel circuit system, comprising: Pixel logic circuit; A storage device coupled to the pixel logic circuitry; A display having at least one main pixel, wherein the main pixel comprises at least two sub-pixels; A first driver device coupled to one of the at least two sub-pixels, wherein the pixel logic circuitry is coupled to the first driver device; and A second driver device is coupled to other pixels among the at least two pixels, wherein the pixel logic circuit is coupled to the second driver device, and wherein the pixel logic circuit controls all sub-pixels among the at least two sub-pixels.

[0071] 2. The display system according to embodiment 1, wherein the first driver device and the second driver device are current driver devices, and the display is a micro LED display, an OLED display, or an LED display.

[0072] 3. The display system according to embodiment 1, wherein the first driver device and the second driver device are voltage driver devices, and the display is an LCoS display or an LCD display.

[0073] 4. The display system according to embodiment 1, wherein the pixel logic circuit maintains one of the at least two sub-pixels in an off state, while changing the state of the other sub-pixels among the at least two sub-pixels between an on state and an off state.

[0074] 5. The display system according to embodiment 1, wherein the at least two sub-pixels are four sub-pixels including two green sub-pixels, one blue sub-pixel and one red sub-pixel, or including other multi-color combinations, and wherein the pixel logic circuit maintains the red sub-pixel in an on state while driving the two green sub-pixels and the blue sub-pixel according to the field sequence color (FSC) sub-pixel driving process or method.

[0075] 6. The display system according to embodiments 1 to 5, wherein the display is a micro-LED display and the sub-pixel is a micro-LED.

[0076] 7. The display system according to embodiments 1 to 5, wherein the display is an LCoS display and the sub-pixel is a reflective material or device.

[0077] 8. The display system according to embodiment 1, wherein the at least two sub-pixels are four sub-pixels including two green sub-pixels, one blue sub-pixel and one red sub-pixel or including other multi-color combinations, and wherein the pixel logic circuit drives the two green sub-pixels, the blue sub-pixel and the red sub-pixel according to the field sequence color (FSC) sub-pixel driving process or method.

[0078] 9. The display system according to embodiment 1, wherein the at least two sub-pixels are three sub-pixels including a green sub-pixel, a blue sub-pixel and a red sub-pixel or including other multi-color combinations, and wherein the pixel logic circuit maintains the red sub-pixel in an on state while driving the green sub-pixel and the blue sub-pixel according to the field sequence color (FSC) sub-pixel driving process or method.

[0079] 10. The display system according to implementation scheme 1 further includes: A latch, which is internal or external to the pixel logic circuit; and A master clock that outputs a time-varying waveform for each predetermined cycle of the master clock, the time-varying waveform determining when a pixel should brighten or darken. The pixel logic circuit receives the time-varying waveform. The pixel logic circuit includes logic functions, wherein when the pixel logic circuit receives a row write waveform corresponding to an instruction for writing data from the storage device corresponding to the brightness data of the pixel to the storage device, the data is input into the pixel logic circuit, and In response to the pixel logic circuit receiving an instruction for calculation, the logic function of the pixel logic circuit performs combinational logic based on or using data stored in the storage device and time-varying waveforms input to the logic function, and outputs activation / enable or deactivation / disable corresponding to high voltage values ​​or low voltage values ​​to the first driver device.

[0080] 11. The display system according to embodiment 10, wherein the logic function then outputs activation / enable or deactivation / disable to the first driver device for pixels that have been enabled by a pixel state waveform input to the pixel logic circuit.

[0081] 12. The display system according to implementation scheme 1, wherein: The pixel logic circuit includes combinational logic circuits; The storage device includes at least two sub-pixel memories coupled to the inputs of the combinational logic circuit, and at least two sub-pixel latches coupled to the outputs of the combinational logic circuit; and The combinational logic circuit is configured to operate on the output of the first sub-pixel memory of the at least two sub-pixel memories during a first portion of the frame period, and to operate on the output of the second sub-pixel memory of the at least two sub-pixel memories during a second portion of the frame period.

[0082] 13. A pixel driving circuit, comprising: Pixel logic and storage devices; A first driver device coupled to a first sub-pixel of a pixel, wherein the pixel logic and storage device are coupled to the first driver device; and A second driver device is coupled to a second sub-pixel of the pixel, wherein the pixel logic and storage device is coupled to the second driver device.

[0083] 14. The pixel driving circuit according to embodiment 13, wherein the first driving device and the second driving device are current driving devices, and the pixel is a micro LED pixel, an OLED pixel or an LED pixel.

[0084] 15. The pixel driving circuit according to embodiment 13, wherein the first driving device and the second driving device are voltage driving devices, and the pixel is an LCoS pixel or an LCD pixel.

[0085] 16. The pixel driving circuit according to embodiment 13 further includes: A third driver device is coupled to a third sub-pixel of the sub-pixel, wherein the pixel logic and storage device is coupled to the third driver device, and The pixel logic and storage device are configured to operate the second driver device and the third driver device in a field-sequence manner.

[0086] 17. The pixel driving circuit according to embodiment 16, wherein the pixel logic and storage device is configured to operate the first driving device during the time period during which the pixel logic and storage device operates the second driving device and the third driving device in the field sequence manner.

[0087] 18. The pixel driving circuit according to embodiment 16, wherein the pixel logic and storage device is configured to operate the first driver device, the second driver device, and the third driver device in the field sequence manner.

[0088] 19. The pixel driving circuit according to embodiment 13, wherein the pixel logic and storage device includes at least one sub-pixel memory, a digital comparator circuit, and at least one sub-pixel latch.

[0089] 20. The pixel driving circuit according to embodiment 19, wherein: The at least one sub-pixel memory includes a first sub-pixel memory and a second sub-pixel memory. The at least one sub-pixel latch includes a first sub-pixel latch and a second sub-pixel latch, and The digital comparator circuit is configured to operate on the output of the first sub-pixel memory during a first portion of the frame period and on the output of the second sub-pixel memory during a second portion of the frame period.

[0090] It should be understood that the disclosed subject matter, in its application, is not limited to the details of the construction and the arrangement of components as set forth in the following description or shown in the accompanying drawings. The disclosed subject matter can have other embodiments and can be practiced and performed in various ways. Furthermore, it should be understood that the wording and terminology used herein are for descriptive purposes and should not be construed as limiting. Therefore, those skilled in the art will recognize that the concepts upon which this disclosure is based can readily be used as the basis for designing other structures, methods, and systems for performing several purposes of the disclosed subject matter. Therefore, it is important that the claims be considered to include such equivalent constructions without departing from the spirit and scope of the disclosed subject matter. Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that this disclosure is by way of example only, and many changes can be made to the details of the implementation of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter, which is limited only by the appended claims.

Claims

1. A display system, comprising: Pixel logic circuitry controls multiple pixels of the display in the following ways: Receive a master clock, wherein for each predetermined period of the master clock, the master clock includes a time-varying waveform for each of the plurality of pixels; as well as For each of the plurality of pixels: Combinational logic is applied to the luminance data stored in the memory device and the time-varying waveform corresponding to the pixel; and The result of the combinational logic is output as an activation signal to the driver device corresponding to the pixel.

2. The display system according to claim 1, wherein, The combinational logic includes at least one of an AND function, an OR function, an XOR function, or an equivalent function applied to the brightness data and the time-varying waveform.

3. The display system according to claim 1, wherein: The pixel logic circuit includes combinational logic circuitry for applying the combinational logic; and The combinational logic circuit is shared by a second plurality of pixels of the display.

4. The display system according to claim 3, wherein, The combinational logic circuit operates in a time-multiplexed manner to alternately apply the combinational logic to the plurality of pixels and the second plurality of pixels.

5. The display system according to claim 1, wherein, The time-varying waveform includes a multi-bit count value that increments during each predetermined cycle of the master clock.

6. The display system according to claim 5, wherein, The combinational logic determines whether the activation signal is set to high or low for each predetermined period based on the comparison result between the brightness data and the multi-bit count value.

7. The display system according to any one of claims 1 to 6, wherein, The pixel logic circuit includes: Combinational logic circuits for applying the combinational logic; The storage device includes at least one pixel memory coupled to the input of the combinational logic circuit to store the brightness data; and At least one pixel latch is coupled to the output of the combinational logic circuit to output the activation signal.

8. The display system according to claim 7, wherein, The combinational logic circuit includes a digital comparator circuit that compares luminance data from the at least one pixel memory with the time-varying waveform.

9. The display system according to any one of claims 1 to 6, wherein, The activation signal controls the driver device to drive the corresponding pixel according to the pulse width modulation operation mode.

10. The display system according to any one of claims 1 to 6, wherein: The plurality of pixels includes four sub-pixels of the main pixel, and the four sub-pixels include two green sub-pixels, one blue sub-pixel, and one red sub-pixel; and According to the field sequence color sub-pixel driving process, the pixel logic circuit drives the two green sub-pixels and the one blue sub-pixel to be in the on state at the same time.

11. The display system according to any one of claims 1 to 6, wherein: The plurality of pixels includes four sub-pixels of the main pixel, and the four sub-pixels include two green sub-pixels, one blue sub-pixel, and one red sub-pixel; and The pixel logic circuit drives the two green sub-pixels, the one blue sub-pixel, and the one red sub-pixel according to the field sequence color sub-pixel driving process.

12. The display system according to any one of claims 1 to 6, wherein: The pixel logic circuit includes combinational logic circuitry for applying the combinational logic; The storage device includes at least two pixel memories coupled to the inputs of the combinational logic circuit, and at least two pixel latches coupled to the outputs of the combinational logic circuit. and The combinational logic circuit applies the combinational logic to the output of the first pixel memory among the at least two pixel memories during a first portion of the frame period, and applies the combinational logic to the output of the second pixel memory among the at least two pixel memories during a second portion of the frame period, wherein the brightness data includes the output of the first pixel memory and the output of the second pixel memory.

13. A method for controlling a display system, comprising: The master clock is received via pixel logic circuitry, and for each predetermined period of the master clock, the master clock includes a time-varying waveform for each of a plurality of pixels of the display. as well as For each of the plurality of pixels: The pixel logic circuit applies combinational logic to the brightness data stored in the storage device and the time-varying waveform corresponding to that pixel; and The pixel logic circuit outputs the result of the combinational logic as an activation signal to the driver device corresponding to the pixel.

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