Memory device including multiple unit layers

Abstract

A memory device includes a first cell layer, a second cell layer stacked on the first cell layer, a third cell layer stacked on the second cell layer, a fourth cell layer stacked on the third cell layer, a first page buffer connected to a first string included in the first cell layer and a third string included in the third cell layer, a second page buffer connected to a second string included in the second cell layer and a fourth string included in the fourth cell layer, and a control logic circuit configured to control the first page buffer and the second page buffer to perform respective core operations on the first cell layer and the second cell layer, respectively.

Description

Technical Field

[0001] This disclosure relates to storage devices comprising multiple unit layers. Background Technology

[0002] Memory is used to store data and includes volatile memory and non-volatile memory. Flash memory devices (examples of non-volatile memory devices) can be used in mobile phones, digital cameras, portable computer devices, fixed computer devices, or other devices.

[0003] With the increasing multifunctionality of information and communication devices, the demand for memory devices with larger capacity and higher integration density is growing. Therefore, three-dimensional (3D) non-volatile memory devices, including multiple word lines vertically stacked on a substrate, have been proposed. Furthermore, research is underway on bonding technologies that connect cell layers formed on different wafers. Summary of the Invention

[0004] One or more embodiments provide a storage device that controls two adjacent cell layers among a plurality of stacked cell layers via different page buffers.

[0005] According to one or more embodiments, a storage device includes: a first cell layer; a second cell layer stacked on the first cell layer; a third cell layer stacked on the second cell layer; a fourth cell layer stacked on the third cell layer; a first page buffer connected to a first string of the first cell layer and a third string of the third cell layer; a second page buffer connected to a second string of the second cell layer and a fourth string of the fourth cell layer; and control logic circuitry configured to control the first page buffer and the second page buffer to perform corresponding core operations on the first cell layer and the second cell layer, respectively.

[0006] According to one or more embodiments, a storage device includes: a first cell layer including a first string; a second cell layer stacked on the first cell layer and including a second string; a first page buffer connected to the first string; a second page buffer connected to the second string; and control logic circuitry configured to control the first page buffer and the second page buffer to perform corresponding core operations on the first cell layer and the second cell layer, respectively.

[0007] According to one or more embodiments, a storage device includes: a first cell layer including a first string; a second cell layer stacked on the first cell layer and including a second string; a third cell layer stacked on the second cell layer and including a third string; a fourth cell layer stacked on the third cell layer and including a fourth string; and peripheral circuitry connected to the first cell layer, the second cell layer, the third cell layer, and the fourth cell layer. The peripheral circuitry may include a first page buffer connected to the first string and the third string, and a second page buffer connected to the second string and the fourth string. Attached Figure Description

[0008] Figure 1 It is a block diagram of a storage device according to one or more embodiments.

[0009] Figure 2 This is a diagram illustrating the configuration of a storage device comprising multiple unit layers according to one or more embodiments.

[0010] Figure 3 It is a cross-sectional view of a storage device according to one or more embodiments.

[0011] Figure 4A It is a circuit diagram of a storage device according to one or more embodiments.

[0012] Figure 4B It is a circuit diagram of a storage device according to one or more embodiments.

[0013] Figure 4C It is a circuit diagram of a storage device according to one or more embodiments.

[0014] Figure 5 It is a circuit diagram of the first series according to one or more implementation methods.

[0015] Figure 6 It is a circuit diagram of a transmission transistor circuit connected between multiple word lines and a voltage generator according to one or more embodiments.

[0016] Figure 7 This is a graph illustrating the differences in programming speed between unit layers according to one or more implementations.

[0017] Figure 8A This is a diagram illustrating a configuration for controlling the forcing voltage based on the programming speed difference between the first and second unit layers, according to one or more implementations.

[0018] Figure 8BThis is a diagram illustrating a configuration for controlling the forced voltage based on the programming speed difference between the third and fourth unit layers, according to one or more implementations.

[0019] Figure 9 This is a graph illustrating the programming speed difference between the first unit layer and the third unit layer according to one or more embodiments.

[0020] Figure 10 This is a diagram illustrating a configuration for controlling word line voltage based on the programming speed difference between the first and third cell layers, according to one or more embodiments.

[0021] Figure 11A This is a diagram illustrating the first leakage current leaking from the first cell layer to the common source line according to one or more embodiments.

[0022] Figure 11B This is a diagram illustrating the second leakage current leaking to the common source line in the third cell layer according to one or more embodiments.

[0023] Figure 12 This is a diagram illustrating a configuration for controlling the common source line voltage based on the difference in leakage current between the first and third cell layers, according to one or more embodiments.

[0024] Figure 13 It is a cross-sectional view of a storage device according to one or more embodiments.

[0025] Figure 14 It is a cross-sectional view of a storage device comprising multiple stacked cell layers according to one or more embodiments.

[0026] Figure 15 It is a cross-sectional view of a storage device comprising multiple stacked cell layers according to one or more embodiments.

[0027] Figure 16 It is a cross-sectional view of a storage device including a first unit layer to a sixth unit layer according to one or more embodiments. Detailed Implementation

[0028] In the following description, one or more embodiments will be described with reference to the accompanying drawings.

[0029] The terms “first,” “second,” etc., used herein may modify various elements regardless of their order and / or priority, and are used only to distinguish one element from another, without limiting one or more implementations.

[0030] Figure 1 It is a block diagram of a storage device according to one or more embodiments.

[0031] refer to Figure 1 According to some embodiments, the storage device 100 may include a storage cell array 110 and peripheral circuitry 120. The peripheral circuitry 120 may include an address decoder 130, a page buffer circuit 140, an input / output (I / O) circuit 150, a voltage generator 160, and control logic circuitry 170.

[0032] The memory cell array 110 may include multiple memory blocks. Each memory block may have a two-dimensional or three-dimensional structure. In a memory block with a two-dimensional (or horizontal) structure, memory cells may be formed in a horizontal direction relative to the substrate. In a memory block with a three-dimensional (or vertical) structure, memory cells may be formed in a direction perpendicular to the substrate.

[0033] The memory cell array 110 may include multiple cell layers CL1 to CL1n. Each of the multiple cell layers CL1 to CL1n may be formed on a different wafer. For example, each of the multiple cell layers CL1 to CL1n may be formed on a different chip, and the chips on which the cell layers are formed may be interconnected by a bonding method.

[0034] For example, the first unit layer CL1 and the second unit layer CL2 can be formed on different stacked wafers. For example, the second unit layer CL2 can be formed on a wafer stacked on top of the wafer on which the first unit layer CL1 is formed.

[0035] Address decoder 130 can be connected to memory cell array 110 via row lines RL. Row lines RL may include serial select lines, ground select lines, and word lines.

[0036] Page buffer circuit 140 can be connected to memory cell array 110 via bit line BL. Page buffer circuit 140 can temporarily store data to be programmed in a selected page, or temporarily store data read from a selected page.

[0037] Page buffer circuit 140 may include a plurality of page buffers PB1 to PBn. Each of the plurality of page buffers PB1 to PBn according to one or more embodiments may correspond to one of a plurality of cell layers CL1 to CL1n.

[0038] For example, the first page buffer PB1 may correspond to the first cell layer CL1. For example, the first page buffer PB1 may be connected to a string included in the first cell layer CL1. A string can be understood as a set of memory cells connected to a specific line.

[0039] Furthermore, for example, the second page buffer PB2 may correspond to the second cell layer CL2. For example, the second page buffer PB2 may be connected to a string included in the second cell layer CL2.

[0040] According to one or more implementations, each of the plurality of page buffers PB1 to PBn can perform core operations on the plurality of cell layers CL1 to CL1n under the control of control logic circuitry 170.

[0041] The core operation can be understood as at least one of the following: erasure operation, programming operation, verification operation, or read operation on the storage unit.

[0042] I / O circuit 150 can be internally connected to page buffer circuit 140 via data line DL, and externally connected to memory controller via I / O line.

[0043] Voltage generator 160 can generate various voltages required for the operation of storage device 100. For example, voltage generator 160 can be configured to generate various voltages provided to row line RL, bit line BL, or common source line based on the operation of storage device 100, such as multiple programming voltages, multiple programming verification voltages, multiple pass voltages, multiple force voltages, multiple read voltages, multiple read pass voltages, multiple erase voltages, etc.

[0044] The control logic circuit 170 can control the overall operation of the storage device 100 in response to commands and / or addresses provided from outside the storage device 100.

[0045] The control logic circuit 170 can be electrically connected to the page buffer circuit 140 and / or the memory cell array 110.

[0046] The control logic circuit 170 can perform core operations on at least a portion of the multiple cell layers CL1 to CLn. For example, the control logic circuit 170 can control the page buffer circuit 140 to perform programming and / or reading operations on at least a portion of the multiple cell layers CL1 to CLn.

[0047] According to one or more embodiments, the control logic circuit 170 can perform core operations on two adjacent cell layers among a plurality of cell layers CL1 to CLn.

[0048] The control logic circuit 170 can perform core operations on the first unit layer CL1 and the second unit layer CL2 that are stacked adjacent to each other among the multiple unit layers CL1 to CLn.

[0049] For example, control logic circuit 170 can perform core operations on the first cell layer CL1 through the first page buffer PB1. Control logic circuit 170 can perform core operations on the second cell layer CL2 through the second page buffer PB2.

[0050] Each of the page buffers PB1 to PBn can be connected to a page of a specified size in the memory cell array 110. A page can be understood as a set of memory cells connected to a specific row line (or word line). Furthermore, the page size can be understood as the number of memory cells connected to a specific row line (or word line).

[0051] For example, each of the page buffers PB1 to PBn can be connected to a specified number of memory cells (e.g., 8KB) connected to a particular word line (or row line).

[0052] Referring to the above configuration, the control logic circuit 170, according to one or more embodiments, can perform core operations on two stacked cell layers CL1 and CL2 using different page buffers PB1 and PB2.

[0053] Each of the different page buffers PB1 and PB2 can be connected to a memory cell corresponding to a specified page size (or number of memory cells).

[0054] Therefore, the storage device 100 according to one or more embodiments can increase the page size controlled by the core operation of two adjacent cell layers CL1 and CL2 among the stacked multiple cell layers CL1 to CLn.

[0055] In addition, according to one or more embodiments, the control logic circuit 170 can control the core operations on each unit layer based on the unit characteristics of each unit layer.

[0056] For example, the control logic circuit 170 can control the magnitude of the voltage applied to different cell layers during operation to vary based on the cell characteristics of each layer.

[0057] Additionally, for example, the control logic circuit 170 can control the timing and / or duration of voltage application to be different for operations on different cell layers, based on the specific cell characteristics of each layer.

[0058] Therefore, the storage device 100 according to one or more embodiments can compensate for the differences in characteristics of each of the plurality of cell layers CL1 to CLn.

[0059] Figure 2 This is a diagram illustrating the configuration of a storage device comprising multiple unit layers according to one or more embodiments.

[0060] refer to Figure 2 The storage device 100A according to one or more embodiments may include a first cell layer CL1 to a fourth cell layer CL4 and a peripheral circuit layer PCL.

[0061] Figure 2 The storage device 100A shown can be understood as Figure 1 An example of the storage device 100 shown. Therefore, identical or substantially identical parts are indicated by the same reference numerals, and redundant descriptions will be omitted to avoid repetition.

[0062] The storage device 100A may include a peripheral circuit layer PCL, a first cell layer CL1, a second cell layer CL2, a third cell layer CL3, and a fourth cell layer CL4 stacked in the vertical direction (e.g., the Z direction).

[0063] According to one or more implementations, the peripheral circuit layer PCL may include Figure 1 120.

[0064] For example, the peripheral circuit layer (PCL) may include the row decoder region (DEC), the page buffer region (PBA), and other circuit regions (OCA). Figure 1 The address decoder 130 can be set in the line decoder area DEC. Figure 1 The page buffer circuit 140 can be set in the page buffer area PBA. Figure 1 The control logic circuit 170, input / output circuit 150, and / or voltage generator 160 can be located in other circuit areas.

[0065] Each of the first unit layer CL1 to the fourth unit layer CL4 may include a storage unit area MCA. Figure 1 At least a portion of the storage cell array 110 may be disposed in the storage cell region MCA of each of the first cell layer CL1 to the fourth cell layer CL4.

[0066] According to one or more embodiments, the peripheral circuit layer PCL and the first unit layers CL1 to the fourth unit layers CL4 can be connected to each other by a bonding method.

[0067] For example, the peripheral circuit layer PCL and the first unit layers CL1 to the fourth unit layers CL4 can be manufactured using different wafers and then bonded together.

[0068] For example, the first unit layer CL1 and the second unit layer CL2 can be manufactured using different wafers and then bonded together. The third unit layer CL3 and the fourth unit layer CL4 can be manufactured using different wafers and then bonded together. Structures combining the first unit layer CL1 and the second unit layer CL2, as well as structures combining the third unit layer CL3 and the fourth unit layer CL4, can be bonded together.

[0069] The peripheral circuit layer PCL can be bonded to a structure combining the first cell layers CL1 to the fourth cell layers CL4. Therefore, the peripheral circuit layer PCL can be connected to multiple memory cells included in the first cell layers CL1 to the fourth cell layers CL4.

[0070] According to one or more other embodiments, the third unit layer CL3 and the fourth unit layer CL4 may be omitted. For example, the peripheral circuit layer PCL may be connected to the first unit layer CL1 and the second unit layer CL2 that are bonded to each other.

[0071] According to one or more embodiments, the control logic circuit 170 can perform core operations on two adjacent cell layers formed among the stacked first cell layers CL1 to fourth cell layers CL4.

[0072] For example, the control logic circuit 170 can perform core operations on the first cell layer CL1 and the second cell layer CL2 that are stacked adjacent to each other in the stacked first cell layer CL1 to the fourth cell layer CL4.

[0073] The control logic circuit 170 can perform core operations on the first cell layer CL1 through the first page buffer PB1. Additionally, the control logic circuit 170 can perform core operations on the second cell layer CL2 through the second page buffer PB2.

[0074] Referring to the above configuration, the control logic circuit 170, according to one or more embodiments, can perform core operations on two stacked cell layers CL1 and CL2 using different page buffers PB1 and PB2.

[0075] Each of the page buffers PB1 to PBn can be connected to a corresponding number of storage units within each cell layer, defined by a specified page size (e.g., 8KB) or the number of storage units.

[0076] Therefore, the memory device 100A according to one or more embodiments can increase the page size controlled by the core operation of two cell layers CL1 and CL2 stacked adjacent to the peripheral circuit layer PCL.

[0077] Storage cells located in different cell layers can have different cell characteristics.

[0078] For example, memory cells located in the first cell layer CL1 and memory cells located in the third cell layer CL3 can have different cell characteristics. For example, the core operating speed of memory cells located in the first cell layer CL1 and the core operating speed of memory cells located in the third cell layer CL3 can be different from each other.

[0079] For example, the length of the word line connecting the memory cell in the second cell layer CL2 to the address decoder 130 in the peripheral circuit layer PCL can be different from the length of the word line connecting the memory cell in the fourth cell layer CL4 to the address decoder 130. For example, the difference in word line length may lead to a change in load characteristics.

[0080] According to one or more embodiments, the control logic circuit 170 can control the voltage applied to each cell layer during operation based on the characteristics of each cell layer to compensate for such differences in the characteristics of each cell layer.

[0081] Therefore, the differences in characteristics of memory cells formed on different cell layers can be compensated, thereby improving the reliability of the core operation of the memory device 100A.

[0082] Figure 3 It is a cross-sectional view of a storage device according to one or more embodiments. Figure 4A It is a circuit diagram of a storage device according to one or more embodiments. Figure 4B It is a circuit diagram of a storage device according to one or more embodiments. Figure 4C It is a circuit diagram of a storage device according to one or more embodiments. Figure 5 It is a circuit diagram of the first series according to one or more implementation methods. Figure 6 It is a circuit diagram of a transmission transistor circuit connected between multiple word lines and a voltage generator according to one or more embodiments.

[0083] refer to Figure 3 and Figure 4A The storage device 100A according to one or more embodiments may include a peripheral circuit layer PCL, a first unit layer CL1, a second unit layer CL2, a third unit layer CL3, and a fourth unit layer CL4.

[0084] Figure 3 and Figure 4A The storage device 100A shown can be understood as Figure 1 An example of the storage device 100 shown. Therefore, identical or substantially identical parts are indicated by the same reference numerals, and redundant descriptions will be omitted to avoid repetition.

[0085] For example, the storage device 100A may include a peripheral circuit layer PCL, a first cell layer CL1, a second cell layer CL2, a third cell layer CL3, and a fourth cell layer CL4 stacked on top of each other.

[0086] The peripheral circuit layer PCL may include Figure 1 The peripheral circuitry 120. The peripheral circuitry layer PCL may include a transmission transistor circuit PTC, a first page buffer PB1, and a second page buffer PB2.

[0087] The transmission transistor circuit PTC can be included. Figure 1 The address decoder 130 contains the first page buffer PB1 and the second page buffer PB2. Figure 1In the page buffer circuit 140. For example, the peripheral circuit layer PCL can be called the peripheral circuit region PERI.

[0088] The peripheral circuit layer PCL and the first unit layer CL1 can be connected to each other by a bonding method.

[0089] The storage device 100A may include a first cell layer CL1 to a fourth cell layer CL4 stacked on a peripheral circuit layer PCL along a first direction (e.g., the Y direction). Each of the first cell layer CL1 to the fourth cell layer CL4 may include a plurality of storage cells.

[0090] For example, storage device 100A may include a first cell layer CL1 stacked on the peripheral circuit layer PCL.

[0091] For example, the first unit layer CL1 may include multiple first word lines WL1 and first string selection lines SSL0 stacked in a first direction (e.g., the Y direction).

[0092] Multiple first word lines WL1 and first string selection lines SSL0 can each have a shape that extends in a second direction (e.g., the X direction).

[0093] Furthermore, the multiple first word lines WL1 and the first selection line SSL0 can have shapes extending in a second direction (e.g., the X direction) with different lengths. For example, compared to the (1-1)th word line WL11 (also referred to as the first word line in the first group of word lines), the first selection line SSL0 can extend in the second direction (e.g., the X direction) with a relatively shorter length. Similarly, compared to the (1-4)th word line WL14 (also referred to as the fourth word line in the first group of word lines), the (1-1)th word line WL11 can extend in the second direction (e.g., the X direction) with a relatively shorter length.

[0094] Furthermore, multiple first word lines WL1 can be connected to the transmission transistor circuit PTC of the peripheral circuit layer PCL. For example, the (1-1)th word line WL11 can be connected to the transmission transistor circuit PTC through the first metal contact MC1.

[0095] The first unit layer CL1 may include a plurality of first strings ST1 extending in a first direction (e.g., the Y direction) that is substantially perpendicular to the plurality of first word lines WL1.

[0096] Multiple first strings ST1 can extend along a first direction (e.g., the Y direction) on the first substrate 311 and the common source line 330.

[0097] According to one or more embodiments, among a plurality of first strings ST1, the first string ST1 can be connected to the first page buffer PB1 via a first metal wiring 321. Therefore, the first metal wiring 321 can be referred to as the first bit line BL1 connected to the first string ST1.

[0098] refer to Figure 5 According to one or more embodiments, the first string ST1 may include a plurality of transistors connected in series between the first bit line BL1 and the common source line CSL.

[0099] For example, the first string ST1 may include a first string select transistor SST1 connected to the first bit line BL1. The first string select transistor SST1 may operate based on a signal applied through the first string select line SSL0.

[0100] Furthermore, the first string ST1 may include a first ground selection transistor GST1 connected to the common source line CSL. The first ground selection transistor GST1 may operate based on a signal applied through the first ground selection line GSL0.

[0101] Furthermore, the first string ST1 may include a plurality of first memory cells MC11 to MC14 connected in series between the first string selection transistor SST1 and the first ground selection transistor GST1. The transistors corresponding to the plurality of first memory cells MC11 to MC14 may be operated based on signals applied through word lines (1-1) WL11 to (1-4) WL14.

[0102] In addition, the storage device 100A may include a second cell layer CL2 stacked on the first cell layer CL1.

[0103] According to one or more embodiments, the second unit layer CL2 may have substantially the same shape as a mirror image of the first unit layer CL1 relative to the virtual line A extending in a second direction (e.g., the X direction).

[0104] For example, the second unit layer CL2 may include multiple second word lines WL2 and a first selection line SSL0, each of which extends in a second direction (e.g., the X direction).

[0105] Multiple second word lines WL2 and first selection line SSL0 can have shapes that extend in a second direction (e.g., the X direction) with different lengths. For example, compared to word line (2-4) WL24, word line (2-1) WL21 can extend in a second direction (e.g., the X direction) with a relatively shorter length.

[0106] In addition, multiple second word lines WL2 can be connected to the transmission transistor circuit PTC in the peripheral circuit layer PCL.

[0107] For example, word line (2-1) WL21 can be connected to the transmission transistor circuit PTC via the first metal contact MC1 and the second metal contact MC2. The first metal contact MC1 and the second metal contact MC2 can be electrically connected to each other via the bonding structure between the first unit layer CL1 and the second unit layer CL2.

[0108] The second unit layer CL2 may include a plurality of second strings ST2 extending in a first direction (e.g., the Y direction) substantially perpendicular to the plurality of second word lines WL2.

[0109] Multiple second strings ST2 can extend from the second substrate 312 and the common source line 330 in the opposite direction to the first direction (e.g., the Y direction).

[0110] According to one or more embodiments, in a plurality of second strings ST2, the second string ST2 can be connected to the second page buffer PB2 via a second metal wiring 322. Therefore, the second metal wiring 322 can be referred to as the second bit line BL2 connected to the second string ST2.

[0111] The second string ST2 can have the same... Figure 5 The first string ST1 shown has a substantially the same shape. For example, the second string ST2 may include multiple transistors (or memory cells) connected in series between the second bit line BL2 and the common source line CSL.

[0112] In addition, the storage device 100A may include a third cell layer CL3 stacked on the second cell layer CL2.

[0113] According to one or more embodiments, the third unit layer CL3 may have substantially the same shape as a mirror image of the second unit layer CL2 relative to the virtual line B extending in a second direction (e.g., the X direction).

[0114] For example, the third unit layer CL3 may include multiple third word lines WL3 and a second selection line SSL1, each of which extends in a second direction (e.g., the X direction).

[0115] Multiple third word lines WL3 and second selection lines SSL1 can have shapes that extend in a second direction (e.g., the X direction) with different lengths. For example, compared to the (3-4) word line WL34, the (3-1) word line WL31 can extend in a second direction (e.g., the X direction) with a relatively shorter length.

[0116] In addition, multiple third word lines WL3 can be connected to the transmission transistor circuit PTC of the peripheral circuit layer PCL.

[0117] For example, word line (3-1) WL31 can be connected to the transmission transistor circuit PTC via the first metal contact MC1, the second metal contact MC2, and the third metal contact MC3. The first metal contact MC1 to the third metal contact MC3 can be electrically connected to each other through a bonding structure formed from the first unit layer CL1 to the third unit layer CL3.

[0118] The third unit layer CL3 may include a plurality of third strings ST3 extending in a first direction (e.g., the Y direction) substantially perpendicular to the plurality of third word lines WL3.

[0119] Multiple third strings T3 can extend from the third substrate 313 and the common source line 330 in a first direction (e.g., the Y direction).

[0120] According to one or more embodiments, among a plurality of third strings ST3, the third string ST3 can be connected to the first page buffer PB1 via a third metal wiring 323. Therefore, the third metal wiring 323 can be referred to as the third bit line BL3 connected to the third string ST3.

[0121] The third string ST3 can have the same... Figure 5 The first string ST1 shown has essentially the same configuration. For example, the third string ST3 may include multiple transistors or memory cells connected in series between the third bit line BL3 and the common source line CSL.

[0122] In addition, the storage device 100A may include a fourth unit layer CL4 stacked on the third unit layer CL3.

[0123] According to one or more embodiments, the fourth unit layer CL4 may have substantially the same shape as a mirror image of the third unit layer CL3 relative to the virtual line C extending in a second direction (e.g., the X direction).

[0124] For example, the fourth unit layer CL4 may include multiple fourth word lines WL4 and a second selection line SSL1, each of which extends in a second direction (e.g., the X direction).

[0125] Multiple fourth word lines WL4 and second selection lines SSL1 can have shapes that extend in a second direction (e.g., the X direction) with different lengths. For example, compared to the (4-4) word line WL44, the (4-1) word line WL41 can extend in a second direction (e.g., the X direction) with a relatively shorter length.

[0126] In addition, multiple fourth word lines WL4 can be connected to the transmission transistor circuit PTC of the peripheral circuit layer PCL.

[0127] For example, word line (4-1) WL41 can be connected to the transmission transistor circuit PTC via the first metal contact MC1, the second metal contact MC2, the third metal contact MC3, and the fourth metal contact MC4. The first metal contact MC1 to the fourth metal contact MC4 can be electrically connected to each other through a bonding structure formed from the first unit layer CL1 to the fourth unit layer CL4.

[0128] The fourth unit layer CL4 may include multiple fourth strings ST4 extending in a first direction (e.g., the Y direction) substantially perpendicular to the multiple fourth word lines WL4.

[0129] Multiple fourth strings of ST4 can extend from the fourth substrate 314 and the common source line 330 in the opposite direction to the first direction (e.g., the Y direction).

[0130] According to one or more embodiments, among a plurality of fourth strings ST4, the fourth string ST4 can be connected to the second page buffer PB2 via a fourth metal wiring 324. Therefore, the fourth metal wiring 324 can be referred to as the fourth bit line BL4 connected to the fourth string ST4.

[0131] The fourth string ST4 can have the same as Figure 5 The first string ST1 shown has essentially the same configuration. For example, the fourth string ST4 may include multiple transistors (or memory cells) connected in series between the fourth bit line BL4 and the common source line CSL.

[0132] Although each of the cell layers CL1, CL2, CL3, and CL4 is described as including four word lines, this is only an example, and the number of word lines included in each cell layer is not limited to this.

[0133] According to one or more embodiments, at least a portion of the common source line 330 included in each of the first unit layer CL1 to the fourth unit layer CL4 can be implemented as a single wiring. For example, the common source line 330 included in the second unit layer CL2 and the third unit layer CL3 can be implemented as a single wiring.

[0134] Additionally, refer to Figure 4A The common source line 330 included in each of the first unit layer CL1 to the fourth unit layer CL4 can be connected to the common source line driver CSL_DRV.

[0135] refer to Figure 3 and Figure 4A According to one or more embodiments, the first page buffer PB1 can be connected to the first string ST1 and the third string ST3.

[0136] For example, the first page buffer PB1 can be connected to the first string ST1 of the first cell layer CL1 via the first metal wiring 321 (or the first bit line BL1). In addition, the first page buffer PB1 can be connected to the third string ST3 of the third cell layer CL3 via the third metal wiring 323 (or the third bit line).

[0137] In addition, the second page buffer PB2 can be connected to the second string ST2 and the fourth string ST4.

[0138] For example, the second page buffer PB2 can be connected to the second string ST2 of the second cell layer CL2 via the second metal wiring 322 (or the second bit line). Furthermore, the second page buffer PB2 can be connected to the fourth string ST4 of the fourth cell layer CL4 via the fourth metal wiring 324 (or the fourth bit line).

[0139] According to one or more embodiments, the control logic circuit 170 can control the first page buffer PB1 to perform core operations on the first cell layer CL1 and / or the third cell layer CL3.

[0140] For example, during core operations on the first unit layer CL1, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the first string ST1 through the first bit line BL1 (or the first metal wiring 321).

[0141] Additionally, during core operations on the third unit layer CL3, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the third string ST3 through the third metal wiring 323 (or the third bit line).

[0142] According to one or more embodiments, the control logic circuit 170 can control the second page buffer PB2 to perform core operations on the second cell layer CL2 and / or the fourth cell layer CL4.

[0143] For example, during core operations on the second unit layer CL2, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 through the second metal wiring 322 (or the second bit line).

[0144] Additionally, during core operations on the fourth unit layer CL4, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the fourth string ST4 through the fourth metal wiring 324 (or the fourth bit line).

[0145] According to one or more embodiments, the control logic circuit 170 may use the first page buffer PB1 and the second page buffer PB2 to perform core operations on the first cell layer CL1 and the second cell layer CL2.

[0146] For example, control logic circuit 170 can control the first page buffer PB1 to apply voltage to the first string ST1 to perform core operations on the first cell layer CL1.

[0147] Additionally, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 to perform core operations on the second cell layer CL2.

[0148] For example, when a core operation is requested on a structure including a first unit layer CL1 and a second unit layer CL2, the control logic circuit 170 according to one or more embodiments may use a first page buffer PB1 and a second page buffer PB2 to perform the core operation.

[0149] Furthermore, when a core operation is requested on a structure including the third unit layer CL3 and the fourth unit layer CL4, the control logic circuit 170 according to one or more embodiments may use the first page buffer PB1 and the second page buffer PB2 to perform the core operation.

[0150] Each of the page buffers PB1 to PBn can be connected to a corresponding number of storage units within each cell layer, defined by a specified page size (e.g., 8KB) or the number of storage units.

[0151] For example, the first page buffer PB1 can be connected to a memory cell in the first cell layer CL1 corresponding to a specified page size. Similarly, the second page buffer PB2 can be connected to a memory cell in the second cell layer CL2 corresponding to a specified page size.

[0152] Therefore, the storage device 100A according to one or more embodiments can increase the page size controlled during core operation of two adjacent stacked cell layers CL1 and CL2 and CL3 and CL4.

[0153] refer to Figure 4B The first string ST1 and the second string ST2 included in the storage device 100A1 according to one or more embodiments can be connected to the first source select line SSL0. Figure 4B The storage device 100A1 shown can be understood as Figure 4A An example of the storage device 100A shown.

[0154] For example, the first ST1 and the second ST2 can be connected to the first source select line SSL0 via a single node. Alternatively, the first ST1 and the second ST2 can be connected to the first source select line SSL0 via a single metal wire (or contact).

[0155] Furthermore, according to one or more embodiments, the first string ST1 and the second string ST2 can be connected to the first ground selection line GSL0 via a single node. For example, the first string ST1 and the second string ST2 can be connected to the first ground selection line GSL0 via a single metal wire (or contact).

[0156] Furthermore, the third string ST3 and the fourth string ST4, according to one or more embodiments, can be connected to the second source selection line SSL1.

[0157] For example, the third ST3 and the fourth ST4 can be connected to the second source select line SSL1 via a single node. Alternatively, the third ST3 and the fourth ST4 can be connected to the second source select line SSL1 via a single metal wire (or contact).

[0158] Furthermore, the third string ST3 and the fourth string ST4 according to one or more embodiments can be connected to the second ground selection line GSL1 via a single node. For example, the third string ST3 and the fourth string ST4 can be connected to the second ground selection line GSL1 via a single metal wiring (or contact).

[0159] refer to Figure 4C The first string ST1 and the second string ST2 included in the storage device 100A2 can be connected to the first common source line CSL1. Figure 4C The storage device 100A2 shown can be understood as Figure 4A An example of the storage device 100A shown.

[0160] For example, the first string ST1 and the second string ST2 can be connected to the first common source line CSL1 through a single node. For example, the first string ST1 and the second string ST2 can be connected to the first common source line CSL1 via a single metal wire (or contact).

[0161] The first string ST1 and the second string ST2 can be connected to the first common source driver CSL_DRV1 via the first common source line CSL1.

[0162] Furthermore, the third string ST3 and the fourth string ST4, according to one or more embodiments, can be connected to the second common source line CSL2.

[0163] For example, the third string ST3 and the fourth string ST4 can be connected to the second common source line CSL2 via a single node. Alternatively, the third string ST3 and the fourth string ST4 can be connected to the second common source line CSL2 via a single metal wire (or contact).

[0164] The third string ST3 and the fourth string ST4 can be connected to the second common source driver CSL_DRV2 via the second common source line CSL2.

[0165] Referring to the above configuration, the control logic circuit 170 can independently control the first common source line CSL1 and the second common source line CSL2 using separate common source line drivers CSL_DRV1 and CSL_DRV2.

[0166] For example, the control logic circuit 170 according to one or more embodiments may use separate common source line drivers CSL_DRV1 and CSL_DRV2 to independently control the common source line voltage for the first string ST1 and the second string ST2, as well as the common source line voltage for the third string ST3 and the fourth string ST4.

[0167] Additionally, refer to Figure 6 According to one or more embodiments, a transfer transistor circuit PTC may include a plurality of transfer transistors PT11 to PT44 connected to multiple word lines included in each cell layer.

[0168] The transfer transistor circuit PTC may include switching circuits SW1 to SW4 connected to at least a portion of the plurality of transfer transistors PT11 to PT44. Optionally, the switching circuits SW1 to SW4 may be configured as a single circuit comprising a single set of switches, but one or more embodiments are not limited thereto.

[0169] The transfer transistor circuit PTC may include a (1-1) transfer transistor PT11 (also referred to as the first transfer transistor of the first group of transfer transistors), one end of which is connected to the (1-1) word line WL11 (also referred to as the first word line of the first group of word lines). The transfer transistor PTC may also include: a (2-1) transfer transistor PT21 (also referred to as the first transfer transistor of the second group of transfer transistors), one end of which is connected to the (2-1) word line WL21 (also referred to as the first word line of the second group of word lines); a (3-1) transfer transistor PT31 (also referred to as the first transfer transistor of the third group of transfer transistors), one end of which is connected to the (3-1) word line WL31 (also referred to as the first word line of the third group of word lines); and a (4-1) transfer transistor PT41 (also referred to as the first transfer transistor of the fourth group of transfer transistors), one end of which is connected to the (4-1) word line WL41 (also referred to as the first word line of the fourth group of word lines). The transfer transistor circuit PTC may also include a first switching circuit SW1, which is connected to the (1-1)th transfer transistor PT11 (also known as the first transfer transistor of the first group of transfer transistors) to the (4-1)th transfer transistor PT41 (also known as the first transfer transistor of the fourth group of transfer transistors). Although in Figure 6 The diagram shows four different transmission transistors PT11, PT21, PT31, and PT41 that can be connected to word lines WL11, WL21, WL31, and WL41, respectively, but this disclosure is not limited thereto. For example, in another embodiment, a single transmission transistor (e.g., which may be referred to as "first transmission transistor PT1") can be connected to word lines WL11, WL21, WL31, and WL41. In this case, the first switching circuit SW1 can be omitted or retained. That is, in embodiments of this disclosure, multiple transmission transistors can be connected to corresponding word lines in each group of word lines, or a single transmission transistor can be connected to a corresponding word line in each group of word lines.

[0170] The other ends of the (1-1) transmission transistor PT11 to the (4-1) transmission transistor PT41 can be connected to the first line RL1 via the first switching circuit SW1.

[0171] Therefore, the control logic circuit 170 according to one or more embodiments can control the first switching circuit SW1 to control the voltage applied to the (1-1) transfer transistor PT11 to the (4-1) transfer transistor PT41.

[0172] For example, control logic circuit 170 can control the first switching circuit SW1 to apply the voltage transmitted from the first row line RL1 to at least one of the (1-1) transmission transistors PT11 to (4-1) transmission transistors PT41.

[0173] For example, according to one or more embodiments, the control logic circuit 170 can control the first switching circuit SW1 to apply a voltage (e.g., via voltage) for core operation to one of the (1-1) word lines WL11 to (1-4) word lines WL14.

[0174] The transmission transistor circuit PTC may include a (1-4) transmission transistor PT14, one end of which is connected to word line WL14. The transmission transistor PTC may include a (2-4) transmission transistor PT24 connected to word line WL24, a (3-4) transmission transistor PT34 connected to word line WL34, and a (4-4) transmission transistor PT44 connected to word line WL44. Furthermore, the transmission transistor circuit PTC may include a fourth switching circuit SW4 connected to the other ends of transmission transistors PT14 through PT44.

[0175] The other end of the (1-4) transmission transistor PT14 to the (4-4) transmission transistor PT44 can be connected to the fourth line RL4 through the fourth switching circuit SW4.

[0176] Therefore, the control logic circuit 170 according to one or more embodiments can control the fourth switching circuit SW4 to control the voltage applied to the (4-1) transfer transistor PT41 to the (4-4) transfer transistor PT44.

[0177] For example, control logic circuit 170 can control the fourth switch circuit SW4 to apply the voltage transmitted from the fourth row line RL4 to at least one of the (4-1) transmission transistors PT41 to (4-4) transmission transistors PT44.

[0178] For example, according to one or more embodiments, the control logic circuit 170 can control the fourth switching circuit SW4 to apply a voltage (e.g., via voltage) for core operation to one of the (4-1) word lines WL41 to (4-4) word lines WL44.

[0179] The gate electrodes of multiple transmission transistors PT11 to PT44 can be connected to the block word line BLKWL1.

[0180] For example, the (1-1) transmission transistor (PT11) can respond to the voltage level of the block word line BLKWL1 by providing the voltage received from the voltage generator 160 via the first row line RL1 to the (1-1) word line WL11.

[0181] Referring to the above configuration, the corresponding word lines in the first unit layer CL1 to the fourth unit layer CL4 can be driven simultaneously by voltage transmitted from the same row line.

[0182] Therefore, compared to the configuration where row lines are respectively connected to word lines from the first unit layer CL1 to the fourth unit layer CL4, the transmission transistor circuit PTC according to one or more embodiments can be implemented with a relatively smaller area.

[0183] Therefore, the storage device 100A according to one or more embodiments may have a relatively smaller area.

[0184] Figure 7 This is a graph illustrating the differences in programming speed between unit layers according to one or more implementations. Figure 8A This is a diagram illustrating a configuration for controlling the forced voltage based on the programming speed difference between the first and second unit layers, according to one or more embodiments. Figure 8B This is a diagram illustrating a configuration for controlling the forced voltage based on the programming speed difference between the third and fourth unit layers, according to one or more implementations.

[0185] refer to Figure 7 , Figure 8A and Figure 8B According to one or more implementations, the control logic circuit (170) can control the magnitude of the forced voltage VFBL applied through the bit line of each cell layer based on the characteristics of adjacent stacked cell layers.

[0186] For example, when adjacent stacked cell layers have different characteristics, the control logic circuit 170 can apply different sizes of forced voltage VFBL to each cell layer through different page buffers.

[0187] refer to Figure 7 The first unit layer CL1 and the second unit layer CL2 can exhibit different characteristics during programming operations.

[0188] For example, memory cells in the first cell layer CL1 can be programmed earlier than memory cells in the second cell layer CL2. For example, the programming speed of memory cells in the first cell layer CL1 can be higher than the programming speed of memory cells in the second cell layer CL2.

[0189] Furthermore, the change in the threshold voltage of a memory cell in the first cell layer CL1, based on the programming voltage, can be greater than the change in the threshold voltage of a memory cell in the second cell layer CL2. This "threshold voltage change" can also be referred to as the "magnitude of the threshold voltage offset" of the memory cell. For example, when the same programming voltage is applied to the first cell layer CL1 and the second cell layer CL2, the change in the threshold voltage of a memory cell in the first cell layer CL1 can be greater than the change in the threshold voltage of a memory cell in the second cell layer CL2.

[0190] refer to Figure 7 and Figure 8A According to one or more embodiments, the control logic circuit 170 can apply a first forced voltage VBL1 to the first cell layer CL1 through the first page buffer PB1.

[0191] For example, control logic circuit 170 can apply a first forced voltage VBL1 to the first cell layer CL1, which exhibits a relatively large variation in threshold voltage based on the programming voltage, via the first bit line BL1 connected to the first page buffer PB1 (e.g., control logic circuit 170 can control the first page buffer PB1 to apply the first forced voltage VBL1 to the first bit line of the first string of the first cell layer CL1). Therefore, control logic circuit 170 can reduce the variation in threshold voltage based on the programming voltage of the memory cells in the first cell layer CL1.

[0192] Additionally, the control logic circuit 170 can apply a second forced voltage VBL2, which is less than the first forced voltage VBL1, to the second cell layer CL2 via the second page buffer PB2 (for example, the control logic circuit 170 can control the second page buffer PB2 to apply the second forced voltage VBL2 to the second bit line of the second string of the second cell layer CL2).

[0193] For example, control logic circuit 170 can apply a second forced voltage VBL2, which is relatively smaller than the first forced voltage VBL1, to the second cell layer CL2, which exhibits a relatively small change in threshold voltage according to the programming voltage, by connecting a second bit line to the second page buffer PB2.

[0194] Therefore, the control logic circuit 170 can reduce the change in the threshold voltage of the memory cells in the second cell layer CL2 based on the programming voltage, thereby reducing the difference between the change in the threshold voltage of the memory cells in the second cell layer CL2 and the change in the threshold voltage of the memory cells in the first cell layer CL1.

[0195] According to the above configuration, the control logic circuit 170 according to one or more embodiments can compensate for the characteristic differences (e.g., programming speed) between the first unit layer CL1 and the second unit layer CL2.

[0196] refer to Figure 7 The characteristics of the third unit layer CL3 and the fourth unit layer CL4 can differ during programming operations.

[0197] For example, memory cells in the third unit layer CL3 can be programmed earlier than memory cells in the fourth unit layer CL4. For example, the programming speed of memory cells in the third unit layer CL3 can be higher than the programming speed of memory cells in the fourth unit layer CL4.

[0198] Furthermore, the threshold voltage change of the memory cells in the third cell layer CL3, based on the programming voltage, can be relatively greater than the threshold voltage change of the memory cells in the fourth cell layer CL4. For example, when the same programming voltage is applied to both the third cell layer CL3 and the fourth cell layer CL4, the threshold voltage change of the memory cells in the third cell layer CL3 can be greater than the threshold voltage change of the memory cells in the fourth cell layer CL4.

[0199] refer to Figure 7 and Figure 8B According to one or more embodiments, the control logic circuit 170 can apply a third forced voltage VBL3 to the third cell layer CL3 through the first page buffer PB1.

[0200] For example, control logic circuit 170 can apply a third forced voltage VBL3 to the third cell layer CL, which exhibits a relatively large variation in threshold voltage based on the programming voltage, via the first bit line BL1 connected to the first page buffer PB1. Therefore, control logic circuit 170 can reduce the variation in threshold voltage based on the programming voltage for the memory cells in the third cell layer CL3.

[0201] In addition, the control logic circuit 170 can apply a fourth forced voltage VBL4, which is less than the third forced voltage VBL3, to the fourth cell layer CL4 through the second page buffer PB2.

[0202] For example, control logic circuit 170 can apply a fourth forced voltage VBL4, which is less than the third forced voltage VBL3, to the fourth cell layer CL4, which exhibits relatively small changes in threshold voltage according to the programmed voltage, by connecting a second bit line to the second page buffer PB2.

[0203] Therefore, the control logic circuit 170 can reduce the change in the threshold voltage of the memory cells in the fourth unit layer CL4 based on the programming voltage, thereby reducing the difference between the change in the threshold voltage of the memory cells in the fourth unit layer CL4 and the change in the threshold voltage of the memory cells in the third unit layer CL3.

[0204] According to the above configuration, the control logic circuit 170 according to one or more embodiments can compensate for the characteristic differences (e.g., programming speed) between the third unit layer CL3 and the fourth unit layer CL4.

[0205] Despite Figures 7 to 8B The different characteristics between unit layers have been described in terms of programming speed, but the characteristics are not limited to this and may include other characteristics exhibited in various operations, such as reading voltage output.

[0206] For example, compared to the bit line voltage applied during a read operation on the first cell layer CL1 (or the first string ST1), the control logic circuit 170 can apply a relatively higher bit line voltage during a read operation on the second cell layer CL2 (or the second string ST2), which has a larger resistance.

[0207] Referring to the above configuration, when adjacent stacked cell layers exhibit different characteristics, the control logic circuit 170, according to one or more embodiments, can control the magnitude of the forced voltage VFBL applied through the bit lines of each cell layer to be different. Therefore, the control logic circuit 170 can compensate for the characteristic differences between stacked cell layers.

[0208] With the above configuration, the storage device 100 according to one or more embodiments can improve the reliability of core operations.

[0209] Furthermore, the storage device 100 can control the voltage applied to the bit lines to compensate for characteristic differences between stacked cell layers. Therefore, the storage device 100 can reduce the overhead necessary to mitigate such differences.

[0210] Figure 9 This is a graph illustrating the programming speed difference between the first unit layer and the third unit layer according to one or more embodiments. Figure 10 This is a diagram illustrating a configuration for controlling word line voltage based on the programming speed difference between the first and third cell layers, according to one or more embodiments.

[0211] refer to Figure 9 and Figure 10 According to one or more embodiments, the control logic circuit 170 can control the magnitude of the voltage applied to the word line of each cell layer based on the characteristics of the stacked cell layers.

[0212] For example, the control logic circuit 170 can control the magnitude of the voltage applied to the word line of each cell layer to be different based on the characteristics of two of the stacked cell layers CL1 to CL4.

[0213] refer to Figure 9 During programming operations, the characteristics of the first unit layer CL1 and the third unit layer CL3 can be different.

[0214] For example, memory cells in the first cell layer CL1 can be programmed earlier than memory cells in the third cell layer CL3. For example, the programming speed of memory cells in the first cell layer CL1 can be higher than the programming speed of memory cells in the third cell layer CL3.

[0215] Furthermore, the change in the threshold voltage of the memory cells in the first cell layer CL1, based on the programming voltage, can be greater than the change in the threshold voltage of the memory cells in the third cell layer CL3. For example, when the same programming voltage is applied to both the first cell layer CL1 and the third cell layer CL3, the change in the threshold voltage of the memory cells in the first cell layer CL1 can be greater than the change in the threshold voltage of the memory cells in the third cell layer CL3.

[0216] refer to Figure 9 and Figure 10 During the programming operation of the first unit layer CL1, the control logic circuit 170 according to one or more embodiments can apply a first programming voltage VPGM1 to the (1-1) word line WL11.

[0217] For example, during programming operations on the first cell layer CL1, the control logic circuit 170 can apply a string selection voltage VSSL via the first string selection line SSL0. The voltage of the second string selection line SSL1 can be set to ground GND. Therefore, the control logic circuit 170 can activate the first cell layer CL1 connected to the first string selection line SSL0.

[0218] Furthermore, the control logic circuit 170 can turn on the first transmission transistor PT1 connected to the (1-1) word line WL11 of the transmission transistor circuit PTC. For example, the control logic circuit 170 can apply a first pass voltage VPASS1 to the first transmission transistor PT1 to turn on the first transmission transistor PT1.

[0219] Additionally, the control logic circuit 170 can apply a first programming voltage VPGM1 to the (1-1) word line WL11. For example, the control logic circuit 170 can apply the first programming voltage VPGM1 to the (1-1) word line WL11 through the first transmission transistor PT1 and the first metal contact MC1.

[0220] Additionally, during programming operations on the third unit layer CL3, control logic circuit 170, according to one or more embodiments, can apply a second programming voltage VPGM2, which is greater than the first programming voltage VPGM1, to the (3-1) word line WL31.

[0221] For example, during programming operations on the third cell layer CL3, the control logic circuit 170 can apply a string selection voltage VSSL via the second string selection line SSL1. The voltage of the first string selection line SSL0 can be set to ground GND. Therefore, the control logic circuit 170 can activate the third cell layer CL3 connected to the second string selection line SSL1.

[0222] In addition, the control logic circuit 170 can turn on the first transmission transistor PT1 in the transmission transistor circuit PTC, which is connected to the (3-1) word line WL31.

[0223] For example, control logic circuit 170 can apply a second pass voltage VPASS2 to the first pass transistor PT1 to turn on the first pass transistor PT1. The second pass voltage VPASS2 can have a larger value than the first pass voltage VPASS1.

[0224] Additionally, the control logic circuit 170 can apply a second programming voltage VPGM2, which is greater than the first programming voltage VPGM1, to the (3-1) word line WL31. For example, the control logic circuit 170 can apply the second programming voltage VPGM2 to the (3-1) word line WL31 through the first transmission transistor PT1, the first metal contact MC1, the second metal contact MC2, and the third metal contact MC3.

[0225] For example, during programming operations on the third cell layer CL3 at a relatively low programming speed, the control logic circuit 170 according to one or more embodiments can apply a relatively high programming voltage (or voltage) through the word lines of the third cell layer CL3.

[0226] Therefore, the control logic circuit 170 can compensate for the difference in characteristics (e.g., programming speed) between the first unit layer CL1 and the third unit layer CL3.

[0227] According to one or more embodiments, during programming operations on the third cell layer CL3 at a relatively high programming speed, the control logic circuit 170 can apply the first programming voltage PGM1 to the third cell layer CL3 for a relatively longer period of time (compared to the time for applying the first programming voltage PGM1 to the first cell layer CL1). Therefore, the control logic circuit 170 can compensate for differences in characteristics (e.g., programming speed) between the first cell layer CL1 and the third cell layer CL3.

[0228] Despite Figures 9 to 10 The different characteristics between unit layers have been described in terms of programming speed, but the characteristics are not limited to this and may include other characteristics exhibited in various operations, such as reading voltage output.

[0229] For example, compared to the read voltage applied during a read operation on the first cell layer CL1 (or the first string ST1), the control logic circuit 170 can apply a relatively higher read voltage to the third cell layer CL3 (or the third string ST3), which is electrically farther away from the peripheral circuit layer (PCL).

[0230] Referring to the above configuration, when the stacked cell layers have different characteristics, the control logic circuit 170, according to one or more embodiments, can control the magnitude of the voltage (e.g., programming voltage) applied through the word lines of each cell layer to be different. Therefore, the control logic circuit 170 can compensate for the characteristic differences between multiple cell layers.

[0231] With the above configuration, the storage device 100 according to one or more embodiments can improve the reliability of core operations.

[0232] Figure 11AThis is a diagram illustrating the first leakage current leaking from the first cell layer to the common source line according to one or more embodiments. Figure 11B This is a diagram illustrating the second leakage current leaking to the common source line in the third cell layer according to one or more embodiments. Figure 12 This is a diagram illustrating a configuration for controlling the common source line voltage based on the difference in leakage current between the first and third cell layers, according to one or more embodiments.

[0233] refer to Figure 11A , Figure 11B and Figure 12 According to one or more embodiments, the control logic circuit 170 can control the magnitude of the common source line voltage VCSL applied through the common source line CSL during core operation of each cell layer based on the characteristics of the stacked cell layers.

[0234] refer to Figure 11A and Figure 11B According to one or more implementations, currents IL1 and IL2 that leak from multiple memory cells to the common source line CSL can be generated in series ST1 and ST3, respectively.

[0235] For example, during core operations on the first string ST1, a first leakage current IL1 can be generated that leaks from multiple first memory cells MC11 to MC14 to the common source line CSL.

[0236] During core operations on the third string ST3, a second leakage current IL2 can be generated, which leaks from multiple third memory cells MC31 to MC34 to the common source line CSL.

[0237] The second leakage current IL2 can have a larger value than the first leakage current IL1.

[0238] refer to Figure 11A , Figure 11B and Figure 12 According to one or more embodiments, the control logic circuit 170 can apply a first common source line voltage VCSL1 to the common source line CSL during core operation of the first unit layer CL1 (or the first string ST1).

[0239] Therefore, the control logic circuit 170 can reduce the voltage difference between the plurality of first memory cells MC11 to MC14 and the common source line CSL during the core operation of the first cell layer CL1 (or the first string ST1) to reduce the first leakage current IL1.

[0240] Additionally, according to one or more embodiments, the control logic circuit 170 may apply a second common source line voltage VCSL2, which is greater than the first common source line voltage VCSL1, to the common source line CSL during core operation of the third unit layer CL3 (or the third string ST3).

[0241] Therefore, the control logic circuit 170 can reduce the voltage difference between multiple third memory cells MC31 to MC34 and the common source line CSL during core operation of the third cell layer CL3 (or the third string ST3) to reduce the second leakage current IL2.

[0242] Referring to the above configuration, the control logic circuit 170 can apply a relatively large second common source line voltage VCSL2 during core operation of the third cell layer CL3 (or the third string ST3) which has a relatively large leakage current (e.g., the second leakage current IL2).

[0243] Using the above configuration, the control logic circuit 170 according to one or more embodiments can compensate for the difference in characteristics (e.g., the amount of leakage current) between the first unit layer CL1 and the third unit layer CL3.

[0244] Therefore, the storage device 100 according to one or more embodiments can improve the reliability of core operations.

[0245] Figure 13 It is a cross-sectional view of a storage device according to one or more embodiments.

[0246] refer to Figure 13 The storage device 100B according to one or more embodiments may include a peripheral circuit layer PCL and first unit layers CL1 to fourth unit layers CL4 stacked on top of each other.

[0247] According to one or more other embodiments, the third unit layer CL3 and the fourth unit layer CL4 may be omitted. For example, the peripheral circuit layer PCL may be connected to the first unit layer CL1 and the second unit layer CL2 that are bonded to each other.

[0248] Figure 13 The storage device 100B shown can be understood as Figure 1 An example of the storage device 100 shown. Additionally... Figure 13 The storage device 100B shown can have the same as Figure 3 The configuration of the storage device 100A shown is substantially the same as at least a portion of the configuration.

[0249] Therefore, identical or substantially identical parts are indicated by the same reference numerals, and redundant descriptions will be omitted to avoid repetition.

[0250] The storage device 100B may include a first cell layer CL1 stacked on the peripheral circuit layer PCL.

[0251] The first unit layer CL1 may include multiple first word lines WL1 and multiple first strings ST1 extending in a substantially perpendicular first direction (e.g., the Y direction).

[0252] According to one or more embodiments, the first string of ST1s among a plurality of first strings of ST1s can be connected to the first page buffer PB1 via the first metal wiring 321. Therefore, the first metal wiring 321 can be referred to as the first bit line BL1 connected to the first string of ST1s.

[0253] In addition, the storage device 100B may include a second cell layer CL2 stacked on the first cell layer CL1.

[0254] The second unit layer CL2 may include multiple second word lines WL2 and multiple second strings ST2 extending in a substantially perpendicular first direction (e.g., the Y direction).

[0255] According to one or more embodiments, a second string ST2 of a plurality of second strings ST2 can be connected to a second page buffer PB2 via a second metal wiring 322. Therefore, the second metal wiring 322 can be referred to as a second bit line connected to the second string ST2.

[0256] In addition, the storage device 100B may include a third cell layer CL3 stacked on the second cell layer CL2.

[0257] The third unit layer CL3 may include multiple third word lines WL3 and multiple third strings ST3 extending in a substantially perpendicular first direction (e.g., the Y direction).

[0258] According to one or more embodiments, the third string ST3 of a plurality of third strings ST3 can be connected to the second page buffer PB2 via a third metal wiring 323. Therefore, the third metal wiring 323 can be referred to as a third bit line connected to the third string ST3.

[0259] Furthermore, at least a portion of the common source line 330 included in each of the first unit layers CL1 to the fourth unit layers CL4 can be implemented as a single wiring. For example, the common source line 330 included in each of the second unit layers CL2 and the third unit layers CL3 can be implemented as a single wiring.

[0260] In addition, the storage device 100B may include a fourth unit layer CL4 stacked on the third unit layer CL3.

[0261] The fourth unit layer CL4 may include multiple fourth word lines WL4 and multiple fourth strings ST4 extending in a substantially perpendicular first direction (e.g., the Y direction).

[0262] According to one or more embodiments, the fourth string of ST4s can be connected to the first page buffer PB1 via the fourth metal wiring 324. Therefore, the fourth metal wiring 324 can be referred to as the fourth bit line connected to the fourth string of ST4s.

[0263] According to one or more implementations, the first page buffer PB1 can be connected to the first string ST1 and the fourth string ST4.

[0264] For example, the first page buffer PB1 can be connected to the first string ST1 of the first cell layer CL1 via the first metal wiring 321 (or the first bit line BL1). Furthermore, the first page buffer PB1 can be connected to the fourth string ST4 of the fourth cell layer CL4 via the fourth metal wiring 324 (or the fourth bit line).

[0265] In addition, the second page buffer PB2 can be connected to the second string ST2 and the third string ST3.

[0266] For example, the second page buffer PB2 can be connected to the second string ST2 of the second cell layer CL2 via the second metal wiring 322 (or the second bit line). Furthermore, the second page buffer PB2 can be connected to the third string ST3 of the third cell layer CL3 via the third metal wiring 323 (or the third bit line).

[0267] According to one or more embodiments, the control logic circuit 170 can control the first page buffer PB1 to perform core operations on the first cell layer CL1 and / or the fourth cell layer CL4.

[0268] For example, during core operations on the first unit layer CL1, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the first string ST1 through the first bit line BL1 (or the first metal wiring 321).

[0269] Additionally, during core operations on the fourth unit layer CL4, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the fourth string ST4 through the fourth metal wiring 324 (or the fourth bit line).

[0270] According to one or more embodiments, the control logic circuit 170 can control the second page buffer PB2 to perform core operations on the second cell layer CL2 and / or the third cell layer CL3.

[0271] For example, during core operations on the second unit layer CL2, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 through the second metal wiring 322 (or the second bit line).

[0272] Additionally, during core operations on the third unit layer CL3, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the third string ST3 through the third metal wiring 323 (or the third bit line).

[0273] According to one or more embodiments, the control logic circuit 170 may use the first page buffer PB1 and the second page buffer PB2 to perform core operations on the first cell layer CL1 and the second cell layer CL2.

[0274] For example, control logic circuit 170 can control the first page buffer PB1 to apply a voltage to the first string ST1 to perform core operations on the first cell layer CL1.

[0275] Additionally, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 in order to perform core operations on the second cell layer CL2.

[0276] For example, when a core operation is requested on a structure including a first unit layer CL1 and a second unit layer CL2, the control logic circuit 170 can use the first page buffer PB1 and the second page buffer PB2 to perform the core operation.

[0277] Furthermore, when a core operation is requested on a structure including the third unit layer CL3 and the fourth unit layer CL4, the control logic circuit 170 according to one or more embodiments may use the first page buffer PB1 and the second page buffer PB2 to perform the core operation.

[0278] Each of the first page buffer PB1 and the second page buffer PB2 can be connected to a specified number of storage units (e.g., 8KB) in each cell layer.

[0279] For example, the first page buffer PB1 can be connected to a memory cell in the first cell layer CL1 corresponding to a specified page size. Similarly, the second page buffer PB2 can be connected to a memory cell in the second cell layer CL2 corresponding to a specified page size.

[0280] Therefore, the memory device 100B according to one or more embodiments can increase the page size controlled by the core operation of two cell layers CL1 and CL2 stacked adjacent to the peripheral circuit layer PCL.

[0281] Figure 14 It is a cross-sectional view of a storage device comprising multiple stacked cell layers according to one or more embodiments.

[0282] refer to Figure 14 The storage device 100C according to one or more embodiments may include a peripheral circuit layer PCL and first unit layers CL1 to fourth unit layers CL4 stacked on top of each other.

[0283] Figure 14 The storage device 100C shown can be understood as Figure 1 An example of the storage device 100 shown. Additionally... Figure 14 The storage device 100C shown can have the same as Figure 3 The configuration of the storage device 100A shown is substantially the same as at least a portion of the configuration.

[0284] Therefore, identical or substantially identical parts are indicated by the same reference numerals, and redundant descriptions will be omitted to avoid repetition.

[0285] The storage device 100C may include a first cell layer CL1 stacked on the peripheral circuit layer PCL.

[0286] The first unit layer CL1 may include multiple first word lines WL1 and a first string select line SSL0 stacked along a first direction (e.g., the Y direction).

[0287] For example, the first unit layer CL1 may include a first string of select lines SSL0, a (1-1) word line WL11 (also known as the first word line of the first group of word lines), a (1-2) word line WL12 (also known as the second word line of the first group of word lines), a (1-3) word line WL13 (also known as the third word line of the first group of word lines), and a (1-4) word line WL14 (also known as the fourth word line of the first group of word lines) arranged in order adjacent to the peripheral circuit layer PCL.

[0288] For example, compared to word line (1-1) WL11, the first string select line SSL0 can be set to be relatively closer to the peripheral circuit layer PCL. Furthermore, compared to word line (1-4) WL14, word line (1-1) WL11 can be set to be closer to the peripheral circuit layer PCL.

[0289] For example, compared to the (1-4)th character line WL14, the (1-1)th character line WL11 can have a relatively smaller length and extend in a second direction (e.g., the X direction).

[0290] The first unit layer CL1 may include a first string ST1 extending from the first substrate 311 (or common source line 330) in the opposite direction to the first direction (e.g., the Y direction).

[0291] The first string ST1 can be connected to the first page buffer PB1 via the first metal wiring 321. Therefore, the first metal wiring 321 can be referred to as the first bit line BL1 connected to the first string ST1.

[0292] In addition, the storage device 100C may include a second cell layer CL2 stacked on the first cell layer CL1.

[0293] According to one or more embodiments, the second unit layer CL2 may have a shape substantially the same as the inverted shape of the first unit layer CL1 relative to the virtual line A extending in a second direction (e.g., the X direction).

[0294] The second unit layer CL2 may include multiple second word lines WL2 and a first string selection line SSL0 stacked in a first direction (e.g., the Y direction).

[0295] For example, the second unit layer CL2 may include the (2-4) word line WL24, the (2-3) word line WL23, the (2-2) word line WL22, the (2-1) word line WL21 and the first string selection line SSL0 arranged in the order adjacent to the first unit layer CL1.

[0296] For example, compared to the first selection line SSL0, the (2-1)th word line WL21 can be set to be relatively closer to the first unit layer CL1. Furthermore, compared to the (2-1)th word line WL21, the (2-4)th word line WL24 can be set to be closer to the first unit layer CL1.

[0297] Additionally, for example, compared to the (2-4)th character line WL24, the (2-1)th character line WL21 may have a relatively smaller length and extend in a second direction (e.g., the X direction).

[0298] The second unit layer CL2 may include a second string ST2 extending from the second substrate 312 (or common source line 330) along a first direction (e.g., the Y direction).

[0299] The second string ST2 can be connected to the second page buffer PB2 via the second metal wiring 322. Therefore, the second metal wiring 322 can be referred to as the second bit line connected to the second string ST2.

[0300] In addition, the storage device 100C may include a third cell layer CL3 stacked on the second cell layer CL2.

[0301] According to one or more embodiments, the third unit layer CL3 may have a shape substantially the same as the inverted shape of the second unit layer CL2 relative to the virtual line B extending in a second direction (e.g., the X direction).

[0302] The third unit layer CL3 may include multiple third word lines WL3 and a second selection line SSL1 stacked along a first direction (e.g., the Y direction).

[0303] For example, the third unit layer CL3 may include a second string of selection lines SSL1, the (3-1) word line WL31 (also known as the first word line of the third group of word lines), the (3-2) word line WL32 (also known as the second word line of the third group of word lines), the (3-3) word line WL33 (also known as the third word line of the third group of word lines), and the (3-4) word line WL34 (also known as the fourth word line of the third group of word lines) arranged in the order adjacent to the second unit layer CL2.

[0304] For example, compared to word line (3-1) WL31, the second string selection line SSL1 can be set relatively closer to the second unit layer CL2. Furthermore, compared to word line (3-4) WL34, word line (3-1) WL31 can be set closer to the second unit layer CL2.

[0305] For example, compared to the (3-4)th character line WL34, the (3-1)th character line WL31 can have a relatively smaller length and extend in a second direction (e.g., the X direction).

[0306] The third unit layer CL3 may include a third string ST3 extending from the third substrate 313 (or common source line 330) in the opposite direction to the first direction (e.g., the Y direction).

[0307] The third string ST3 can be connected to the first page buffer PB1 via the third metal wiring 323. Therefore, the third metal wiring 323 can be referred to as the third bit line connected to the third string ST3.

[0308] In addition, the storage device 100C may include a fourth unit layer CL4 stacked on the third unit layer CL3.

[0309] According to one or more embodiments, the fourth unit layer CL4 may have a shape substantially the same as the inverted shape of the third unit layer CL3 relative to the virtual line C extending in a second direction (e.g., the X direction).

[0310] The fourth unit layer CL4 may include multiple fourth word lines WL4 and a second selection line SSL1 stacked along a first direction (e.g., the Y direction).

[0311] For example, the fourth unit layer CL4 may include the (4-4) word line WL44 (also known as the fourth word line of the fourth group of word lines), the (4-3) word line WL43 (also known as the third word line of the fourth group of word lines), the (4-2) word line WL42 (also known as the second word line of the fourth group of word lines), the (4-1) word line WL41 (also known as the first word line of the fourth group of word lines), and the second string selection line SSL1, arranged in the order adjacent to the third unit layer CL3.

[0312] For example, compared to the second selection line SSL1, the (4-1) word line WL41 can be set relatively closer to the third unit layer CL3. Furthermore, compared to the (4-1) word line WL41, the (4-4) word line WL44 can be set closer to the third unit layer CL3.

[0313] Additionally, for example, compared to the (4-4)th character line WL44, the (4-1)th character line WL41 may have a relatively smaller length and extend in a second direction (e.g., the X direction).

[0314] The fourth unit layer CL4 may include a fourth string ST4 extending from the fourth substrate 314 (or common source line 330) along a first direction (e.g., the Y direction).

[0315] The fourth string ST4 can be connected to the second page buffer PB2 via the fourth metal wire 324. Therefore, the fourth metal wire 324 can be referred to as the fourth bit line connected to the fourth string ST4.

[0316] According to one or more implementations, the first page buffer PB1 can be connected to the first string ST1 and the third string ST3.

[0317] For example, the first page buffer PB1 can be connected to the first string ST1 of the first cell layer CL1 via the first metal wiring 321 (or the first bit line BL1). In addition, the first page buffer PB1 can be connected to the third string ST3 of the third cell layer CL3 via the third metal wiring 323 (or the third bit line).

[0318] In addition, the second page buffer PB2 can be connected to the second string ST2 and the fourth string ST4.

[0319] For example, the second page buffer PB2 can be connected to the second string ST2 of the second cell layer CL2 via the second metal wiring 322 (or the second bit line). Furthermore, the second page buffer PB2 can be connected to the fourth string ST4 of the fourth cell layer CL4 via the fourth metal wiring 324 (or the fourth bit line).

[0320] According to one or more embodiments, the control logic circuit 170 can control the first page buffer PB1 to perform core operations on the first cell layer CL1 and / or the third cell layer CL3.

[0321] For example, during core operations on the first unit layer CL1, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the first string ST1 through the first bit line BL1 (or the first metal wiring 321).

[0322] Additionally, during core operations on the third unit layer CL3, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the third string ST3 through the third metal wiring 323 (or the third bit line).

[0323] According to one or more embodiments, the control logic circuit 170 can control the second page buffer PB2 to perform core operations on the second cell layer CL2 and / or the fourth cell layer CL4.

[0324] For example, during core operations on the second unit layer CL2, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 through the second metal wiring 322 (or the second bit line).

[0325] Additionally, during core operations on the fourth unit layer CL4, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the fourth string ST4 through the fourth metal wiring 324 (or the fourth bit line).

[0326] According to one or more embodiments, the control logic circuit 170 may use the first page buffer PB1 and the second page buffer PB2 to perform core operations on the first cell layer CL1 and the second cell layer CL2.

[0327] For example, control logic circuit 170 can control the first page buffer PB1 to apply a voltage to the first string ST1 to perform core operations on the first cell layer CL1.

[0328] Additionally, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 in order to perform core operations on the second cell layer CL2.

[0329] For example, when a core operation is requested on a structure including a first unit layer CL1 and a second unit layer CL2, the control logic circuit 170 can use the first page buffer PB1 and the second page buffer PB2 to perform the core operation.

[0330] Furthermore, when a core operation is requested on a structure including the third unit layer CL3 and the fourth unit layer CL4, the control logic circuit 170 according to one or more other embodiments may use the first page buffer PB1 and the second page buffer PB2 to perform the core operation.

[0331] Each of the first page buffer PB1 and the second page buffer PB2 can be connected to a memory cell in each cell layer corresponding to a specified page size (e.g., 8KB) (or the number of memory cells).

[0332] For example, the first page buffer PB1 can be connected to a memory cell in the first cell layer CL1 corresponding to a specified page size. Similarly, the second page buffer PB2 can be connected to a memory cell in the second cell layer CL2 corresponding to a specified page size.

[0333] Therefore, the memory device 100C according to one or more embodiments can increase the page size controlled in the core operation of two cell layers CL1 and CL2 stacked adjacent to the peripheral circuit layer PCL.

[0334] Figure 15 It is a cross-sectional view of a storage device comprising multiple stacked cell layers according to one or more embodiments.

[0335] refer to Figure 15 The storage device 100D according to one or more embodiments may include a peripheral circuit layer PCL and a first cell layer CL1 to a fourth cell layer CL4 stacked on top of each other.

[0336] Figure 15 The storage device 100D shown can be understood as Figure 1 An example of the storage device 100 shown. Additionally... Figure 15 The storage device 100D shown can have the same as Figure 3 The configuration of the storage device 100A shown is substantially the same as at least a portion of the configuration.

[0337] Therefore, identical or substantially identical parts are indicated by the same reference numerals, and redundant descriptions will be omitted to avoid repetition.

[0338] The storage device 100D may include a first cell layer CL1 stacked on the peripheral circuit layer PCL.

[0339] The first unit layer CL1 may include multiple first word lines WL1 and a first string select line SSL0 stacked along a first direction (e.g., the Y direction).

[0340] For example, the first unit layer CL1 may include a first string of select lines SSL0, (1-1) word line WL11, (1-2) word line WL12, (1-3) word line WL13, and (1-4) word line WL14 arranged in order adjacent to the peripheral circuit layer PCL.

[0341] For example, compared to word line (1-1) WL11, the first string select line SSL0 can be set relatively closer to the peripheral circuit layer PCL. Furthermore, compared to word line (1-4) WL14, word line (1-1) WL11 can be set closer to the peripheral circuit layer PCL.

[0342] The first unit layer CL1 may include a first string ST1 extending from the first substrate 311 (or common source line 330) in the opposite direction to the first direction (e.g., the Y direction).

[0343] The first string ST1 can be connected to the first page buffer PB1 via the first metal wiring 321. Therefore, the first metal wiring 321 can be referred to as the first bit line BL1 connected to the first string ST1.

[0344] In addition, the storage device 100D may include a second cell layer CL2 stacked on the first cell layer CL1.

[0345] According to one or more embodiments, the second unit layer CL2 may have a shape substantially the same as that of the first unit layer CL1.

[0346] The second unit layer CL2 may include multiple second word lines WL2 and a first string selection line SSL0 stacked in a first direction (e.g., the Y direction).

[0347] For example, the second unit layer CL2 may include a first selection line SSL0, a (2-1) word line WL21 (also known as the first word line of the second group of word lines), a (2-2) word line WL22 (also known as the second word line of the second group of word lines), a (2-3) word line WL23 (also known as the third word line of the second group of word lines), and a (2-4) word line WL24 (also known as the fourth word line of the second group of word lines) arranged in the order adjacent to the first unit layer CL1.

[0348] For example, compared to word line (2-1) WL21, the first string selection line SSL0 can be set closer to the first unit layer CL1. Furthermore, compared to word line (2-4) WL24, word line (2-1) WL21 can be set closer to the first unit layer CL1.

[0349] The second unit layer CL2 may include a second string ST2 extending from the second substrate 312 (or common source line 330) in the opposite direction to the first direction (e.g., the Y direction).

[0350] The second string ST2 can be connected to the second page buffer PB2 via the second metal wiring 322. Therefore, the second metal wiring 322 can be referred to as the second bit line BL2 connected to the second string ST2.

[0351] In addition, the storage device 100D may include a third cell layer CL3 stacked on the second cell layer CL2.

[0352] According to one or more embodiments, the third unit layer CL3 may have a shape substantially the same as that of the second unit layer CL2.

[0353] The third unit layer CL3 may include multiple third word lines WL3 and a second selection line SSL1 stacked along a first direction (e.g., the Y direction).

[0354] For example, the third unit layer CL3 may include a second string of selection lines SSL1, (3-1) word line WL31, (3-2) word line WL32, (3-3) word line WL33 and (3-4) word line WL34 arranged in order adjacent to the second unit layer CL2.

[0355] For example, compared to word line (3-1) WL31, the second string selection line SSL1 can be set closer to the second unit layer CL2. Furthermore, compared to word line (3-4) WL34, word line (3-1) WL31 can be set closer to the second unit layer CL2.

[0356] The third unit layer CL3 may include a third string ST3 extending from the third substrate 313 (or common source line 330) in the opposite direction to the first direction (e.g., the Y direction).

[0357] The third string ST3 can be connected to the first page buffer PB1 via the third metal wiring 323. Therefore, the third metal wiring 323 can be referred to as the third bit line BL3 connected to the third string ST3.

[0358] In addition, the storage device 100D may include a fourth unit layer CL4 stacked on the third unit layer CL3.

[0359] According to one or more embodiments, the fourth unit layer CL4 may have a structure substantially the same as that of the third unit layer CL3.

[0360] The fourth unit layer CL4 may include multiple fourth word lines WL4 and a second selection line SSL1 stacked along a first direction (e.g., the Y direction).

[0361] For example, the fourth unit layer CL4 may include a second string of selection lines SSL1, (4-1) word line WL41, (4-2) word line WL42, (4-3) word line WL43 and (4-4) word line WL44 arranged in order adjacent to the third unit layer CL3.

[0362] For example, compared to word line (4-1) WL41, the second string selection line SSL1 can be set closer to the third unit layer CL3. Furthermore, compared to word line (4-4) WL44, word line (4-1) WL41 can be set closer to the third unit layer CL3.

[0363] The fourth unit layer CL4 may include a fourth string ST4 extending from the fourth substrate 314 (or common source line 330) in the opposite direction to the first direction (e.g., the Y direction).

[0364] The fourth string ST4 can be connected to the second page buffer PB2 via the fourth metal wiring 324. Therefore, the fourth metal wiring 324 can be referred to as the fourth bit line BL4 connected to the fourth string ST4.

[0365] According to one or more implementations, the first page buffer PB1 may be connected to the first string ST1 and the third string ST3.

[0366] For example, the first page buffer PB1 can be connected to the first string ST1 of the first cell layer CL1 via the first metal wiring 321 (or the first bit line BL1). In addition, the first page buffer PB1 can be connected to the third string ST3 of the third cell layer CL3 via the third metal wiring 323 (or the third bit line BL3).

[0367] The second page buffer PB2 can be connected to the second string ST2 and the fourth string ST4.

[0368] For example, the second page buffer PB2 can be connected to the second string ST2 of the second cell layer CL2 via the second metal wiring 322 (or the second bit line BL2). Furthermore, the second page buffer PB2 can be connected to the fourth string ST4 of the fourth cell layer CL4 via the fourth metal wiring 324 (or the fourth bit line BL4).

[0369] According to one or more embodiments, the control logic circuit 170 can control the first page buffer PB1 to perform core operations on the first cell layer CL1 and / or the third cell layer CL3.

[0370] For example, during core operations on the first unit layer CL1, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the first string ST1 through the first bit line BL1 (or the first metal wiring 321).

[0371] Additionally, during the core operation of the third unit layer CL3, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the third string ST3 through the third metal wiring 323 (or the third bit line BL3).

[0372] According to one or more embodiments, the control logic circuit 170 can control the second page buffer PB2 to perform core operations on the second cell layer CL2 and / or the fourth cell layer CL4.

[0373] For example, during the core operation of the second unit layer CL2, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 through the second metal wiring 322 (or the second bit line BL2).

[0374] Additionally, during the core operation of the fourth unit layer CL4, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the fourth string ST4 through the fourth metal wiring 324 (or the fourth bit line BL4).

[0375] According to one or more embodiments, the control logic circuit 170 may use the first page buffer PB1 and the second page buffer PB2 to perform core operations on the first cell layer CL1 and the second cell layer CL2.

[0376] For example, control logic circuit 170 can control the first page buffer PB1 to apply a voltage to the first string ST1 to perform core operations on the first cell layer CL1.

[0377] Additionally, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 in order to perform core operations on the second cell layer CL2.

[0378] For example, when a core operation is requested on a structure including a first unit layer CL1 and a second unit layer CL2, the control logic circuit 170 can use the first page buffer PB1 and the second page buffer PB2 to perform the core operation.

[0379] Each of the first page buffer PB1 and the second page buffer PB2 can be connected to a memory cell in each cell layer corresponding to a specified page size (e.g., 8KB).

[0380] For example, the first page buffer PB1 can be connected to a memory cell in the first cell layer CL1 corresponding to a specified page size. Similarly, the second page buffer PB2 can be connected to a memory cell in the second cell layer CL2 corresponding to a specified page size.

[0381] Therefore, the storage device 100D according to one or more embodiments can increase the page size controlled during core operations on stacked cell layers CL1 and CL2.

[0382] Figure 16 It is a cross-sectional view of a storage device including a first unit layer to a sixth unit layer according to one or more embodiments.

[0383] refer to Figure 16 The memory device 100E according to one or more embodiments may include a peripheral circuit layer PCL and a first cell layer CL1 to a sixth cell layer CL6 stacked on top of each other.

[0384] Figure 16 The storage device 100E shown can be understood as Figure 1 An example of the storage device 100 shown. Additionally... Figure 16 The storage device 100E shown can be understood as having the same characteristics as... Figure 3 The configuration of the storage device 100A shown is basically the same as that of the storage device shown.

[0385] Therefore, identical or substantially identical parts are indicated by the same reference numerals, and redundant descriptions will be omitted to avoid repetition.

[0386] The storage device 100E may include a fifth unit layer CL5 stacked on the fourth unit layer CL4.

[0387] The fifth unit layer CL5 may have a shape that extends in a second direction (e.g., the X direction) and may include multiple fifth word lines WL5 and third string selection lines SSL2 stacked in a first direction (e.g., the Y direction).

[0388] Additionally, the fifth unit layer CL5 may include a plurality of fifth strings ST5 extending along a first direction (e.g., the Y direction).

[0389] According to one or more embodiments, the fifth string ST5 of a plurality of fifth strings ST5 can be connected to the first page buffer PB1 via the fifth metal wiring 325. Therefore, the fifth metal wiring 325 can be referred to as the fifth bit line connected to the fifth string ST5.

[0390] In addition, the storage device 100E may include a sixth unit layer CL6 stacked on the fifth unit layer CL5.

[0391] The sixth unit layer CL6 may have a shape that extends in a second direction (e.g., the X direction) and may include multiple sixth word lines WL6 and third string selection lines SSL2 stacked in a first direction (e.g., the Y direction).

[0392] Additionally, the sixth unit layer CL6 may include a plurality of sixth strings ST6 extending along a first direction (e.g., the Y direction).

[0393] According to one or more embodiments, the sixth string ST6 of a plurality of sixth strings ST6 can be connected to the second page buffer PB2 via the sixth metal wiring 326. Therefore, the sixth metal wiring 326 can be referred to as the sixth bit line connected to the sixth string ST6.

[0394] According to one or more implementations, the first page buffer PB1 can be connected to the first string ST1, the third string ST3, and the fifth string ST5.

[0395] For example, the first page buffer PB1 can be connected to the first string ST1 of the first cell layer CL1 via the first metal wiring 321 (or the first bit line BL1). Furthermore, the first page buffer PB1 can be connected to the third string ST3 of the third cell layer CL3 via the third metal wiring 323 (or the third bit line). Additionally, the first page buffer PB1 can be connected to the fifth string ST5 of the fifth cell layer CL5 via the fifth metal wiring 325 (or the fifth bit line).

[0396] In addition, the second page buffer PB2 can be connected to the second string ST2, the fourth string ST4, and the sixth string ST6.

[0397] For example, the second page buffer PB2 can be connected to the second string ST2 of the second cell layer CL2 via the second metal wiring 322 (or the second bit line). Furthermore, the second page buffer PB2 can be connected to the fourth string ST4 of the fourth cell layer CL4 via the fourth metal wiring 324 (or the fourth bit line). Additionally, the second page buffer PB2 can be connected to the sixth string ST6 of the sixth cell layer CL6 via the sixth metal wiring 326 (or the sixth bit line).

[0398] According to one or more embodiments, the control logic circuit 170 can control the first page buffer PB1 to perform core operations on the first unit layer CL1, the third unit layer CL3 and the fifth unit layer CL5.

[0399] For example, during core operations on the first unit layer CL1, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the first string ST1 through the first bit line BL1 (or the first metal wiring 321).

[0400] Furthermore, during core operations on the third unit layer CL3, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the third string ST3 through the third metal wiring 323 (or the third bit line).

[0401] Additionally, during core operations on the fifth unit layer CL5, the control logic circuit 170 can control the first page buffer PB1 to apply voltage to the fifth string ST5 through the fifth metal wiring 325 (or the fifth bit line).

[0402] According to one or more embodiments, the control logic circuit 170 can control the second page buffer PB2 to perform core operations on the second unit layer CL2, the fourth unit layer CL4 and the sixth unit layer CL6.

[0403] For example, during core operations on the second unit layer CL2, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the second string ST2 through the second metal wiring 322 (or the second bit line).

[0404] Additionally, during core operations on the fourth unit layer CL4, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the fourth string ST4 through the fourth metal wiring 324 (or the fourth bit line).

[0405] Additionally, during core operations on the sixth unit layer CL6, the control logic circuit 170 can control the second page buffer PB2 to apply voltage to the sixth string ST6 through the sixth metal wiring 326 (or the sixth bit line).

[0406] According to one or more embodiments, the control logic circuit 170 may use the first page buffer PB1 and the second page buffer PB2 to perform core operations on the first cell layer CL1 and the second cell layer CL2.

[0407] For example, control logic circuit 170 can control the first page buffer PB1 to apply a voltage to the first string ST1 to perform core operations on the first cell layer CL1. Furthermore, control logic circuit 170 can control the second page buffer PB2 to apply a voltage to the second string ST2 to perform core operations on the second cell layer CL2.

[0408] For example, when a core operation is requested on a structure including a first unit layer CL1 and a second unit layer CL2, the control logic circuit 170 can use the first page buffer PB1 and the second page buffer PB2 to perform the core operation.

[0409] Furthermore, when a core operation is requested on a structure including the third unit layer CL3 and the fourth unit layer CL4, the control logic circuit 170 according to one or more embodiments may use the first page buffer PB1 and the second page buffer PB2 to perform the core operation.

[0410] Furthermore, when a core operation is requested on a structure including the fifth unit layer CL5 and the sixth unit layer CL6, the control logic circuit 170, according to one or more embodiments, can perform the core operation using the first page buffer PB1 and the second page buffer PB2.

[0411] Each of the first page buffer PB1 and the second page buffer PB2 can be connected to a specified page size (e.g., 8KB) or a corresponding number of storage units in each cell layer.

[0412] For example, the first page buffer PB1 can be connected to a memory cell in the first cell layer CL1 corresponding to a specified page size. Similarly, the second page buffer PB2 can be connected to a memory cell in the second cell layer CL2 corresponding to a specified page size.

[0413] Therefore, the storage device 100E according to one or more embodiments can increase the page size controlled during core operations on two stacked cell layers CL1 and CL2.

[0414] As described above, the control logic circuit 170 according to one or more embodiments can use different page buffers PB1 and PB2 to perform core operations on two cell layers CL1 and CL2 stacked adjacent to the peripheral circuit layer PCL.

[0415] Therefore, the storage device 100 according to one or more embodiments can increase the page size controlled during core operation of adjacent cell layers CL1 and CL2 in a plurality of stacked cell layers CL1 to CL4.

[0416] Furthermore, according to one or more embodiments, word lines corresponding to each other in the first unit layer CL1 to the fourth unit layer CL4 can be driven simultaneously by the same transmission transistor.

[0417] Therefore, compared to the case where word lines of the first unit layer CL1 to the fourth unit layer CL4 are driven individually, the memory device 100 (or transmission transistor circuit PTC) according to one or more embodiments can be implemented in a relatively smaller area.

[0418] In addition, when the characteristics of the stacked cell layers are different, the control logic circuit 170 according to one or more embodiments can control the magnitude and / or timing of the voltage applied to each cell layer to be different.

[0419] For example, when the cell layers connected to different page buffers PB1 and PB2 have different characteristics, the control logic circuit 170 can control the magnitude of the voltage applied through the bit lines of each cell layer (e.g., the forced voltage VFBL) to be different.

[0420] For example, when the characteristics of the stacked cell layers are different, the control logic circuit 170 can control the magnitude of the voltage (e.g., programming voltage or pass voltage) applied to the word line of each cell layer to be different.

[0421] Therefore, the control logic circuit 170 can compensate for the characteristic differences between multiple unit layers. Furthermore, the memory device 100 according to one or more embodiments can improve the reliability of core operation.

[0422] As described above, according to one or more embodiments, the storage device can increase the page size of core operations of two adjacent cell layers in a stacked plurality of cell layers.

[0423] While one or more embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, the storage device comprising: First unit layer; A second unit layer is stacked on top of the first unit layer; A third unit layer, which is stacked on top of the second unit layer; A fourth unit layer, which is stacked on top of the third unit layer; A first page buffer is connected to a first string and a third string, wherein the first string is included in the first unit layer and the third string is included in the third unit layer; A second page buffer, connected to a second string and a fourth string, wherein the second string is included in the second unit layer, and the fourth string is included in the fourth unit layer; and The control logic circuit is configured to control the first page buffer and the second page buffer to perform corresponding core operations on the first unit layer and the second unit layer, respectively.

2. The storage device according to claim 1, wherein, The control logic circuit is configured to: during the execution of corresponding core operations on the first unit layer and the second unit layer, respectively. Perform a first core operation on the first string through the first page buffer; and The second core operation is performed on the second string through the second page buffer.

3. The storage device according to claim 1, further comprising: A first metal contact is connected to the (1-1)th word line included in the first unit layer; The second metal contact is connected to the (2-1)th word line included in the second unit layer; The third metal contact is connected to the (3-1)th word line included in the third unit layer; A fourth metal contact, the fourth metal contact being connected to the (4-1)th word line included in the fourth unit layer; as well as A first transmission transistor is connected to the first end of the first metal contact. The first metal contact, the second metal contact, the third metal contact, and the fourth metal contact are electrically connected to each other.

4. The storage device according to claim 3, wherein, The first unit layer and the second unit layer are connected to the first selection line, and The third unit layer and the fourth unit layer are connected to the second selection line.

5. The storage device according to claim 1, wherein, The control logic circuit is configured such that, during programming operations, the change in the threshold voltage dependent on the programming voltage of the memory cell is greater in the first cell layer than in the second cell layer. Control the first page buffer to apply a first forced voltage to the first bit line connected to the first string, and The second page buffer is controlled to apply a second forced voltage, less than the first forced voltage, to the second bit line connected to the second string.

6. The storage device according to claim 3, wherein, The control logic circuit is configured to: during the programming operation of the first string, Activate the first string by selecting the first string; as well as A first programming voltage is applied to the (1-1) word line through the first transmission transistor and the first metal contact.

7. The storage device according to claim 6, wherein, The control logic circuit is configured such that, during programming operations on the third string, the programming speed based on the memory cells in the third cell layer is lower than the programming speed of the memory cells in the first cell layer. The third string is activated by selecting the second string of lines; as well as A second programming voltage greater than the first programming voltage is applied to the (3-1) word line through the first transmission transistor, the first metal contact, the second metal contact, and the third metal contact.

8. The storage device according to claim 2, wherein, The control logic circuit is configured such that the amount of current leaking from the first memory cell included in the first string to the common source line is less than the amount of current leaking from the third memory cell included in the third string to the common source line. During the core operation of the first string, a first common source line voltage is applied to the common source line, and During the core operation of the third string, a second common source line voltage greater than the first common source line voltage is applied to the common source line.

9. The storage device according to claim 3, wherein, The control logic circuit is configured as follows: During the read operation of the first string, a first read voltage is applied to the (1-1)th word line, and During the read operation of the third string, a second read voltage greater than the first read voltage is applied to the (3-1) word line.

10. The storage device according to claim 3, wherein, The control logic circuit is configured such that, during read operations on the first unit layer and the second unit layer, the resistance of the first string is less than the resistance of the second string: Control the first page buffer to apply the first bit line voltage to the first string; as well as The second page buffer is controlled to apply a second bit line voltage greater than the first bit line voltage to the second string.

11. The storage device according to claim 8, wherein, The control logic circuit is configured as follows: Perform a third core operation on the third string through the first page buffer; and The fourth core operation is performed on the fourth string through the second page buffer.

12. The storage device according to claim 1, further comprising: The fifth unit layer is stacked on top of the fourth unit layer; as well as The sixth unit layer is stacked on top of the fifth unit layer. in, The first page buffer is connected to the fifth string of the fifth unit layer. The second page buffer is connected to the sixth string of the sixth unit layer, and, The control logic circuit is further configured to control the first page buffer and the second page buffer to perform corresponding core operations on the fifth unit layer and the sixth unit layer, respectively.

13. A storage device, the storage device comprising: The first unit layer includes a first string; A second unit layer, which is stacked on top of the first unit layer, and includes a second string; The first page buffer is connected to the first string; The second page buffer is connected to the second string; as well as The control logic circuit is configured to control the first page buffer and the second page buffer to perform corresponding core operations on the first unit layer and the second unit layer, respectively.

14. The storage device according to claim 13, wherein, The control logic circuit is configured as follows: Perform a first core operation on the first string through the first page buffer; and The second core operation is performed on the second string through the second page buffer.

15. The storage device of claim 13, further comprising: A third unit layer, which is stacked on top of the second unit layer, and includes a third string; as well as A fourth unit layer, stacked on top of the third unit layer, and including a fourth string, in, The first page buffer is connected to the fourth string, and The second page buffer is connected to the third string.

16. The storage device according to claim 15, wherein, The control logic circuit is configured as follows: Perform a first core operation on the fourth string through the first page buffer; and The second core operation is performed on the third string through the second page buffer.

17. The storage device of claim 15, further comprising: A first metal contact is connected to the (1-1)th word line included in the first unit layer; The second metal contact is connected to the (2-1)th word line included in the second unit layer; The third metal contact is connected to the (3-1)th word line included in the third unit layer; A fourth metal contact, the fourth metal contact being connected to the (4-1)th word line included in the fourth unit layer; as well as A first transmission transistor is connected to the first end of the first metal contact. in, The first metal contact, the second metal contact, the third metal contact, and the fourth metal contact are electrically connected to each other.

18. A storage device, the storage device comprising: The first unit layer includes a first string; A second unit layer, which is stacked on top of the first unit layer, and includes a second string; A third unit layer, which is stacked on top of the second unit layer, and includes a third string; A fourth unit layer, stacked on top of the third unit layer, and including a fourth string; and The peripheral circuit is connected to the first unit layer, the second unit layer, the third unit layer, and the fourth unit layer. in, The peripheral circuit includes: The first page buffer is connected to the first string and the third string, and The second page buffer connects the second string and the fourth string.

19. The storage device according to claim 18, wherein, The peripheral circuitry includes a control logic circuitry configured to perform a first core operation on the first string via the first page buffer, and a second core operation on the second string via the second page buffer.

20. The storage device according to claim 19, wherein, The peripheral circuit also includes a transmission transistor circuit, which is connected to the (1-1) word line included in the first unit layer, the (2-1) word line included in the second unit layer, the (3-1) word line included in the third unit layer, and the (4-1) word line included in the fourth unit layer. The control logic circuit is further configured to apply a word line voltage to each of the first cell layer, the second cell layer, the third cell layer, and the fourth cell layer via the transmission transistor circuit.

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