Apparatus and method for writing data to memory

Abstract

This application relates to apparatus and methods for writing data to memory. When data is repeated across multiple data lines, the data can be transmitted across a single line of a bus rather than driving the repeated data across all of the data lines. The data from the single data line can be provided to write amplifiers of additional data lines to provide the data from all of the data lines to the memory for writing. In some examples, error correction can be performed on data from the single data line rather than all of the data lines.

Description

[0001] Divisional application

[0002] This application is a divisional application of the invention patent application filed on September 28, 2020, with application number 202080072216.2 and entitled "Apparatus and Method for Writing Data to a Memory". Technical Field

[0003] This disclosure generally relates to memory. More specifically, this disclosure relates to apparatus and methods for writing data to memory. Background Technology

[0004] Electronic memory is used to store information in many electronic systems, such as mobile phones, tablet computers, computers, servers, and other electronic systems that contain processors or require information storage. Memory can be controlled by memory commands received via a command bus, such as write commands and read commands. Information to be stored can be written to the memory using a write command and retrieved later using a read command.

[0005] Information can be fed back and forth to memory via multiple lines. While multiple lines allow information to be written to and read from memory in parallel, driving multiple lines consumes more power than a single line. Summary of the Invention

[0006] According to at least one embodiment of this disclosure, an apparatus may include: a first data line configured to transmit a first data to a memory array; a plurality of second data lines configured to transmit a second data to the memory array; a first controller coupled to the plurality of second data lines; and a second controller coupled to the plurality of second data lines and the first data line, wherein the first controller and the second controller are configured to receive an enable signal and a control signal, wherein when the enable signal is valid and the control signal is in a first state during a write operation, the first controller is configured to prevent the second data from being provided from the plurality of second data lines to the second controller, and the second controller is configured to provide the first data from the first data line to a plurality of write amplifiers.

[0007] According to at least one embodiment of this disclosure, a method may include: providing a mode register write command to a memory to program the mode register to enable a write data copy operation; providing operands for each burst cycle of a burst to the memory to indicate whether each of the burst cycles of the burst will perform a write data copy operation or a non-data copy write operation; providing a write command to the memory; and providing data written to the memory to a plurality of data lines.

[0008] According to at least one embodiment of this disclosure, a memory may include: a data bus configured to receive data from a plurality of data pads; a global data bus configured to receive the data from the data bus; a main data bus configured to receive the data from the global data bus; a local data bus configured to receive the data from the main data bus; a plurality of write amplifiers configured to receive the data from the local data bus; a first controller coupled between the data bus and a first subset of the plurality of data pads; and a second controller coupled between the local data bus and a subset of the plurality of write amplifiers, wherein when enabled by an enable signal and activated by a control signal during a write operation, the first controller is configured to maintain data lines of the data bus corresponding to the first subset of the plurality of data pads in a previous state, and the second controller is configured to receive data from data lines of the local data bus corresponding to a second subset of the plurality of data pads and provide the data to the subset of the plurality of write amplifiers. Attached Figure Description

[0009] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a chip layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 3 This is a block diagram of a data burst according to an embodiment of the present disclosure.

[0012] Figure 4 This is a flowchart of a method according to an embodiment of the present disclosure.

[0013] Figure 5 This is a timing diagram of memory operations according to embodiments of the present disclosure.

[0014] Figure 6 This is a schematic diagram of the data path between a data pad and a memory cell array in a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 7 This is a schematic diagram of the data path between a data pad and a memory cell array in a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 8 This is a schematic diagram of the data path between a data pad and a memory cell array in a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 9This is a schematic diagram of the data path between the memory cell array and the data pad in a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0018] Certain details are described to provide a full understanding of examples of this disclosure. However, those skilled in the art will appreciate that examples of this disclosure can be practiced without these specific details. Furthermore, the specific examples of this disclosure described herein should not be construed as limiting the scope of this disclosure to those specific examples. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail to avoid unnecessarily obscuring this disclosure. Additionally, terms such as "coupled" mean that two components can be electrically coupled directly or indirectly. Indirect coupling may imply that two components are coupled through one or more intermediate components.

[0019] As previously described, information can be provided to and from memory via multiple lines (e.g., data lines), allowing information to be written to and read from memory in parallel. In many cases, the information written to memory is repetitive or has repeating portions across multiple lines. For example, one or more bytes provided to memory may be the same data across at least some of multiple lines. According to the principles of this disclosure, in cases where information is repeated across multiple lines, the information can be provided to memory via one of the lines. This reduces the number of lines that need to be driven when writing information to memory. In some applications, reducing the number of lines driven during write operations can reduce the power consumption of the memory.

[0020] Figure 1 This is a block diagram of a semiconductor device 10 according to an embodiment of the present disclosure. For example, the semiconductor device 10 may be a memory (e.g., LPDD5 SDRAM) integrated into a single semiconductor chip. The semiconductor device 10 may be mounted on an external substrate 2, such as a memory module substrate, motherboard, or the like.

[0021] exist Figure 1 In the example shown, semiconductor device 10 includes memory cell array 11. Memory cell array 11 includes multiple memory banks BANK0 to 7. In other examples, memory cell array 11 may include more or fewer memory banks. Each memory bank may include multiple word lines WL, multiple bit lines BL and / or BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / or BL. The selection of word lines WL is performed by row decoder 12, and the selection of bit lines BL is performed by column decoder 13. Sensing amplifier (SAMP) 18 is coupled to the corresponding bit lines BL and / or BL and to local I / O line pair LIOT / B. Local I / O line pair LIOT / B is coupled to main I / O line pair MIOT / B via transmission gate TG 19, which acts as a switch.

[0022] Read data from bit line BL or / BL is amplified by sense amplifier 18 and provided to transmission gate 19 via complementary local data line LIOT / B. Transmission gate 19 can be used as a switch to form a conductive path between the appropriate LIOT / B and the appropriate shared main data line MIOT / B. Read data can be passed from local data line LIOT / B to main data line MIOT / B via a conductive path provided to read / write amplifier 15 through transmission gate 119, and read / write amplifier 15 provides the data to IO circuit 17. Write data received from IO circuit 17 is output from read / write amplifier 15 and provided to sense amplifier 18 via complementary main data line MIOT / B, transmission gate 19, and complementary local data line LIOT / B, and written to memory cell MC coupled to bit line BL or / BL.

[0023] Turning to the explanation of the plurality of external terminals included in semiconductor device 10, the plurality of external terminals include address terminal 21, command terminal 22, clock terminal 23, data terminal 24, and power supply terminals 25 and 26. Input signal block 41 may include address terminal 21, command terminal 22, and clock terminal 23. Data interface includes data terminal 24. Data terminal 24 may be coupled to an output buffer for memory read operations. Alternatively, data terminal 24 may be coupled to an input buffer for memory read / write access, as described later. Figure 1 Examples of dynamic random access memory (DRAM) are shown; however, any device having external terminals for signal input / output may include external terminals as embodiments of this disclosure.

[0024] Address terminal 21 is supplied with address signal ADD and memory address signal BADD, which are provided to address input circuit 31. The address can be provided to address decoder 32 by address input circuit 31. Command terminal 22 is supplied with command signal COM. Command signal COM can contain one or more individual signals. Command signal COM input to command terminal 21 is provided to command input circuit 33. Command input circuit 33 can provide command signal COM to command decoder 34.

[0025] Alternatively, address terminal 21 and command terminal 22 can be combined command / address terminals configured to provide command and address signals CA to command / address input circuit 42. In this embodiment, command / address input circuit 42 receives the CA signal at the command / address terminal and provides the address signal and internal command signals to address decoder 32 and command decoder 34, respectively. The address signal and command signal can be based on a combination of the values ​​of the CA signal received by command / address input circuit 42.

[0026] The received address signal ADD and memory address signal BADD are provided to address decoder 32. Address decoder 32 receives address signal ADD and supplies the decoded row address signal XADD to row decoder 12 and the decoded column address signal YADD to column decoder 13. Address decoder 32 also receives memory address signal BADD and supplies memory address signal BADD to row decoder 12 and column decoder 13.

[0027] Command decoder 34 decodes the command signal COM to generate various internal command signals. For example, internal commands may include row command signals for selecting word lines and column command signals for selecting bit lines (e.g., read or write commands), and mode register commands provided to mode register 46 for selecting memory operation conditions (e.g., memory conditions that enable write data copy operations), as will be described in more detail.

[0028] When a row activation command is issued and an activation command is supplied in a timely manner for the bank address and row address, and a read command is supplied in a timely manner for the column address, read data is read from the memory cell MC in the memory cell array 11 specified by these row and column addresses. Read data DQ is output to the outside via read / write amplifier 15 and input / output circuitry 17 from data terminal 24. Similarly, when a row activation command is issued and an activation command is supplied in a timely manner for the bank address and row address, and a write command is supplied in a timely manner for the column address, input / output circuitry 17 can receive write data DQ at data terminal 24. In some embodiments, a mask signal may also be provided at the DM terminal (also referred to as the DMI pin) during a write operation, indicating that the write data provided at data terminal 24 is written to the memory cell array 11. In some embodiments, the data terminal may be a pad, such as a DQ pad. Write data DQ is supplied to the memory cell array 11 via input / output circuitry 17 and read / write amplifier 15 and written to the memory cell MC specified by the row and column addresses. According to at least one embodiment, input / output circuitry 17 may include an input buffer and an output buffer.

[0029] Clock terminals 23 are supplied with external clock signals CK_t and CK_c, respectively. These external clock signals CK_t and CK_c are complementary and supplied to clock input circuit 35. Clock input circuit 35 receives external clock signals CK_t and CK_c and generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to internal clock generator 36, and thus the phase-controlled internal clock signal LCLK is generated based on the internal clock signal ICLK received from command input circuit 33 and clock enable signal CKE. Although not limited thereto, the DLL circuit can be used as internal clock generator 36. The phase-controlled internal clock signal LCLK is supplied to input / output circuit 17 and can be used to read the output timing of data DQ via the DQS terminal (which can also be called the RDQS pin). The internal clock signal ICLK is also supplied to timing generator 37, and thus various internal clock signals can be generated.

[0030] Mode register 46 can be used to define various modes of programmable operation and configuration of semiconductor device 10. The mode register retains stored information until it is reprogrammed, reset, or the semiconductor device 10 is powered off. Mode register 46 can be programmed via mode register write commands. Mode register 46 may contain one or more registers for storing information related to different memory operations and configurations. For example, mode register 46 can be used to set burst length, burst type, latency, frequency setpoint, enable programmable termination components, enable certain memory operations, and others. Mode register 46 can also be programmed with information that can be read to provide status information about semiconductor device 10. For example, mode register 46 can be used to provide ready state, calibration state, and other status information. The read information can be programmed by the circuitry of semiconductor device 10. Mode register 46 can be read via mode register read commands. Reading mode register 46 allows information about the operational and configuration status to be provided by semiconductor device 10.

[0031] According to embodiments of this disclosure, mode register 46 can be programmed to enable write data copy operation. The write data copy operation can be performed in response to a write command. In a non-data copy write operation, data from all data terminals 24 (e.g., all DQ pads) crosses the data line drive corresponding to each of the data terminals 24. The data lines may be included in one or more buses in the semiconductor device 10. Data from all data lines may be stored in memory array 11. In contrast, during a write data copy operation, data from a subset (e.g., one) of data terminals 24 crosses the data line drive corresponding to that subset of data terminals 24. As will be described in more detail herein, the data from the subset of data lines may be copied at read / write amplifier 15 to store the data in memory.

[0032] When mode register 46 is programmed to enable write data copy operation, mode register 46 can provide a control signal WDC_EN to enable write data copy control circuitry 30, which may include one or more controllers. When write data copy control circuitry 30 is enabled by the control signal WDC_EN from mode register 46, write data copy control circuitry 30 can respond to a command signal WDC DC0_3 provided by command decoder 34. In some instances, command signal WDC DC0_3 can be a multi-bit signal. Based on command signal WDC DC0_3, write data copy control circuitry 30 can prevent certain data lines or portions thereof from being driven when data is provided at data terminal 24 during or during a write operation. In some embodiments (e.g.) Figure 1 In the embodiment shown, the WDC_EN signal from the mode register 46 can be provided to the command decoder 34. In some embodiments, the WDC_EN signal can enable the command decoder 34 to generate the command signal WDC DC0_3.

[0033] Power supply terminal 25 is supplied with power supply voltages VDD and VSS. These power supply voltages VDD and VSS are supplied to the internal power supply circuit 39. The internal power supply circuit 39 generates various internal voltages VPP, VOD, VARY, VPERI, and Vdd2H. The Vdd2H voltage can be used as the output voltage to drive the output signal. The internal voltage VPP is mainly used in the line decoder 12, the internal voltages VOD and VARY are mainly used in the sense amplifier 18 contained in the memory cell array 11, and the internal voltage VPERI is used in many other circuit blocks.

[0034] Power supply terminal 26 is supplied with power supply voltages VDDQ and VSSQ. These power supply voltages VDDQ and VSSQ are supplied to input / output circuit 17. Power supply voltages VDDQ and VSSQ can be the same as the power supply voltages VDD and VSS supplied to power supply terminal 25. However, as... Figure 1 As shown, dedicated power supply voltages VDDQ and VSSQ can be used in input / output circuit 17 to prevent power supply noise generated by input / output circuit 17 from propagating to other circuit blocks.

[0035] Figure 2 This is a chip layout diagram of a semiconductor device 200 according to an embodiment of the present disclosure. In some embodiments, the semiconductor device 200 may include... Figure 1The semiconductor device 200 is shown as at least a portion of the semiconductor device 10. In short, the semiconductor device 200 may include one or more memory banks 202 of a memory array (e.g., memory array 11) and row decoders 204 and column decoders 206 for each memory bank 202. In some embodiments, each memory bank 202 may have its own data sensing amplifier and error correction code (DSA / ECC) circuitry 208. In other embodiments, the DSA / ECC circuitry 208 may be shared between two or more memory banks 202.

[0036] Figure 2 The diagram illustrates an example arrangement of the data lines of a semiconductor device 200. During a write operation, data can be received from DQ pads DQ15 to 0 and provided to the data bus DBUS. Data from each of the DQ pads DQ15 to 0 can be serial data (e.g., provided one bit at a time sequentially). In some embodiments, data from the DQ pads DQ15 to 0 can be deserialized by a deserializer circuit before being provided to the data bus DBUS. Figure 2 (Not shown) Deserialization. The data bus DBUS can provide data to the appropriate global data bus GBUS via DBUS / GBUS buffer 210. The global data bus GBUS can provide data to the appropriate master data bus MBUS via GBUS / MBUS buffer 212. The master data bus MBUS can provide data to the appropriate local data bus LBUS via MBUS / LBUS buffer 214. The local data bus LBUS can provide data to the appropriate DSA / ECC circuit 208 for storage in the desired memory bank 202. The appropriate MBUS and LBUS can be selected at least in part based on the memory bank address and / or column address provided with a write command (not shown). The transfer of data across data lines through one or more buses and / or other components of the semiconductor device 200 within the memory array can be referred to as a data path.

[0037] In some cases, data provided on some or all DQ pads DQ15 to 0 may be identical for one or more time periods. For example, one or more bytes of data may be identical across DQ7 to 0, and one or more bytes of data may be identical across DQ15 to 8. During non-data copy write operations, data across all DQ pads is provided across all data buses DBUS, GBUS, MBUS, and LBUS to store the data in memory. However, according to embodiments of this disclosure, write data copy operations may be performed while data is repeated across one or more data lines. In some embodiments of this disclosure, during write data copy operations, data provided from one or more of the DQ pads may be provided to the data buses DBUS, GBUS, MBUS, and LBUS in some embodiments of this disclosure. Then, data from one or more of the DQ pads may be provided across all data lines at LBUS or DSA / ECC circuit 208, such that all data from DQ15 to 0 is stored in memory. For example, in some embodiments, data can be driven across the data lines of one of the DQ pads from DQ7 to DQ0 and / or the data lines of one of the DQ pads from DQ15 to DQ8. This can reduce the number of data lines that need to be driven across the data buses DBUS, GBUS, MBUS, and / or LBUS. In some embodiments, reducing the number of data lines that need to be driven by data during write operations can reduce the power consumption of the memory device 200.

[0038] In some embodiments, the write operation may have a burst structure. That is, a set number of data bits to be written to memory may be provided serially on one or more lines (e.g., DQ15 to 0) in response to a write command. Figure 3 This is a block diagram of a burst 300 according to embodiments of the present disclosure. In some embodiments, a burst 300 may include a plurality of burst cycles 302. Each burst cycle 302 may include a plurality of beats 304. In some embodiments, bits may be provided during each beat 304 of a burst cycle 302. In the example described herein, a burst cycle 302 includes 8 beats 304 and each burst 300 includes 4 burst cycles 302, for a total of 32 beats 304. Therefore, 32 bits per line can be transmitted during a burst 300. However, Figure 3 The burst structure shown is for illustrative purposes only. In other embodiments, bursts may have different numbers of beats and / or may be divided into different numbers of burst cycles.

[0039] While in some cases data may be identical across two or more lines for all 32 ticks of a burst, it is more common for data to be identical across two or more lines for a portion of the burst. Therefore, if a write data copy operation requires data to be identical across two or more lines for the entire burst in response to a write command, the power savings of the write copy operation cannot be significantly utilized. Therefore, in some embodiments, a write operation may comprise a combination of a non-data copy write operation and a write data copy operation. For example, a write operation may include providing data to all lines (e.g., DQ pads) across all data buses (e.g., DBUS, GBUS, MBUS, LBUS) during a non-data copy write operation for a portion of the burst in response to a write command, and also includes providing data to one or more of the lines provided and copied across one or more groups of data buses. In some embodiments of this disclosure, a write command or other command may include information designating a portion of the burst as a non-data copy write operation or a write data copy operation. For example, in some embodiments of this disclosure, for a 32-bit burst within four burst cycles, a write command may include operands designating each burst cycle as a non-data copy write operation or a write data copy operation. Other embodiments of this disclosure also include different combinations of burst length, burst cycle, and designating portions of the burst as non-data copy write operations or write data copy operations.

[0040] Figure 4 This is a flowchart 400 of a method according to an embodiment of the present disclosure. At block 402, the step of executing a programming mode register (MR) to enable a write data copy (WDC) mode is described. For example, a command provided by command input circuitry 33 can be used in programming mode register 46 to enable WDC mode of semiconductor device 10. WDC mode enables write data copy operation in response to a write command.

[0041] At block 404, the step of providing an access command CAS comprising operands DC0 through 3 can be performed. Operands DC0 through 3 can indicate which burst cycles of a burst for a write operation should be performed as non-data copy write operations and which burst cycles of a burst should be performed as write data copy operations. For example, in some embodiments, a "1" or high value of the operands can indicate a write data copy operation of a burst cycle and a "0" or low value of the operands can indicate a non-data copy write operation of a burst cycle. Operands DC0 through 3 comprise 4 bits, each corresponding to one of the 4 burst cycles of the burst. However, for bursts with different numbers of burst cycles, the CAS command may contain a different number of operands. In some embodiments, operands DC0 through 3 can be provided as control signals WDC_DC0 through 3 to write data copy control circuitry (e.g., write data copy control circuitry 30). Alternatively, in some embodiments, operands DC0 through 3 may be provided as a write command at block 406 instead of a CAS command at block 404.

[0042] In box 406, the step of providing a write command can be performed. The memory can then perform a write operation in response to the write command. Based at least in part on the values ​​of operands DC0 to 3, a non-data copy write operation can be performed for some burst cycles, and a data copy write operation can be performed for other burst cycles.

[0043] Figure 5 This is a timing diagram 500 of memory operations according to embodiments of the present disclosure. Timing diagram 500 illustrates examples of ways in which a write operation including both data copy and non-data copy write operations can be performed in some embodiments of the present disclosure. In some embodiments, the memory operations depicted in timing diagram 500 may be performed by semiconductor device 10 and / or semiconductor device 200.

[0044] The first row of timing diagram 500 illustrates the differential clock signals CK_c and CK_t. The intersection of the differential clock signals CK_c and CK_t can be the rising and falling edges of the clock signal used for sequential memory operations. The rising edge of the differential clock signal is indicated by arrow 502. The second row of timing diagram 500 illustrates the command address signal CA. The third row illustrates the data lines corresponding to DQ pad DQ0 (e.g., data line DQ0). The fourth row illustrates the data lines corresponding to DQ pads DQ7 to 1 (e.g., data lines DQ7 to 1). Individual timing lines are described for the data lines corresponding to DQ7 to 1 because the operation of these data lines can be substantially the same. The fifth row illustrates the data lines corresponding to DQ pad DQ8 (e.g., data line DQ8), and the sixth row illustrates the data lines corresponding to data pads DQ15 to 9 (e.g., data lines DQ15 to 9). Individual lines are described for the data lines corresponding to DQ15 to 9 because the operation of these data lines can be substantially the same. Although the memory operation illustrated in timing diagram 500 indicates that the memory device has 16 data lines DQ15 to 0, in other embodiments, the memory device performing the memory operation may have more or fewer data lines (e.g., 8, 32).

[0045] exist Figure 5 In the example operation shown, the burst contains four burst cycles, each of which contains eight beats. In this example, the data across data lines DQ7 to 0 is identical in both the first and third burst cycles. That is, the first byte of the data across data lines DQ7 to 0 is the same as the third byte of the data. The data across data lines DQ15 to 8 is identical in both the first and third burst cycles. As previously noted, although the example provided herein has a burst containing 32 beats, in other embodiments, the burst may have a different number of beats and / or a different number of burst cycles.

[0046] A CAS command may be provided at or approximately at time T-1. The CAS command may contain operands DC0 through 3. In some embodiments, operands DC0 through 3 may be provided via the falling edge of a clock signal CK_t. Figure 5 In the example shown, DC0=1, DC1=0, DC2=1, and DC3=0. In this example, the operands of the CAS command indicate the response to subsequent write commands. Data copy operations should be executed within the first and third burst cycles of the burst, and non-data copy write operations should be executed within the second and fourth burst cycles of the burst.

[0047] At or approximately time T0, a write command may be provided. After a write wait time (WL), at or approximately time Ta1, within a first burst cycle that may be from approximately time Ta1 to time Ta2, a write data copy operation may be performed in response to DC0=1. During the write data copy operation, data to be written to memory may be provided to memory from data lines DQ0 and DQ8. Data provided from data line DQ0 is copied and written to memory as data corresponding to data lines DQ7 to 1, and data provided from data line DQ8 is written to memory as data corresponding to data lines DQ15 to 9. Data from data lines DQ7 to 1 and data lines DQ15 to 9 is not provided to memory, even if this data exists at the corresponding DQ pad. In some embodiments of this disclosure, the data lines in the memory bus configured to receive data from DQ7 to 1 and DQ15 to 9 do not need to be driven during the first burst cycle.

[0048] During the second burst cycle, which can be from approximately time Ta2 to time Ta3, a non-data copy write operation can be performed in response to DC1=0. During the write operation, data to be written to memory can be provided to memory from all data lines DQ15 to 0. All lines of the memory's data bus, configured to receive data from all data lines DQ15 to 0, can be driven during the second burst cycle.

[0049] Within the third burst cycle, which may run from approximately time Ta3 to time Ta4, the write data copy operation may be performed in response to DC2=1. Similar to the first burst cycle, data from data lines DQ7 to 1 and data lines DQ15 to 9 are not provided to memory. Specifically, data from data line DQ0 is written to memory as data corresponding to data lines DQ7 to 1, and data provided from data line DQ8 is written to memory as data corresponding to data lines DQ15 to 9. In some embodiments of this disclosure, the data bus of the memory, configured to receive data from DQ7 to 1 and DQ15 to 9, does not need to be driven during the third burst cycle.

[0050] Within the fourth burst cycle, which can be from approximately time Ta4 to time Ta5, non-data copy write operations can be performed in response to DC3=0. Similar to the second burst cycle, data to be written to memory can be provided to memory from all data lines DQ15 to 0. During the fourth burst cycle, all data buses of the memory, configured to receive data from all data lines DQ15 to 0, can be driven.

[0051] although Figure 5The examples shown illustrate memory operations that alternate between non-data copy and write data copy operations within each burst cycle of a burst, but any combination of operations is possible. For example, a non-data copy write operation or a write data copy operation may be performed in all burst cycles. In another example, a write data copy operation may be performed in the first two burst cycles and a non-data copy write operation may be performed in the last two burst cycles. In yet another example, a non-data copy write operation may be performed in the first burst cycle and a write data copy operation may be performed in the remaining three burst cycles.

[0052] exist Figure 5 In the example shown, one data line is used to provide data that repeats across eight data lines (e.g., DQ0 for DQ7 to 0 and DQ8 for DQ15 to 8). However, other combinations can be used to provide repeating data. For example, one data line can be used to provide data that repeats across four data lines. In another example, one data line can be used to provide data that repeats across sixteen data lines. Furthermore, in Figure 5 In the examples shown, operands DC0 to 3 are used to specify the type of write operation for burst cycles of data lines DQ7 to 0 and DQ15 to 8. In some embodiments of this disclosure, more or fewer operands may be included in the CAS command to provide greater granularity in specifying the type of write operation for the write command. For example, in some embodiments of this disclosure, the CAS command includes operands for specifying the type of write operation for burst cycles of data lines DQ7 to 0 that are separate from the burst cycles of data lines DQ15 to 8.

[0053] Figure 6 This is a schematic diagram 600 illustrating a data path from the DQ pad to a memory cell array in a semiconductor device according to an embodiment of the present disclosure. Selected components of the semiconductor device are also shown for context. In some embodiments, the data path and components shown in schematic diagram 600 may be included in semiconductor device 10 and / or semiconductor device 200. Figure 6 In the example shown, there are eight data lines (e.g., data lines DQ7 to 0) corresponding to eight DQ pads. However, as... Figure 1 , 2 As shown in Figure 5, in other embodiments, there may be other numbers of data lines (e.g., 4, 16, 32). It should be understood that each data line DQ7 to 1 has a corresponding data path to the memory array. However, for simplicity, one path is described for data lines DQ1 to 7, since the operation of the data paths for data lines DQ7 to 1 can be substantially the same.

[0054] like Figure 6As shown, during a write operation (either a non-data copy write operation or a write-data copy operation), data from DQ0 can be provided to deserializer 608 via buffer 602. The data from DQ0 can be provided as a series of bits (e.g., 32 bits). Deserializer 608 can receive the series of bits from DQ0 and output the bits in parallel to the data bus DBUS. In some embodiments, the width of DBUS can be multiple bits and can match the width of the output of deserializer 608. In an example where the deserializer receives 32 bits, the DBUS of DQ0 can be a 32-bit bus. Similar to the reference... Figure 2 The DBUS can provide data to the global data bus GBUS via buffer 616. GBUS can provide data to the appropriate main data bus MBUS via buffer 618, and MBUS can provide data to the appropriate local data bus LBUS via buffer 620. The appropriate MBUS and LBUS can be selected at least in part based on the bank address and / or column address provided with a write command (not shown). Data can be provided from LBUS to one or more write amplifiers 622. The write amplifiers 622 can write data from LBUS to the memory array (…). Figure 6 (Memory cells not shown in the image).

[0055] Moving to DQ7 to 1, during non-data copy write operations, data from DQ7 to 1 can be provided to the memory cells of the memory array in a manner similar to that provided from DQ0. That is, data from DQ7 to 1 can be provided via buffer 604 to deserializer 610, to the data bus DBUS, and via buffer 624 from DBUS to the global data bus GBUS, and then via buffer 626 to the appropriate main data bus MBUS and via buffer 628 to the appropriate local data bus LBUS to write amplifier 632.

[0056] In some embodiments of this disclosure, a controller 614 may be present after the deserializer 610. In some embodiments, the controller 614 may include multiple control circuits, for example, one corresponding to each data line from DQ7 to 1. In other embodiments, multiple controllers 614 may be present, one corresponding to each data line from DQ7 to 1. In some embodiments, the controller 614 may be included in write data copy control circuitry, for example... Figure 1The write data copy control circuitry 30 is shown in the diagram. In some embodiments, controller 614 may be enabled by a valid WDC_EN signal. In some embodiments, the WDC_EN signal may be provided by a mode register, such as mode register 46. When controller 614 is disabled (e.g., WDC_EN is invalid), data from DQ7 to 1 is passed along the corresponding data path during a write operation. When controller 614 is enabled (e.g., WDC_EN is valid), controller 614 may be controlled at least in part based on the control signal WDC DC0_3 received by controller 614. In some embodiments, WDC DC0_3 may be provided by a command decoder, such as command decoder 34. The control signal WDC DC0_3 may be based on the operands included in the access command or write command, as previously referenced. Figure 4 and 5 describe.

[0057] The control signal WDC DC0_3 can indicate, in response to a write command, whether to perform a non-data copy write operation or a write data copy operation during a specific burst cycle of the burst. When WDC DC0_3 indicates that a non-data copy write operation will be performed during the burst cycle, the controller 614 can remain inactive, and data from DQ7 to 1 can be provided to the memory array along the corresponding data paths. That is, the data lines of the DBUS, GBUS, MBUS, and LBUS data paths of DQ7 to 1 are driven to provide data from all DQ pads during the burst cycle. When WDC DC0_3 indicates that a write data copy operation will be performed during the burst cycle, the controller 614 can effectively prevent the data lines of the DBUS, GBUS, MBUS, and / or LBUS of DQ7 to 1 from being driven within the burst cycle. In some embodiments, the controller 614 can keep the data lines in a previous state (e.g., keep the data lines high or low).

[0058] The controller 630 may be included along or after the LBUS corresponding to DQ7 to 1. In some embodiments, the controller 630 may include multiple control circuits, for example, one for each data line corresponding to DQ7 to 1. In other embodiments, multiple controllers 630 may be present, one for each data line corresponding to DQ7 to 1. In some embodiments, the controller 630 may be included in write data copy control circuitry, for example... Figure 1The write data replication control circuitry 30 is shown in the diagram. In some embodiments, controller 630 may be enabled by a valid WDC_EN signal. When controller 630 is disabled (e.g., WDC_EN is invalid), data from DQ7 to 1 is passed to write amplifier 632 along all LBUS during a write operation. When controller 630 is enabled (e.g., WDC_EN is valid), the second controller 630 may be controlled at least in part based on the control signal WDC DC0_3 received by controller 630.

[0059] When WDC DC0_3 indicates that a non-data copy write operation will be performed during a burst cycle, data from DQ7 to 1 can be provided along the corresponding data path to write amplifier 632 for storage in the memory cells of the memory array within the burst cycle. That is, controller 630 can remain inactive. When WDC DC0_3 indicates that a write data copy operation will be performed during a burst cycle, controller 630 becomes active and can receive data from the LBUS corresponding to DQ0 and provide data from the DQ0 LBUS to the write amplifier 632 associated with DQ7 to 1 for writing to the memory array within the burst cycle.

[0060] Therefore, in some embodiments, during write copy data operations, it is necessary to drive the DBUS, GBUS, MBUS, and / or LBUS corresponding to the data path of DQ0 to transfer the data from DQ7 to 0 to the memory array. This can allow for reduced power consumption during some write operations.

[0061] exist Figure 6In the embodiment shown, the semiconductor device may further include a Data Mask Inversion (DMI) pin. The DMI pin provides a mask signal, which may contain multiple bits provided serially. The mask signal from the DMI pin can be provided to write amplifiers 622 and 632 in a manner similar to that provided from DQ0. That is, the mask signal can be provided via buffer 606 to deserializer 612 to the data bus DBUS, and via buffer 634 from DBUS to the global data bus GBUS, and then via buffer 636 to the appropriate main data bus MBUS and via buffer 638 to the appropriate local data bus LBUS to write amplifiers 622 and 632. When the mask signal is active, write amplifiers 622 and 632 can be deactivated. When deactivated, write amplifiers 622 and 632 cannot write data from LBUS to the memory cell during a write operation. That is, an active mask signal causes write amplifiers 622 and 632 to "ignore" the received data. Therefore, existing data in the memory cell can be preserved. When the mask signal is invalid, write amplifiers 622 and 632 can write data from the LBUS to the memory cell during a write operation. The mask signal allows for more targeted writing to memory cells. That is, not every memory cell indicated by a write command needs to be written during a write operation in response to the write command. In some embodiments, the DMI pin can be used for other purposes during other memory operations. For example, the DMI pin can be used to... Figure 9 Parity data is provided during the read operation shown in the image.

[0062] Figure 7 This is a schematic diagram 700 illustrating a data path from the DQ pad to a memory cell array in a semiconductor device according to an embodiment of the present disclosure. Selected components of the semiconductor device are also shown for context. In some embodiments, the data path and components shown in schematic diagram 700 may be included in semiconductor device 10 and / or semiconductor device 200. Figure 7 The same as Figure 6 The data paths and components include numerous data paths and components such as DQ7 to 0, DMI, deserializers 708, 710, 712, buffers 702, 704, 706, 716, 718, 720, 724, 726, 728, 734, 736, 738, DBUS, GBUS, MBUS, LBUS, first and second controllers 714, 730, and write amplifiers 722, 732. These data paths and components can be substantially the same as... Figure 6 The layout and operation of the corresponding data paths and components are shown in the diagram. Therefore, for the sake of simplicity, these data paths, components, and their operations will not be discussed further here.

[0063] In some embodiments, the semiconductor device may include error correction features. Figure 7 The example shown may include error correction code (ECC) circuitry, more specifically, ECC decoder circuitry 744. In some embodiments, ECC decoder circuitry 744 may analyze data provided by deserializers 708, 710, 712 from DQ7 to 0, DMI and provide corrected data to the DBUS data lines. In some embodiments, this may reduce erroneous data written to the memory array.

[0064] Parity data corresponding to the data provided on DQ7 to 0, DMI can be provided on the Parity / RDQS pin, via buffer 740 to deserializer 742. The deserialized parity data can be provided to ECC decoder circuitry 744 via the deserialized parity data shared and used for Read Data Stochastic (RDQS) data bus. The Parity / RDQS pin can be a multi-purpose pin. During a write operation, the Parity / RDQS pin can be used to provide parity data. However, during a read operation, the Parity / RDQS pin can be used for... Figure 9 The clock signal that strobs data during the read operation is shown in the image.

[0065] In addition to parity data, the ECC decoder circuit 744 can also receive the WDC_EN signal from the mode register and the control signal WDC DC0_3 from the command decoder. When the WDC_EN signal is invalid and / or WDC DC0_3 indicates that a non-data copy write operation will be performed within the burst cycle, the ECC decoder circuit 744 can perform error correction calculations on the data provided from deserializers 708 and 710 based on the parity data received from deserializer 742 within the burst cycle. The corrected data can be provided from the ECC decoder circuit 744 across all data paths (e.g., for DQ7 to 0) to write amplifiers 722 and 732.

[0066] When the WDC_EN signal is valid and the control signal WDC DC0_3 indicates that a write data copy operation will be performed within a burst cycle, the ECC decoder circuit 744 can perform error correction calculations on the data provided from the deserializer 708 based on the parity data received from the deserializer 742 within the burst cycle. That is, the ECC decoder circuit 744 can perform error correction on the data provided from DQ0. The ECC decoder circuit 744 can provide the corrected data to the write amplifier 722 along the data path corresponding to DQ0. However, as referenced... Figure 6 The second controller 730 can provide corrected data from the data path used for DQ0 to the write amplifier 732. Therefore, in some embodiments, the ECC decoder circuit 744 can perform fewer error correction calculations during write data copying operations, which can reduce power consumption in some applications.

[0067] In some embodiments, during a write data copy operation, controller 714 may provide all zeros to the ECC decoder circuit 744 at the inputs for DQ7 to 1. In these embodiments, ECC decoder circuit 744 may perform calculations based on DQ0 data and all-zero DQ1 to 7 inputs and parity data provided from the parity / RDQS pin. In some embodiments, although ECC decoder circuit 744 receives inputs (e.g., all zeros) on DQ1 to 7, buffers 724, 726, and 728 may remain invalid and controller 730 may copy data from the data path for DQ0 to write amplifier 732. Therefore, in some embodiments, power can be saved because buffers 724, 726, and 728 do not require driving.

[0068] Figure 8 This is a schematic diagram 800 illustrating a data path from the DQ pad to a memory cell array in a semiconductor device according to an embodiment of the present disclosure. Selected components of the semiconductor device are also shown for context. In some embodiments, the data path and components shown in schematic diagram 800 may be included in semiconductor device 10 and / or semiconductor device 200. Figure 8 The same as Figure 6 and 7 The data paths and components in the circuit include numerous data paths and components such as DQ7 to 0, DMI, parity pins, deserializers 808, 810, 812, 842, buffers 802, 804, 806, 816, 818, 820, 824, 826, 828, 834, 836, 838, 840, DBUS, GBUS, MBUS, LBUS, DBUS for RDQS, first and second controllers 814, 830, write amplifiers 822, 832, and ECC decoder circuitry 844. These data paths and components can be substantially the same as those in the circuit. Figure 6 and 7 The layout and operation of the corresponding data paths and components are shown in the diagram. Therefore, for the sake of simplicity, these data paths, components, and their operations will not be discussed further here.

[0069] In some embodiments, the semiconductor device may include error correction features. Figure 8The example shown may include error correction code (ECC) circuitry, more specifically, ECC encoder circuitry 846. In some embodiments, ECC encoder circuitry 846 may receive data written to the memory array from write amplifiers 822 and 832 during a write operation and generate parity data corresponding to the data written to the memory array. The parity data generated by ECC encoder circuitry 846 may be provided to the memory array for storage (not shown). In some embodiments, the parity data may be stored separately from the data written to the memory array. In some embodiments, this may reduce erroneous data read from the memory array. Figure 8 As shown, in some embodiments, the ECC encoder circuit 846 can operate in the same manner, regardless of whether the write operation is a non-data copy write operation or a write data copy operation.

[0070] Figure 9 This is a schematic diagram 900 illustrating a data path from a memory cell array to a DQ pad in a semiconductor device according to an embodiment of the present disclosure. Selected components of the semiconductor device are also shown for context. In some embodiments, the data paths and components shown in schematic diagram 900 may be included in semiconductor device 10 and / or semiconductor device 200. In some embodiments, at least some of the data paths and components shown in schematic diagram 900 may be... Figure 6 , 7 And / or use the data paths and component combinations shown in section 8.

[0071] like Figure 9 As shown, during a read operation, data from a memory array (not shown) can be provided to ECC decoder circuit 942 along with parity data. ECC decoder circuit 942 can perform error correction calculations on the data from the memory array based on the parity data. The corrected data can be provided to read amplifiers 924 and 932. Parity data can be provided to read amplifier 940. Read amplifiers 924, 932, and 940 can provide data and parity data to the local data bus LBUS. LBUS can provide data and parity data to the main data bus MBUS via buffers 922, 930, and 938. MBUS can provide data and parity data to the global data bus GBUS via buffers 920, 928, and 936. GBUS can provide data from the memory array to the data bus DBUS via buffers 918 and 926. GBUS can provide parity data to the data bus used for the DMI pin.

[0072] Data from memory can be serialized by serializers 912 and 914. Data can be provided to the appropriate data pads DQ7 to 0 via buffers 904 and 906. Parity data can be serialized by serializer 916 and provided to the parity pin via buffer 908. (See reference...) Figure 6 It is noted that in some embodiments, during a write operation, the pin used to provide parity data during a read operation is used to provide a mask signal during the write operation. In some embodiments, a multipurpose pin can reduce the number of pins and / or data lines required by the semiconductor device.

[0073] During a read operation, the read data strobe signal RDQS can be provided to the RDQS pin via serializer 910 and buffer 902. In some embodiments, RDQS can be generated by an internal clock generator and / or timing generator (e.g., internal clock generator 36, timing generator 37). See reference... Figure 7 In some embodiments, the pin used to provide the RDQS signal during a read operation can also be used to provide parity data during a write operation. In some embodiments, a multipurpose pin can reduce the number of pins and / or data lines required by the semiconductor device.

[0074] As described herein, in some embodiments, write data copying operations can reduce the power consumption of a semiconductor device containing memory. In some embodiments, the repetitive nature of data written to memory can be utilized to avoid driving one or more data lines or portions thereof.

[0075] As will be understood from the foregoing, although specific embodiments of the invention have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of the invention. Therefore, the invention is limited only by the appended claims.

Claims

1. A method comprising: Provide the mode register write command to the memory to program the mode register to enable write data copy operation; The operands for each burst cycle of the burst are provided to the memory to indicate whether each of the burst cycles of the burst will perform a write data copy operation or a non-data copy write operation. The write command is provided to the memory; as well as The data written to the memory is provided to multiple data lines.

2. The method according to claim 1, further comprising: During the burst cycle of the burst, when the operand used for the burst cycle indicates that a write data copy operation will be performed, the logical state of a subset of the multiple data lines is maintained.

3. The method of claim 1, wherein the operands are provided with an access command prior to the write command.

4. The method of claim 3, wherein the operands are provided on the falling clock edge during the access command.

5. The method of claim 1, wherein the burst comprises 4 burst cycles and each burst cycle comprises 8 beats, and wherein the operation bit comprises 4 bits.

6. The method of claim 1, wherein the operation bit for each burst cycle is provided with the write command.

7. The method of claim 1, further comprising providing an access command.

8. The method of claim 7, wherein the operation bits for each burst cycle are provided with the access command.

9. The method of claim 7, wherein the access command is provided prior to the write command.

10. A method comprising: At the mode register, receive the mode register write command and value; In response to the mode register write command, the value is written to the mode register; In response to the value being written to the mode register, an enable signal from the mode register is provided to the write data copy control circuitry; The operand bits are received at the write data copy control circuit; Receive write command; Data written to the memory array is received at at least one of the multiple data terminals; as well as In response to the write command: When the operand has a first value, a write data copy operation is performed; and When the operand has a second value, a non-data copy write operation is performed.

11. The method of claim 10, further comprising receiving a plurality of operands, wherein each of the plurality of operands is associated with a burst cycle in a plurality of burst cycles.

12. The method of claim 11, wherein the plurality of burst cycles are contained in a burst.

13. The method of claim 6, wherein performing the write data copy operation comprises: The data provided at the at least one data terminal is copied to multiple data lines; as well as The data from the multiple data lines is written to the memory array.

14. The method of claim 10, further comprising: Receive valid data mask signal; as well as In response to the valid data mask signal, at least some of the data written to the memory array is ignored.

15. The method of claim 10, further comprising receiving parity data corresponding to the data written to the memory array.

16. A method comprising: Receive enable signal and operands at the first and second controllers; In response to a valid enable signal and the operand having a first value: The first controller maintains at least one of the multiple data lines at a first level; and The second controller copies data from at least one other data line to the remainder of the plurality of data lines. In response to an invalid enable signal or the operand having a second value: The first controller allows at least one data line to change its logic level.

17. The method of claim 16, further comprising: The data from the multiple data lines is written to the memory array.

18. The method of claim 16, wherein the enable signal is provided via a mode register.

19. The method of claim 16, wherein the operands are provided via a command decoder.

20. The method of claim 19, wherein the operands are provided in response to an access command.

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