Memory device with parity block allocation

Abstract

A memory device includes a memory bank array including a plurality of memory cells, a row decoder connected to the memory bank array through a plurality of word lines, and a column decoder connected to the memory bank array through a plurality of column selection lines. The memory bank array can include a first region including a plurality of normal sub word line drivers, and a second region including at least one partial sub word line driver. One of a plurality of column blocks corresponding to the plurality of normal sub word line drivers in the first region can be allocated as a parity check block.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0177960, filed with the Korean Intellectual Property Office on December 3, 2024, and Korean Patent Application No. 10-2025-0168783, filed with the Korean Intellectual Property Office on November 10, 2025, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a storage device. Background Technology

[0004] Storage devices can be used to store data and can be classified as volatile storage devices and non-volatile storage devices. Volatile storage devices lose the data they store when their power is interrupted. Among volatile storage devices, Dynamic Random Access Memory (DRAM) can be used in various fields such as mobile systems, servers, and graphics devices. Summary of the Invention

[0005] Embodiments of this disclosure provide a storage device that satisfies bounded fault (BF) conditions while supporting error correction code (ECC) operation and / or metadata mode.

[0006] One aspect of this disclosure provides a storage device comprising: a memory bank array including a plurality of memory cells; a row decoder connected to the memory bank array via a plurality of word lines; and a column decoder connected to the memory bank array via a plurality of column select lines. The memory bank array may include: a first region including a plurality of normal sub-word line drivers; and a second region including at least one partial sub-word line driver. One of a plurality of column blocks corresponding to the plurality of normal sub-word line drivers in the first region may be assigned as a parity block.

[0007] Another aspect of this disclosure provides a storage device comprising: a memory bank array, each memory bank array including a plurality of memory cells; a row decoder connected to the memory bank array via a plurality of word lines; and a column decoder connected to the memory bank array via a plurality of column select lines. The memory bank array may include: a first region adjacent to one side of the memory bank array and including column blocks disposed in a direction for distributing the column decoder; a second region adjacent to the first region and including column blocks disposed in the direction for distributing the column decoder; a third region adjacent to the second region and including column blocks disposed in the direction for distributing the column decoder; and a fourth region adjacent to the other side of the memory bank array and including at least one column block disposed in the direction for distributing the column decoder. Parity data may be output from the second region.

[0008] Another aspect of this disclosure provides a storage device comprising: a storage device including a plurality of memory banks; and a storage controller configured to send data packets to and receive data packets from the plurality of memory banks. The storage device may include: a memory bank array including a plurality of memory cells; a row decoder connected to the memory bank array via a plurality of word lines; and a column decoder connected to the memory bank array via a plurality of column select lines. The memory bank array includes: a first region including a plurality of normal sub-word line drivers; and a second region including at least one partial sub-word line driver. One of a plurality of column blocks corresponding to the plurality of normal sub-word line drivers in the first region is assigned as a parity block. Attached Figure Description

[0009] Figure 1A It is a block diagram showing an example of a storage device, and Figure 1B This is a conceptual block diagram illustrating an example of a memory array.

[0010] Figure 2 This is a block diagram illustrating an example configuration of a storage device.

[0011] Figure 3 This is a diagram showing an example of a memory array.

[0012] Figure 4 This is a diagram illustrating an example of a memory bank structure for a storage device.

[0013] Figure 5 , Figure 6A , Figure 6B and Figure 7 This is a diagram illustrating examples of the storage device operating in the first mode, the second A mode, the second B mode, and the third mode.

[0014] Figure 8 This is a diagram showing examples of data packets and sub-packets.

[0015] Figure 9A and Figure 9B This is a diagram illustrating an example of BF conditions based on packet size.

[0016] Figure 10 , Figure 11A , Figure 11B and Figure 11C This is a diagram showing an example of a sub-word line driver and a column block corresponding to each sub-word line driver.

[0017] Figure 12 It shows Figure 10 , Figure 11A , Figure 11B and Figure 11CA diagram illustrating the layout relationships between subword drivers, subwords, and column blocks.

[0018] Figure 13 This is a diagram illustrating a comparison example when a column block corresponding to a partial subword line driver is assigned as a parity block.

[0019] Figure 14 This is a diagram illustrating an example of a column block corresponding to a normal subword line driver being assigned as a parity block.

[0020] Figure 15 This is a diagram showing a comparative example when a column block corresponding to a bounded subword line driver is assigned as a meta block.

[0021] Figure 16 This is a diagram illustrating an example of column blocks being assigned as meta blocks in relation to an unbounded subword line driver.

[0022] Figure 17 This is a block diagram illustrating an example of a storage device.

[0023] Figure 18 It shows Figure 17 A diagram illustrating an example of a memory array.

[0024] Figure 19 This is a block diagram illustrating an example of a storage device.

[0025] Figure 20 It shows Figure 19 A diagram illustrating an example of a memory array.

[0026] Figure 21 This is a block diagram illustrating an example of a storage device.

[0027] Figure 22 It shows Figure 21 A diagram illustrating an example of a memory array.

[0028] Figure 23 This is a block diagram illustrating an example of a storage device.

[0029] Figure 24 It shows Figure 23 A diagram illustrating an example of a memory array. Detailed Implementation

[0030] The following description, provided with reference to the accompanying drawings, is intended to aid in a comprehensive understanding of the various embodiments of this disclosure.

[0031] Figure 1A This is a block diagram illustrating a storage device 10A according to some embodiments, and Figure 1B This is a conceptual block diagram illustrating an example of a memory array according to some implementations.

[0032] According to some embodiments, the storage device 10A may include a plurality of storage banks Bank 1 to Bank n, and each storage bank may include a storage bank array. Each storage bank array may include a first region RG1 and a second region RG2. The first region RG1 may primarily refer to a region including column blocks corresponding to normal sub-word line drivers, and the second region RG2 may primarily refer to a region including column blocks corresponding to some sub-word line drivers. For example, the number of column blocks corresponding to normal sub-word line drivers may be greater than the number of column blocks corresponding to some sub-word line drivers.

[0033] According to some embodiments, the storage device 10A may select one of a plurality of normal subword line drivers in a first region RG1, and assign at least one column block from the column blocks corresponding to the selected normal subword line driver as a parity block. A parity block may refer to a column block in which parity data for error correction code operations (hereinafter referred to as "ECC operations") is stored.

[0034] As described below, the selected normal subword line drivers become unbounded. Therefore, the number of bounded subword line drivers can be reduced compared to the case where column blocks corresponding to some subword line drivers are allocated as parity blocks. Consequently, the design complexity for satisfying bounded fault conditions (hereinafter referred to as "BF conditions") can be reduced.

[0035] According to some embodiments, the storage device 10A may allocate at least one column block from the column blocks of the unbounded subword line driver as a meta block. A meta block is a column block used to support metadata mode and may refer to a column block that stores metadata in meta-open mode and normal data in meta-closed mode.

[0036] As will be described below, the number of combinations of data blocks that need to be considered to satisfy the BF condition is reduced, or data blocks no longer need to be considered. Therefore, the design complexity for satisfying the BF condition can be reduced compared to the case where column blocks of bounded subword line drivers are allocated as meta blocks.

[0037] As a result, the storage device 10A according to some implementations can be implemented to satisfy the BF condition while supporting ECC operation and / or metadata mode.

[0038] refer to Figure 1A and Figure 1B According to some embodiments, the storage device 10A may include a storage controller 100 and a storage device 200.

[0039] Storage controller 100 can control storage device 200. For example, storage controller 100 can control storage device 200 based on requests from a processor that supports various applications, such as server applications, personal computer (PC) applications, or mobile applications. For example, storage controller 100 can be included in a host containing a processor and can control storage device 200 based on requests from the processor.

[0040] The storage controller 100 can send commands and / or addresses to the storage device 200 to control the storage device 200. Additionally, the storage controller 100 can send data to or receive data from the storage device 200.

[0041] The storage device 200 can receive and store data from the storage controller 100. The storage device 200 can read the stored data in response to a request from the storage controller 100 and send the read data to the storage controller 100.

[0042] In some embodiments, the storage device 200 may be a storage device that includes volatile memory cells. For example, the storage device 200 may be one of various DRAM devices, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) devices, DDR2 SDRAM devices, DDR3 SDRAM devices, DDR4 SDRAM devices, DDR5 SDRAM devices, DDR6 SDRAM devices, Low Power Double Data Rate (LPDDR) SDRAM devices, LPDDR2 SDRAM devices, LPDDR3 SDRAM devices, LPDDR4 SDRAM devices, LPDDR4X SDRAM devices, LPDDR5 SDRAM devices, Graphics Double Data Rate Synchronous Graphics Random Access Memory (GDDR SGRAM) devices, GDDR2 SGRAM devices, GDDR3 SGRAM devices, GDDR4 SGRAM devices, GDDR5 SGRAM devices, or GDDR6 SGRAM devices.

[0043] In some examples, the storage device 200 may be a stacked storage device in which DRAM dies are stacked (e.g., a high bandwidth memory (HBM) device, an HBM2 device, an HBM3 device, or an HBM4 device).

[0044] In some implementations, storage device 200 may be included in a storage module (e.g., a dual in-line memory module (DIMM)). For example, storage device 200 may be included in a registered DIMM (RDIMM), a lightly loaded DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), or a small outline DIMM (SO-DIMM). However, this is only an example, and storage device 200 may be included in other storage modules such as a single in-line memory module (SIMM).

[0045] In some implementations, the storage device 200 may be an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, an FRAM device, a PRAM device, a TRAM device, or an MRAM device.

[0046] The storage device 200 may include a plurality of storage banks Bank 1 to Bank n.

[0047] Each of the plurality of storage banks Bank 1 to Bank n may include a storage bank array, a row decoder, and a column decoder. For example, the first storage bank Bank 1 may include a first storage bank array BA1, a first row decoder RD1, and a first column decoder CD1.

[0048] Multiple memory bank arrays BA1 to BAn can each include memory cells for storing data. A row decoder can activate a selected word line from multiple word lines based on the row address. A column decoder can activate a selected column selection line from multiple column selection lines based on the column address.

[0049] For ease of description, each memory bank array is defined as including DRAM cells. However, this is merely an example, and each memory bank array can be implemented to include other volatile memory cells besides DRAM cells. In some implementations, each memory bank array can be implemented to include the same type of memory cells, or it can be implemented to include different types of memory cells.

[0050] Each of the plurality of memory bank arrays BA1 to BAn according to some embodiments may include a first region RG1 and a second region RG2.

[0051] The first region RG1 may include column blocks corresponding to normal subword line drivers. For example, normal subword line drivers and their corresponding column blocks may be set in the first region RG1.

[0052] For example, such as Figure 1BAs shown, three normal sub-word line drivers SWD1, SWD2, and SWD3, along with their corresponding column blocks CB, can be located in the first region RG1. However, this is merely an example, and the number of normal sub-word line drivers located in the first region RG1 is not limited to this. Furthermore, according to some embodiments, the normal sub-word line drivers in the first region RG1 can be configured with a symmetrical structure having both even and odd numbers. A portion of some sub-word line drivers can be located in the first region RG1.

[0053] The second region RG2 may include column blocks corresponding to certain sub-word line drivers. For example, certain sub-word line drivers and their corresponding column blocks may be set in the second region RG2.

[0054] For example, such as Figure 1B As shown, a single part-word line driver SWD4 and its corresponding single column block CB can be set in the second region RG2. However, this is only an example, and the number of part-word line drivers and column blocks set in the second region RG2 is not limited to this. According to some embodiments, two or more part-word line drivers can be set in the second region RG2. In addition, two or three column blocks can correspond to part-word line drivers.

[0055] According to some implementations, subword line drivers can be classified as normal subword line drivers and partial subword line drivers based on the number of corresponding column blocks.

[0056] In some implementations, the normal subword line driver can be located in the middle and / or on one side of the memory bank array. Subword lines can be connected to the opposite side of the normal subword line driver. The normal subword line driver can be electrically connected to the column block via two corresponding subword lines. For example, as... Figure 1B As shown, a single subword line SWL can correspond to two column blocks. Each of the normal subword line drivers SWD1, SWD2, and SWD3 can be electrically connected to four column blocks CB.

[0057] In some implementations, partial subword line drivers may be located at the edge of the memory array. Subword lines may be connected to one side or the opposite side of the partial subword line driver. The partial subword line driver may be electrically connected to the column block via one or two corresponding subword lines.

[0058] For example, such as Figure 1B As shown, a partial subword line driver can be connected to a single subword line SWL, and this single subword line SWL can correspond to a single column block. The partial subword line driver SWD4 can be electrically connected to a single column block. However, this is merely an example, and implementations are not limited to this.

[0059] For example, a partial subword line driver can be connected to a single subword line SWL, and this single subword line SWL can correspond to two column blocks. A partial subword line driver SWD4 can be electrically connected to two column blocks.

[0060] For example, a partial subword line driver can be connected to two subword lines (SWL). One of the two subword lines (SWL) can correspond to two column blocks, and the other subword line (SWL) can correspond to a single column block. The partial subword line driver SWD4 can be electrically connected to three column blocks.

[0061] According to some implementations, subword line drivers can be classified as bounded subword line drivers and unbounded subword line drivers based on whether ECC errors that may occur during error correction code (ECC) operation should be restricted to a predetermined area to satisfy the BF condition.

[0062] For ease of description, the BF condition is defined as data affected by a bounded fault being limited to a maximum of four sub-packets. Additionally, data output from a single data block is defined as forming a single sub-packet.

[0063] In some implementations, when a fault occurs in the first normal sub-word line driver SWD1, among the normal sub-word line drivers SWD1, SWD2, and SWD3 located in the first region RG1, a fault may also occur in the four column blocks corresponding to the first normal sub-word line driver SWD1. The four column blocks connected to the first normal sub-word line driver SWD1 can all be data blocks storing normal data ND. For example, data output from the four column blocks connected to the first normal sub-word line driver SWD1 can form four sub-packets.

[0064] Correction errors should be limited to the four data blocks connected to the first normal subword line driver SWD1 to satisfy the BF condition. For example, correction errors occurring during ECC operation should not propagate to column blocks connected to another subword line driver. As a result, a normal subword line driver with all corresponding column blocks allocated as data blocks can be classified as a bounded subword line driver.

[0065] In some implementations, when a failure occurs in the second normal sub-word line driver SWD2, which is one of the normal sub-word line drivers SWD1, SWD2, and SWD3 located in the first region RG1, a failure may also occur in the four column blocks corresponding to the second normal sub-word line driver SWD2. However, one of the four column blocks connected to the second normal sub-word line driver SWD2 is a parity block storing parity data PD. The parity data PD does not form sub-packets. For example, the parity block is not related to the BF condition, so only the three column blocks connected to the second normal sub-word line driver SWD2 need to be considered to satisfy the BF condition.

[0066] Error correction is not limited to column blocks connected to the second normal subword line driver SWD2 satisfying the BF condition. For example, even if a correction error occurring during ECC operation propagates to data blocks connected to another subword line driver, and the number of faulty sub-packets is four, this indicates that the BF condition is still satisfied. As a result, a normal subword line driver whose corresponding column block is assigned as a parity block can be classified as an unbounded subword line driver.

[0067] In some implementations, when a fault occurs in the partial subword line driver SWD4 located in the second region RG2, a fault may also occur in the column block corresponding to the partial subword line driver SWD4. Since only one column block is connected to the partial subword line driver SWD4, the number of faulty data blocks is also 1.

[0068] Even when correction errors propagate to data blocks connected to another subword line driver, the BF condition can still be satisfied. As a result, partial subword line drivers can be classified as unbounded subword line drivers.

[0069] According to some implementations, storage device 10A can support ECC operation. An H-matrix must be designed for ECC operation. For example, the H-matrix must be designed considering bounded sub-word line drivers. The design complexity of the H-matrix increases as the number of bounded sub-word line drivers increases. Conversely, the design complexity of the H-matrix decreases as the number of unbounded sub-word line drivers increases. As mentioned above, unbounded sub-word line drivers include sub-word line drivers with parity blocks allocated within normal sub-word line drivers, as well as partial sub-word line drivers.

[0070] According to some embodiments, the storage device 10A can select one of a plurality of normal subword line drivers in a first region RG1, and assign at least one column block from the column blocks corresponding to the selected normal subword line driver as a parity block. Therefore, the selected normal subword line driver can be an unbounded subword line driver. Thus, compared to the case where column blocks corresponding to some subword line drivers are assigned as parity blocks, the number of bounded subword line drivers can be reduced. As a result, the design complexity of the H matrix used to satisfy the BF condition can be reduced.

[0071] Continue to refer to Figure 1A and Figure 1B Storage device 10A, according to some implementations, can support metadata mode. For example, Figure 1A and Figure 1B An implementation of setting up two meta-blocks to support metadata modes is shown. The metadata modes may include a first mode Mode 1, a second mode A Mode 2A, a second mode B Mode 2B, and a third mode Mode 3.

[0072] The first mode, Mode 1, can be a mode in which normal data ND and its corresponding metadata MD are stored together in and read together from the storage device 200. The metadata is related to the normal data and can be data used to improve the performance of the storage device 200 or enhance the security of the storage device 200. For example, the metadata may include information related to the type, length, and attributes of the corresponding normal data, but the implementation is not limited to this.

[0073] In Mode 1, both metablocks can be used to store metadata (MD).

[0074] For example, refer to Figure 1A and Figure 1B In Mode 1, the metablock connected to the second normal subword line driver SWD2 in the first region RG1 can store metadata MD, and the metablock connected to the partial subword line driver SWD4 in the second region RG2 can store metadata MD. Because the metadata MD is input and output together with the normal data ND, Mode 1 can be referred to as, for example, "meta-open" mode.

[0075] In Mode 1, read or write operations on normal data ND and its corresponding metadata MD can be performed simultaneously. For example, a single read operation can output normal data ND and its corresponding metadata MD from both a data block and a meta block. Conversely, a single write operation can store normal data ND and its corresponding metadata MD into both a data block and a meta block.

[0076] The second A mode, Mode 2A, and the second B mode, Mode 2B, can be modes in which normal data ND and its corresponding metadata MD are stored together in the storage device 200 and read together from the storage device 200.

[0077] In Mode 2A and Mode 2B, one metablock can be used to store metadata MD, and other metablocks can be used to store normal data ND.

[0078] For example, refer to Figure 1A and Figure 1B In Mode 2A, the metablock connected to the second normal subword line driver SWD2 in the first region RG1 can store metadata MD, and the metablock connected to the partial subword line driver SWD4 in the second region RG2 can store normal data ND.

[0079] In Mode 2B, the metablock connected to the second normal subword line driver SWD2 in the first region RG1 can store normal data ND, and the metablock connected to the partial subword line driver SWD4 in the second region RG2 can store metadata MD.

[0080] Because metadata MD is input and output together with normal data ND, both Mode 2A (second A mode) and Mode 2B (second B mode) can be referred to as, for example, “meta-open” mode or “semi-meta-open” mode.

[0081] In Mode 2A and Mode 2B, read or write operations on normal data ND and its corresponding metadata MD can be performed simultaneously. For example, a single read operation can output normal data ND and its corresponding metadata MD from both a data block and a meta block. Conversely, a single write operation can store normal data ND and its corresponding metadata MD into both a data block and a meta block.

[0082] The third mode, Mode 3, can be a mode in which only normal data ND is stored in and read from the storage device 200.

[0083] In Mode 3, both metablocks can be used to store normal data (ND). For example, see reference... Figure 1A and Figure 1B In Mode 3, the metablock connected to the second normal subword line driver SWD2 in the first region RG1 can store normal data ND, and the metablock connected to some subword line drivers SWD4 in the second region RG2 can also store normal data ND. Because the metadata MD is not input or output, Mode 3 can be referred to as, for example, a "meta-off" mode.

[0084] In Mode 3, read or write operations on normal data NDs stored in both data blocks and meta blocks can be performed simultaneously. For example, a single read operation can output normal data NDs stored in both data blocks and meta blocks. Conversely, a single write operation can store normal data NDs in both data blocks and meta blocks.

[0085] According to some embodiments, the storage device 10A can allocate at least one column block from the column blocks of an unbounded subword line driver as a meta block. For example, a meta block can be allocated to an unbounded subword line driver.

[0086] For example, refer to Figure 1A and Figure 1BTwo element blocks can be assigned to an unbounded subword line driver. For example, an element block can be assigned to the unbounded second normal subword line driver SWD2 in the first region RG1. Alternatively, an element block can be assigned to the unbounded partial subword line driver SWD4 in the second region RG2.

[0087] The metablocks allocated to the second normal subword line driver SWD2 in the first region RG1 can be used to store metadata MD in the first mode (Mode 1) and the second mode A (Mode 2A), and can be used to store normal data ND in the second mode B (Mode 2B) and the third mode 3. Additionally, some metablocks allocated to the subword line driver SWD4 in the second region RG2 can be used to store metadata MD in the first mode (Mode 1) and the second mode B (Mode 2B), and can be used to store normal data ND in the second mode A (Mode 2A) and the third mode 3.

[0088] When using meta-blocks to store normal data NDs, the normal data NDs stored in the meta-blocks can supplement or replace data in other data blocks. For example, the normal data NDs of a meta-block can be mapped to other data blocks. Therefore, when assigning meta-blocks to bounded subword line drivers, the number of data blocks that should be considered to design an H matrix that satisfies the BF condition increases the number of data blocks to which the meta-blocks are mapped. This means that the design complexity of the H matrix may increase.

[0089] Conversely, according to some embodiments, the storage device 10A can allocate at least one column block from the column blocks of the unbounded subword line driver as a meta block. Therefore, the number of combinations of data blocks to be considered to satisfy the BF condition can be reduced, or eliminated altogether. As a result, the design complexity for satisfying the BF condition can be reduced compared to the case where column blocks of the bounded subword line driver are allocated as meta blocks.

[0090] As described above, the storage device 10A according to some embodiments can support ECC operation and can allocate at least one column block from the column blocks corresponding to the normal subword line driver as a parity block. Therefore, the design complexity for satisfying the BF condition can be reduced. Furthermore, the storage device 10A according to some embodiments supports a metadata model and can allocate at least one column block from the column blocks of the unbounded subword line driver as a meta block. As a result, the design complexity for satisfying the BF condition can be reduced.

[0091] exist Figure 1A and Figure 1BIn this example, for ease of description, at least one column block from the column blocks corresponding to the normal sub-word line driver is assigned as a parity block, and one column block from the column blocks of the unbounded sub-word line driver created by assigning parity blocks is assigned as a meta-block. However, this is merely an example, and the implementation is not limited thereto. For example, implementations that reduce the design complexity of the H matrix by assigning at least one column block from the column blocks corresponding to the normal sub-word line driver as a parity block, and implementations that reduce the design complexity of the H matrix by assigning at least one column block from the column blocks of the unbounded sub-word line driver as a meta-block, can be implemented independently.

[0092] Figure 2 This is a block diagram illustrating the configuration of a storage device 200 according to some embodiments. Figure 2 The storage device 200 can correspond to Figure 1A Storage device 200.

[0093] refer to Figure 2 The storage device 200 may include control logic circuitry 210, address register 220, memory bank control circuitry 230, refresh control circuitry 400, row address multiplexer (RA Mux) 240, column address (CA) latch 250, row decoder group 260, column decoder group 270, memory cell array 310, sense amplifier unit 285, input / output (I / O) gate circuitry 290, ECC engine 350, and data input / output buffer 320.

[0094] The memory cell array 310 may include multiple memory bank arrays 310_1 to 310_n. Each of the multiple memory bank arrays 310_1 to 310_n may include multiple memory cells. For example, each of the multiple memory cells may be formed at the intersection of a corresponding word line and a corresponding bit line.

[0095] The row decoder group 260 may include multiple row decoders 260_1 to 260_n. Each of the multiple row decoders 260_1 to 260_n may be connected to a corresponding memory array among the multiple memory arrays 310_1 to 310_n.

[0096] The sense amplifier unit 285 may include a plurality of sense amplifiers 285_1 to 285_n. Each of the plurality of sense amplifiers 285_1 to 285_n may be connected to a corresponding memory array among the plurality of memory arrays 310_1 to 310_n.

[0097] The column decoder group 270 may include multiple column decoders 270_1 to 270_n. Each of the multiple column decoders 270_1 to 270_n may be connected to a corresponding memory array among the multiple memory arrays 310_1 to 310_n via a column select line.

[0098] According to some implementations, each of the plurality of memory bank arrays 310_1 to 310_n may include a first region RG1 and a second region RG2. The first region RG1 may primarily house normal sub-word line drivers and their corresponding column blocks. The second region RG2 may primarily house partial sub-word line drivers and their corresponding column blocks.

[0099] According to some implementations, one of a plurality of normal subword line drivers disposed in the first region RG1 is selected, and a parity block is assigned to at least one column block in the column blocks corresponding to the selected normal subword line driver. The selected normal subword line driver can be unbounded. Therefore, the design complexity for satisfying the BF condition can be reduced.

[0100] According to some implementations, at least one column block of the unbounded subword line driver can be assigned as a meta block. For example, column blocks of normal subword line drivers with parity blocks allocated among the plurality of normal subword line drivers in the first region RG1, and / or column blocks of some subword line drivers in the second region RG2 can be assigned as meta blocks. Therefore, the design complexity for satisfying the BF condition can be reduced.

[0101] Address register 220 can be accessed from memory controller 100 (see...) Figure 1A The address register 220 receives the address ADDR, which includes the bank address BANK_ADDR, the row address ROW_ADDR, and the column address COL_ADDR. The address register 220 can provide the received bank address BANK_ADDR to the bank control circuit 230, the received row address ROW_ADDR to the row address multiplexer 240, and the received column address COL_ADDR to the column address latch 250.

[0102] The memory bank control circuit 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. For example, the row decoders 260_1 to 260_n corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal. The column decoders 270_1 to 270_n corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0103] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 240 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 can be applied to each of the row decoders 260_1 to 260_n.

[0104] The refresh control circuit 400 can respond to the refresh signal from the control logic circuit 210 by sequentially increasing or decreasing the refresh row address REF_ADDR in normal refresh mode.

[0105] The refresh control circuit 400 can receive the hammer address HADDR in hammer refresh mode. The refresh control circuit 400 can output the address of the adjacent memory cell row that is adjacent to the attacker's memory cell row as the refresh row address REF_ADDR based on the hammer address HADDR.

[0106] The row decoder selected by the memory control circuit 230 from among the multiple row decoders 260_1 to 260_n can activate the word line corresponding to the row address RA output from the row address multiplexer 240. For example, the selected row decoder can apply a word line drive voltage to the word line corresponding to the row address.

[0107] Column address latch 250 can receive column address COL_ADDR from address register 220 and can temporarily store the received column address COL_ADDR. Additionally, for example, in burst mode, column address latch 250 can gradually increment the received column address COL_ADDR. Column address latch 250 can apply the column address COL_ADDR' obtained by temporary storage or gradual incrementing to each of column decoders 270_1 to 270_n.

[0108] The column decoder activated by the memory bank control circuit 230 among the multiple column decoders 270_1 to 270_n can activate the read amplifier corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR through the I / O gate circuit 290.

[0109] I / O gating circuit 290 may include circuitry for gating input and output data. Additionally, I / O gating circuit 290 may include a data latch for storing codewords output from memory arrays 310_1 to 310_n, and a write driver for writing data to memory arrays 310_1 to 310_n.

[0110] In some implementations, the codeword CW read from a selected memory array among memory arrays 310_1 to 310_n during a read operation can be read by a sense amplifier corresponding to the selected memory array and stored in a data latch of the I / O gate circuit 290. Additionally, the codeword CW stored in the data latch can be ECC decoded by the ECC engine 350 and provided as a data DTA to the data I / O buffer 320. The data I / O buffer 320 can generate a data signal DQ based on the data DTA and can provide the data signal DQ together with the data strobe signal DQS to the memory controller 100.

[0111] In some implementations, during a write operation, the data DTA to be written to a selected memory array among memory arrays 310_1 to 310_n can be received as a data signal DQ by the data I / O buffer 320. The data I / O buffer 320 can convert the data signal DQ into a data DTA and provide the data DTA to the ECC engine 350. The ECC engine 350 can generate parity bits or parity data based on the data DTA and can provide a codeword CW including the data DTA and the parity bits to the I / O gating circuit 290. The I / O gating circuit 290 can write the codeword CW to the selected memory array.

[0112] The data I / O buffer 320 can convert the data signal DQ to the data DTA during a write operation and can provide the data DTA to the ECC engine 350. The data I / O buffer 320 can convert the data DTA provided by the ECC engine 350 to the data signal DQ during a read operation.

[0113] The ECC Engine 350 can perform ECC encoding on the data DTA during write operations. The ECC Engine 350 can also perform ECC decoding on the codeword CW during read operations.

[0114] Control logic circuitry 210 can control the operation of storage device 200. As an example, control logic circuitry 210 can generate control signals to allow storage device 200 to perform write operations, read operations, normal refresh operations, and hammer refresh operations. Control logic circuitry 210 may include a command decoder 211 that decodes commands (CMD) provided from storage controller 100, and a mode register set (MRS) 212 that sets the operating mode of storage device 200.

[0115] Command decoder 211 can decode command CMD to generate internal command signals (e.g., internal activation signal IACT, internal precharge signal IPRE, internal read signal IRD, internal write signal IWR, etc.). Additionally, command decoder 211 can decode chip select signals and command / address signals to generate control signals corresponding to command CMD.

[0116] The mode register group 212 can set the operating mode of the storage device 200. According to some embodiments, the mode register group 212 may include a mode register that sets the operating mode of the storage device 200 to a first mode (Mode 1), a second mode (Mode 2A), a second mode (Mode 2B), or a third mode (Mode 3). For example, when a first value is set in the mode register, the storage device 200 can operate in the first mode (Mode 1). When a second value is set in the mode register, the storage device 200 can operate in the second mode (Mode 2A). Similarly, when a third or fourth value is set in the mode register, the storage device 200 can operate in the second mode (Mode 2B) or the third mode (Mode 3).

[0117] According to some implementations, the first region RG1 and the second region RG2 can be jointly connected to multiple word lines. Therefore, when a single word line corresponding to a row address is activated among the multiple word lines, the regions corresponding to the activated word line in the first region RG1 and the second region RG2 can be activated together. When a column address is applied, the column select line in the first region RG1 corresponding to the applied column address and the column select line in the second region RG2 corresponding to the applied column address can be activated simultaneously.

[0118] Therefore, when the storage device 200 operates in the first mode (Mode 1), the second mode (Mode 2A), and the second mode (Mode 2B), it can simultaneously input or output normal data, metadata, and parity data. Furthermore, when the storage device 200 operates in the third mode (Mode 3), it can simultaneously input or output normal data and parity data.

[0119] As described above, the storage device 200 according to some embodiments can support ECC operation, and at least one column block from the column blocks corresponding to the normal subword line driver can be assigned as a parity block. Therefore, the design complexity for satisfying the BF condition can be reduced. The storage device 200 according to some embodiments can support metadata mode, and at least one column block from the column blocks of the unbounded subword line driver can be assigned as a meta-block. Therefore, the design complexity for satisfying the BF condition can be reduced.

[0120] Figure 3This is a diagram illustrating an example of a memory array according to some implementations. Figure 3 The storage array BA1 can be used with Figure 1A and Figure 1B as well as Figure 2 The storage array BA1 corresponds to this, but the implementation method is not limited to this.

[0121] refer to Figure 3 The first memory bank array BA1 may include multiple word lines WL0 to WLi, multiple bit lines BL0 to BLj, and multiple memory cells MC. The multiple memory cells MC may be located at the intersection of word lines WL0 to WLi and bit lines BL0 to BLj.

[0122] In some implementations, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor connected to word lines and bit lines, and a cell capacitor connected to the cell transistor.

[0123] A single column select line (CSL) can be electrically connected to multiple bit lines. For example, a single column select line (CSL) can be electrically connected to eight bit lines BL0 through BL7. In some examples, 8 bits of data can be read from or written to the memory cell MC using a single word line and a single column select line (CSL). However, this is just an example, and the single column select line (CSL) can also be implemented to be electrically connected to various numbers of bit lines other than eight.

[0124] In some implementations, word lines extending in the row direction may be referred to as rows of the memory bank array BA1. Additionally, column select lines CSL extending in the column direction may be referred to as columns of the memory bank array BA1.

[0125] Figure 4 This is a diagram illustrating the memory structure of a memory device according to some embodiments. Figure 4 The storage device can be, for example Figure 1A or Figure 2 This is one of the memory cells included in the storage device 200, but the implementation is not limited to this. For ease of description, it is related to... Figure 3 Similarly, a single column select line (CSL) is defined to correspond to eight bit lines.

[0126] refer to Figure 4 The storage bank may include a storage bank array BA, a row decoder RD0 corresponding to the storage bank array BA, and a column decoder CD0 corresponding to the storage bank array BA. Figure 4 In Chinese, WL can represent a word line, and CSL can represent a column selection line.

[0127] The storage array BA may include multiple column blocks CB0 to CBj. At least one column block from CB0 to CBj may be assigned as a parity block. At least one column block from CB0 to CBj may be assigned as a meta block. Among the multiple column blocks CB0 to CBj, column blocks other than meta blocks and parity blocks may be assigned as data blocks.

[0128] The first column block CB0 to the (j-1)th column block CBj-1 are defined to correspond to the first region RG1 mentioned above, and the j-th column block CBj corresponds to the second region RG2 mentioned above. In addition, two meta-blocks and one parity block are defined to be allocated.

[0129] At least one column block from the first column block CB0 to the (j-1)th column block CBj-1 in the first region RG1 that is connected to the normal subword line driver can be assigned as a parity block. For example, the (i+1)th column block CBi+1 can be assigned as a parity block.

[0130] Alternatively, the column block adjacent to the (i+1)th column block CBi+1, which is assigned as a parity block, can be allocated as a meta block from the first column block CB0 to the (j-1)th column block CBj-1 in the first region RG1. For example, the i-th column block CBi, which corresponds to the same subword line driver as the (i+1)th column block CBi+1, can be allocated as a meta block.

[0131] Alternatively, the j-th column block CBj in the second region RG2 can be assigned as a meta block. For example, a column block connected to a partial subword line driver can be assigned as a meta block.

[0132] Additionally, column blocks other than those assigned as parity blocks and meta blocks, such as CBi, CBi+1, and CBj, can be assigned as data blocks.

[0133] In some implementations, the number of column selection lines CSL0 to CSL1 for column blocks CBi and CBj assigned as meta blocks may differ from the number of column selection lines CSL0 to CSLk for column blocks assigned as data blocks. For example, the number of column selection lines CSL0 to CSL1 for column blocks CBi and CBj assigned as meta blocks may be 64 (e.g., l=63), and the number of column selection lines CSL0 to CSLk for column blocks assigned as data blocks may be 60 (e.g., k=59). However, this is merely an example, and the implementation is not limited thereto. According to some implementations, the number of column selection lines for column blocks assigned as meta blocks may be the same as the number of column selection lines for column blocks assigned as data blocks.

[0134] Additionally, in some implementations, the number of column selection lines CSL0 to CSLm for column block CBi+1, which is assigned as a parity block, may differ from the number of column selection lines CSL0 to CSLk for column block assigned as a data block. For example, the number of column selection lines CSL0 to CSLm for column block CBi+1, which is assigned as a parity block, may be 64 (e.g., m=63), and the number of column selection lines CSL0 to CSLk for column block assigned as a data block may be 60 (e.g., k=59). However, this is merely an example, and the implementation is not limited thereto. According to some implementations, the number of column selection lines for column block assigned as a parity block may be the same as the number of column selection lines for column block assigned as a data block.

[0135] Row decoder RD0 can activate the word line corresponding to the applied row address, and column decoder CD0 can activate the column select line corresponding to the applied column address. According to some implementations, column decoder CD0 may include j+1 sub-column decoders SCD0 to SCDj corresponding to j+1 column blocks CB0 to CBj respectively, and the operation of each column block may be controlled by the corresponding sub-column decoder. However, the implementation is not limited to this.

[0136] According to some implementation methods, the memory can support one of the above-mentioned first mode (Mode 1), second mode (Mode 2A), second mode (Mode 2B), and third mode (Mode 3). The following will... Figures 5 to 7 This will be described in more detail in the text.

[0137] Figures 5 to 7 This is a diagram illustrating examples of the operation of a storage device 200 according to some embodiments in a first mode (Mode 1), a second mode (Mode 2A), a second mode (Mode 2B), and a third mode (Mode 3). For ease of description, Figures 5 to 7 The following example is shown: the memory bank comprises 19 column blocks, the column blocks allocated as data blocks comprise 60 column select lines, and the column blocks allocated as meta blocks or parity blocks comprise 64 column select lines. Additionally, Figures 5 to 7 The following example is shown: two of the 19 column blocks CB0 to CB18, CB8 and CB18, are assigned as meta blocks, one column block CB9 is assigned as a parity block, and the remaining 16 column blocks are assigned as data blocks.

[0138] refer to Figure 5 In Mode 1, both blocks M0 and M1 can be used to store metadata MD. The storage can be operated on based on 60 column addresses corresponding to the 60 column select lines.

[0139] For example, when the column address corresponding to a column select line (e.g., CSL0) is applied while the first word line WL0 is active, the column decoder CD0 can activate the column select line CSL0 for each of the 19 column blocks CB0 to CB18.

[0140] Each activated column selection line CSL0 corresponds to 8 bit lines. Therefore, in the first region RG1, column block CB9, assigned as parity block P, can input or output 8 bits of parity data PD; column block CB8, assigned as the 0th element block M0, can input or output 8 bits of metadata MD; and each of the remaining column blocks assigned as data blocks D0 to D15 can input or output 8 bits of normal data ND. Additionally, in the second region RG2, column block CB18, assigned as the first element block M1, can input or output 8 bits of metadata. This can be equivalently applied to the remaining column addresses CSL1 to CSL59.

[0141] refer to Figure 6A and Figure 6B In Mode 2A, of the two element blocks M0 and M1, element block M0 can be used to store metadata MD, and element block M1 can be used to store normal data ND. The storage can be operated on based on 64 column addresses corresponding to 64 column select lines.

[0142] In some implementations, the normal data ND stored in the first metablock M1 can be data for data blocks D0 to D15 (0th to 15th data blocks). For example, the column select lines of the first metablock M1 can be mapped to data blocks D0 to D15 (4 units each). The 60 column select lines included in each data block and the 4 column select lines included in the first metablock M1 can form a column address for a single data block.

[0143] For example, the 60 column select lines included in data block D0 and the 4 column select lines included in the first metablock M1 can form a column address for data block D0. The column addresses of the 60 column select lines included in data block D0 can be set to "0 to 59", and the column addresses of the 4 column select lines included in the first metablock M1 can be set to "60 to 63".

[0144] Additionally, for example, the 60 column select lines included in the first data block D1 and the 4 column select lines included in the first meta-block M1 can form a column address for the first data block D1. The column addresses of the 60 column select lines included in the first data block D1 can be set to "0 to 55 and 60 to 63", and the column addresses of the 4 column select lines included in the first meta-block M1 can be set to "56 to 59".

[0145] Similarly, the column addresses for the remaining data blocks D2 to D15 can be configured using each data block and the column selection line of the corresponding first meta block M1.

[0146] In Mode 2B, of the two meta-blocks M0 and M1, meta-block M0 can be used to store normal data ND, and meta-block M1 can be used to store metadata MD. The normal data ND stored in meta-block M0 can be data for data blocks D0 to D15. The operation of Mode 2B is similar to that of Mode 2A, and therefore its detailed description will be omitted.

[0147] Based on the above mapping relationship, under Mode 2A and Mode 2B, the memory bank can be operated based on 64 column addresses.

[0148] refer to Figure 7 In Mode 3, both element blocks M0 and M1 can be used to store normal data ND.

[0149] In some implementations, the normal data ND stored in the 0th metablock M0 can be data for data blocks D0 through D7. For example, the column select lines of the 0th metablock M0 can be mapped to data blocks D0 through D7 in units of 8. The 60 column select lines included in each data block and the 8 column select lines included in the 0th metablock M0 can form the column address for a single data block.

[0150] In some implementations, the normal data ND stored in the first metablock M1 can be data for data blocks D8 through D15 (8th to 15th data blocks D15). For example, the column select lines of the first metablock M1 can be mapped to data blocks D8 through D15 in units of 8. The 60 column select lines included in each data block and the 8 column select lines included in the first metablock M1 can form a column address for a single data block.

[0151] Based on the above mapping relationship, in Mode 3, the memory bank can be operated on based on up to 68 column addresses.

[0152] like Figures 5 to 7 As shown, storage devices according to some embodiments can support various modes by supporting ECC operation and metadata mode. In each mode, storage devices according to some embodiments can read normal data, metadata, and / or parity data together from the storage array in a single read operation, or store normal data, metadata, and / or parity data together into the storage array in a single write operation.

[0153] Furthermore, as will be described below, storage devices according to some embodiments can reduce the design complexity of the H matrix by assigning at least one column block from the column blocks corresponding to the normal subword line drivers as parity blocks, or by assigning at least one column block from the column blocks of the unbounded subword line drivers as meta-blocks. As a result, storage devices can be implemented efficiently.

[0154] Figure 8 This is a diagram illustrating the structure of data packets and sub-packets according to some implementation methods.

[0155] refer to Figure 8 A single data packet can include multiple sub-packets. A data packet can refer to a data storage device 200 (see [link to storage device 200]). Figure 1A ) is sent to storage controller 100 (see Figure 1A (or a unit of data received by storage device 200 from storage controller 100).

[0156] In some implementations, the size of the sub-packet can be the same as the size of the data input or output via a single column select line. For example, when... Figures 5 to 7 When a single column selection line corresponds to 8 bit lines, the unit of input or output data for each data block can be 8 bits, and the unit of sub-packets can also be 8 bits.

[0157] Sub-packets can be data received from or sent to storage controller 100. Therefore, on-chip ECC parity data that is not sent to storage controller 100 will not form sub-packets.

[0158] In some implementations, sub-packets may include normal data. For example, in the first mode (Mode 1) described above, normal data output from each data block may form a single sub-packet. Alternatively, in the second mode (Mode 2A), the second mode (Mode 2B), or the third mode (Mode 3) described above, normal data output from each data block and meta-block may form a single sub-packet.

[0159] Alternatively, in some implementations, the sub-package may include normal data and metadata. For example, metadata may also form a sub-package when it is data to be sent to storage controller 100.

[0160] Figure 9A and Figure 9B This is a diagram illustrating an example of BF conditions according to some implementation methods.

[0161] refer to Figure 9A Data packets can be 128 bits. For example, 16 8-bit sub-packets can form a single data packet.

[0162] The BF condition can be that the data affected by a bounded fault is limited to a maximum of four sub-packets. For example, when... Figures 5 to 7 As shown, when outputting and acquiring 128 bits of data in a single read operation, the data affected by bounded faults can be limited to a maximum of 4 sub-packets.

[0163] Alternative locations, for reference Figure 9B Data packets can be 64 bits. For example, eight 8-bit sub-packets can form a single data packet.

[0164] The BF condition can be that data affected by a bounded fault is limited to a maximum of 3 sub-packets.

[0165] Storage devices according to some implementations can be designed to meet the BF condition even when a failure occurs in the subword line driver.

[0166] For example, a storage device according to some implementations can satisfy the BF condition while reducing the design complexity of the H matrix by allocating at least one column block in the column blocks corresponding to the normal subword line driver as a parity block. References will follow. Figures 10 to 14 This will be described in more detail.

[0167] Alternatively, storage devices according to some embodiments can satisfy the BF condition while reducing the design complexity of the H matrix by allocating at least one column block of the column blocks of the unbounded subword line driver as a meta block. References will follow. Figures 15 to 18 This will be described in more detail.

[0168] In the following text, for ease of description, the BF condition is defined as the data affected by a bounded fault being limited to a maximum of 4 sub-packets.

[0169] Figures 10 to 11C This is a diagram illustrating sub-word line drivers according to some embodiments, and column blocks corresponding to each sub-word line driver. For example, Figure 10 The structure of a memory bank array of a memory device according to some embodiments is shown. Figure 11A The diagram shows the subword line driver located at the left edge of the memory array and its corresponding column block. Figure 11B The diagram shows the subword line driver located at the right edge of the memory array and its corresponding column block. Figure 11C The diagram shows the subword line driver located in the middle of the memory array and its corresponding column block.

[0170] For example, Figures 10 to 11C The storage array can be Figures 1A to 7 This is one of the memory bank arrays included in the memory bank of a memory device, but the implementation is not limited to this. For ease of description, it is similar to... Figures 5 to 7The memory array is defined to consist of 19 column blocks CB0 to CB18.

[0171] refer to Figure 10 The storage array may include multiple column blocks CB0 to CB18 and multiple subword line blocks O_SWB0 to O_SWB5 and E_SWB0 to E_SWB4 disposed between the multiple column blocks CB0 to CB18.

[0172] Multiple column blocks CB0 to CB18 can each be assigned as one of the data blocks, parity blocks, or meta blocks. Multiple column blocks CB0 to CB18 can correspond to... Figures 5 to 7 The columns CB0 to CB18 are described in the text.

[0173] Multiple subword line blocks O_SWB0 to O_SWB5 and E_SWB0 to E_SWB4 can be set between multiple column blocks CB0 to CB18. Each of the multiple subword line blocks O_SWB0 to O_SWB5 and E_SWB0 to E_SWB4 may include at least one subword line driver, and each subword line driver can drive the corresponding subword line.

[0174] Multiple subword line blocks O_SWB0 to O_SWB5 and E_SWB0 to E_SWB4 can be classified as odd-numbered subword line blocks O_SWB0 to O_SWB5 and even-numbered subword line blocks E_SWB0 to E_SWB4.

[0175] Odd-numbered sub-word blocks O_SWB0 to O_SWB5 and even-numbered sub-word blocks E_SWB0 to E_SWB4 can be set alternately.

[0176] For example, the 0th odd-numbered sub-word block O_SWB0 can be located at the left edge of the memory array, and the 0th even-numbered sub-word block E_SWB0 can be located between the first column block CB1 and the second column block CB2. Additionally, the first odd-numbered sub-word block O_SWB1 can be located between the third column block CB3 and the fourth column block CB4, and the first even-numbered sub-word block E_SWB1 can be located between the fifth column block CB5 and the sixth column block CB6. Similarly, the second odd-numbered sub-word blocks O_SWB2 to the fifth odd-numbered sub-word blocks O_SWB5 and the second even-numbered sub-word blocks E_SWB2 to the fourth even-numbered sub-word blocks E_SWB4 can be alternately arranged.

[0177] Each of the odd-numbered subword line blocks O_SWB0 to O_SWB5 may include multiple odd-numbered subword line drivers.

[0178] For example, the 0th odd-numbered subword line block O_SWB0 may include multiple 0th odd-numbered subword line drivers O_SWD0. The first odd-numbered subword line block O_SWB1 may include multiple first odd-numbered subword line drivers O_SWD1. Similarly, the second odd-numbered subword line blocks O_SWB2 through the fifth odd-numbered subword line blocks O_SWB5 may each include multiple odd-numbered subword line drivers.

[0179] The odd-numbered subword line blocks O_SWB0 to O_SWB5 located at the edges may include a portion of the subword line driver.

[0180] For example, such as Figure 10 and Figure 11A As shown, the odd-numbered sub-word driver O_SWD0 included in the 0th odd-numbered sub-word block O_SWB0 located at the left edge can drive a single sub-word line O_SWL0 and can be electrically connected to the two column blocks CB0 and CB1. Therefore, the odd-numbered sub-word driver O_SWD0 included in the 0th odd-numbered sub-word block O_SWB0 can be a partial sub-word driver.

[0181] Additionally, for example, such as Figure 10 and Figure 11B As shown, the odd-numbered sub-word line driver O_SWD5 included in the fifth odd-numbered sub-word line block O_SWB5 located at the right edge can drive a single sub-word line O_SWL9 and can be electrically connected to a single column block CB18. Therefore, the odd-numbered sub-word line driver O_SWD5 included in the fifth odd-numbered sub-word line block O_SWB5 can be a partial sub-word line driver.

[0182] The odd-numbered subword line blocks set in the middle of the odd-numbered subword line blocks O_SWB0 to O_SWB5 may include normal subword line drivers.

[0183] For example, such as Figure 10 As shown, the odd-numbered sub-word line driver O_SWD1, located in the middle of the first odd-numbered sub-word line block O_SWB1, can drive two sub-word lines O_SWL1 and O_SWL2, and can be electrically connected to four column blocks CB2, CB3, CB4, and CB5. Therefore, the odd-numbered sub-word line driver O_SWD1 included in the first odd-numbered sub-word line block O_SWB1 can be a normal sub-word line driver. Similarly, the odd-numbered sub-word line drivers O_SWD2, O_SWD3, and O_SWD4 included in the second odd-numbered sub-word line blocks O_SWB2 to the fourth odd-numbered sub-word line blocks O_SWB4 can be normal sub-word line drivers.

[0184] Each of the even-numbered subword line blocks E_SWB0 to E_SWB4 may include multiple even-numbered subword line drivers.

[0185] For example, the 0th even-numbered subword line block E_SWB0 may include multiple 0th even-numbered subword line drivers E_SWD0. The first even-numbered subword line block E_SWB1 may include multiple first even-numbered subword line drivers E_SWD1. Similarly, the second even-numbered subword line blocks E_SWB2 through the fourth even-numbered subword line blocks E_SWB4 may each include multiple even-numbered subword line drivers.

[0186] The even-numbered subword line blocks E_SWB0 to E_SWB4 located at the edges may include a portion of the subword line driver.

[0187] For example, such as Figure 10 and Figure 11B As shown, the even-numbered subword line driver E_SWD4 included in the fourth even-numbered subword line block E_SWB4 located at the right edge can drive two subword lines E_SWL8 and E_SWL9, and can be electrically connected to three column blocks CB16, CB17, and CB18. Therefore, the even-numbered subword line driver E_SWD4 included in the fourth even-numbered subword line block E_SWB4 can be a partial subword line driver.

[0188] The even-numbered subword line blocks set in the middle of the even-numbered subword line blocks E_SWB0 to E_SWB4 may include normal subword line drivers.

[0189] For example, such as Figure 10 and Figure 11C As shown, the even-numbered sub-word line driver E_SWD1 included in the first even-numbered sub-word line block E_SWB1, located in the middle, can drive two sub-word lines E_SWL2 and E_SWL3, and can be electrically connected to four column blocks CB4, CB5, CB6, and CB7. Therefore, the even-numbered sub-word line driver E_SWD1 included in the first even-numbered sub-word line block E_SWB1 can be a normal sub-word line driver. Similarly, the even-numbered sub-word line drivers E_SWD0, E_SWD2, and E_SWD3 included in the 0th even-numbered sub-word line block E_SWB0, the second even-numbered sub-word line block E_SWB2, and the third even-numbered sub-word line block E_SWB3 can be normal sub-word line drivers.

[0190] Continue to refer to Figure 10 Each word line can include multiple sub-word lines. Each sub-word line can be driven by a corresponding sub-word line driver.

[0191] For example, word line 0 (WL0) may include multiple odd-numbered sub-word lines O_SWL0 to O_SWL9. ​​Each odd-numbered sub-word line may be driven by a corresponding odd-numbered sub-word line driver. For example, the 0th odd-numbered sub-word line O_SWL0 may be driven by the 0th odd-numbered sub-word line driver O_SWD0. The first odd-numbered sub-word line O_SWL1 and the second odd-numbered sub-word line O_SWL2 may be driven by the first odd-numbered sub-word line driver O_SWD1, the third odd-numbered sub-word line O_SWL3 and the fourth odd-numbered sub-word line O_SWL4 may be driven by the second odd-numbered sub-word line driver O_SWD2, the fifth odd-numbered sub-word line O_SWL5 and the sixth odd-numbered sub-word line O_SWL6 may be driven by the third odd-numbered sub-word line driver O_SWD3, and the seventh odd-numbered sub-word line O_SWL7 and the eighth odd-numbered sub-word line O_SWL8 may be driven by the fourth odd-numbered sub-word line driver O_SWD4. The ninth odd sub-word line O_SWL9 can be driven by the fifth odd sub-word line driver O_SWD5.

[0192] Similarly, the first word line WL1 may include multiple even-numbered sub-word lines E_SWL0 to E_SWL9, and each even-numbered sub-word line may be driven by a corresponding even-numbered sub-word line driver.

[0193] Figure 12 It is a simplification Figures 10 to 11C A diagram illustrating the layout relationships between subword drivers, subwords, and column blocks.

[0194] refer to Figure 12 According to some implementations, the 0th even-numbered subword line driver E_SWD0 to the 4th even-numbered subword line driver E_SWD4 can be located in the memory array.

[0195] The 0th even-numbered subword line driver E_SWD0 to the 3rd even-numbered subword line driver E_SWD3 can all be normal subword line drivers and can correspond to four column blocks.

[0196] For example, the 0th even-numbered subword line driver E_SWD0 can drive the 0th subword line SWL0 and the first subword line SWL1, and can be electrically connected to column blocks CB0 through CB3. The 0th subword line SWL0 is the subword line corresponding to column block CB0 and the first column block CB1, and can include the 0th odd-numbered subword line O_SWL0 (see [link to driver]). Figure 10 ) and the 0th even-numbered subword line E_SWL0 (see Figure 10 Additionally, the first subword line SWL1 is the subword line corresponding to the second column block CB2 and the third column block CB3, and may include the first odd-numbered subword line O_SWL1 (see [link]). Figure 10 ) and the first even-numbered subword line E_SWL1 (see Figure 10 ).

[0197] The fourth even-numbered subword line driver, E_SWD4, is a partial subword line driver and can correspond to three column blocks.

[0198] For example, the fourth even-numbered subword line driver E_SWD4 can drive the eighth subword line SWL8 and the ninth subword line SWL9, and can be electrically connected to the 16th column block CB16 to the 18th column block CB18.

[0199] According to some implementations, the 0th odd subword line driver O_SWD0 to the 5th odd subword line driver O_SWD5 can be located in the memory array.

[0200] The first odd-numbered subword line driver O_SWD1 to the fourth odd-numbered subword line driver O_SWD4 can all be normal subword line drivers, and can each correspond to one of the four column blocks.

[0201] For example, the first odd-numbered sub-word line driver O_SWD1 can drive the first sub-word line SWL1 and the second sub-word line SWL2, and can be electrically connected to the second column block CB2 to the fifth column block CB5.

[0202] The 0th odd subword line driver O_SWD0 and the 5th odd subword line driver O_SWD5 are both partial subword line drivers and can correspond to two column blocks and a single column block, respectively.

[0203] For example, the 0th odd-numbered sub-word line driver O_SWD0 can drive the 0th sub-word line SWL0 and can be electrically connected to the 0th column block CB0 and the first column block CB1. The 5th odd-numbered sub-word line driver O_SWD5 can drive the 9th sub-word line SWL9 and can be electrically connected to the 18th column block CB18.

[0204] The first region RG1 may include column blocks connected to the normal subword line driver. For example, the first region RG1 may include column blocks 0 through 17, CB17.

[0205] The subword line drivers corresponding to the second column block CB2 through the 15th column block CB15 can all be normal subword line drivers. For example, the second column block CB2 and the third column block CB3 correspond to the 0th even-numbered subword line driver E_SWD0 and the first odd-numbered subword line driver O_SWD1, and the 0th even-numbered subword line driver E_SWD0 and the first odd-numbered subword line driver O_SWD1 can both be normal subword line drivers.

[0206] Additionally, a portion of the subword line drivers corresponding to column 0 block CB0, column 1 block CB1, column 16 block CB16, and column 17 block CB17 can be normal subword line drivers, and the remainder can be partial subword line drivers. For example, column 0 block CB0 and column 1 block CB1 can correspond to even-numbered subword line driver E_SWD0 and odd-numbered subword line driver O_SWD0. Even-numbered subword line driver E_SWD0 can be a normal subword line driver, and odd-numbered subword line driver O_SWD0 can be a partial subword line driver.

[0207] The second region RG2 may include column blocks connected to partial subword line drivers. For example, the second region RG2 may include column block CB18 (column 18). The subword line drivers E_SWD4 and O_SWD5 corresponding to column block CB18 may both be partial subword line drivers.

[0208] Figure 13 This is a diagram illustrating a comparison example where column blocks corresponding to partial subword line drivers are assigned as parity blocks. For ease of description, the following definitions are used: Figure 13 The structure of the memory array and Figure 12 The memory arrays have the same structure. Additionally, a fault occurred in the 0th even-numbered subword line driver E_SWD0.

[0209] refer to Figure 13 In the comparison example, the column block of the second region RG2 is assigned as the parity block P.

[0210] The subword drivers E_SWD4 and O_SWD5, corresponding to the parity block P, were originally both partial subword drivers. Therefore, regardless of whether parity block P is assigned, subword drivers E_SWD4 and O_SWD5 can be unbounded subword drivers. Additionally, the 0th odd-numbered subword driver O_SWD0 in the first region RG1 is also a partial subword driver, and therefore can also be an unbounded subword driver.

[0211] Additionally, all column blocks corresponding to the eight normal subword line drivers E_SWD0 to E_SWD3 and O_SWD1 to O_SWD4 are allocated as data blocks and / or meta blocks. Therefore, all eight normal subword line drivers E_SWD0 to E_SWD3 and O_SWD1 to O_SWD4 can be bounded subword line drivers.

[0212] In these cases, when a fault occurs in one of the bounded subword line drivers, faults may occur in all four column blocks connected to it. Additionally, when a correction error occurs during ECC operation, the fault may propagate to another column block. For example, when a fault occurs in the 0th even-numbered subword line driver E_SWD0, the fault caused by the correction error mc may occur not only in the corresponding data blocks D0 through D3, but also in another data block D5. When the BF condition is restricted to a maximum of four sub-packets as described above, the BF condition may not be satisfied.

[0213] Therefore, to satisfy the BF condition, correction errors should not propagate to other column blocks even if a fault occurs in a bounded subword line driver. For example, bounded subword line drivers should be considered when designing the H matrix. This means that the design complexity of the H matrix increases with the number of bounded subword line drivers. Figure 13 In the comparison example, eight bounded subword line drivers should be considered when designing the H matrix.

[0214] Figure 14 This is a diagram illustrating some implementations where column blocks corresponding to normal subword line drivers are assigned as parity blocks. For ease of description, definitions are provided. Figure 14 The structure of the memory array and Figure 12 and Figure 13 The structure of the memory array is the same.

[0215] refer to Figure 14 According to some implementations, one of the column blocks in the first region RG1 can be assigned as parity block P. For example, the ninth column block in the first region RG1 can be assigned as parity block P.

[0216] The sub-word line drivers E_SWD2 and O_SWD2 corresponding to the parity block P are both normal sub-word line drivers. Since the parity block P is allocated, sub-word line drivers E_SWD2 and O_SWD2 can be classified as unbounded sub-word line drivers. Therefore, the number of bounded sub-word line drivers can be reduced by two. For example, in Figure 13 In the comparison examples, the number of delimited word line drivers is 8, while... Figure 14 In this implementation, the number of bounded subword line drivers can be reduced from 6 to 2. Therefore, when designing the H matrix, only 6 bounded subword line drivers need to be considered, thereby reducing the design complexity of the H matrix.

[0217] Continue to refer to Figure 14 The first region RG1 can be classified into three regions: RG1A, RG1B, and RG1C. In region RG1B, each column block can correspond to two normal subword line drivers. Therefore, as... Figure 14As shown, when one of the column blocks in region RG1B of 1B is assigned as parity block P, the two normal subword line drivers can be unbounded. For example, the number of bounded subword line drivers can be reduced by 2.

[0218] However, this is merely an example, and the implementation is not limited to this. According to some implementations, one of the column blocks in region RG1A of 1A or region RG1C of 1C can also be assigned as a parity block. The number of bounded subword line drivers can be reduced by 1. The following will... Figures 21 to 24 This will be described in more detail in the text.

[0219] Figure 15 This is a diagram illustrating a comparative example when column blocks corresponding to bounded subword line drivers are assigned as meta-blocks. For ease of description, the following definitions are used: Figure 15 The structure of the memory array and Figures 12 to 14 The memory bank array has the same structure. Additionally, the tenth column block is defined as being assigned as parity block P, and a failure occurs in the second odd-numbered subword line driver O_SWD2. Furthermore, the memory bank array is defined to operate in Mode 3.

[0220] refer to Figure 15 In the comparison example, the column blocks corresponding to the second odd subword line driver O_SWD2, which is a bounded subword line driver, are assigned as meta blocks M0 and M1.

[0221] In these cases, when a fault occurs in the second odd-numbered subword line driver O_SWD2, a fault may occur in the four column blocks D6, D7, M0, and M1 connected to the second odd-numbered subword line driver O_SWD2.

[0222] Similar to the operation of Mode 3 described above, the column selection lines of the 0th element block M0 can be mapped to data blocks D0 through D7, and the column selection lines of the 1st element block M1 can be mapped to data blocks D8 through D15. Therefore, the combination of data blocks that fail can be (D6, D7, D0 through D7, and D8 through D15). For example, failures can occur in combinations of data blocks such as (D6, D7, D0, D8), (D6, D7, D1, D8), ..., (D6, D7, D7, D14), and (D6, D7, D7, D15). As a result, when the BF condition is restricted to a maximum of four sub-packets as described above, many such combinations of data blocks must be considered when designing the H matrix. This indicates an increase in the design complexity of the H matrix.

[0223] Figure 16 This is a diagram illustrating an example of column blocks corresponding to unbounded subword line drivers being allocated as meta-blocks. For ease of description, the following definitions are provided. Figure 16The structure of the memory array and Figures 12 to 15 The structure is the same as that of the memory array. Additionally, it is similar to... Figure 14 Similarly, the ninth column block is defined as being assigned as parity block P.

[0224] refer to Figure 16 The ninth column block in the first region RG1 can be assigned as the parity block P. Therefore, the two normal subword line drivers E_SWD2 and O_SWD2 can be unbounded. The first region RG1 can be classified into a strongly bounded region SBRG, a weakly bounded region WBRG, and an unbounded region NBRG based on the bounded state of the subword line driver corresponding to each column block.

[0225] For example, data block 0, D0, and data block 1, D1, correspond to a single bounded subword line driver, E_SWD0. Therefore, data block 0, D0, and data block 1, D1, can belong to the first weakly bounded region, WBRG1.

[0226] For example, data blocks D2 through D5 correspond to two bounded subword line drivers. For instance, data blocks D2 and D3 correspond to two bounded subword line drivers E_SWD0 and O_SWD1, and data blocks D4 and D5 correspond to two bounded subword line drivers O_SWD1 and E_SWD1. Therefore, data blocks D2 through D5 can belong to the first strongly bounded region SBRG1.

[0227] For example, the sixth data block D6 and the seventh data block D7 correspond to a single bounded subword line driver E_SWD1. Therefore, the sixth data block D6 and the seventh data block D7 can belong to the second weakly bounded region WBRG2.

[0228] For example, the 0th element block M0 and the first parity block P do not correspond to the bounded subword line driver. Therefore, the 0th element block M0 and the first parity block P can belong to the first unbounded region NBRG1.

[0229] Similarly, the eighth data block D8 and the ninth data block D9 can belong to the third weakly bounded region WBRG3, the tenth data block D10 to the thirteenth data block D13 can belong to the second strongly bounded region SBRG2, and the fourteenth data block D14 and the fifteenth data block D15 can belong to the fourth weakly bounded region WBRG4.

[0230] The first element block M1 in the second region RG2 does not correspond to the bounded subword line driver, and therefore can belong to the second unbounded region NBRG2.

[0231] In these cases, according to some implementations, the zero-element block M0 can be assigned to the first unbounded region NBRG1. For example, the zero-element block M0 can be arranged adjacent to the parity block P. For example, the zero-element block M0 and the parity block P can correspond to the same subword line driver and the same subword line.

[0232] For example, even if a fault occurs in the second odd-numbered sub-word line driver O_SWD2, the combination of column blocks to be considered for the BF condition could be D6, D7, and M0. For instance, only three column blocks should be considered to satisfy the BF condition. When the BF condition is restricted to a maximum of four sub-packets as described above, the BF condition can be satisfied even if a correction error occurs. Therefore, when designing the H matrix, it is not necessary to consider the combination of data blocks. Alternatively, when considering the combination of data blocks, only the combinations of D6, D7, and D0 through D7 need to be considered. As a result, the design complexity of the H matrix can be reduced.

[0233] In addition, according to some implementation methods, such as Figure 16 As shown, the first metablock M1 can be assigned to the second unbounded region NBRG2. For example, the first metablock M1 can be assigned to the second region RG2 corresponding to a portion of the subword line.

[0234] For example, even if a fault occurs in the fourth even-numbered sub-word line driver E_SWD4, the combination of column blocks to be considered for the BF condition can be D14, D15, and M1. Therefore, when the BF condition is restricted to a maximum of four sub-packets as described above, the BF condition can be satisfied even if a correction error occurs. Therefore, when designing the H matrix, it is not necessary to consider the combination of data blocks. Alternatively, when considering the combination of data blocks, only the combinations of D14, D15, and D8 through D15 need to be considered. As a result, the design complexity of the H matrix can be reduced.

[0235] As a result, storage devices according to some implementations can reduce the design complexity of the H matrix by arranging element blocks M0 and M1 adjacent to the parity block P, or by arranging element blocks M0 and M1 at the edge of the storage array.

[0236] exist Figure 16 In this example, both metablocks M0 and M1 are described as column blocks assigned to an unbounded region. However, this is merely an example, and the implementation is limited to this. According to some implementations, only one of the two metablocks M0 and M1 can be placed in an unbounded region.

[0237] Figure 17 This is a block diagram illustrating a storage device 10B according to some embodiments. Figure 18 It shows Figure 17 A diagram illustrating an example of a memory array. Figure 17 and Figure 18 storage devices and storage arrays and Figure 1A and Figure 14 The storage devices and storage arrays are similar. Therefore, identical or similar configurations are indicated by identical or similar reference numerals, and redundant descriptions will be omitted.

[0238] exist Figures 1A to 18 In the text, the second region RG2 is described as being formed at the right edge of the memory array. For example, in... Figures 1A to 18 In this context, some sub-word lines are described as being positioned at the right edge of the memory array. However, this is merely illustrative, and implementations are not limited to this.

[0239] refer to Figure 17 and Figure 18 According to some embodiments, the storage device 10B may include a storage controller 100 and a storage device 200. In the storage bank array of each storage bank, a second region RG2 may be formed on the left side of the storage bank array. For example, the 0th even-numbered sub-word line driver E_SWD0 and the 0th odd-numbered sub-word line driver O_SWD0, which are part of the sub-word line drivers, may be located on the left side of the storage bank array.

[0240] According to some implementations, storage device 10B can select one of a plurality of normal subword line drivers in the first region RG1, and assign at least one column block of the column blocks corresponding to the selected normal subword line driver as parity block P. Additionally, the 0th element block M0 can be assigned to a subword line driver and a subword line corresponding to the same parity block P, and the first element block M1 can be assigned to a partial subword line driver.

[0241] Therefore, storage device 10B can meet BF conditions while supporting ECC operation and / or metadata mode.

[0242] Figure 19 This is a block diagram illustrating a storage device 10C according to some embodiments. Figure 20 It shows Figure 19 A diagram illustrating an example of a memory array. Figure 21 This is a block diagram illustrating a storage device 10D according to some embodiments. Figure 22 It shows Figure 21 A diagram illustrating an example of a memory array. Figures 19 to 22 storage devices and storage arrays and Figure 1A and Figure 14 The storage devices and storage arrays are similar. Therefore, identical or similar configurations are indicated by identical or similar reference numerals, and redundant descriptions will be omitted.

[0243] exist Figure 1A and Figure 14In this example, the first region RG1 is described as being divided into three regions RG1A, RG1B, and RG1C, and one of the column blocks in region RG1B is described as being assigned as parity block P. However, this is merely illustrative, and the implementation is not limited thereto.

[0244] refer to Figure 19 and Figure 20 Storage device 10C can assign one of the column blocks in region RG1A of 1A as parity block P.

[0245] In region 1A RG1A, each column block can correspond to a single normal subword line driver and a single partial subword line driver. Therefore, when one of the column blocks in region 1A RG1A is assigned as parity block P, the single normal subword line driver can be unbounded. For example, the number of bounded subword line drivers can be reduced by one. Therefore, compared to... Figure 13 Compared to the comparison examples, this can reduce the design complexity of the H matrix.

[0246] Alternative locations, for reference Figure 21 and Figure 22 According to some implementations, storage device 10D may assign one of the column blocks in 1C region RG1C as parity block P.

[0247] In region RG1C of 1C, each column block can correspond to a single normal subword line driver and a single partial subword line driver. Therefore, when one of the column blocks in region RG1C of 1C is assigned as parity block P, the single normal subword line driver can be unbounded. For example, the number of bounded subword line drivers can be reduced by one. Therefore, compared to... Figure 13 Compared to the comparison examples, this can reduce the design complexity of the H matrix.

[0248] Figure 23 This is a block diagram illustrating a storage device 10E according to some embodiments, and Figure 24 It shows Figure 23 A diagram illustrating an example of a memory array. Figure 23 and Figure 24 storage devices and storage arrays and Figures 1A to 18 The storage devices and storage arrays are similar. Therefore, identical or similar configurations are indicated by identical or similar reference numerals, and redundant descriptions will be omitted.

[0249] exist Figures 1A to 18 The text describes setting up two meta-blocks. However, this is merely illustrative, and the implementation is not limited to this. According to some implementations, only one meta-block may be set, or no meta-block may be set at all.

[0250] refer to Figure 23 and Figure 24According to some implementations, the storage device 10E may only have one element block M0. For example, as Figure 24 As shown, element block M0 can be assigned to a column block adjacent to the parity block P assigned to region RG1B of region 1B. The operation corresponding to Mode 2A described above can be performed. Alternatively, element block M0 can be assigned to a column block of the second region RG2, and the operation corresponding to Mode 2B described above can be performed.

[0251] As a result, according to some implementations, the storage device 10E can be configured with only one element and can support more than just one element. Figure 1A Metadata modes other than Mode 1.

[0252] As described above, according to the implementation, the storage device can satisfy bounded fault conditions while supporting error correction operations and / or metadata modes.

[0253] Although this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of any invention or claim, but rather as descriptions of features specific to a particular implementation of a particular invention. In a single embodiment, specific features described in the context of an independent embodiment may also be implemented in combination. Conversely, different features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in appropriate sub-combinations. Furthermore, although features may be described above as functioning in certain combinations, one or more features in a combination may be removed from the combination in some cases, and the combination may be for sub-combinations or variations thereof.

[0254] While various embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, comprising: A storage array, comprising multiple storage units; The line decoder is connected to the memory array via multiple word lines; as well as The column decoder is connected to the memory array via multiple column select lines. The storage array includes: The first region includes multiple normal subword line drivers, and The second region includes at least one partial subword line driver, and Among them, column blocks in a plurality of column blocks are assigned as parity blocks, and the plurality of column blocks correspond to the plurality of normal subword line drivers in the first region.

2. The storage device according to claim 1, wherein: The plurality of normal subword line drivers in the first region include: The first normal sub-word line driver is adjacent to one side of the memory bank array; The second normal sub-word line driver is adjacent to the second region; and The third normal sub-word line driver is located between the first normal sub-word line driver and the second normal sub-word line driver; and The column block connected to the column block of the third normal subword line driver is assigned as the parity block.

3. The storage device according to claim 1, wherein: The column block corresponding to the at least one sub-word line driver in the second region is assigned as a meta block.

4. The storage device according to claim 1, wherein: Among the plurality of column blocks in the first region, the column block adjacent to the parity block is assigned as a meta block.

5. The storage device according to claim 4, wherein: The parity block and the meta block correspond to the same subword line of the same normal subword line driver among the plurality of normal subword line drivers in the first region.

6. The storage device according to claim 1, wherein: The first column block adjacent to the parity check block among the plurality of column blocks in the first region is assigned as the first meta-block; and The second column block corresponding to the at least one sub-word line driver in the second region is assigned as the second meta block.

7. The storage device according to claim 1, wherein: The plurality of normal subword line drivers in the first region include: The first normal sub-word line driver is adjacent to one side of the memory bank array. The second normal sub-word line driver is adjacent to the second region, and A third normal sub-word line driver is located between the first and second normal sub-word line drivers of the plurality of normal sub-word line drivers; and The first column block connected to the first normal subword line driver is assigned as the parity block.

8. The storage device according to claim 7, wherein: A second column block adjacent to the first column block within the column block connected to the first normal sub-word line driver is assigned as a first element block; and A third column block corresponding to at least one of the sub-word line drivers in the second region is assigned as a second meta block.

9. The storage device according to claim 1, wherein: The plurality of normal subword line drivers in the first region include: The first normal sub-word line driver is adjacent to one side of the memory bank array. The second normal sub-word line driver is adjacent to the second region, and The third normal sub-word line driver is located between the first normal sub-word line driver and the second normal sub-word line driver; and The first column block connected to the column block of the second normal subword line driver is assigned as the parity block.

10. The storage device according to claim 9, wherein: The second column block adjacent to the first column block in the column block of the second normal sub-word line driver connected to the first region is assigned as the first element block; and A third column block corresponding to at least one of the sub-word line drivers in the second region is assigned as a second meta block.

11. The storage device according to claim 10, wherein: The parity check block, the first element block, and the second element block are adjacent to each other.

12. The storage device according to claim 1, wherein: The first normal subword line driver, which is assigned the parity block among the plurality of normal subword line drivers in the first region, is configured to operate as an unbounded subword line driver. The second normal subword line driver among the plurality of normal subword line drivers in the first region is configured to operate as a bounded subword line driver; and Based on the occurrence of a correction error in the bounded subword line driver, the region where the correction error occurs is limited to the column block corresponding to the bounded subword line driver.

13. The storage device according to claim 12, wherein: The at least one partial subword line driver in the second region is configured to operate as an unbounded subword line driver.

14. The storage device according to claim 1, wherein: Data output from the first region and data output from the second region are output simultaneously through a single read operation.

15. The storage device according to claim 1, wherein: The first column block of a plurality of column blocks corresponding to the plurality of normal subword line drivers in the first region is assigned as a data block; The second column block corresponding to the at least one partial sub-word line driver in the second region is assigned as a meta block; and The number of column select lines in the data block is less than the number of column select lines in the meta block.

16. A storage device comprising: A storage array, each storage array comprising multiple storage units; The line decoder is connected to the memory array via multiple word lines; as well as The column decoder is connected to the memory array via multiple column select lines. The storage array includes: The first region is adjacent to a first side of the memory array and includes column blocks positioned along the direction of the column decoder. The second region, adjacent to the first region, includes column blocks positioned along the direction of the column decoder. The third region, adjacent to the second region, includes column blocks positioned along the direction of the column decoder, and The fourth region, adjacent to the second side of the memory array, includes at least one column block positioned along the direction of the column decoder. Parity check data is configured to be output from the second region.

17. The storage device according to claim 16, wherein: In the meta-open mode, the parity data is configured to be output from the first column block in the second region, the first metadata is configured to be output from the second column block adjacent to the first column block in the second region, and the second metadata is configured to be output from the third column block in the fourth region.

18. The storage device according to claim 16, wherein: In the meta-enabled mode, the parity data is configured to be output from the first column block in the second region, and the metadata is configured to be output from one of the following: (i) the second column block in the second region that is adjacent to the first column block, or (ii) the third column block in the fourth region.

19. The storage device according to claim 16, wherein: The first region, the second region, and the third region all include column blocks corresponding to the normal subword line driver; and The fourth region includes column blocks corresponding to a portion of the subword line driver.

20. A storage device, comprising: Storage devices, including multiple memory banks; as well as The storage controller is configured to send data packets to and receive data packets from the plurality of storage units. The storage device includes: A storage array, comprising multiple storage cells, The line decoder is connected to the memory array via multiple word lines, and The column decoder is connected to the memory array via multiple column select lines, and The storage array includes: The first region includes multiple normal subword line drivers, and The second region includes at least one partial subword line driver, and Among them, column blocks of multiple column blocks corresponding to the multiple normal subword line drivers in the first region are assigned as parity blocks.

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