A phase uniform interleaved fully integrated coupled oscillatory dc-dc converter
By designing a fully integrated coupled oscillating DC-DC converter with uniform phase interleaving, the power loss problem of traditional converters in the process of high frequency is solved, current balance and high-speed switching control are realized, and the efficiency and response speed of the power supply system are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF MACAU
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-05
AI Technical Summary
Traditional buck converters face significant power loss issues during the process of increasing frequency, which limits their application in high-efficiency and high-power-density power supply systems.
Design a fully integrated coupled oscillating DC-DC converter with uniform phase interleaving. Employ a multiphase converter, error amplifier, and multiphase control logic module. Through a self-excited oscillator, switching rectifier, and charge recovery network, achieve uniform phase interleaving and current balance, reduce the number of inductors per phase, and adopt a fast start-up scheme.
It significantly improves load transient performance, reduces device complexity, and enhances the response speed and space utilization efficiency of the power supply system.
Smart Images
Figure CN122159693A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of DC-DC converter technology, and more specifically to a fully integrated coupled oscillation DC-DC converter with uniform phase interleaving. Background Technology
[0002] As applications such as AI CPU power supply and data centers place stringent demands on power systems for high efficiency and high power density, power technology must continuously evolve to meet these growing needs. Specifically, these fields require power supplies to provide stable power while minimizing energy loss and reducing physical size to support more complex computing tasks and more compact device layouts.
[0003] To further improve dynamic response and power density, DC-DC converters are evolving towards higher frequencies and smaller sizes, which helps accelerate power system response and optimize space utilization. Furthermore, this trend is driving innovation in power supply design to adapt to the rapidly changing technological environment.
[0004] However, traditional buck converters face significant power loss issues as the operating frequency increases, mainly including gate drive losses and switching losses, resulting in poor performance and limiting their effectiveness in practical applications. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a fully integrated coupled oscillation DC-DC converter with uniform phase interleaving.
[0006] The first aspect of this invention provides a fully integrated coupled oscillating DC-DC converter with uniform phase interleaving, comprising a multiphase converter, an error amplifier, and a multiphase control logic module. The multiphase converter consists of multiple cascaded single-phase converters. The signal output of a preceding single-phase converter is connected to the signal input of a subsequent single-phase converter, and the signal output of the final single-phase converter is connected to the signal input of the preceding single-phase converter and other intermediate single-phase converters. The load output of each single-phase converter is connected in parallel to the negative input of the error amplifier, outputting a voltage signal to the error amplifier. The positive input of the error amplifier is connected to a reference voltage input, and its output is connected to the multiphase control logic module. The error amplifier generates a control signal based on the multiphase converter output voltage and the reference voltage, and outputs it to the multiphase control logic module. The multiphase control logic module generates a corresponding pulse width modulation signal based on the control signal, which serves as the enable signal input for the single-phase converter, controlling the number of activated single-phase converters to achieve uniform phase interleaving of the multiphase converter output voltage.
[0007] Furthermore, each of the single-phase converters comprises a self-excited oscillator, a switching rectifier, and a charge recovery network; The self-excited oscillator includes a first resonant inductor, a second resonant inductor, a first NMOS transistor, a second NMOS transistor, a first input NMOS transistor, and a second input NMOS transistor; wherein the first NMOS transistor and the second NMOS transistor form a cross-coupled pair, the gate of the first NMOS transistor is connected to the drain of the second resonant inductor and the drain of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the first resonant inductor and the drain of the first NMOS transistor; the drain and source of the first input NMOS transistor are respectively connected to the drain and source of the first NMOS transistor, and the gate is connected to the positive inverting signal input in the signal input terminal; the second input NMOS transistor... The drain and source of the first NMOS transistor are connected to the drain and source of the second NMOS transistor, respectively, and the gate is connected to the negative phase signal input in the signal input terminal. The drain of the first NMOS transistor is connected to the positive phase signal output in the signal output terminal, and the drain of the second NMOS transistor is connected to the negative phase signal output in the signal output terminal. The sources of the first and second NMOS transistors are connected to the load output terminal. The self-excited oscillator uses the parasitic capacitance of the first and second NMOS transistors as the resonant capacitance to generate a resonant signal to control the first and second NMOS transistors to conduct alternately, and uses the resonant signal as the drive signal of the switching rectifier. The switching rectifier includes a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a filter inductor, a first filter capacitor, and a second filter capacitor. The third NMOS transistor, the fourth NMOS transistor, the first PMOS transistor, and the second PMOS transistor form a rectifier bridge. One end of the filter inductor is connected to the midpoint of the rectifier bridge, and the other end is connected to the load output terminal. The first filter capacitor is connected to the drain of the fourth NMOS transistor and the second PMOS transistor and to the positive phase signal output terminal. The second filter capacitor is connected to the drain of the third NMOS transistor and the first PMOS transistor and to the negative phase signal output terminal. The switching rectifier receives the drive signal from the self-excited oscillator through the first filter capacitor and the second filter capacitor for synchronous rectification, and outputs the rectified voltage signal to the load output terminal through the filter inductor. The charge recovery network includes multiple AC coupling capacitors; the AC coupling capacitors are disposed between the gate of the first NMOS transistor and the second resonant inductor, between the gate of the second NMOS transistor and the first resonant inductor, between the gate of the third NMOS transistor and the second filter capacitor, between the gate of the fourth NMOS transistor and the first filter capacitor, between the gate of the first PMOS transistor and the second filter capacitor, and between the gate of the second PMOS transistor and the first filter capacitor; the charge recovery network is used to form a capacitive voltage divider with the gate capacitance of the MOS transistor to achieve charge recovery.
[0008] Furthermore, each of the single-phase converters has a symmetrical and complementary first operating state and a second operating state; In the first operating state, in the self-excited oscillator, the first NMOS transistor is turned on and the second NMOS transistor is turned off; the parasitic capacitance of the second NMOS transistor and the second resonant inductor form a first resonant circuit, generating a resonant signal whose voltage rises first and then falls; this resonant signal is transmitted to the first NMOS transistor through the AC coupling capacitor to turn it on; the voltage at the drain of the first NMOS transistor is stabilized at the output voltage level and charges the first resonant inductor. In the switching rectifier, the third NMOS transistor and the second PMOS transistor are turned on, and the filter inductor acts as a current source, drawing current from the first resonant circuit through the second PMOS transistor; the third NMOS transistor outputs current to the first filter capacitor; the amount of charge released by the second resonant inductor is equal to the amount of charge received by the filter inductor; In the second operating state, in the self-excited oscillator, the second NMOS transistor is turned on and the first NMOS transistor is turned off; the parasitic capacitance of the first NMOS transistor and the first resonant inductor form a second resonant circuit, generating a resonant signal whose voltage rises first and then falls; this resonant signal is transmitted to the second NMOS transistor through the AC coupling capacitor to turn it on; the voltage at the drain of the second NMOS transistor is stabilized at the output voltage level and charges the second resonant inductor. In the switching rectifier, the fourth NMOS transistor and the first PMOS transistor are turned on, and the filter inductor acts as a current source, drawing current from the second resonant circuit through the first PMOS transistor; the fourth NMOS transistor outputs current to the second filter capacitor; the amount of charge released by the first resonant inductor is equal to the amount of charge received by the filter inductor.
[0009] Furthermore, the first input NMOS transistor and the second input NMOS transistor also constitute a fast start-up circuit. When the single-phase converter is activated, the first input NMOS transistor and the second input NMOS transistor are turned on simultaneously and apply the positive phase signal input and the negative phase signal input at the signal input terminal to the first resonant inductor and the second resonant inductor, so that the energy of the first resonant inductor and the second resonant inductor increases rapidly and triggers resonance.
[0010] Furthermore, the enable signal controls the activation and deactivation of the single-phase converter by controlling the voltage difference between the gate and source of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the first PMOS transistor, and the second PMOS transistor.
[0011] Furthermore, each of the single-phase converters has a multiplexer at its signal input port; in the first and last stage single-phase converters, the low-level input terminal of the multiplexer is left floating, and the high-level input terminal of the first stage single-phase converter is cross-coupled to the signal output terminal of the last stage single-phase converter; in the intermediate stage single-phase converter, the high-level input terminal of the multiplexer is directly coupled to the signal output terminal of the preceding stage single-phase converter, and the low-level input terminal is connected to the signal output terminal of the last stage single-phase converter; the signal input to the single-phase converter is selected by the multiplexer.
[0012] Furthermore, the error amplifier is a type II compensator, which integrates the error between the output voltage of the multiphase converter and the reference voltage to obtain a control signal that is output to the multiphase control logic module.
[0013] Furthermore, the multiphase control logic module generates a corresponding pulse width modulation signal based on the control signal, specifically including the following steps: Based on the number of single-phase converters in the multiphase converter, generate a corresponding number of ramp signals with different voltages; The voltage of the control signal is compared with the ramp signal. For the ramp signal whose voltage is not higher than the control signal, the multiphase control logic module outputs a high-level pulse width modulation signal to activate the corresponding single-phase converter. For the ramp signal whose voltage is higher than the control signal, the multiphase control logic module outputs a low-level pulse width modulation signal to shut down the corresponding single-phase converter.
[0014] Furthermore, the multiphase control logic module outputs the pulse width modulation signal through the following steps: The counting period is divided into multiple equal intervals, each interval corresponding to a phase of a single-phase converter; Based on the comparison result between the voltage of the control signal and the ramp signal, the pulse width modulation signals of the corresponding single-phase converters are output sequentially. The first / second input NMOS transistors of each phase and the corresponding NMOS transistors of the next phase are determined to be directly coupled or cross-coupled according to the Barkhausen criterion, so that the activation time of the corresponding single-phase converter is evenly distributed within the counting period, thereby realizing the phase uniform interleaving of the output voltage of the multi-phase converter.
[0015] Furthermore, it also includes a transient detection circuit; the transient detection circuit is connected in parallel between the negative phase input terminal and the output terminal of the error amplifier; the transient detection circuit is used to perform transient detection on the output voltage, and when the output voltage experiences a transient undershoot during a load transient, it instantaneously increases the voltage of the control signal output by the error amplifier.
[0016] The embodiments of the present invention have the following beneficial effects: The present invention provides a fully integrated coupled oscillating DC-DC converter with uniform phase interleaving, which, while retaining the gate charge recovery characteristics of a single-phase design, achieves inherent even-phase interleaving, current balancing per phase, and current balancing per inductor. The converter significantly improves load transient performance by reducing the number of inductors per phase, lowering device complexity, and employing a fast-start scheme to support high-speed switching control.
[0017] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the basic structure of a fully integrated coupled oscillation DC-DC converter with uniform phase interleaving according to the present invention. Figure 2 This is a schematic diagram illustrating the working principle of a single-phase converter in a fully integrated coupled oscillation DC-DC converter with uniform phase interleaving according to the present invention.
[0020] Figure reference numerals: #1~4 - Single-phase converter, EA - Error amplifier, L1 - First resonant inductor, L2 - Second resonant inductor, M1 - First NMOS transistor, M2 - Second NMOS transistor, M3 - Third NMOS transistor, M4 - Fourth NMOS transistor, M5 - First PMOS transistor, M6 - Second PMOS transistor, L3 - Filter inductor, M in1 -First input NMOS transistor, M in2 -Second input NMOS transistor, C F1 -First filter capacitor, C F2 - Second filter capacitor. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0022] The first aspect of this invention provides a fully integrated coupled oscillating DC-DC converter with uniform phase interleaving, such as... Figure 1As shown, the system includes a multiphase converter, an error amplifier, and a multiphase control logic module. The multiphase converter consists of multiple cascaded single-phase converters. The signal output of the preceding single-phase converter is connected to the signal input of the following single-phase converter, and the signal output of the final single-phase converter is connected to the signal input of the preceding single-phase converter and other intermediate single-phase converters. The load output of each single-phase converter is connected in parallel to the negative input of the error amplifier, outputting a voltage signal to the error amplifier. The positive input of the error amplifier is connected to a reference voltage input, and its output is connected to the multiphase control logic module. The error amplifier generates a control signal based on the multiphase converter output voltage and the reference voltage, and outputs it to the multiphase control logic module. The multiphase control logic module generates a corresponding pulse width modulation signal based on the control signal, which serves as the enable signal input for the single-phase converter, controlling the number of activated single-phase converters to ensure uniform phase interleaving of the multiphase converter output voltage.
[0023] This invention, while retaining the gate charge recovery characteristics of a single-phase design, achieves inherent even-phase interleaving, phase-to-phase current balancing, and inductor-to-inductor current balancing. The converter significantly improves load transient performance by reducing the number of inductors per phase, lowering device complexity, and employing a fast-start scheme to support high-speed switching control.
[0024] The implementation process of each part of this invention is described in detail below: Multiphase converter: In this embodiment of the invention, the multiphase converter consists of multiple cascaded single-phase converters. For example... Figure 1 As shown, each single-phase converter consists of a self-excited oscillator, a switching rectifier, and a charge recovery network; The self-excited oscillator includes a first resonant inductor, a second resonant inductor, a first NMOS transistor, a second NMOS transistor, a first input NMOS transistor, and a second input NMOS transistor. The first and second NMOS transistors form a cross-coupled pair. The gate of the first NMOS transistor is connected to the drain of the second resonant inductor and the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the drain of the first resonant inductor and the drain of the first NMOS transistor. The drain and source of the first input NMOS transistor are respectively connected to the drain and source of the first NMOS transistor, and its gate is connected to the positive inverting signal input in the signal input terminal. The second input NMOS transistor... The drain and source of the first NMOS transistor are connected to the drain and source of the second NMOS transistor, respectively, and the gate is connected to the negative phase signal input in the signal input terminal. The drain of the first NMOS transistor is connected to the positive phase signal output in the signal output terminal, and the drain of the second NMOS transistor is connected to the negative phase signal output in the signal output terminal. The sources of the first and second NMOS transistors are connected to the load output terminal. The self-excited oscillator uses the parasitic capacitance of the first and second NMOS transistors as the resonant capacitance to generate a resonant signal to control the first and second NMOS transistors to conduct alternately, and uses the resonant signal as the drive signal of the switching rectifier.
[0025] The switching rectifier includes a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a filter inductor, a first filter capacitor, and a second filter capacitor. The third NMOS transistor, the fourth NMOS transistor, the first PMOS transistor, and the second PMOS transistor form a rectifier bridge. One end of the filter inductor is connected to the midpoint of the rectifier bridge, and the other end is connected to the load output terminal. The first filter capacitor is connected to the drain of the fourth NMOS transistor and the second PMOS transistor and to the positive phase signal output terminal. The second filter capacitor is connected to the drain of the third NMOS transistor and the first PMOS transistor and to the negative phase signal output terminal. The switching rectifier receives the drive signal from the self-excited oscillator through the first and second filter capacitors for synchronous rectification, and outputs the rectified voltage signal to the load output terminal through the filter inductor. The charge recovery network includes multiple AC coupling capacitors; the AC coupling capacitors are disposed between the gate of the first NMOS transistor and the second resonant inductor, between the gate of the second NMOS transistor and the first resonant inductor, between the gate of the third NMOS transistor and the second filter capacitor, between the gate of the fourth NMOS transistor and the first filter capacitor, between the gate of the first PMOS transistor and the second filter capacitor, and between the gate of the second PMOS transistor and the first filter capacitor; the charge recovery network is used to form a capacitive voltage divider with the gate capacitance of the MOS transistors to achieve charge recovery.
[0026] In this embodiment of the invention, the gate of the first NMOS transistor is connected to the drain node (VTX-) of the second NMOS transistor via an AC coupling capacitor; similarly, the gate of the second NMOS transistor is connected to the drain node (VTX+) of the first NMOS transistor via an AC coupling capacitor. Therefore, these two stages generate a near-sinusoidal high-voltage slew rate resonant waveform with a 180-degree phase difference, acting as resonant nodes. The resonant signals generated by the VTX+ and VTX- resonant nodes satisfy the Barkhausen oscillation condition, driving the first and second NMOS transistors to conduct alternately, and simultaneously serving as the driving signal for the switching rectifier. The switching rectifier is directly driven by the VTX+ / VTX- resonant signals of the self-excited oscillator for synchronous rectification. The rectification process draws current from the first / second resonant inductor and supplies power to the load through a filter inductor. Simultaneously, an AC coupling capacitor is provided between the gates of each transistor, providing a fixed DC bias voltage, thus forming a capacitive voltage divider with the intrinsic gate capacitance of the transistor. When the resonant signal swings significantly, a moderately large AC voltage suitable for driving the switch is generated on the gate through capacitive voltage division. When a transistor is turned on, the charging energy of its gate capacitance comes from the resonant node; when it is turned off, most of this energy is fed back to the resonant node, thus achieving a charge recovery effect.
[0027] The operating state of the single-phase converter in this embodiment of the invention is as follows: Figure 2 As shown, each single-phase converter has a symmetrical and complementary first and second operating states; In the first operating state, in the self-excited oscillator, the first NMOS transistor is turned on and the second NMOS transistor is turned off; the parasitic capacitance of the second NMOS transistor and the second resonant inductor form the first resonant circuit, generating a resonant signal whose voltage rises first and then falls; this resonant signal is transmitted to the first NMOS transistor through the AC coupling capacitor to turn it on; the voltage at the drain of the first NMOS transistor is stabilized at the output voltage level and charges the first resonant inductor. In the switching rectifier, the third NMOS transistor and the second PMOS transistor are turned on, and the filter inductor acts as a current source, drawing current from the first resonant circuit through the second PMOS transistor; the third NMOS transistor outputs current to the first filter capacitor; the amount of charge released by the second resonant inductor is equal to the amount of charge received by the filter inductor. In the second operating state, in the self-excited oscillator, the second NMOS transistor is turned on and the first NMOS transistor is turned off; the parasitic capacitance of the first NMOS transistor and the first resonant inductor form a second resonant circuit, generating a resonant signal whose voltage rises first and then falls; this resonant signal is transmitted to the second NMOS transistor through the AC coupling capacitor to turn it on; the voltage at the drain of the second NMOS transistor is stabilized at the output voltage level and charges the second resonant inductor. In the switching rectifier, the fourth NMOS transistor and the first PMOS transistor are turned on. The filter inductor acts as a current source, drawing current from the second resonant circuit through the first PMOS transistor. The fourth NMOS transistor outputs current to the second filter capacitor. The amount of charge released by the first resonant inductor is equal to the amount of charge received by the filter inductor.
[0028] In this embodiment of the invention, due to the complete symmetry of the circuit, the duration of each operating state is determined by the first resonant circuit and its resonant period. Since the periods of these two resonant circuits are naturally equal, an inherent 50% duty cycle operation is achieved. Simultaneously, since the charge Q1 flowing through the first resonant inductor is equal to the charge Q2 flowing through the second resonant inductor, automatic DC current balancing is naturally achieved among the first resonant inductor, the second resonant inductor, and the filter inductor. When the circuit state switches, this embodiment of the invention recovers charge through the first and second filter capacitors directly connected between the resonant node and the rectifier bridge. For example, when the circuit switches from the first operating state to the second operating state, the previously conducting third NMOS transistor and second PMOS transistor turn off, and the charge on their gate capacitors is drawn away through the first filter capacitor. Simultaneously, this charge is injected through the second filter capacitor into the gate capacitors of the soon-to-be-conducted fourth NMOS transistor and first PMOS transistor, thereby realizing the internal recycling of driving energy between the switching pairs and significantly reducing the power consumption of the driving circuit itself.
[0029] Preferably, in this embodiment of the invention, the DC bias level (VBIAS, VBIASn, or BVIASp) of the MOS transistor gate is selected to minimize power switching losses. To disable under light load, each gate is pulled to its source by an enable signal.
[0030] In some embodiments, the first and second input NMOS transistors also constitute a fast-start circuit. When the single-phase converter is activated, the first and second input NMOS transistors simultaneously turn on, applying the positive and negative phase signals from the signal input terminals to the first and second resonant inductors. This causes the energy of the first and second resonant inductors to increase rapidly and trigger resonance. This embodiment of the invention uses a fast-start circuit to instantaneously close the first and second input NMOS transistors, directly applying the input voltage to the first and second resonant inductors, causing their current to rise rapidly and linearly. This bypasses the resonance establishment process, greatly shortening the circuit's response time and significantly enhancing the load transient performance.
[0031] In some embodiments, each single-phase converter's signal input port is equipped with a multiplexer. In the first and last stage single-phase converters, the low-level input terminal of the multiplexer is left floating, and the high-level input terminal of the first-stage single-phase converter is cross-coupled to the signal output terminal of the last-stage single-phase converter. In the intermediate stage single-phase converter, the high-level input terminal of the multiplexer is directly coupled to the signal output terminal of the preceding stage single-phase converter, and the low-level input terminal is connected to the signal output terminal of the last stage single-phase converter. The signal input to the single-phase converter is selected by the multiplexer. In this embodiment of the invention, the multiplexer enables free adjustment of the number of single-phase converters in the multi-phase converter and automatic phase interleaving distribution. The signal output terminal of the single-phase converter is connected to the high-level input terminal of the next-phase multiplexer, forming a circular phase chain. The phase is sequentially transmitted and offset to subsequent single-phase converters. When a single-phase converter is disabled, the multiplexer can directly route the signal from the previous stage to the next stage, maintaining the continuity of the phase chain.
[0032] Specifically, the enable signal controls the activation and deactivation of the single-phase converter by controlling the voltage difference between the gate and source of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the first PMOS transistor, and the second PMOS transistor.
[0033] Error amplifier: In this embodiment of the invention, the error amplifier is a type II compensator, which integrates the error between the output voltage of the multiphase converter and the reference voltage to obtain a control signal output to the multiphase control logic module.
[0034] Multiphase control logic module: In this embodiment of the invention, the multiphase logic control module generates a corresponding pulse width modulation signal based on the control signal, specifically including the following steps: S101. Generate a corresponding number of ramp signals with different voltages based on the number of single-phase converters in the multiphase converter; S102. Compare the voltage of the control signal with the ramp signal. For the ramp signal whose voltage is not higher than the control signal, the multiphase control logic module outputs a high-level pulse width modulation signal to activate the corresponding single-phase converter. For the ramp signal whose voltage is higher than the control signal, the multiphase control logic module outputs a low-level pulse width modulation signal to shut down the corresponding single-phase converter.
[0035] Preferably, the multiphase control logic module outputs the pulse width modulation signal through the following steps: The counting period is divided into multiple equal intervals, each interval corresponding to a phase of a single-phase converter; Based on the comparison results of the control signal voltage and the ramp signal, the pulse width modulation signals of the corresponding single-phase converters are output sequentially. The coupling mode between the first / second input NMOS transistor of each phase and the corresponding NMOS transistor of the next phase is determined by the Barkhausen criterion as either direct coupling or cross coupling, so that the activation time of the corresponding single-phase converter is evenly distributed within the counting period, thereby realizing the phase interleaving of the output voltage of the multi-phase converter.
[0036] In this embodiment of the invention, the multiphase control logic module converts the control signal (V) output by the error amplifier into a signal that is controlled by the error amplifier. EA ), and the four internally generated low-frequency ramp signals (V) with sequentially delayed phases. RAMP_i The comparison is performed using (i=1~4). Based on the comparison results, a multi-channel digital enable signal (EN) is dynamically generated. j It precisely controls the operating state of each phase in the multiphase converter (continuous on, pulse width modulation start / stop, or off), thereby enabling flexible expansion (phase expansion) and reduction (phase reduction) of the number of phases, optimizing efficiency and transient response under different loads.
[0037] In some embodiments, a transient detection circuit is also included; the transient detection circuit is connected in parallel between the negative input terminal and the output terminal of the error amplifier; the transient detection circuit is used to detect transients in the output voltage, and when a transient undershoot occurs in the output voltage during a load transient, it instantaneously increases the voltage of the control signal output by the error amplifier. This embodiment of the invention detects the undershoot of the output voltage through the transient detection circuit and instantaneously raises the voltage of the control signal to achieve maximum output current supply.
[0038] Compared with traditional multiphase buck converters, the converter in this embodiment of the invention has the following features: 1) Gate charge recovery to reduce gate losses; 2) The inherent phase interleaving can be achieved without complex active control; 3) Inherent phase current balance.
[0039] Compared to existing oscillator-based converters (EMLC), this invention further achieves the following: 1) Expand to multiphase operation; 2) Reduce the number of inductors per phase from 4 to 3; 3) Ensure inherent current balance in each inductor; 4) Propose a fast start-up scheme to achieve high-speed switching operation and enhance load transient performance.
[0040] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0041] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.
[0042] In embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of the present invention may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.
[0043] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. Other embodiments of the present invention will readily conceive of by considering the specification and practicing the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.
Claims
1. A fully integrated coupled oscillating DC-DC converter with uniform phase interleaving, characterized in that, The system includes a multiphase converter, an error amplifier, and a multiphase control logic module. The multiphase converter consists of multiple cascaded single-phase converters. The signal output of the preceding single-phase converter is connected to the signal input of the following single-phase converter, and the signal output of the final single-phase converter is connected to the signal input of the preceding single-phase converter and other intermediate single-phase converters. The load output of each single-phase converter is connected in parallel to the negative input of the error amplifier, outputting a voltage signal to the error amplifier. The positive input of the error amplifier is connected to a reference voltage input, and its output is connected to the multiphase control logic module. The error amplifier is used to generate a control signal based on the output voltage and reference voltage of the multiphase converter and output it to the multiphase control logic module. The multiphase control logic module generates a corresponding pulse width modulation signal based on the control signal, which is used as the enable signal input of the single-phase converter to control the number of activated single-phase converters so that the phases of the multiphase converter output voltage are uniformly interleaved.
2. The fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 1, characterized in that, Each of the single-phase converters consists of a self-excited oscillator, a switching rectifier, and a charge recovery network; The self-excited oscillator includes a first resonant inductor, a second resonant inductor, a first NMOS transistor, a second NMOS transistor, a first input NMOS transistor, and a second input NMOS transistor; wherein the first NMOS transistor and the second NMOS transistor form a cross-coupled pair, the gate of the first NMOS transistor is connected to the drain of the second resonant inductor and the drain of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the drain of the first resonant inductor and the drain of the first NMOS transistor; the drain and source of the first input NMOS transistor are respectively connected to the drain and source of the first NMOS transistor, and the gate is connected to the positive inverting signal input in the signal input terminal; the second input NMOS transistor... The drain and source of the first NMOS transistor are connected to the drain and source of the second NMOS transistor, respectively, and the gate is connected to the negative phase signal input in the signal input terminal. The drain of the first NMOS transistor is connected to the positive phase signal output in the signal output terminal, and the drain of the second NMOS transistor is connected to the negative phase signal output in the signal output terminal. The sources of the first and second NMOS transistors are connected to the load output terminal. The self-excited oscillator uses the parasitic capacitance of the first and second NMOS transistors as the resonant capacitance to generate a resonant signal to control the first and second NMOS transistors to conduct alternately, and uses the resonant signal as the drive signal of the switching rectifier. The switching rectifier includes a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a filter inductor, a first filter capacitor, and a second filter capacitor. The third NMOS transistor, the fourth NMOS transistor, the first PMOS transistor, and the second PMOS transistor form a rectifier bridge. One end of the filter inductor is connected to the midpoint of the rectifier bridge, and the other end is connected to the load output terminal. The first filter capacitor is connected to the drain of the fourth NMOS transistor and the second PMOS transistor and to the positive phase signal output terminal. The second filter capacitor is connected to the drain of the third NMOS transistor and the first PMOS transistor and to the negative phase signal output terminal. The switching rectifier receives the drive signal from the self-excited oscillator through the first filter capacitor and the second filter capacitor for synchronous rectification, and outputs the rectified voltage signal to the load output terminal through the filter inductor. The charge recovery network includes multiple AC coupling capacitors; the AC coupling capacitors are disposed between the gate of the first NMOS transistor and the second resonant inductor, between the gate of the second NMOS transistor and the first resonant inductor, between the gate of the third NMOS transistor and the second filter capacitor, between the gate of the fourth NMOS transistor and the first filter capacitor, between the gate of the first PMOS transistor and the second filter capacitor, and between the gate of the second PMOS transistor and the first filter capacitor; the charge recovery network is used to form a capacitive voltage divider with the gate capacitance of the MOS transistor to achieve charge recovery.
3. The fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 2, characterized in that, Each of the single-phase converters has a symmetrical and complementary first operating state and a second operating state; In the first operating state, in the self-excited oscillator, the first NMOS transistor is turned on and the second NMOS transistor is turned off; the parasitic capacitance of the second NMOS transistor and the second resonant inductor form a first resonant circuit, generating a resonant signal whose voltage rises first and then falls; this resonant signal is transmitted to the first NMOS transistor through the AC coupling capacitor to turn it on; the voltage at the drain of the first NMOS transistor is stabilized at the output voltage level and charges the first resonant inductor. In the switching rectifier, the third NMOS transistor and the second PMOS transistor are turned on, and the filter inductor acts as a current source, drawing current from the first resonant circuit through the second PMOS transistor; the third NMOS transistor outputs current to the first filter capacitor; the amount of charge released by the second resonant inductor is equal to the amount of charge received by the filter inductor; In the second operating state, in the self-excited oscillator, the second NMOS transistor is turned on and the first NMOS transistor is turned off; The parasitic capacitance of the first NMOS transistor and the first resonant inductor form a second resonant circuit, generating a resonant signal whose voltage rises and then falls. This resonant signal is transmitted to the second NMOS transistor through an AC coupling capacitor, which turns it on. The voltage at the drain of the second NMOS transistor is stabilized at the output voltage level, and it charges the second resonant inductor. In the switching rectifier, the fourth NMOS transistor and the first PMOS transistor are turned on, and the filter inductor acts as a current source, drawing current from the second resonant circuit through the first PMOS transistor; the fourth NMOS transistor outputs current to the second filter capacitor; the amount of charge released by the first resonant inductor is equal to the amount of charge received by the filter inductor.
4. A fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 2, characterized in that, The first input NMOS transistor and the second input NMOS transistor also constitute a fast start-up circuit. When the single-phase converter is activated, the first input NMOS transistor and the second input NMOS transistor are turned on simultaneously and apply the positive phase signal input and the negative phase signal input at the signal input terminal to the first resonant inductor and the second resonant inductor, so that the energy of the first resonant inductor and the second resonant inductor increases rapidly and triggers resonance.
5. A fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 2, characterized in that, The enable signal controls the activation and deactivation of the single-phase converter by controlling the voltage difference between the gate and source of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the first PMOS transistor, and the second PMOS transistor.
6. The fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 1, characterized in that, Each of the single-phase converters has a multiplexer at its signal input port. In the first and last stage single-phase converters, the low-level input of the multiplexer is left floating, and the high-level input of the first stage single-phase converter is cross-coupled to the signal output of the last stage single-phase converter. In the intermediate stage single-phase converter, the high-level input of the multiplexer is directly coupled to the signal output of the preceding stage single-phase converter, and the low-level input is connected to the signal output of the last stage single-phase converter. The signal input to the single-phase converter is selected by the multiplexer.
7. A fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 1, characterized in that, The error amplifier is a type II compensator. It integrates the error between the output voltage of the multiphase converter and the reference voltage to obtain a control signal, which is then output to the multiphase control logic module.
8. A fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 1, characterized in that, The multiphase control logic module generates a corresponding pulse width modulation signal based on the control signal, specifically including the following steps: Based on the number of single-phase converters in the multiphase converter, generate a corresponding number of ramp signals with different voltages; The voltage of the control signal is compared with the ramp signal. For the ramp signal whose voltage is not higher than the control signal, the multiphase control logic module outputs a high-level pulse width modulation signal to activate the corresponding single-phase converter. For the ramp signal whose voltage is higher than the control signal, the multiphase control logic module outputs a low-level pulse width modulation signal to shut down the corresponding single-phase converter.
9. A fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 8, characterized in that, The multiphase control logic module outputs a pulse width modulation signal through the following steps: The counting period is divided into multiple equal intervals, each interval corresponding to a phase of a single-phase converter; Based on the comparison result between the voltage of the control signal and the ramp signal, the pulse width modulation signals of the corresponding single-phase converters are output sequentially. The first / second input NMOS transistors of each phase and the corresponding NMOS transistors of the next phase are determined to be directly coupled or cross-coupled according to the Barkhausen criterion, so that the activation time of the corresponding single-phase converter is evenly distributed within the counting period, thereby realizing the phase uniform interleaving of the output voltage of the multi-phase converter.
10. A fully integrated coupled oscillating DC-DC converter with uniform phase interleaving according to claim 1, characterized in that, It also includes a transient detection circuit; the transient detection circuit is connected in parallel between the negative phase input terminal and the output terminal of the error amplifier; the transient detection circuit is used to detect the transient output voltage, and when the output voltage experiences a transient undershoot during a load transient, it instantaneously increases the voltage of the control signal output by the error amplifier.