Modulation, power balance method and extended topology system of hybrid cascaded h-bridge inverter

Abstract

The application discloses a modulation and power balance method of a hybrid cascaded H-bridge inverter and an extended topology system, belongs to the technical field of power electronic converters, and core comprises the following steps: constructing a thirteen-level basic topology with a DC side voltage ratio of 1:1:2:2, which is cascaded by two low-voltage H-bridge units and two high-voltage H-bridge units; adopting a hybrid modulation strategy, the high-voltage unit works at a fundamental frequency by using a staircase wave modulation to reduce loss, and the low-voltage unit uses an improved carrier phase-shifted PWM modulation based on a reconstructed laminated triangular carrier to eliminate reverse circulating current and improve the equivalent switching frequency; the high-voltage unit driving signals are cyclically exchanged with 1 / 4 output voltage period as a rotation period, so that power self-balance is realized; and a general extended topology scheme is provided, which is cascaded by n high-voltage modules and k low-voltage modules, avoids level loss under the constraint of k≥m, and can use the modulation and power balance logic of the basic topology.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter technology, specifically to a modulation method, a power equalization control method, and an extended topology system for a hybrid cascaded H-bridge multilevel inverter. Background Technology

[0002] Multilevel inverters are widely used in medium-voltage motor drives and new energy grid connection due to their advantages such as high output waveform quality, low electromagnetic interference, and suitability for medium and high voltage applications. Cascaded H-bridge inverters are favored for their modular design and ease of expansion.

[0003] However, in application scenarios where the number of modules is limited, hybrid cascaded H-bridge inverters (i.e., each H-bridge unit has a different DC-side voltage) can output more levels with fewer devices by optimizing the voltage ratio, but they also introduce new technical challenges: 1) Traditional hybrid modulation strategies are prone to backflow of current between high-voltage and low-voltage units, increasing losses and device stress; 2) Due to the different fundamental components of the output voltage of each unit, the power is unevenly distributed among the units, affecting the system reliability and lifespan; 3) Existing power balancing schemes mostly rely on complex closed-loop control, which is difficult and costly to implement; 4) The voltage ratio of existing hybrid topologies is fixed, and there is a lack of a systematic and universal expansion method, making it difficult to flexibly adapt to the needs of different voltage levels and number of levels.

[0004] Therefore, there is an urgent need to propose a hybrid cascaded H-bridge inverter solution that can simultaneously solve the problems of reverse circulating current (current backflow) and power balance, has simple control logic, and has good scalability. Summary of the Invention

[0005] 1. Technical problem to be solved: This invention aims to overcome the shortcomings of existing technologies and provide a modulation and power balancing method and an extended topology system for hybrid cascaded H-bridge inverters.

[0006] 2. Technical Solution: To solve the above problems, the present invention adopts the following technical solution.

[0007] In a first aspect, the present invention provides a modulation and power equalization method for a hybrid cascaded H-bridge inverter, comprising: Step S1: Construct the basic topology of the hybrid cascaded H-bridge inverter. This basic topology consists of two low-voltage H-bridge units with a DC-side voltage of E and two high-voltage H-bridge units with a DC-side voltage of 2E cascaded together, which can output thirteen levels from 0 to ±6E.

[0008] Step S2: A hybrid modulation strategy is adopted. The high-voltage H-bridge unit uses stepped-wave modulation, directly comparing the sinusoidal modulated wave with a fixed potential, operating at the fundamental frequency, which greatly reduces switching losses. The low-voltage H-bridge unit uses improved carrier phase-shift PWM modulation. This modulation constructs forward and reverse stacked triangular carrier bands by layering a single isosceles triangular carrier in the amplitude direction and dividing and recombining it in the time direction. The reconstructed carrier bands are then phase-shifted to generate multiple phase-shifted carriers. Based on these phase-shifted carriers, the switching transistors of the low-voltage unit are controlled to ensure that the polarity of the synthesized output voltage on the low-voltage side remains consistent with that on the high-voltage side, thereby fundamentally eliminating the reverse circulating current phenomenon. At the same time, this modulation method increases the equivalent switching frequency of the low-voltage unit to eight times the carrier frequency, optimizing the output harmonic spectrum.

[0009] Step S3: Implement high-voltage unit power self-balancing. Using a 1 / 4 cycle of the output voltage as the switching period, the drive signals of the two high-voltage units are cyclically exchanged (i.e., they take turns undertaking the modulation task of high and low comparison potentials). After half a cycle, the average output voltages of the two high-voltage units are equal, thus achieving automatic power balancing. This method requires no current sampling or complex calculations, and the control is simple and reliable.

[0010] Step S4: Propose a general extension scheme. Based on the basic topology, a general extension topology is proposed, consisting of n high-voltage modules with DC voltage mE and k low-voltage modules with DC voltage E cascaded together. To ensure the continuity of the output level, the constraint k≥m must be satisfied. This extension topology can fully utilize the hybrid modulation strategy and 1 / 4-cycle alternating power balancing method of the basic topology, requiring only adjustment of the modulation wave and comparison potential parameters. No redesign of the control algorithm is necessary, demonstrating extremely high scalability.

[0011] Secondly, the present invention provides a system for implementing the above method, comprising a topology construction module, a hybrid modulation module, a power balancing module, and an extended control module.

[0012] Thirdly, the present invention provides an electronic device comprising a processor and a memory, wherein the memory stores a computer program that, when executed, can implement the above-described method.

[0013] 3. Beneficial effects: Compared with the prior art, the technical solution provided by this invention has the following advantages: (1) Effectively eliminate reverse circulating current: Through improved CPS-PWM modulation, the polarity consistency between the low-voltage side synthesized voltage and the high-voltage side voltage is forcibly guaranteed, which eliminates the circulating current between the high and low voltage DC sources in principle and improves the system reliability; Through the 1 / 4 cycle rotation strategy, the power self-balancing between high-voltage units is realized, without the need for closed-loop control, and the dynamic response is fast.

[0014] (2) Optimization of switching losses: The high-voltage unit operates at the fundamental frequency, resulting in extremely low switching losses; although the low-voltage unit operates at a high frequency, its switching losses are relatively small due to its low voltage level. The overall system efficiency is optimized.

[0015] (3) Power balancing is simple and reliable: The open-loop power balancing method based on fixed cycle rotation is adopted. There is no need for complex real-time calculation or sensor feedback. The control logic is extremely simple, easy to implement digitally, and has fast dynamic response and strong robustness.

[0016] (4) Excellent output harmonic characteristics: The equivalent switching frequency of the low-voltage unit is increased to eight times the carrier frequency, which effectively suppresses the low-order harmonics of the output voltage and shifts the harmonic spectrum to a higher frequency, reducing the design difficulty and size of the output filter.

[0017] (5) Strong topology scalability: The proposed general extended topology and the corresponding modulation and balancing rules form a complete scalable solution. Users only need to configure the parameters (n,m,k) according to the target voltage and level number to automatically adapt, which greatly enhances the engineering practical value and application flexibility of the present invention.

[0018] (6) Combining cost and reliability: The thirteen-level basic topology achieves the same output performance but saves the number of switching devices compared to the traditional symmetrical cascaded H-bridge topology, reducing system cost and potential failure points.

[0019] It should be noted that any parts not mentioned in this invention are the same as or can be implemented using existing technologies, and will not be described in detail here. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the basic thirteen-level hybrid cascaded H-bridge topology provided in an embodiment of the present invention.

[0021] Figure 2 This is a waveform diagram illustrating the stepped wave modulation principle of the high-voltage unit in an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of the triangular carrier reconstruction process in an embodiment of the present invention; (a) is the original single triangular carrier, and (b) is the reconstructed stacked triangular carrier band.

[0023] Figure 4 (a) is a schematic diagram of the improved carrier phase-shift modulation of the low-voltage unit of the present invention; Figure 4 (b) is a schematic diagram of the output voltage waveform of the inverter with improved carrier phase shift according to the present invention; Figure 5 This is a schematic diagram of the power balance mechanism of the high-voltage unit in this invention; Figure 6 This is a schematic diagram of the general extended topology of the hybrid cascaded H-bridge inverter of the present invention; Figure 7 (a) is a schematic diagram of the high voltage module modulation strategy principle of the general extended topology of the hybrid cascaded H-bridge inverter of the present invention; Figure 7 (b) is a schematic diagram of the low-voltage module modulation strategy principle of the general extended topology of the hybrid cascaded H-bridge inverter of the present invention. Figure 8 (a) is a schematic diagram of the output voltage waveforms under different modulation indices under the conventional modulation of the basic topology of this invention; Figure 8 (b) is a schematic diagram of the output voltage waveforms under different modulation intensities under the basic topology improvement modulation of the present invention; Figure 9 (a) M is the traditional modulation strategy of the basic topology of this invention. a Schematic diagram of the output voltage spectrum when =0.9; Figure 9 (b) is the M under the traditional modulation strategy of the basic topology of this invention. a Schematic diagram of the output voltage spectrum when =0.6 (harmonics are concentrated at 12kHz); Figure 10 (a) M under the basic topology improvement modulation strategy of this invention a Schematic diagram of the output voltage spectrum when =0.9; Figure 10 (b) M under the basic topology improvement modulation strategy of this invention a Schematic diagram of the output voltage spectrum when =0.6 (harmonics are concentrated at 24kHz); Figure 11 This is a schematic representation of the output level and switch state mapping in the thirteen-level basic topology of Embodiment 1 of the present invention; Figure 12 (a) is a schematic diagram of the voltage output waveforms of the high-voltage and low-voltage units of the inverter when Ma=0.9 in this invention; Figure 12 (b) is a schematic diagram of the voltage output waveform and corresponding spectrum of the inverter when Ma=0.9 according to the present invention; Figure 13 (a) is a schematic diagram of the voltage output waveforms of the high-voltage and low-voltage units of the inverter when Ma=0.9 in this invention; Figure 13 (b) is a schematic diagram of the voltage output waveform and corresponding spectrum of the inverter when Ma=0.9 according to the present invention; Figure 14 (a) is a schematic diagram of the experimental waveforms of the output voltage, current and instantaneous power of the inverter L1 unit when Ma=0.9 according to the present invention; Figure 14 (b) is a schematic diagram of the experimental waveforms of the output voltage, current and instantaneous power of the inverter L2 unit when Ma=0.9 according to the present invention; Figure 14 (c) is a schematic diagram of the output voltage, current and instantaneous power of inverter H1 unit when Ma=0.9 according to the present invention; Figure 13(d) is a schematic diagram of the experimental waveforms of the output voltage, current and instantaneous power of the inverter H2 unit when Ma=0.9 in this invention; Figure 15 (a) is a schematic diagram of the output voltage, current and instantaneous power of the inverter L1 unit when Ma=0.6 according to the present invention; Figure 15 (b) is a schematic diagram of the experimental waveforms of the output voltage, current and instantaneous power of the inverter L2 unit when Ma=0.6 according to the present invention; Figure 15 (c) is a schematic diagram of the experimental waveforms of the output voltage, current and instantaneous power of the inverter H1 unit when Ma=0.6 according to the present invention; Figure 15 (d) is a schematic diagram of the output voltage, current and instantaneous power of the inverter H2 unit when Ma=0.6 according to the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, specific embodiments of the invention will be described in detail below with reference to the accompanying drawings. The following embodiments are for illustrative purposes only and should not be considered as limitations on the invention.

[0025] Example 1: Specific Implementation of a Hybrid Cascaded H-Bridge Thirteen-Level Inverter This embodiment uses Figure 1 Taking the thirteen-level basic topology shown as an example, the specific implementation of the present invention will be explained.

[0026] 1. Topology Construction like Figure 1 As shown, a basic topology for a hybrid cascaded H-bridge inverter is constructed. This topology consists of two low-voltage H-bridge units (L1, L2) and two high-voltage H-bridge units (H1, H2) cascaded together. The DC-side voltage of the low-voltage H-bridge units is E, and the DC-side voltage of the high-voltage H-bridge units is 2E. For ease of explanation, the DC-side voltage of the low-voltage unit is set to E = 100V, and the DC-side voltage of the high-voltage unit is set to 2E = 200V. Each H-bridge unit consists of four switching transistors and their anti-parallel diodes. By controlling the on / off combinations of the switching transistors in each unit, this topology can output thirteen voltage levels (±6E, ±5E, ±4E, ±3E, ±2E, ±E, 0) from -600V to +600V.

[0027] 2. Implementation of Hybrid Modulation Strategy High-voltage unit stepped wave modulation: Set the modulation ratio Ma = 0.9 and the fundamental frequency f = 50Hz. Generate a sinusoidal modulation signal v. r1 =M a ×6E×sin(2πft).

[0028] Set two comparison potentials: v l1 =2E=200V, v l2=4E=400V.

[0029] The control logic for the first high-voltage unit H1 is as follows: when v r1 >+v l1 When v is at its maximum, control its output to +2E (i.e., +200V); when ... r1 <−v l1 When -v, control its output to -2E (i.e., -200V); when -v l1 ≤v r1 ≤+v l1 When H1 outputs a zero level.

[0030] The control logic for the second high-voltage unit H2 is as follows: when v r1 >+v l2 When v is at its maximum, control its output to +2E (i.e., +200V); when ... r1 <−v l2 When -v, control its output to -2E (i.e., -200V); when -v l2 ≤v r1 ≤+v l2 At that time, H2 outputs a zero level.

[0031] The output voltage u of high voltage units H1 and H2 H1 and u H2 By superposition, the high-voltage side composite voltage u is obtained. H =u H1 +u H2 Throughout the process, the high-voltage unit switch operates only when the modulation wave crosses the fixed potential, with the switching frequency being the fundamental frequency (50Hz), resulting in extremely low switching losses.

[0032] Low-voltage unit improved carrier phase-shift PWM modulation: Set carrier frequency f c =3kHz, corresponding to carrier period T s =1 / f c .

[0033] First, triangular carrier reconstruction is performed. An isosceles triangular carrier with an amplitude of 4E = 400V and a period of Ts is used as the reference (see...). Figure 3 (a) First, divide it into 4 equal parts in the vertical (amplitude) direction, each with an amplitude of E = 100V. Second, divide one cycle into 8 equal parts in the horizontal (time) direction. For the negative half-cycle (-400V to 0V), use an amplitude of E and a base width of T. sThe reverse small isosceles triangle of 1 / 8 has a waveform that first linearly rises from -400V to 0V and then linearly drops back to -400V, forming a reverse stacked carrier band. For the positive half-cycle (0V to 400V), small isosceles triangles with the same parameters are used to move from 0V to 400V and back to 0V along the diagonal, forming a forward stacked carrier band. Finally, a new stacked triangular carrier band as shown in Figure 3 (b) is formed.

[0034] Secondly, carrier phase shifting is performed. The reconstructed stacked triangular carrier band is phase shifted by θ c = 90° (i.e., T s / 4) in sequence to obtain four carrier signals, denoted as v1, v2, v3, and v4 respectively.

[0035] Finally, switching control is carried out. A low-voltage side modulation signal v r2 is generated. v r2 is compared with the four carriers to control the switching tubes of the low-voltage unit: When v r2 > v1, control the low-voltage unit L1 to output +100V; when v r2 < v3, control L1 to output -100V.

[0036] When v r2 > v2, control the low-voltage unit L2 to output +100V; when v r2 < v4, control L2 to output -100V.

[0037] The output voltages u L1 and u L2 of the low-voltage units L1 and L2 are superimposed to obtain the low-voltage side synthesized voltage u L . Through the above modulation, it can be ensured that at any time, the polarity of the low-voltage side synthesized voltage u L is consistent with the polarity of the high-voltage side synthesized voltage u H , thus fundamentally eliminating the reverse circulating current phenomenon. At the same time, the equivalent switching frequency of the low-voltage unit reaches 8f c = 24kHz, and the output harmonics concentrate in the high-frequency region.

[0038] 3. Implementation of Power Self-Balancing of High-Voltage Units To achieve power balance between the two high-voltage units H1 and H2, a driving signal exchange strategy based on 1 / 4 output cycle rotation is adopted.

[0039] A complete cycle (20 ms) of the output voltage is equally divided into four regions, and each region lasts for 5 ms (i.e., 1 / 4 cycle).

[0040] Two modulation modes are defined: Mode a: The first high-voltage unit H1 is based on the comparison potential vl1 (200V) is used for control, and the second high-voltage unit H2 is based on the comparison potential v l2 (400V) is used for control.

[0041] Mode b: The first high-voltage unit H1 is based on the comparison potential v l2 (400V) is used for control, and the second high-voltage unit H2 is based on the comparison potential v l1 (200V) is used for control.

[0042] Within a complete output cycle, the two modes are applied cyclically in the following order: Region 1 (0-5ms) uses mode a; Region 2 (5-10ms) uses mode b; Region 3 (10-15ms) uses mode a; Region 4 (15-20ms) uses mode b (e.g., ...). Figure 5 (As shown).

[0043] Through the aforementioned cyclical exchange, within half an output cycle (10ms), H1 and H2 each handle the high and low comparison potential control for half the time, ensuring that their average output voltages are equal, thereby achieving automatic power balance. Calculations show that under specific parameters in this embodiment (e.g., E=100V, load R=25Ω, L=5.6mH), when M... a When M = 0.9, the average power of the two high-voltage units is equal; when M a The result is the same when the coefficient is 0.6. Simulation and experimental results verify the effectiveness of the method.

[0044] Example 2: Specific Implementation of the General Extended Topology This embodiment illustrates how the basic scheme of the present invention can be extended to a more general topology to meet the needs of different voltage levels and number of voltage levels.

[0045] 1. Construction of extended topology like Figure 6 As shown, the general extended topology consists of n high-voltage modules (H1, H2, ..., Hn) and k low-voltage modules (L1, L2, ..., Lk) cascaded sequentially. The DC-side voltage of each high-voltage module is m·E (m is a positive integer), and the DC-side voltage of each low-voltage module is E. To ensure the continuity of the output level sequence and avoid level gaps, the topology parameters must satisfy the constraint: k ≥ m.

[0046] The key parameter N is defined as the ratio of the maximum output voltage amplitude of the extended topology to the low-voltage module voltage E, i.e., N = n·m + k. The maximum number of output voltage levels of this topology is λ = 2N + 1.

[0047] 2. Modulation and Power Balancing Strategies for Extended Topologies The extended topology fully adopts the hybrid modulation strategy and power self-balancing principle described in Example 1, requiring only parameterization configuration and no redesign of the control algorithm.

[0048] High-voltage module modulation: All n high-voltage modules employ stepped-wave modulation in the same manner as in Example 1. For the i-th (i=1, 2, ..., n) high-voltage module, its corresponding comparison potential is set to ±V. Hi V Hi =(N−m·i)·E. All high-voltage modules operate at the fundamental frequency.

[0049] Low-voltage module modulation: All k low-voltage modules adopt the same improved carrier phase-shift PWM modulation strategy as in Example 1 to ensure that the polarity of the total output on the low-voltage side is consistent with that on the high-voltage side, eliminate reverse circulating current, and operate at high frequency.

[0050] Power balancing: For high-voltage modules of the same level with the same DC side voltage, a 1 / 4 cycle switching strategy with the same principle as in Example 1 is adopted inside to cyclically exchange drive signals and achieve power self-balancing among the high-voltage modules in this group.

[0051] Example 3: Simulation and Experimental Verification To verify the effectiveness of the method proposed in this invention, simulation and experimental verification were conducted.

[0052] 1. Simulation verification The basic thirteen-level inverter model described in this invention was built in simulation software. The load parameters were set to R=25Ω, L=5.6mH, and the modulation ratios Ma were 0.9 and 0.6, respectively.

[0053] Figure 8 The output voltage waveforms of traditional carrier phase-shift modulation and the improved modulation strategy of this invention are compared. It can be seen that, under different modulation intensities, the voltage waveform output by the method of this invention is completely consistent with the output voltage waveform of traditional carrier phase-shift modulation.

[0054] Figure 9 and Figure 10 The output voltage spectra under two modulation strategies are shown respectively. The output voltage harmonics of the traditional modulation strategy are mainly concentrated around 12kHz (4 times the carrier frequency). However, after adopting the improved modulation strategy of this invention, the output voltage harmonics are mainly concentrated around 24kHz (8 times the carrier frequency), realizing the high-frequency shift of the harmonic spectrum, which is beneficial to reducing the size and cost of the filter.

[0055] 2. Experimental verification An experimental prototype was built with a Field Programmable Gate Array (FPGA) as the core controller. In the prototype, the DC voltage of the low-voltage unit was set to 12V (E), and the DC voltage of the high-voltage unit was set to 24V (2E). The load parameters were consistent with the simulation.

[0056] Experimental results show that: When the modulation ratio Ma=0.9, the inverter successfully outputs a thirteen-level voltage waveform; when Ma=0.6, it outputs a nine-level voltage waveform, and the waveform quality matches the simulation results.

[0057] By measuring the instantaneous power of the two high-voltage units, it was found that they exhibit a symmetrical distribution within one output cycle, and the average power is basically equal, which verifies the effectiveness of the proposed power self-balancing method.

[0058] No reverse circulation was observed throughout the entire operating range, verifying the effectiveness of the improved modulation strategy in eliminating reverse circulation.

[0059] As an example of parametric design for an extended topology, if the system requires a 25V output level (λ=25), then N=12. The designer can choose a voltage multiplier m=2 for the high-voltage unit, which requires N=2n+k=12, and k≥2. One feasible set of parameters is n=5, k=2; another is n=4, k=4. The specific choice can be weighed based on factors such as device withstand voltage and cost. When n=4, k=4, and m=2 are selected, the comparison potential of the high-voltage unit is V. H1 =(12-2)E=10E,V H2 =(12-4)E=8E,V H3 =(12-6)E=6E,V H4 =(12-8)E=4E. The number of low-voltage units k=4 satisfies the constraint condition k≥m=2, which can ensure the continuity of the output level.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A modulation and power equalization method for a hybrid cascaded H-bridge inverter, characterized in that, Includes the following steps: A basic topology for constructing a hybrid cascaded H-bridge inverter is provided, which consists of two low-voltage H-bridge units and two high-voltage H-bridge units cascaded together. The DC-side voltage of the low-voltage H-bridge unit is E, and the DC-side voltage of the high-voltage H-bridge unit is 2E. The basic topology is modulated using a hybrid modulation strategy, wherein: The high-voltage H-bridge unit adopts a stepped-wave modulation mode and operates at the fundamental frequency. The low-voltage H-bridge unit adopts an improved carrier phase-shift pulse width modulation mode, specifically including: performing amplitude layering and time division on a single isosceles triangular carrier, and recombining it into forward and reverse stacked triangular carrier bands; phase-shifting the recombined carrier bands to generate multiple phase-shifted carriers; controlling the switching transistors of the low-voltage H-bridge unit based on the phase-shifted carriers, so that the polarity of the output voltage of each low-voltage H-bridge unit is consistent with the polarity of the combined output voltage of the high-voltage unit; The drive signals of the two high-voltage H-bridge units are cyclically exchanged with a 1 / 4 output voltage cycle as the switching cycle, so as to achieve power self-balancing between high-voltage H-bridge units of the same voltage level.

2. The method according to claim 1, characterized in that, The stepped-wave modulation of the high-voltage H-bridge unit specifically includes: Generate a sinusoidal modulation signal v r1 Set the first comparison potential ±V l1 Second comparison potential ±v l2 , where v l1 =2E, v l2 =4E; The first high-voltage H-bridge unit is based on v r1 With ±v l1 The comparison result outputs +2E, -2E, or 0; The second high-voltage H-bridge unit is based on v r1 With ±v l2 The comparison result outputs +2E, -2E, or 0.

3. The method according to claim 1, characterized in that, The improved carrier phase-shift pulse width modulation of the low-voltage H-bridge unit specifically includes: For an amplitude of 4E and a period of T s The single isosceles triangular carrier is reconstructed by dividing the single isosceles triangular carrier into 4 equal parts in the amplitude direction and dividing one period of it into 8 equal parts in the time direction. The negative half-cycle of the single isosceles triangular carrier wave is divided into 8 segments with a base width of T. s 8. Inverted small triangular waves with amplitude E are sequentially connected end-to-end in chronological order to form an inverted stacked triangular carrier band; the positive half-cycle of the single isosceles triangular carrier is divided into 8 segments with a base width of T. s / 8. Positive small triangular waves with amplitude E are connected end to end in chronological order to form a positive stacked triangular carrier band. The reconstructed forward and reverse stacked triangular carrier bands are sequentially phase-shifted by 90° to obtain four phase-shifted carriers; Generate low-voltage side modulation signal v r2 and v r2 The voltage is compared with the four phase-shifted carrier waves to control the switching of the two low-voltage H-bridge units, so that the output voltage of each low-voltage unit has the same polarity as the combined voltage on the high-voltage side.

4. The method according to claim 1, characterized in that, The power self-balancing specifically includes: dividing the output voltage cycle into four consecutive 1 / 4 cycle regions; in the first and third regions, controlling the first high-voltage unit to operate according to the first comparison potential and the second high-voltage unit to operate according to the second comparison potential, which is defined as a first modulation mode; in the second and fourth regions, controlling the first high-voltage unit to operate according to the second comparison potential and the second high-voltage unit to operate according to the first comparison potential, which is defined as a second modulation mode.

5. The method according to claim 1, characterized in that, This is applied to an extended topology, which consists of n high-voltage modules and k low-voltage modules cascaded together. The DC-side voltage of the high-voltage modules is mE, and the DC-side voltage of the low-voltage modules is E, where n, k, and m are all positive integers, and k≥m to ensure the continuity of the output level. In the extended topology, all high-voltage modules adopt the stepped wave modulation mode, all low-voltage modules adopt the improved carrier phase-shift pulse width modulation mode, and the high-voltage modules of the same voltage level adopt the 1 / 4 cycle rotation strategy to achieve power self-balancing.

6. The method according to claim 5, characterized in that, The ratio of the maximum output voltage amplitude of the extended topology to the DC voltage E of the low-voltage module is N=n·m+k, and the maximum number of output levels is λ=2N+1.

7. The method according to claim 5, characterized in that, The stepped-wave modulation of the high-voltage module in the extended topology is specifically as follows: The comparison potential of the i-th high-voltage module is set to ±V. Hi V Hi =(N−m·i)E, i=1,2,...,n; When the sinusoidal modulation signal v r1 >+V Hi When v is active, control the i-th high-voltage module to output +mE; when v is active, control the i-th high-voltage module to output +mE. r1 <−V Hi When the condition is met, control the output of the i-th high-voltage module to be -mE; otherwise, control its output to be 0.

8. A modulation and power equalization system for a hybrid cascaded H-bridge inverter, characterized in that, A modulation and power equalization method for performing a hybrid cascaded H-bridge inverter as described in any one of claims 1-7, comprising: Topology building module, used to build the basic topology or the extended topology; The hybrid modulation module includes a high-voltage stepped wave modulation submodule and a low-voltage improved carrier phase-shift PWM modulation submodule, which are used to generate switching drive signals for the high-voltage unit and the low-voltage unit, respectively. The power balancing module is used to cyclically exchange the drive signals of high-voltage modules of the same voltage level with a switching cycle of 1 / 4 of the output voltage cycle, so as to achieve power self-balancing. The extended control module is used to configure the extended topology parameters n, k, and m, and to verify the constraint condition k ≥ m.

9. An electronic device, characterized in that, It includes at least one processor and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 7.

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