Method, system, controller and medium for speed upgrade of network analyzer

Abstract

The application relates to the field of radio frequency microwave technology and discloses a network analyzer speed measurement improvement method and system, a controller and a medium, which comprises the following steps: performing detection processing on a radio frequency signal to obtain a detection voltage, and performing integral processing on the detection voltage and a reference voltage to obtain a control voltage of a voltage-controlled attenuator; in a phase-locked loop frequency hopping process, the reference voltage is set as a first preset value, so that the control voltage of the voltage-controlled attenuator changes to the nearest power supply rail; if the phase-locked loop frequency hopping duration reaches a preset duration, the reference voltage is set as a second preset value corresponding to a preset target power; the radio frequency signal is adjusted based on a target control voltage until the power of the radio frequency signal is stabilized to the preset target power. The method changes the reference voltage in a step-by-step manner, so that the control voltage of the voltage-controlled attenuator directly jumps from the power supply rail to a target value after frequency hopping, the amplitude stabilization time of the automatic level control is shortened, and the overall measurement speed of the network analyzer is improved.

Description

Technical Field

[0001] This invention relates to the field of radio frequency and microwave technology, specifically to a method, system, controller, and medium for improving the speed measurement of network analyzers. Background Technology

[0002] Network analyzers are among the most critical measurement instruments in the field of radio frequency and microwave technology. They are widely used in laboratory R&D and production line testing to measure key parameters of devices, such as scattering parameters, gain compression, and time-domain response. With the development of radio frequency communication technology, the requirements for the measurement speed of network analyzers are constantly increasing, especially in production line testing scenarios where measurement time directly affects testing efficiency and cost.

[0003] The measurement time of a network analyzer mainly consists of frequency hopping time, Automatic Level Control (ALC) stabilization time, data acquisition and processing time, and data transmission time. Frequency hopping time depends on the locking speed of the frequency synthesizer, while stabilization time depends on the ALC loop's adjustment speed of the output power. Although the frequency hopping time of a Phase-Locked Loop (PLL) is longer than that of a Direct Digital Frequency Synthesizer (DDS), PLLs are still widely used due to their compact structure and low cost. In terms of power control, to improve the temperature stability of the output power, network analyzers typically employ ALC technology to achieve continuous adjustment and amplitude stabilization control of the signal output power. However, because ALC is a negative feedback control system, the power stabilization process is limited by the loop setup time, resulting in a relatively long stabilization time. Therefore, how to further improve the overall measurement speed of a network analyzer while ensuring frequency stability and power accuracy is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] In view of this, the present invention provides a method, system, controller and medium for improving the speed measurement of a network analyzer, so as to improve the overall measurement speed of the network analyzer.

[0005] In a first aspect, the present invention provides a method for improving the speed measurement of a network analyzer, the method comprising: Obtain the radio frequency signal output by the phase-locked loop; The radio frequency signal is detected to obtain a detection voltage, and the detection voltage is integrated with a reference voltage to obtain the control voltage of the voltage-controlled attenuator. During the phase-locked loop frequency hopping process, the reference voltage is set to a first preset value so that the control voltage of the voltage-controlled attenuator changes to the nearest power rail. The first preset value is the maximum or minimum value within the adjustable range of the reference voltage. If the phase-locked loop frequency hopping duration reaches the preset duration, the reference voltage is set to the second preset value corresponding to the preset target power, so that the control voltage jumps from the power rail to the target control voltage; The radio frequency signal is adjusted based on the target control voltage until the power of the radio frequency signal stabilizes at the preset target power.

[0006] In one optional implementation, the step of detecting the radio frequency signal to obtain a detected voltage, and integrating the detected voltage with a reference voltage to obtain the control voltage of the voltage-controlled attenuator, includes: The radio frequency signal is regulated by a voltage-controlled attenuator, and the regulated radio frequency signal is converted into a detection voltage by a detector. The difference between the detector voltage and the reference voltage is integrated to obtain the control voltage of the voltage-controlled attenuator.

[0007] In one optional implementation, if the distance between the control voltage of the voltage-controlled attenuator and the negative power rail is less than a preset threshold, the first preset value is the maximum value within the adjustable range of the reference voltage. If the distance between the control voltage of the voltage-controlled attenuator and the positive power rail is less than a preset threshold, the first preset value is the minimum value within the adjustable range of the reference voltage.

[0008] In one optional implementation, before acquiring the radio frequency signal output by the phase-locked loop, the method further includes: Obtain the preset phase detection frequency parameters; The phase detection frequency of the phase-locked loop is set based on the preset phase detection frequency parameters so that the phase detection frequency is greater than the preset frequency threshold.

[0009] In one optional implementation, the step of integrating the detector voltage and the reference voltage to obtain the control voltage of the voltage-controlled attenuator includes: integrating the difference between the detector voltage and the reference voltage based on an integration comparison circuit to obtain the control voltage of the voltage-controlled attenuator. The method further includes: Obtain the current resistance and capacitance values ​​of the integration comparator circuit; Decrease the resistance and / or capacitance values ​​in the integration comparator circuit to increase the loop bandwidth of the integration comparator circuit.

[0010] In one optional implementation, reducing the resistance and / or capacitance values ​​in the integrating comparator circuit to increase the loop bandwidth of the integrating comparator circuit includes: Adjust the resistor in the integral comparator circuit from its current resistance value to a first resistance value, where the first resistance value is less than the current resistance value; and / or The capacitor in the integral comparator circuit is adjusted from its current value to a first value, where the first value is less than the current value; the adjusted loop bandwidth is greater than the original loop bandwidth.

[0011] Secondly, the present invention provides a speed measurement enhancement system for a network analyzer, the system comprising: A phase-locked loop (PLL) is used to generate and output radio frequency (RF) signals. A voltage-controlled attenuator, the input of which is connected to the output of the phase-locked loop, is used to receive the radio frequency signal and output the regulated radio frequency signal; A detector, the input of which is connected to the output of the voltage-controlled attenuator, is used to perform detection processing on the regulated radio frequency signal and output a detection voltage; An integrating comparator circuit is provided, wherein the first input terminal of the integrating comparator circuit is connected to the output terminal of the detector, and the second input terminal of the integrating comparator circuit is used to receive a reference voltage. The controller is connected to the control terminal of the phase-locked loop and the second input terminal of the integral comparator circuit, respectively.

[0012] Thirdly, the present invention provides a controller, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the speed measurement improvement method of the network analyzer described in the first aspect or any corresponding embodiment.

[0013] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the speed measurement improvement method of the network analyzer described in the first aspect or any corresponding embodiment thereof.

[0014] The network analyzer speed measurement improvement method provided in this embodiment includes: acquiring the radio frequency (RF) signal output by the phase-locked loop (PLL); performing detection processing on the RF signal to obtain a detection voltage, and integrating the detection voltage and a reference voltage to obtain the control voltage of the voltage-controlled attenuator (VCO); during PLL frequency hopping, setting the reference voltage to a first preset value to cause the control voltage of the VCO to change to the nearest power rail; if the PLL frequency hopping duration reaches a preset duration, setting the reference voltage to a second preset value corresponding to a preset target power to cause the control voltage to jump from the power rail to the target control voltage; adjusting the RF signal based on the target control voltage until the power of the RF signal stabilizes at the preset target power. This method, by changing the reference voltage in a stepwise manner, allows the control voltage of the VCO to jump directly from the power rail to the target value after frequency hopping, shortening the amplitude stabilization time of automatic level control, thereby improving the overall measurement speed of the network analyzer. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a flowchart illustrating the speed measurement improvement method of a network analyzer according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a speed measurement enhancement system for a network analyzer according to an embodiment of the present invention. Figure 3 This is a schematic diagram of an integral comparison circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware structure of the controller according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] According to an embodiment of the present invention, a method for improving the speed measurement of a network analyzer is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0019] This embodiment provides a method for improving the speed measurement of a network analyzer. Figure 1 This is a flowchart of a speed measurement improvement method for a network analyzer according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain the radio frequency signal output by the phase-locked loop.

[0020] First, the RF signal output from the phase-locked loop is acquired. The RF signal is the excitation source signal of the network analyzer. The voltage-controlled attenuator is connected to the phase-locked loop. The output RF signal is first output to the voltage-controlled attenuator, which processes the RF signal before inputting it to the detector.

[0021] Step S102: Detect the radio frequency signal to obtain the detection voltage, and integrate the detection voltage with the reference voltage to obtain the control voltage of the voltage-controlled attenuator.

[0022] The radio frequency (RF) signal is detected, and the detected voltage and reference voltage are integrated to obtain the control voltage of the voltage-controlled attenuator (VCO). Specifically, the RF signal processed by the VCO is input to a detector, which can use a diode detector or a logarithmic detector to convert the RF signal power into a DC detected voltage. The detected voltage and the reference voltage are then input to the two input terminals of an integrator / comparator circuit, which can use a non-inverting or inverting integrator circuit. By integrating the difference between the detected voltage and the reference voltage, the control voltage of the VCO is output. This control voltage is used to adjust the attenuation of the VCO, thereby changing the power of the RF signal. The reference voltage can be generated by a digital-to-analog converter (DAC) based on a preset target power.

[0023] In step S103, during the phase-locked loop frequency hopping process, the reference voltage is set to a first preset value so that the control voltage of the voltage-controlled attenuator changes to the nearest power rail.

[0024] The first preset value is the maximum or minimum value within the adjustable range of the reference voltage. When the phase-locked loop receives a frequency hopping command and begins switching frequencies, the controller adjusts the reference voltage output by the digital-to-analog converter. If the first preset value is the maximum value, the reference voltage is made much higher than the current detector voltage. A difference exists between the detector voltage and the reference voltage. This difference is input to the integrating comparator circuit, which integrates the difference until the control voltage of the voltage-controlled attenuator reaches the nearest power rail, i.e., the positive or negative rail of the operational amplifier's supply voltage.

[0025] In some optional implementations, if the distance between the control voltage of the voltage-controlled attenuator and the negative power rail is less than a preset threshold, the first preset value is the maximum value within the adjustable range of the reference voltage. If the distance between the control voltage of the voltage-controlled attenuator and the positive power rail is less than a preset threshold, the first preset value is the minimum value within the adjustable range of the reference voltage.

[0026] If the distance between the control voltage of the voltage-controlled attenuator and the negative power rail is less than a preset threshold (e.g., 0.5V), it indicates that the control voltage is close to the negative power rail. In this case, the reference voltage is set to the maximum value, making the difference between the detector voltage and the reference voltage a large negative value. The output of the integral comparator circuit then drops rapidly to the negative power rail. If the distance between the control voltage of the voltage-controlled attenuator and the positive power rail is less than a preset threshold, it indicates that the control voltage is close to the positive power rail. In this case, the reference voltage is set to the minimum value, making the difference between the detector voltage and the reference voltage a large positive value. The output of the integral comparator circuit then rises rapidly to the positive power rail.

[0027] Step S104: If the phase-locked loop frequency hopping time reaches the preset time, the reference voltage is set to the second preset value corresponding to the preset target power, so that the control voltage jumps from the power rail to the target control voltage.

[0028] A timer is started simultaneously with the beginning of frequency hopping in the phase-locked loop (PLL) to determine if the hopping duration has reached a preset duration. This preset duration is a value pre-set based on the PLL's locking characteristics, for example, based on the PLL's maximum locking time or the locking time plus a certain margin. When the preset duration is reached, it is determined that the PLL's frequency has been stably locked. At this point, the reference voltage is switched from a first preset value to a second preset value corresponding to the target power. The second preset value is the normal reference voltage value corresponding to the output power required by the network analyzer at the current frequency. Because the control voltage of the voltage-controlled attenuator was on the power rail before the switch, and the input difference of the integral comparator circuit changes after the switch, the control voltage jumps directly from the power rail to near the target control voltage, completing a rapid transition.

[0029] Step S105: Adjust the radio frequency signal based on the target control voltage until the power of the radio frequency signal stabilizes at the preset target power.

[0030] The voltage-controlled attenuator adjusts the attenuation of the RF signal according to the target control voltage, gradually bringing the RF output power closer to the preset target power. Simultaneously, the detector continuously monitors the adjusted RF signal power and outputs a real-time detected voltage. The integrator compares this real-time detected voltage with a reference voltage that is currently at the second preset value, and performs fine-tuning on the difference to form a closed-loop regulation. When the difference between the real-time detected voltage and the reference voltage is less than the preset difference and remains stable for a period of time, it is determined that the RF signal power has stabilized to the preset target power, completing the measurement preparation for the current frequency point. The network analyzer can then proceed to the frequency hopping and amplitude stabilization process for the next frequency point, repeating the above steps until measurements for all frequency points are completed.

[0031] The network analyzer speed measurement improvement method provided in this embodiment includes: acquiring the radio frequency (RF) signal output by the phase-locked loop (PLL); performing detection processing on the RF signal to obtain a detection voltage, and integrating the detection voltage and a reference voltage to obtain the control voltage of the voltage-controlled attenuator (VCO); during PLL frequency hopping, setting the reference voltage to a first preset value to cause the control voltage of the VCO to change to the nearest power rail; if the PLL frequency hopping duration reaches a preset duration, setting the reference voltage to a second preset value corresponding to a preset target power to cause the control voltage to jump from the power rail to the target control voltage; adjusting the RF signal based on the target control voltage until the power of the RF signal stabilizes at the preset target power. This method, by changing the reference voltage in a stepwise manner, allows the control voltage of the VCO to jump directly from the power rail to the target value after frequency hopping, shortening the amplitude stabilization time of automatic level control, thereby improving the overall measurement speed of the network analyzer.

[0032] In some alternative implementations, step S102 includes: Step S201: The radio frequency signal is adjusted based on the voltage-controlled attenuator, and the adjusted radio frequency signal is converted into a detection voltage based on the detector.

[0033] After the radio frequency signal is input to the voltage-controlled attenuator, it is attenuated according to the current control voltage, thereby changing the output power. For example... Figure 2 As shown, the RF signal, after being regulated by the voltage-controlled attenuator (VCA), is output to the device under test via one path as the RF output signal of the network analyzer, and input to the detector via the other path.

[0034] The detector receives the regulated radio frequency signal and converts it into a DC detection voltage. Detectors can be implemented in various ways, such as diode envelope detector circuits, logarithmic detectors, or true RMS detectors. Taking a diode detector circuit as an example, the radio frequency signal is coupled and input to the detector diode. The nonlinear characteristics of the diode are used to convert the radio frequency power into a DC voltage, which is then smoothed by a filter capacitor to obtain the detector voltage.

[0035] In step S202, the difference between the detector voltage and the reference voltage is integrated to obtain the control voltage of the voltage-controlled attenuator.

[0036] Detection voltage and reference voltage Simultaneously, the input integrator and comparator circuit processes the difference and outputs the control voltage for the voltage-controlled attenuator. Control voltage Determine according to the following formula:

[0037] Where R represents the resistance value in the integrator-comparator circuit, and C represents the capacitance value obtained in the integrator-comparator circuit.

[0038] In some optional implementations, step S102 includes: integrating the difference between the detector voltage and the reference voltage based on the integration comparator circuit to obtain the control voltage of the voltage-controlled attenuator; the method further includes: obtaining the current resistance value and the current capacitance value of the integration comparator circuit; reducing the resistance value and / or capacitance value in the integration comparator circuit to increase the loop bandwidth of the integration comparator circuit.

[0039] Specifically, reducing the resistance and / or capacitance values ​​in the integral comparator circuit to increase the loop bandwidth of the integral comparator circuit includes: adjusting the resistance in the integral comparator circuit from the current resistance value to a first resistance value, where the first resistance value is less than the current resistance value; and / or adjusting the capacitance in the integral comparator circuit from the current capacitance value to a first capacitance value, where the first capacitance value is less than the current capacitance value; the adjusted loop bandwidth is greater than the unadjusted loop bandwidth.

[0040] Among them, loop bandwidth R represents the resistance value in the integrator-comparator circuit, and C represents the capacitance value obtained in the integrator-comparator circuit.

[0041] First, obtain the integral comparator circuit, such as... Figure 3 As shown, the current resistance value R and current capacitance value C of the integrating comparator circuit are first read. The resistance and / or capacitance values ​​in the integrating comparator circuit are then decreased, thereby increasing the loop bandwidth. This allows the integrating comparator circuit to respond more quickly to the difference between the detected voltage and the reference voltage, thus shortening the amplitude stabilization time of the level control. The reference voltage is generated by the digital-to-analog converter based on a preset target power.

[0042] Specifically, the resistor in the integrator circuit can be adjusted from its current value to a first resistance value, which is less than the current resistance value; and / or the capacitor in the integrator circuit can be adjusted from its current value to a first capacitance value, which is less than the current capacitance value. Both the first resistance and first capacitance values ​​are set based on actual conditions. Both resistor R and capacitor C are adjustable components; adjusting their parameter values ​​changes the loop bandwidth. Since the loop bandwidth is inversely proportional to R and C, decreasing the value of R or C directly increases the bandwidth, thereby improving the response speed of the integrator circuit.

[0043] In some optional implementations, before acquiring the radio frequency signal output by the phase-locked loop, the method further includes: acquiring a preset phase detection frequency parameter; and setting the phase detection frequency of the phase-locked loop based on the preset phase detection frequency parameter so that the phase detection frequency is greater than a preset frequency threshold.

[0044] The preset phase detection frequency parameter is a frequency value that is pre-set according to the test requirements of the network analyzer. For example, it can be entered through the user interface, read from the configuration file, or automatically generated according to the test frequency band.

[0045] The phase detection frequency of a phase-locked loop (PLL) refers to the operating frequency at which the phase detector compares the phase of the reference signal and the feedback signal, directly determining the PLL's locking speed. According to the PLL's operating principle, with a fixed number of phase detection cycles, a higher detection frequency results in a shorter time for the PLL to complete frequency locking. Therefore, setting a higher detection frequency can significantly shorten the PLL's frequency hopping time.

[0046] The preset frequency threshold can be a pre-defined lower limit, such as one determined based on the system's frequency hopping time requirements or the specifications of the phase-locked loop (PLL) chip. Setting the phase detection frequency higher than the preset threshold ensures that the PLL operates within a sufficiently fast locking speed range. The specific setting of the phase detection frequency can be achieved by configuring the frequency divider parameters within the PLL chip, such as adjusting the division ratio of the reference divider and the feedback divider, so that the phase detector's operating frequency reaches the preset value.

[0047] By implementing the phase detection frequency configuration steps described above, the frequency hopping time of the phase-locked loop is shortened, thereby improving the overall measurement speed of the network analyzer.

[0048] This embodiment also provides a speed measurement enhancement system for a network analyzer, used to implement the above embodiments and implementation methods. The system includes: a phase-locked loop, a voltage-controlled attenuator, a detector, an integrator / comparator circuit, and a controller. Figure 2 As shown, the phase-locked loop (PLL) is used to generate and output the radio frequency (RF) signal; the input of the voltage-controlled attenuator (VCA) is connected to the output of the PLL, used to receive the RF signal and output the regulated RF signal; the input of the detector is connected to the output of the VCA, used to detect the regulated RF signal and output the detection voltage. The first input terminal of the integrator-comparator circuit is connected to the output terminal of the detector, and the second input terminal of the integrator-comparator circuit is used to receive the reference voltage. The controller can be connected to the control terminal of the phase-locked loop and the second input terminal of the integral comparator circuit, respectively.

[0049] In some alternative implementations, the controller also includes a timer configured to: When the phase-locked loop (PLL) starts frequency hopping, a timer is started; the maximum locking time of the PLL is obtained, and the preset duration is determined based on the maximum locking time and the preset time margin; when the timer reaches the preset duration, it is determined that the PLL frequency hopping duration has reached the preset duration.

[0050] The maximum lock-in time can be predetermined based on factors such as the PLL chip's specifications, operating frequency range, phase detection frequency setting, and ambient temperature. It reflects the maximum time required for the PLL to complete frequency locking. The preset time margin provides additional time to ensure reliable locking under various operating conditions. For example, the preset duration can be set to the maximum lock-in time plus 100 microseconds, or 1.2 times the maximum lock-in time. When the timer reaches the preset duration, the controller determines that the PLL's frequency hopping duration has reached the preset duration. At this point, the PLL's frequency is stably locked, and the controller executes the subsequent reference voltage switching operation.

[0051] This invention also provides a controller for a speed measurement enhancement system for a network analyzer.

[0052] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a controller provided in an optional embodiment of the present invention, such as... Figure 4 As shown, the controller includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the controller, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple controllers can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 4 Take a processor 10 as an example.

[0053] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0054] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0055] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the controller. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the controller via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0056] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0057] The controller also includes a communication interface 30 for communicating with other devices or communication networks.

[0058] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0059] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0060] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the invention.

Claims

1. A method for improving the speed measurement of a network analyzer, characterized in that, The method includes: Obtain the radio frequency signal output by the phase-locked loop; The radio frequency signal is detected to obtain a detection voltage, and the detection voltage is integrated with a reference voltage to obtain the control voltage of the voltage-controlled attenuator. During the phase-locked loop frequency hopping process, the reference voltage is set to a first preset value so that the control voltage of the voltage-controlled attenuator changes to the nearest power rail. The first preset value is the maximum or minimum value within the adjustable range of the reference voltage. If the phase-locked loop frequency hopping duration reaches the preset duration, the reference voltage is set to the second preset value corresponding to the preset target power, so that the control voltage jumps from the power rail to the target control voltage; The radio frequency signal is adjusted based on the target control voltage until the power of the radio frequency signal stabilizes at the preset target power.

2. The method for improving the speed measurement of a network analyzer according to claim 1, characterized in that, The step of detecting the radio frequency signal to obtain a detected voltage, and integrating the detected voltage with a reference voltage to obtain the control voltage of the voltage-controlled attenuator, includes: The radio frequency signal is regulated by a voltage-controlled attenuator, and the regulated radio frequency signal is converted into a detection voltage by a detector. The difference between the detector voltage and the reference voltage is integrated to obtain the control voltage of the voltage-controlled attenuator.

3. The method for improving the speed measurement of a network analyzer according to claim 1, characterized in that, If the distance between the control voltage of the voltage-controlled attenuator and the negative power rail is less than a preset threshold, the first preset value is the maximum value within the adjustable range of the reference voltage; If the distance between the control voltage of the voltage-controlled attenuator and the positive power rail is less than a preset threshold, the first preset value is the minimum value within the adjustable range of the reference voltage.

4. The method for improving the speed measurement of a network analyzer according to claim 1, characterized in that, Before acquiring the radio frequency signal output by the phase-locked loop, the method further includes: Obtain the preset phase detection frequency parameters; The phase detection frequency of the phase-locked loop is set based on the preset phase detection frequency parameters so that the phase detection frequency is greater than the preset frequency threshold.

5. The method for improving the speed measurement of a network analyzer according to claim 1, characterized in that, The step of integrating the detector voltage and the reference voltage to obtain the control voltage of the voltage-controlled attenuator includes: integrating the difference between the detector voltage and the reference voltage based on the integration comparison circuit to obtain the control voltage of the voltage-controlled attenuator; The method further includes: Obtain the current resistance and capacitance values ​​of the integration comparator circuit; Decrease the resistance and / or capacitance values ​​in the integration comparator circuit to increase the loop bandwidth of the integration comparator circuit.

6. The method for improving the speed measurement of a network analyzer according to claim 5, characterized in that, The step of reducing the resistance and / or capacitance values ​​in the integral comparator circuit to increase the loop bandwidth of the integral comparator circuit includes: Adjust the resistor in the integral comparator circuit from its current resistance value to a first resistance value, where the first resistance value is less than the current resistance value; and / or, The capacitor in the integral comparator circuit is adjusted from its current value to a first value, where the first value is less than the current value; the adjusted loop bandwidth is greater than the original loop bandwidth.

7. A speed measurement enhancement system for a network analyzer, characterized in that, The system includes: A phase-locked loop (PLL) is used to generate and output radio frequency (RF) signals. A voltage-controlled attenuator, the input of which is connected to the output of the phase-locked loop, is used to receive the radio frequency signal and output the regulated radio frequency signal; A detector, the input of which is connected to the output of the voltage-controlled attenuator, is used to perform detection processing on the regulated radio frequency signal and output a detection voltage; An integrating comparator circuit is provided, wherein the first input terminal of the integrating comparator circuit is connected to the output terminal of the detector, and the second input terminal of the integrating comparator circuit is used to receive a reference voltage. The controller is connected to the control terminal of the phase-locked loop and the second input terminal of the integral comparator circuit, respectively.

8. The system according to claim 7, characterized in that, The controller also includes a timer, which is configured to: The timer is started when the phase-locked loop begins frequency hopping; Obtain the maximum locking time of the phase-locked loop, and determine the preset duration based on the maximum locking time and the preset time margin; When the timer reaches the preset duration, it is determined that the phase-locked loop frequency hopping duration has reached the preset duration.

9. A controller, characterized in that, include: The network analyzer comprises a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the speed measurement improvement method of any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the speed measurement improvement method of the network analyzer according to any one of claims 1 to 6.

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