A network chip fault detection method, device and related equipment

Abstract

The application relates to the technical field of network communication, in particular to a network chip fault detection method and device and related equipment. The method is suitable for a multi-room and multi-service continuous operation environment in an FTTR scene. The method comprises the following steps: acquiring function module information of each function module included in a to-be-detected network chip and connection relationship information between the function modules; based on the function module information of each function module and the connection relationship information between the function modules, a detection model of the to-be-detected network chip is constructed, wherein the detection model comprises function units corresponding to the function modules respectively, and connection relationship between the function units; the message receiving amount and the message sending amount of each function module in a current collection period are collected, and based on the message receiving amount and the message sending amount of each function module in the current period and the detection model, whether the to-be-detected network chip has a chip fault is determined.

Description

Technical Field

[0001] This application relates to the field of network communication technology, and in particular to a method, apparatus and related equipment for network chip fault detection. Background Technology

[0002] With the continuous expansion of services such as artificial intelligence computing, data centers, 5G, IoT, and FTTR (Fiber to the Room) whole-house optical networks, the complexity and concurrency of network traffic have increased significantly. Especially in indoor all-optical networks using FTTR architecture, the number of access nodes and terminals in each room is rapidly increasing. Packet processor chips often need to operate continuously under high load and multi-service concurrency conditions 24 / 7. Any blockage in the processing path or module failure may lead to the loss of critical service data packets, increased latency, or even network interruption, thereby directly affecting the coverage quality and user experience of the FTTR network and causing serious economic losses.

[0003] A packet processor (also known as a network processing chip or network processor) is a type of dedicated programmable chip widely used in high-performance network devices such as routers, switches, firewalls, FTTR indoor optical gateways, and FTTR room ONUs / room optical terminals for high-speed forwarding and processing of data packets. Compared to a general-purpose central processing unit (CPU), a packet processor is architecturally more suitable for parallel data stream processing and is optimized for functions such as multi-protocol parsing, packet classification, and traffic scheduling, enabling low-latency and high-throughput forwarding performance.

[0004] Existing network chip fault detection methods suffer from limitations such as limited detection range, insufficient versatility, and low real-time performance under high load and traffic conditions, making it difficult to meet the stability and refined operation and maintenance requirements of modern network equipment, especially FTTR indoor all-optical network equipment. Therefore, there is an urgent need for a universal, non-intrusive packet processor fault detection method that can operate in real-time under streaming environments, can run uniformly across different architectures and achieve efficient location and repair, and is applicable to various network forms, including FTTR fiber-to-the-room networks. Summary of the Invention

[0005] This application provides a method, apparatus, and related equipment for network chip fault detection.

[0006] In a first aspect, this application provides a network chip fault detection method, applied to a detection device; the method includes: Obtain the functional module information of each functional module included in the network chip under test and the connection relationship information between each functional module; Based on the functional module information of each functional module and the connection relationship information between each functional module, a detection model of the network chip to be detected is constructed. The detection model includes functional units corresponding to each functional module and the connection relationship between each functional unit. The system collects the message reception and transmission volumes of each functional module within the current collection period, and determines whether the network chip under test has a chip fault based on the message reception and transmission volumes of each functional module within the current period and the detection module.

[0007] Optionally, the step of constructing the detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module includes: Based on the functional module information, functional units corresponding to each functional module are constructed respectively, and two external interfaces are defined for each functional unit. The two external interfaces include a first interface and a second interface. The first interface is a message receiving interface, and the second interface is a message sending interface. Based on the external interfaces corresponding to each functional unit and the connection information between each functional module, a connection link between each functional unit is constructed. The detection model of the network chip to be detected is constituted by the functional units corresponding to each functional module and the connection links between each functional unit.

[0008] Optionally, the detection device supports the target data format, and the detection device has preset conversion rules between the data format and the target data format for various functional module information and connection relationship information; If the data format of the functional module information and the connection relationship information between the functional modules included in the network chip to be tested is not the target data format, then the method further includes: The data format of the functional module information and the connection relationship information between the functional modules of the network chip under test is converted into the target data format.

[0009] Optionally, the step of determining whether the network chip under test has a chip fault, based on the message reception and message transmission volume of each module in the current period and the detection module, includes: For each functional unit, maintain the message reception and message transmission volume of the corresponding functional module within the current acquisition period; If it is determined that within n consecutive collection cycles, the difference between the number of received messages and the number of sent messages corresponding to a functional unit is greater than or equal to the first threshold, then it is determined that the functional module corresponding to the functional unit has experienced a message loss / message congestion fault, and the functional module corresponding to the functional unit is reset. If, within m consecutive acquisition cycles, the difference between the message transmission volume of the functional module corresponding to the preceding functional unit and the message reception volume of the functional module corresponding to the following functional unit is greater than or equal to the second threshold, then it is determined that a message loss / congestion fault has occurred in the link between the two functional modules, and the link between the two functional modules is reset.

[0010] Secondly, this application provides a network chip fault detection device, applied to a testing equipment; the device includes: The acquisition unit is used to acquire the functional module information of each functional module included in the network chip under test and the connection relationship information between each functional module; A construction unit is used to construct a detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module. The detection model includes functional units corresponding to each functional module and the connection relationship between each functional unit. The data acquisition unit is used to collect the number of messages received and sent by each functional module during the current data acquisition period. The determining unit is used to determine whether the network chip to be detected has a chip fault based on the message reception and message transmission volume of each energy module in the current period and the detection module.

[0011] Optionally, when constructing the detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module, the construction unit is specifically used for: Based on the functional module information, functional units corresponding to each functional module are constructed respectively, and two external interfaces are defined for each functional unit. The two external interfaces include a first interface and a second interface. The first interface is a message receiving interface, and the second interface is a message sending interface. Based on the external interfaces corresponding to each functional unit and the connection information between each functional module, a connection link between each functional unit is constructed. The detection model of the network chip to be detected is constituted by the functional units corresponding to each functional module and the connection links between each functional unit.

[0012] Optionally, the detection device supports the target data format, and the detection device has preset conversion rules between the data format of various functional module information and connection relationship information and the target data format; the device also includes a conversion unit: If the data format of the functional module information and the connection relationship information between the functional modules included in the network chip to be tested is not the target data format, then the conversion unit is used to: The data format of the functional module information and the connection relationship information between the functional modules of the network chip under test is converted into the target data format.

[0013] Optionally, when determining whether the network chip under test has a chip fault based on the message reception and message transmission volume of each module in the current period and the detection module, the determining unit is specifically used for: For each functional unit, maintain the message reception and message transmission volume of the corresponding functional module within the current acquisition period; If it is determined that within n consecutive collection cycles, the difference between the number of received messages and the number of sent messages corresponding to a functional unit is greater than or equal to the first threshold, then it is determined that the functional module corresponding to the functional unit has experienced a message loss / message congestion fault, and the functional module corresponding to the functional unit is reset. If, within m consecutive acquisition cycles, the difference between the message transmission volume of the functional module corresponding to the preceding functional unit and the message reception volume of the functional module corresponding to the following functional unit is greater than or equal to the second threshold, then it is determined that a message loss / congestion fault has occurred in the link between the two functional modules, and the link between the two functional modules is reset.

[0014] Thirdly, embodiments of this application provide a network chip fault detection device, which includes: Memory, used to store program instructions; A processor is configured to invoke program instructions stored in the memory and execute the steps of the method as described in any one of the first aspects above, according to the obtained program instructions.

[0015] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the steps of the method as described in any of the first aspects above.

[0016] In summary, the network chip fault detection method provided in this application is applied to a testing device. The method includes: acquiring functional module information and connection relationship information between each functional module of the network chip to be tested; constructing a detection model of the network chip to be tested based on the functional module information and connection relationship information between each functional module, wherein the detection model includes functional units corresponding to each functional module and the connection relationship between each functional unit; collecting the message reception volume and message transmission volume of each functional module in the current collection period, and determining whether the network chip to be tested has a chip fault based on the message reception volume and message transmission volume of each functional module in the current period and the detection module.

[0017] The network chip fault detection method provided in this application abstracts the data forwarding path within a packet processor (including network processors, network chips, etc.) into an ordered connection link composed of several functional units, each with collectable input and output counts. This abstract model is independent of the fixed naming and order of specific hardware modules, enabling cross-platform fault detection logic. Under normal service flow conditions in the packet processor, the input / output counts of each functional unit are collected sequentially according to a set (or dynamically adjusted) detection cycle, and the count changes in adjacent detection cycles are compared to achieve continuous monitoring of the forwarding path. This method is applicable to various devices, including FTTR indoor optical gateways and room optical terminals. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments of this application or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings of the embodiments of this application.

[0019] Figure 1 A detailed flowchart of a network chip fault detection method provided in this application embodiment; Figure 2 A schematic diagram of a detection model for a network chip provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a network chip fault detection device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the hardware architecture of a network chip fault detection device provided in an embodiment of this application. Detailed Implementation

[0020] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “the,” and “the” as used in this application and claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any and all possible combinations comprising one or more of the associated listed items.

[0021] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" may also be interpreted as "when," "when," or "in response to a determination."

[0022] Currently, fault detection registers are pre-designed in various functional modules within packet processor chips (including traditional NPs and various network processing ASICs / SoCs) to monitor the module's operating status. When a specified flag bit in the detection register changes (such as an error code being set or a status bit being abnormal), the system can determine that the module has failed and handle it according to a preset recovery procedure.

[0023] This approach is typically defined by hardware engineers during the chip design phase. Each module has its own dedicated registers to record foreseeable anomalies, such as link errors, buffer overflows, and data verification failures. Register values ​​are retrieved via polling or interrupts by the driver or management software, enabling fault monitoring and response.

[0024] This results in registers being able to detect only predefined exception types and failing to detect faults not considered during the chip design phase (such as blocking caused by certain combinations of conditions or deadlocks under special protocol data). In contrast, the embodiments of this application can detect a wide range of actual operational faults by analyzing the flow transmission relationship between modules in real time, but the fault detection coverage is limited. The layout and function of registers are highly dependent on the specific chip architecture of the package processor and cannot be used interchangeably between different manufacturers. Some register values ​​are only set when the fault has seriously affected the module, which is a delayed detection.

[0025] Alternatively, the following method can be used for detection: A dedicated detection message is constructed and transmitted step-by-step within the packet processor chip along a predetermined forwarding path. The final egress module receives and tracks the arrival status of this detection message to determine if the forwarding function of each module is functioning correctly. If the detection message is lost or delayed en route, a problem is identified in the corresponding link, and fault handling is initiated.

[0026] However, this method is typically used when there is no traffic or low load. The detection packets are forwarded through the internal path to verify the packet reception, parsing, scheduling, and sending capabilities of each functional module. It is commonly used for pre-deployment self-testing or periodic inspections. A similar method can be used in FTTR devices to detect the forwarding link between the indoor optical gateway and the room optical terminal. When there are a large number of service packets in the network, the detection packets will mix with the service flow, affecting the normal forwarding path, and it is difficult to separate the detection packet data from the count under high traffic. Detection packets increase additional traffic and may interfere with existing services. In high-load scenarios, the transmission and statistics of detection packets are easily delayed, leading to a lag in fault location. This application provides a cross-platform, real-time packet processor fault detection method that can operate under streaming conditions. It is applicable to various scenarios, including traditional routing and switching equipment, data center equipment, and FTTR (Fiber to the Room) all-optical access network equipment. This method can be deployed in devices such as FTTR indoor optical gateways and room-level optical access units to perform unified, real-time fault detection and recovery on the multi-level forwarding paths of their internal packet processing chips.

[0027] For example, see Figure 1 The diagram shown is a detailed flowchart of a network chip fault detection method provided in an embodiment of this application. This method is applied to a detection device and includes the following steps: Step 100: Obtain the functional module information of each functional module included in the network chip to be tested and the connection relationship information between each functional module.

[0028] In this embodiment of the application, the detection device obtains complex and diverse data processing flow from the network chip (e.g., packet processor), and extracts the functional module information (e.g., functional module identifier, etc.) of each functional module of the network chip, as well as the connection relationship information between each functional module.

[0029] Step 110: Based on the functional module information of each functional module and the connection relationship information between each functional module, construct the detection model of the network chip to be detected.

[0030] The detection model includes functional units corresponding to each functional module, as well as the connection relationships between each functional unit.

[0031] For example, see Figure 2The diagram shown is a schematic of a network chip detection model provided in an embodiment of this application. In practical applications, the detection device may include a functional unit-link abstract model module, used to abstract each functional module into a functional unit (e.g., FU1, FU2, ..., FU5), and define two external interfaces for each functional unit (e.g., an input interface (Input Counter) for counting the number of data packets entering the unit, and an output interface (OutputCounter) for counting the number of data packets leaving the unit). The connection between adjacent functional units is called a link, used to carry data flow, and serves as an interval unit for judging the consistency of traffic transmission in detection analysis.

[0032] As can be seen from the above, in this embodiment of the application, the detection model is based on the internal structural components of the network chip. In this way, the detection model can be configured according to the number of functional modules and the length of the processing path of different packet processor architectures. Whether it is a linear pipeline structure or a branch or parallel path structure, it can be described by a link set.

[0033] In practical applications, network chips from different manufacturers may support the same or different data formats. That is, the data formats of the functional module information and the connection relationship information between the functional modules inside different network chips may be the same or different.

[0034] In this embodiment of the application, the detection device supports the target data format, and the detection device has preset conversion rules between the data format and the target data format for various functional module information and connection relationship information; If the data format of the functional module information and the connection relationship information between the functional modules included in the network chip to be tested is not the target data format, then the method further includes: The data format of the functional module information and the connection relationship information between the functional modules of the network chip under test is converted into the target data format.

[0035] Furthermore, when collecting data on the input interfaces and / or message statistics of each functional module from the chip under test, the format of the message statistics can be converted into a unified target data format.

[0036] In this embodiment of the application, when constructing the detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module, a preferred implementation is as follows: Based on the functional module information, functional units corresponding to each functional module are constructed respectively, and two external interfaces are defined for each functional unit. The two external interfaces include a first interface and a second interface. The first interface is a message receiving interface, and the second interface is a message sending interface. Based on the external interfaces corresponding to each functional unit and the connection information between each functional module, a connection link between each functional unit is constructed. The detection model of the network chip to be detected is constituted by the functional units corresponding to each functional module and the connection links between each functional unit.

[0037] In this embodiment, the detection device also includes a pre-configured unified acquisition interface layer (adaptation layer) module. This module provides a data access abstraction layer for packet processors with different architectures, shielding hardware differences, including register address allocation, data reading methods, and statistical field formats. The implementation can be a driver interface library, firmware module, or a separate acquisition process, defining data access rules for different chips through configuration files.

[0038] In this way, the data acquisition interface can be periodically called to obtain the input / output counts of each functional unit from the corresponding hardware registers or statistical modules; the raw data can be standardized (unified units, field names, timestamps, etc.) for analysis by the detection logic module.

[0039] When new packet processor chips are introduced to meet the detection requirements in practical applications, only the adaptation layer configuration or interface functions need to be updated, without modifying the core detection logic.

[0040] Step 120: Collect the message reception and message transmission volume of each functional module in the current collection period, and based on the message reception and message transmission volume of each functional module in the current period and the detection module, determine whether the network chip to be detected has a chip fault.

[0041] In this embodiment of the application, when determining whether the network chip to be detected has a chip fault based on the message reception and message transmission volume of each module in the current period and the detection module, a preferred implementation is as follows: For each functional unit, maintain the message reception and message transmission volume of the corresponding functional module within the current acquisition period; If it is determined that within n consecutive collection cycles, the difference between the number of received messages and the number of sent messages corresponding to a functional unit is greater than or equal to the first threshold, then it is determined that the functional module corresponding to the functional unit has experienced a message loss / message congestion fault, and the functional module corresponding to the functional unit is reset. If, within m consecutive acquisition cycles, the difference between the message transmission volume of the functional module corresponding to the preceding functional unit and the message reception volume of the functional module corresponding to the following functional unit is greater than or equal to the second threshold, then it is determined that a message loss / congestion fault has occurred in the link between the two functional modules, and the link between the two functional modules is reset.

[0042] The network chip fault detection method provided in this application determines that if the output count of the preceding functional unit increases while the input count of the following functional unit is zero or does not increase within a continuous detection period, the link is considered blocked or the following stage is faulty. Fault type classification can be improved by combining auxiliary indicators such as buffer occupancy rate, packet loss rate, and latency. This method can be applied to the packet processor and its room-level forwarding path within an FTTR device for quickly locating anomalies in specific rooms and links.

[0043] In other words, the detection equipment also includes a periodic detection mechanism module. Under normal business flow conditions, it initiates periodic detection tasks, which can be triggered by a timer or event. The initial detection period can be set to a fixed value (e.g., 3 seconds), and can also be dynamically adjusted based on network load and historical fault ratios. Within each period, all functional units are accessed sequentially, recording their input and output counts. The data collected in this period is compared with the data collected in the previous period to form a time series. The detection module maintains a circular buffer to store the most recent N collection results for trend analysis and abnormal pattern recognition.

[0044] The detection device also includes a blockage determination logic module. In practical applications, the core determination rule can be: for a link L(i) = FU(i) → FU(i+1), if one of the following conditions is met, the link is determined to be blocked or the downstream function is abnormal: The output count of FU(i) increases in two or more consecutive detection cycles, while the input count of FU(i+1) does not increase or remains zero; Traffic consistency deviation exceeds a preset threshold (e.g., output count increment per second – input count increment per second > threshold K). Recommended threshold K = Current module's maximum PPS processing capacity * 64 * 8 Output: The judgment module sends a blocking event to the fault classification and recovery module, which includes information such as the fault link identifier, triggering conditions, and relevant performance indicators.

[0045] The testing equipment may also include a fault classification and precise recovery strategy module, which can classify faults according to the judgment logic results and auxiliary indicators: Queue blocking type: The subsequent buffer queue is occupied at a high level for a continuous period of time, and data cannot be transmitted. The corresponding recovery strategy is to execute a cache cleanup command or trigger a flow table refresh.

[0046] Processing core failure type: The processing capability of the subsequent functional unit decreases or stops working; the corresponding recovery strategy is to partially restart the current functional unit or switch to the backup processing core.

[0047] Configuration table anomaly: Errors in routing / flow table / matching conditions cause data to fail to match or be sent. The corresponding recovery strategy is to reload the configuration table or issue a parameter correction command.

[0048] Recovery strategy execution principle: Prioritize performing recovery operations on a local scale to ensure that other links or global forwarding are not affected, and minimize service interruption time.

[0049] The following describes in detail the fault detection process of the network chip using the detection equipment provided in this application embodiment, taking into account specific application scenarios. The workflow of the detection equipment is as follows: Initialization phase: Construct the functional unit-link model and load the adaptation layer configuration; detect the timer periodic trigger events registered by the module.

[0050] Data acquisition phase: Periodically call the acquisition interface to obtain standardized input / output count data of all functional units.

[0051] Consistency analysis phase: The difference between the counts of adjacent functional units is calculated and the trend is analyzed to generate a consistency report of link traffic transmission.

[0052] Blockage determination phase: Based on the determination rules and multi-dimensional indicators, identify the faulty links and classify them.

[0053] Recovery execution phase: Execute the corresponding local recovery strategy for the classification results.

[0054] Log and Alarm Phase: Record collected data, judgment results, recovery process, and trigger management system alarms.

[0055] For example, the functional unit path built on a packet processor chip is: receive interface (FU1) → packet parsing unit (FU2) → flow scheduling unit (FU3) → output interface (FU4).

[0056] During the detection process, the FU2 output count increased by 5000 and 5200 in two consecutive cycles, while the FU3 input count remained at 0. Simultaneously, the FU3 buffer occupancy rate was 95%, indicating a blockage in the FU2→FU3 link (queue blocking type). The recovery module immediately performed buffer queue cleanup and triggered a flow table refresh. Subsequently, the FU3 input count returned to normal, and the blockage was resolved.

[0057] For example, see Figure 3The diagram shown is a structural schematic of a network chip fault detection device provided in an embodiment of this application. The device includes: The acquisition unit 30 is used to acquire the functional module information of each functional module included in the network chip under test and the connection relationship information between each functional module; The construction unit 31 is used to construct a detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module. The detection model includes functional units corresponding to each functional module and the connection relationship between each functional unit. The acquisition unit 32 is used to acquire the number of messages received and sent by each functional module in the current acquisition period; The determining unit 33 is used to determine whether the network chip to be detected has a chip fault based on the message reception and message transmission volume of each energy module in the current period and the detection module.

[0058] Optionally, when constructing the detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module, the construction unit 31 is specifically used for: Based on the functional module information, functional units corresponding to each functional module are constructed respectively, and two external interfaces are defined for each functional unit. The two external interfaces include a first interface and a second interface. The first interface is a message receiving interface, and the second interface is a message sending interface. Based on the external interfaces corresponding to each functional unit and the connection information between each functional module, a connection link between each functional unit is constructed. The detection model of the network chip to be detected is constituted by the functional units corresponding to each functional module and the connection links between each functional unit.

[0059] Optionally, the detection device supports the target data format, and the detection device has preset conversion rules between the data format of various functional module information and connection relationship information and the target data format; the device also includes a conversion unit: If the data format of the functional module information and the connection relationship information between the functional modules included in the network chip to be tested is not the target data format, then the conversion unit is used to: The data format of the functional module information and the connection relationship information between the functional modules of the network chip under test is converted into the target data format.

[0060] Optionally, when determining whether the network chip under test has a chip fault based on the message reception and message transmission volume of each module in the current period and the detection module, the determining unit 33 is specifically used for: For each functional unit, maintain the message reception and message transmission volume of the corresponding functional module within the current acquisition period; If it is determined that within n consecutive collection cycles, the difference between the number of received messages and the number of sent messages corresponding to a functional unit is greater than or equal to the first threshold, then it is determined that the functional module corresponding to the functional unit has experienced a message loss / message congestion fault, and the functional module corresponding to the functional unit is reset. If, within m consecutive acquisition cycles, the difference between the message transmission volume of the functional module corresponding to the preceding functional unit and the message reception volume of the functional module corresponding to the following functional unit is greater than or equal to the second threshold, then it is determined that a message loss / congestion fault has occurred in the link between the two functional modules, and the link between the two functional modules is reset.

[0061] These units can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when one of these units is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these units can be integrated together to form a system-on-a-chip (SOC).

[0062] Furthermore, regarding the network chip fault detection device provided in this application embodiment, from a hardware perspective, the hardware architecture schematic diagram of the network chip fault detection device can be found in [reference needed]. Figure 4 As shown, the network chip fault detection device may include: a memory 40 and a processor 41. The memory 40 is used to store program instructions; the processor 41 calls the program instructions stored in the memory 40 and executes the above method embodiment according to the obtained program instructions. The specific implementation method and technical effect are similar, and will not be described again here.

[0063] Optionally, this application also provides a network chip fault detection device, including at least one processing element (or chip) for performing the above method embodiments.

[0064] Optionally, this application also provides a program product, such as a computer-readable storage medium storing computer-executable instructions for causing the computer to perform the above-described method embodiments.

[0065] Here, a machine-readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, a machine-readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.

[0066] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0067] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0068] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0069] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0070] Furthermore, these computer program instructions can also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0071] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0072] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for detecting network chip faults, characterized in that, Applied to testing equipment; the method includes: Obtain the functional module information of each functional module included in the network chip under test and the connection relationship information between each functional module; Based on the functional module information of each functional module and the connection relationship information between each functional module, a detection model of the network chip to be detected is constructed. The detection model includes functional units corresponding to each functional module and the connection relationship between each functional unit. The system collects the message reception and transmission volumes of each functional module within the current collection period, and determines whether the network chip under test has a chip fault based on the message reception and transmission volumes of each functional module within the current period and the detection module.

2. The method as described in claim 1, characterized in that, The steps for constructing the detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module include: Based on the functional module information, functional units corresponding to each functional module are constructed respectively, and two external interfaces are defined for each functional unit. The two external interfaces include a first interface and a second interface. The first interface is a message receiving interface, and the second interface is a message sending interface. Based on the external interfaces corresponding to each functional unit and the connection information between each functional module, a connection link between each functional unit is constructed. The detection model of the network chip to be detected is constituted by the functional units corresponding to each functional module and the connection links between each functional unit.

3. The method as described in claim 1, characterized in that, The detection device supports the target data format, and the detection device has preset conversion rules between the data format and the target data format for various functional module information and connection relationship information. If the data format of the functional module information and the connection relationship information between the functional modules included in the network chip to be tested is not the target data format, then the method further includes: The data format of the functional module information and the connection relationship information between the functional modules of the network chip under test is converted into the target data format.

4. The method according to any one of claims 1-3, characterized in that, Based on the message reception and transmission volumes of each module in the current period and the detection module, the steps for determining whether the network chip under test has a chip fault include: For each functional unit, maintain the message reception and message transmission volume of the corresponding functional module within the current acquisition period; If it is determined that within n consecutive collection cycles, the difference between the number of received messages and the number of sent messages corresponding to a functional unit is greater than or equal to the first threshold, then it is determined that the functional module corresponding to the functional unit has experienced a message loss / message congestion fault, and the functional module corresponding to the functional unit is reset. If, within m consecutive acquisition cycles, the difference between the message transmission volume of the functional module corresponding to the preceding functional unit and the message reception volume of the functional module corresponding to the following functional unit is greater than or equal to the second threshold, then it is determined that a message loss / congestion fault has occurred in the link between the two functional modules, and the link between the two functional modules is reset.

5. A network chip fault detection device, characterized in that, Applied to testing equipment; the device includes: The acquisition unit is used to acquire the functional module information of each functional module included in the network chip under test and the connection relationship information between each functional module; A construction unit is used to construct a detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module. The detection model includes functional units corresponding to each functional module and the connection relationship between each functional unit. The data acquisition unit is used to collect the number of messages received and sent by each functional module during the current data acquisition period. The determining unit is used to determine whether the network chip to be detected has a chip fault based on the message reception and message transmission volume of each energy module in the current period and the detection module.

6. The apparatus as claimed in claim 5, characterized in that, When constructing the detection model of the network chip to be detected based on the functional module information of each functional module and the connection relationship information between each functional module, the construction unit is specifically used for: Based on the functional module information, functional units corresponding to each functional module are constructed respectively, and two external interfaces are defined for each functional unit. The two external interfaces include a first interface and a second interface. The first interface is a message receiving interface, and the second interface is a message sending interface. Based on the external interfaces corresponding to each functional unit and the connection information between each functional module, a connection link between each functional unit is constructed. The detection model of the network chip to be detected is constituted by the functional units corresponding to each functional module and the connection links between each functional unit.

7. The apparatus as claimed in claim 5, characterized in that, The detection device supports the target data format, and the device has pre-set conversion rules between the data formats of various functional module information and connection relationship information and the target data format; the device also includes a conversion unit. If the data format of the functional module information and the connection relationship information between the functional modules included in the network chip to be tested is not the target data format, then the conversion unit is used to: The data format of the functional module information and the connection relationship information between the functional modules of the network chip under test is converted into the target data format.

8. The apparatus according to any one of claims 5-7, characterized in that, Based on the message reception and transmission volumes of each module in the current period and the detection module, when determining whether the network chip under test has a chip fault, the determining unit is specifically used for: For each functional unit, maintain the message reception and message transmission volume of the corresponding functional module within the current acquisition period; If it is determined that within n consecutive collection cycles, the difference between the number of received messages and the number of sent messages corresponding to a functional unit is greater than or equal to the first threshold, then it is determined that the functional module corresponding to the functional unit has experienced a message loss / message congestion fault, and the functional module corresponding to the functional unit is reset. If, within m consecutive acquisition cycles, the difference between the message transmission volume of the functional module corresponding to the preceding functional unit and the message reception volume of the functional module corresponding to the following functional unit is greater than or equal to the second threshold, then it is determined that a message loss / congestion fault has occurred in the link between the two functional modules, and the link between the two functional modules is reset.

9. A network chip fault detection device, characterized in that, The network chip fault detection device includes: Memory, used to store program instructions; A processor is configured to invoke program instructions stored in the memory and execute the steps of the method as described in any one of claims 1-4 according to the obtained program instructions.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing the computer to perform the steps of the method as described in any one of claims 1-4.

Images