A method and system for transmitting control of underwater acoustic communication
By employing a ping-pong mechanism of dual-buffered storage and hardware data transfer engine in the embedded underwater acoustic communication system, combined with high-speed cache write-back and anti-multipath OFDM frame structure, the problems of discontinuous signal output and memory access conflicts are solved, and stable communication under high sampling rate is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUJIAN UNIV OF TECH
- Filing Date
- 2026-03-27
- Publication Date
- 2026-06-05
AI Technical Summary
Existing embedded underwater acoustic communication transmission systems suffer from imperfect hardware transmission mechanisms and low memory access efficiency at high sampling rates, resulting in discontinuous signal output, poor timing determinism, and a tendency for memory access conflicts, which affect communication reliability and stability.
The system employs a ping-pong mechanism with dual-buffered storage space and a hardware data transfer engine, combined with high-speed cache forced write-back, and implements parallel pipeline transmission through a multi-level storage architecture to avoid bus conflicts. It also designs an OFDM signal frame structure that resists multipath to ensure signal continuity and correctness.
On resource-constrained embedded platforms, stable and continuous generation of OFDM signals at high sampling rates was achieved, eliminating bus conflicts and buffering risks, maintaining subcarrier orthogonality, and improving communication reliability and multipath resistance.
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Figure CN122160432A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of underwater acoustic communication technology, specifically relating to an underwater acoustic communication transmission control method and system, which is particularly suitable for resource-constrained underwater mobile platforms. Background Technology
[0002] Underwater acoustic communication is a key technology for realizing underwater information transmission. With the rapid development of marine resource development and underwater sensor networks, applications such as underwater unmanned vehicle collaboration and seabed observation have created an urgent need for high-speed, reliable, and real-time underwater acoustic communication systems.
[0003] Orthogonal Frequency Division Multiplexing (OFDM) technology has great potential in underwater acoustic broadband communication due to its high spectral efficiency and strong multipath resistance. However, OFDM signal generation involves intensive computations such as large-point inverse fast Fourier transform and requires extremely high timing accuracy for continuous baseband signal output. In resource-constrained and power-constrained underwater mobile platforms, embedded microcontrollers are typically used as the core control unit. With the continuous improvement of underwater acoustic communication sampling rates and data throughput, existing microcontroller-based transmission schemes are gradually revealing the limitations of their underlying architecture: On the one hand, to meet the high computing power requirements of OFDM, modern high-performance microcontrollers typically introduce multi-level storage and caching mechanisms. However, in high-concurrency transmission scenarios, high-frequency signal calculation and high-throughput data transfer can easily lead to bus access conflicts. When the caching mechanism works in conjunction with a hardware data transfer engine (DMA) independent of the kernel, it is prone to cache consistency problems, causing the transfer engine to read outdated data that has not been updated, resulting in data flow interruption or timing jitter. Any timing disruption at the sampling level will severely damage the orthogonality between OFDM subcarriers, causing severe inter-carrier interference (ICI) and inter-symbol interference (ISI), leading to communication link deterioration.
[0004] On the other hand, the complex and ever-changing underwater channels suffer from severe multipath effects. When conventional communication frame structures are used for broadband high-speed transmission, the receiver often struggles to achieve accurate symbol-level start position locking under long-delay echo interference, which greatly affects the accuracy of demodulation and the reliability of communication.
[0005] Therefore, how to eliminate bus conflicts and cache risks through the coordinated optimization of the underlying hardware and software architecture on resource-constrained embedded platforms, and design an anti-multipath mechanism that matches the underwater acoustic channel to build an underwater acoustic communication system that can stably and continuously transmit high-quality OFDM signals has become a key technical problem that urgently needs to be solved in this field. Summary of the Invention
[0006] To address the aforementioned problems in the existing technology, this application proposes an underwater acoustic communication transmission control method and system to solve the technical difficulties of existing embedded underwater acoustic communication transmission systems under high sampling rate operating conditions, such as discontinuous signal output, poor timing determinism, and easy memory access conflicts under high load, due to imperfect hardware transmission mechanisms and low memory access efficiency. To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides an underwater acoustic communication transmission control method, applied in a processor with a multi-level storage and cache architecture, the method comprising the following steps: Step S1: Pre-allocate double-buffered storage space in the physical storage area of the processor, the double-buffered storage space including a first buffer and a second buffer; Step S2: The underwater acoustic communication data to be transmitted is processed by multi-carrier digital modulation to generate a time-domain digital signal sequence; Step S3: In response to the completion status of the filling of the time-domain digital signal sequence into the first buffer, perform a cache coherence synchronization operation for the first buffer to write back the latest data in the processor's cache to the physical storage area; Step S4: Trigger the hardware data transfer engine, which is independent of the processor core, to transmit the time-domain digital signal sequence in the first buffer to the digital-to-analog converter front end via an external communication interface for signal conversion; Step S5: During the process of the hardware data transport engine transporting the data stream of the first buffer, the subsequently generated time-domain digital signal sequence is filled into the second buffer which is in an idle state to establish a parallel pipeline transmission mechanism based on a multi-level storage architecture. The underwater acoustic communication data to be transmitted is continuously transmitted to the digital-to-analog converter front end through the alternating filling and transmission of the first buffer and the second buffer.
[0007] By constructing a zero-copy and ping-pong buffer mechanism based on a hardware data transfer engine, the CPU is decoupled from tedious data transfer. Combined with forced write-back of the cache, the problem of reading old data and data stream transmission interruption under high sampling rate is completely solved, ensuring the determinism and uninterrupted output of OFDM signal stream.
[0008] Preferably, the processor includes an instruction tightly coupled memory, a data tightly coupled memory, and a static random access memory (SRAM) supporting direct bus matrix connection. The method further includes: storing the instruction code corresponding to the multi-carrier digital modulation processing and the related interrupt service routines into the instruction tightly coupled memory and the data tightly coupled memory respectively, and mapping the double-buffered storage space into the SRAM to avoid bus access conflicts during high-frequency concurrent data access. This fully leverages the advantages of the processor's heterogeneous memory architecture, achieving physical isolation between instruction fetching and large data block access, reducing memory access conflict latency under high system load, and improving the system's real-time execution speed.
[0009] Preferably, step S3 specifically includes: obtaining the addressing start address and data segment length of the first buffer; and forcibly triggering a cache maintenance mechanism based on the addressing start address and data segment length to prevent the hardware data transfer engine from retrieving outdated data from the physical storage area. This achieves precise high-speed cache consistency maintenance, explicitly eliminating the differences between the cache and physical memory before initiating transmission, and ensuring the correctness of the transmitted signals.
[0010] Preferably, the multi-carrier digital modulation processing in step S2 includes: performing QDPSK (orthogonal differential phase shift keying) symbol mapping on the underwater acoustic communication data to be transmitted, and allocating the mapped symbols to predefined data subcarriers and pilot subcarriers; calling the processor's built-in hardware digital signal processing instruction set and floating-point arithmetic unit to perform IFFT (inverse fast Fourier transform) operations to output a data stream converted from the frequency domain to the time domain; embedding a synchronization preamble sequence at the front end of the data stream, and adding anti-multipath protection intervals to each OFDM symbol in the data stream to construct an initial time-domain signal. By fully utilizing the processor's hardware acceleration units (DSP and FPU) to process large-point IFFT operations, efficient generation and anti-multipath processing of high-frequency broadband OFDM signals are achieved on a low-cost embedded platform.
[0011] Preferably, the frame structure of the initial time-domain signal sequentially includes, on the time axis: a linear frequency modulation preamble segment, a first blanking interval, a sweep frequency synchronization segment, a second blanking interval, and a repeating unit sequence containing the anti-multipath protection interval and OFDM symbols; wherein, the linear frequency modulation preamble segment is used to provide an initial time reference, and the sweep frequency synchronization segment is used to precisely lock the starting position of the OFDM symbols. A dedicated frame structure is designed for the characteristics of underwater acoustic channels. Multipath echo energy is eliminated through dual-interval design, and the effectiveness and accuracy of the OFDM demodulation process at the receiving end are ensured through coarse and fine two-stage synchronization design, guaranteeing reliable transmission of the communication link under complex marine channels.
[0012] Preferably, step S2 further includes: performing amplitude normalization processing on the generated time-domain digital signal sequence to avoid the risk of overdrive in the power amplifier of the subsequent RF output stage. Through software-level amplitude limiting, the downstream analog hardware circuitry is protected, and the physical security and signal distortion resistance of the entire transmission system are improved.
[0013] Preferably, after triggering the hardware data transfer engine in step S4, the method further includes: triggering a transmission completion interrupt in response to the hardware data transfer engine completing the data transfer in the current buffer; and in the interrupt service routine, toggling a global status flag, and the main program, according to the indication of the global status flag, alternately filling the currently idle first buffer or second buffer with the subsequently generated time-domain digital signal sequence. This effectively avoids transmission interruptions caused by CPU polling or untimely data preparation.
[0014] In a second aspect, the present invention provides an underwater acoustic communication transmission system, comprising: The processor integrates multi-level memory, cache, and a hardware data transfer engine independent of the processor core. The digital-to-analog converter front end is connected to the processor via a digital communication bus; A power amplifier network is connected to the analog output node of the digital-to-analog converter front end; The transducer is electrically coupled to the output of the power amplifier network; The processor is configured to execute the underwater acoustic communication transmission control method described above.
[0015] Preferably, the processor is an STM32H743 microcontroller, and the digital-to-analog converter front end is a WM8978 audio codec.
[0016] Preferably, the power amplification network includes a Class D amplifier; the GPIO pins of the processor are coupled to the enable control terminal of the Class D amplifier, and the processor is configured to output a specific level signal to release the Class D amplifier from its sleep state in response to a start command for underwater acoustic transmission. While ensuring the driving capability of the transmitter, precise dynamic enable control of high-power analog devices via digital pins achieves system-level low-power management, making it particularly suitable for resource-constrained underwater platforms powered by batteries.
[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) Compared with the high power consumption of traditional DSP (Digital Signal Processor) or the high complexity and high dynamic power consumption of FPGA (Field Programmable Gate Array), this invention fully explores the high clock frequency, double precision FPU (Floating Point Unit) and heterogeneous memory potential of modern microcontrollers (especially STM32H743), and realizes the continuous generation of complex OFDM (Orthogonal Frequency Division Multiplexing) signals efficiently and stably on a low-cost, resource-constrained embedded platform.
[0018] (2) Compared with the existing MCU-based underwater acoustic solutions, which are prone to timing jitter and frame loss at high sampling rates, this invention deeply integrates hardware DMA (hardware data transfer engine), heterogeneous memory space mapping, MPU (memory protection unit) attribute control and explicit cache (cache) consistency maintenance mechanism, eliminates transmission gaps caused by internal processing delays and bus contention, maintains strict subcarrier orthogonality, and effectively avoids ICI (inter-subcarrier interference) and ISI (inter-symbol interference). Attached Figure Description
[0019] The accompanying drawings provide further illustration of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Other features, objects, and advantages of this application will become more apparent from reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A main flowchart of an underwater acoustic communication transmission control method provided in a specific embodiment of the present invention; Figure 2 A hardware architecture diagram of an underwater acoustic communication transmission system provided in a specific embodiment of the present invention; Figure 3 A schematic diagram of the peripheral circuit of the WM8978 audio codec provided in a specific embodiment of the present invention; Figure 4 The software and hardware processing architecture and storage mapping diagram of the launch system provided in a specific embodiment of the present invention; Figure 5 A timing block diagram of an OFDM (Orthogonal Frequency Division Multiplexing) signal frame structure provided in a specific embodiment of the present invention; Figure 6 The software sending logic and double-buffered scheduling flowchart provided for a specific embodiment of the present invention.
[0020] The meanings of the numbers in the diagram are as follows: 01-Processor, 02-Digital-to-analog conversion front end, 03-Power amplifier network, 04-Transducer, 05-Power management module. Detailed Implementation
[0021] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0022] In the description of this invention, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
[0023] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed", "equipped", "sleeved / connected", "connected", etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.
[0024] To facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0025] This invention first provides an underwater acoustic communication transmission system. The system's overall architecture mainly includes: a processor, which integrates multi-level memory, cache, and a hardware data transfer engine independent of the processor core; a digital-to-analog converter front-end connected to the processor via a digital communication bus; a power amplifier network connected to the analog output node of the digital-to-analog converter front-end; and a transducer electrically coupled to the output of the power amplifier network.
[0026] Based on the above system architecture, embodiments of the present invention also provide an underwater acoustic communication transmission control method. For example... Figure 1 The main flowchart shown illustrates that this method, which can be executed by the processor in the aforementioned system, specifically includes the following steps: Step S1: Pre-allocate double-buffered storage space in the physical storage area of the processor, the double-buffered storage space including a first buffer and a second buffer; Step S2: The underwater acoustic communication data to be transmitted is processed by multi-carrier digital modulation to generate a time-domain digital signal sequence; Step S3: In response to the completion status of the filling of the time-domain digital signal sequence into the first buffer, perform a cache coherence synchronization operation for the first buffer to write back the latest data in the processor's cache to the physical storage area; Step S4: Trigger the hardware data transfer engine, which is independent of the processor core, to transmit the time-domain digital signal sequence in the first buffer to the digital-to-analog converter front end via an external communication interface for signal conversion; Step S5: During the process of the hardware data transport engine transporting the data stream of the first buffer, the subsequently generated time-domain digital signal sequence is filled into the second buffer which is in an idle state, and the underwater acoustic communication data to be sent is continuously transmitted to the digital-to-analog converter front end through the alternating filling and transmission of the first buffer and the second buffer.
[0027] To further illustrate the preferred implementation of the above system and method in specific engineering practice, the following section provides a detailed explanation of specific chip selection, circuit connection relationships, and specific underwater acoustic channel frame structures.
[0028] like Figure 2 The hardware architecture diagram of the specific underwater acoustic communication transmission system shown is as follows. In order to correspond with the aforementioned system architecture, the system mainly includes the following components in its overall physical architecture: processor 01, digital-to-analog conversion front end 02, power amplifier network 03, and transducer 04. In addition, it also includes a power management module 05 that provides physical power support for the system.
[0029] In terms of physical hardware connections, the processor 01 is connected to the digital-to-analog converter front-end 02 via a digital communication bus; the input terminal of the power amplifier network 03 is connected to the analog output node of the digital-to-analog converter front-end 02; and the transducer 04 is electrically coupled to the output terminal of the power amplifier network 03.
[0030] Specifically, in the model implementation and detailed architecture of this preferred embodiment, the processor 01 is a microcontroller of model STM32H743, the digital-to-analog conversion front-end 02 is an audio codec of model WM8978, and the transducer 04 is an underwater acoustic transducer.
[0031] Specifically, the STM32H743 microcontroller, which serves as processor 01, internally includes a Cortex-M7 core, an FPU (floating-point unit), a DSP (digital signal processing) instruction set, a cache, and a DMA (direct memory access) controller. Processor 01 is also connected to external SDRAM (synchronous dynamic random access memory), as well as communication peripheral interfaces such as USART (Universal Synchronous Asynchronous Receiver / Transmitter), SAI (Serial Audio Interface), and I2C (Internal Integrated Circuit).
[0032] In terms of specific pin and bus connections, processor 01 connects to the WM8978 audio codec (digital-to-analog converter front-end 02) via the I2C bus and transmits digital audio data to it via the SAI interface. The power amplifier network 03 specifically includes a power amplifier, a boost circuit, and a switching circuit. It receives the analog signal converted by the WM8978, amplifies it, and then unidirectionally drives the transducer 04. Preferably, the power amplifier is a Class D amplifier. Because Class D amplifiers have the advantage of high electroacoustic conversion efficiency but also have a certain static power consumption, in terms of system control, processor 01 is directly coupled to the enable control terminal of the Class D amplifier via its GPIO pin, responding to a task by outputting a specific level to control its sleep or wake-up state.
[0033] like Figure 3 The WM8978 peripheral circuit design and configuration shown demonstrate its hardware and software integration with processor 01. Processor 01 connects to the control pins of WM8978 via an I2C interface to configure its registers and complete initialization processes such as power management, sampling rate, and output gain. In the digital audio data transmission channel, processor 01's SAI interface is configured in master mode, operating in I2S (Integrated Audio Bus) mode or LSB / MSB (Least Significant Bit / Most Significant Bit) aligned mode, interacting with WM8978's digital audio interface. To meet the high sampling rate requirements of broadband underwater acoustic communication, the system sets the PLL3 (Phase-Locked Loop) multiplier within processor 01 to ensure the SAI interface outputs a precise 96kHz sampling rate clock to WM8978. WM8978 converts the received digital audio into an analog signal via its built-in digital-to-analog converter, which, after internal output stage conditioning, is sent to the subsequent power amplifier network 03.
[0034] For the specific hardware platform mentioned above, combined with Figures 4 to 6 The core steps of the underwater acoustic communication transmission control method are broken down and explained in detail: In step S1, system initialization and memory mapping are performed: High-concurrency sampling streams can easily lead to bus access conflicts within the microcontroller. For example... Figure 4As shown in the hardware and software processing architecture and storage mapping diagram, this embodiment implements system-level hardware and software co-optimization. By configuring a distributed loading file, the instruction code corresponding to the OFDM (Orthogonal Frequency Division Multiplexing) modulation core algorithm is embedded in the processor's ITCM-RAM (Instruction Tightly Coupled Memory), while real-time response code such as DMA interrupt service routines is placed in DTCM-RAM (Data Tightly Coupled Memory) to achieve zero-wait execution latency. Simultaneously, the double-buffered storage space required for DMA transfer (i.e., the first buffer Ping and the second buffer Pong) is physically mapped to AXI SRAM (Static Random Access Memory) that supports direct bus matrix connection, ensuring the independence of high-bandwidth data access. Furthermore, the system utilizes the microcontroller's MPU (Memory Protection Unit) to configure corresponding access attributes and caching strategies for the aforementioned code area, data buffer, and peripheral register area, avoiding bus contention from the underlying layer.
[0035] In step S2, signal modulation and frame construction are performed: Combination Figure 4 The processing architecture on the left and Figure 5 As shown in the timing block diagram of the OFDM signal frame structure, the baseband data processing first performs QDPSK (orthogonal differential phase shift keying) symbol mapping on a segment of characters, and allocates the symbol matrix to predefined data subcarriers and pilot subcarriers; then, it calls the processor's efficient hardware DSP instruction set and FPU (floating point unit) to perform IFFT (inverse fast Fourier transform) operation to generate time-domain OFDM symbols, and appends CP (cyclic prefix) to each symbol to mitigate multipath effects.
[0036] To ensure accurate demodulation at the receiver in complex underwater acoustic channels, the system combines the processed signals into a specially designed frame structure (see...). Figure 5 The time-axis layout is as follows: An LFM (Linear Frequency Modulation) preamble signal segment is embedded at the beginning for signal presence detection and initial time reference synchronization within a large uncertainty range; this is followed by a first blank interval; then a sweep frequency synchronization signal segment is inserted to accurately capture and lock the starting position of subsequent OFDM symbols; this is followed by a second blank interval; finally, a repeating unit sequence consisting of CP plus OFDM symbols. This dual-interval and dual-stage synchronization design effectively overcomes the interference of underwater long-delay multipath echoes. Finally, the constructed initial time-domain signal sequence is amplitude normalized to avoid the risk of power amplifier overdrive due to peak-to-average power ratio (PAPR) issues.
[0037] In step S3, cache consistency maintenance is performed: Because the CPU uses a cache to accelerate data processing, after the CPU fills the processed normalized signal data into the first buffer (Ping area), the latest data often remains temporarily in the cache and is not actually written to the AXI SRAM. To ensure the absolute correctness of independent DMA transfers, before initiating DMA transfer, the system obtains the addressing start address and data segment length of the first buffer, explicitly calls the cache clean function, and forcibly triggers the cache coherency maintenance mechanism to ensure that the data subsequently retrieved from physical memory by DMA is necessarily the latest updated data.
[0038] In steps S4 and S5, pipelined delivery and double-buffered scheduling are performed: like Figure 6 As shown in the software transmission logic and double-buffered scheduling flowchart, the system configures the DMA controller to circular buffer mode. When a transmission command is received and a free buffer is available, the CPU performs data filling. After filling and buffer clearing are completed, the DMA hardware data transfer engine is triggered to achieve zero-copy data transfer from the first buffer to the SAI interface register.
[0039] During the independent and continuous transfer of the first buffer data stream in the background by DMA, the CPU main program enters a loop to judge. If it detects that the second buffer (Pong area) is in an idle state, the CPU does not need to block and wait for DMA to end. Instead, it directly fills the second buffer with the subsequently generated underwater acoustic communication data, thus establishing a parallel pipeline in space and time.
[0040] When the DMA completes the data transfer in the current buffer, a transfer completion interrupt is automatically triggered. In the interrupt service routine, the global status flag (Isread) is toggled by polling the DMA status register. The main program then alternately locks the filling target based on the indication of this status flag, and the DMA seamlessly connects to point the SAI interface to the next buffer for outgoing data. This ping-pong mechanism of alternating hardware and software state machine handshakes greatly reduces the CPU's interrupt response overhead and completely realizes strictly continuous and uninterrupted OFDM data push under high sampling rate conditions.
[0041] At the same time, combined Figure 6 In the logical judgment branch, the main program continuously checks whether all underwater acoustic communication data to be sent has been transmitted during the scheduling process. If not, the system continues to execute double buffering alternating filling and cyclic transmission according to the above process; if it is determined that all data has been transmitted, the current transmission task ends, and related peripherals and interfaces are simultaneously shut down (such as controlling the aforementioned power amplifier to enter sleep mode), thereby effectively reducing the overall power consumption of the system.
[0042] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.
Claims
1. A method for controlling underwater acoustic communication transmission, characterized in that, Applied to processors with multi-level storage and cache architecture, the method includes the following steps: Step S1: Pre-allocate double-buffered storage space in the physical storage area of the processor, the double-buffered storage space including a first buffer and a second buffer; Step S2: The underwater acoustic communication data to be transmitted is processed by multi-carrier digital modulation to generate a time-domain digital signal sequence; Step S3: In response to the completion of filling the first buffer by the time-domain digital signal sequence, perform a cache coherence synchronization operation for the first buffer to write back the latest data in the processor's cache to the physical storage area. Step S4: Trigger the hardware data transfer engine, which is independent of the processor core, to transmit the time-domain digital signal sequence in the first buffer to the digital-to-analog converter front end via an external communication interface for signal conversion; Step S5: During the process of the hardware data transport engine transporting the data stream of the first buffer, the subsequently generated time-domain digital signal sequence is filled into the second buffer which is in an idle state, and the underwater acoustic communication data to be sent is continuously transmitted to the digital-to-analog converter front end through the alternating filling and transmission of the first buffer and the second buffer.
2. The underwater acoustic communication transmission control method according to claim 1, characterized in that, The processor includes an instruction tightly coupled memory, a data tightly coupled memory, and a static random access memory that supports direct bus matrix connection; the method further includes: storing the instruction code corresponding to the multi-carrier digital modulation processing and the related interrupt service routine into the instruction tightly coupled memory and the data tightly coupled memory respectively, and mapping the double buffer storage space to the static random access memory.
3. The underwater acoustic communication transmission control method according to claim 1, characterized in that, Step S3 specifically includes: Obtain the starting address and data segment length of the first buffer; The cache maintenance mechanism is forcibly triggered based on the addressing start address and data segment length.
4. The underwater acoustic communication transmission control method according to claim 1, characterized in that, The multi-carrier digital modulation processing in step S2 includes: The underwater acoustic communication data to be transmitted is subjected to QDPSK symbol mapping, and the mapped symbols are assigned to predefined data subcarriers and pilot subcarriers. The processor's built-in hardware digital signal processing instruction set and floating-point arithmetic unit are invoked to perform IFFT operations, so as to output the data stream after frequency domain to time domain conversion; A synchronization preamble sequence is embedded at the front end of the data stream, and anti-multipath guard intervals are added to each OFDM symbol in the data stream to construct an initial time-domain signal.
5. The underwater acoustic communication transmission control method according to claim 4, characterized in that, The frame structure of the initial time-domain signal includes, in sequence on the time axis: a linear frequency modulation preamble segment, a first blanking interval, a sweep frequency synchronization segment, a second blanking interval, and a repeating unit sequence containing the anti-multipath protection interval and OFDM symbols; wherein, the linear frequency modulation preamble segment is used to provide an initial time reference, and the sweep frequency synchronization segment is used to precisely lock the starting position of the OFDM symbols.
6. The underwater acoustic communication transmission control method according to claim 1, characterized in that, Step S2 further includes: performing amplitude normalization processing on the generated time-domain digital signal sequence.
7. The underwater acoustic communication transmission control method according to claim 1, characterized in that, After the hardware data transfer engine is triggered in step S4, the method further includes: triggering a transfer completion interrupt in response to the hardware data transfer engine completing the data transfer of the current buffer; and in the interrupt service routine, flipping the global status flag, and the main program, according to the indication of the global status flag, alternately filling the currently idle first buffer or second buffer with the subsequently generated time-domain digital signal sequence.
8. An underwater acoustic communication transmission system, characterized in that, include: The processor integrates multi-level memory, cache, and a hardware data transfer engine independent of the processor core. The digital-to-analog converter front end is connected to the processor via a digital communication bus; A power amplifier network is connected to the analog output node of the digital-to-analog converter front end; The transducer is electrically coupled to the output of the power amplifier network; The processor is configured to execute the underwater acoustic communication transmission control method as described in any one of claims 1 to 7.
9. The underwater acoustic communication transmission system according to claim 8, characterized in that, The processor is an STM32H743 microcontroller, and the digital-to-analog converter front end is a WM8978 audio codec.
10. The underwater acoustic communication transmission system according to claim 8, characterized in that, The power amplifier network includes a Class D amplifier; the processor's GPIO pin is coupled to the enable control terminal of the Class D amplifier, and the processor is configured to output a specific level signal to release the Class D amplifier from sleep state in response to a start command of the underwater acoustic transmission task.