Wiring substrate
By employing a multi-layer structure and a low thermal expansion coefficient glass plate on the wiring substrate, combined with a reasonable through-hole conductor configuration, the problem of easy cracking of the glass substrate was solved, realizing a high-quality and thin wiring substrate design, and ensuring the reliable installation of electronic components.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- IBIDEN CO LTD
- Filing Date
- 2025-11-25
- Publication Date
- 2026-06-05
Smart Images
Figure CN122161004A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to wiring substrates. Background Technology
[0002] Patent Document 1 discloses a wiring substrate. The wiring substrate has a glass substrate and a core substrate containing through-hole conductors that penetrate the substrate. Resin insulating layers and conductor layers are alternately laminated on both sides of the core substrate.
[0003] Patent Document 1: Japanese Patent Application Publication No. 2024-118643
[0004] Multiple through holes are formed on a glass substrate. Due to the characteristics of the glass substrate, cracks may occur around the through holes. Summary of the Invention
[0005] The wiring substrate of the present invention includes: a core comprising a glass plate having a first side and a second side opposite to the first side; and a laminated portion formed on both sides of the glass plate, comprising stacked conductor layers and insulating layers. The laminated portion comprises four or more conductor layers and four or more insulating layers. The core includes a plurality of through-hole conductors connecting the conductor layers formed in the laminated portion on the first side to the conductor layers formed in the laminated portion on the second side. The glass plate has a thickness of 0.4 mm or more and 1.2 mm or less, and a coefficient of thermal expansion of 3 ppm / °C or more and 5 ppm / °C or less. The minimum spacing between the plurality of through-hole conductors is 200 μm or more and 400 μm or less.
[0006] According to embodiments of the present invention, a high-quality wiring substrate can be provided that suppresses the generation of cracks in the glass plate constituting the core. Attached Figure Description
[0007] Figure 1 This is a cross-sectional view illustrating an example of a wiring substrate according to an embodiment of the present invention.
[0008] Figure 2 This is a top view showing the surface of the core portion in a wiring substrate according to an embodiment of the present invention.
[0009] Figure 3A This is a cross-sectional view illustrating an example of the manufacturing process of a wiring board.
[0010] Figure 3B This is a cross-sectional view illustrating an example of the manufacturing process of a wiring board.
[0011] Figure 3C This is a cross-sectional view illustrating an example of the manufacturing process of a wiring board.
[0012] Figure 3DThis is a cross-sectional view illustrating an example of the manufacturing process of a wiring board.
[0013] Figure 3E This is a cross-sectional view illustrating an example of the manufacturing process of a wiring board.
[0014] Figure 3F This is a cross-sectional view illustrating an example of the manufacturing process of a wiring board.
[0015] Figure 3G This is a cross-sectional view illustrating an example of the manufacturing process of a wiring board.
[0016] Figure 3H This is a cross-sectional view illustrating an example of the manufacturing process of a wiring board.
[0017] Label Explanation
[0018] 1: Wiring substrate; 11: First stacked layer; 12: Second stacked layer; 113, 123: Through-hole conductors; 100A: First surface; 100B: Second surface; 100G: Glass plate; 100: Core; 111, 121: Insulating layer; 112, 122: Conductor layer; 100t: Through-hole conductor; PT: Spacing; CT: Center; DA: Diameter; SP: Space. Detailed Implementation
[0019] The wiring substrate of the present invention is described with reference to the accompanying drawings. Figure 1 A cross-sectional view of a wiring substrate 1, as an example of a wiring substrate according to an embodiment, is shown. The wiring substrate 1 has a core 100, which has a first surface 100A and a second surface 100B, which is the opposite surface of the first surface 100A. The core 100 is composed of a glass plate 100G and a through-hole conductor 100t that fills the through holes 100h formed in the glass plate 100G with a conductor.
[0020] The wiring substrate of this embodiment has laminated portions formed by four or more insulating layers and four or more conductor layers on each of its two sides of the core. The first side 100A and the second side 100B are formed by the surface of the glass plate 100G and the surface of the through-hole conductor 100t. A first laminated portion 11 is formed on the first side 100A. A second laminated portion 12 is formed on the second side 100B.
[0021] Furthermore, in the description of the wiring substrate in this embodiment, the side away from the core 100 is also referred to as "upper," "upper side," "outer side," or "outer," and the side closer to the core 100 is also referred to as "lower," "lower side," "inner side," or "inner." Additionally, in each insulating layer and conductor layer, the surface facing the side opposite to the core 100 is also referred to as the "upper surface," and the surface facing the core 100 is also referred to as the "lower surface." Therefore, for example, in the description of the elements constituting the first stacked portion 11 and the second stacked portion 12, the side away from the core 100 is also referred to as "upper side," "above," "upper layer side," "outer side," or simply "upper" or "outer," and the side closer to the core 100 is also referred to as "lower side," "below," "lower layer side," "inner side," or simply "lower" or "inner."
[0022] The first stacked layer 11 is composed of an insulating layer 111 and a conductor layer 112 alternately stacked on a first surface 100A of the core 100. The second stacked layer 12 is composed of an insulating layer 121 and a conductor layer 122 alternately stacked on a second surface 100B of the core 100. The insulating layer 111 constituting the first stacked layer 11 includes a via conductor 113 that connects conductors (conductor layers 112 or conductor layers 112 and via conductors 100t) formed on opposite sides of the insulating layer 111 in the thickness direction. The insulating layer 121 constituting the second stacked layer 12 includes a via conductor 123 that connects conductors (conductor layers 122 or conductor layers 122 and via conductors 100t) formed on opposite sides of the insulating layer 121 in the thickness direction.
[0023] A solder resist layer SR1 is formed on the first laminate 11. A solder resist layer SR2 is formed on the second laminate 12. An opening SR1o is formed in the solder resist layer SR1, through which the conductor pad 112p of the outermost conductor layer 112 in the first laminate 11 is exposed. An opening SR2o is formed in the solder resist layer SR2, through which the conductor pad 122p of the outermost conductor layer 122 in the second laminate 12 is exposed.
[0024] Conductor pad 112p can be a connection pad for mounting external electronic components, etc. As shown, conductor pad 112p can be electrically and mechanically connected to connection pads of external element IP, such as silicon interposers, through bonding materials such as solder. In the illustrated example, electronic components (e.g., logic chips, memory elements) such as semiconductor integrated circuit devices, transistors, etc., i.e., components E1 and E2, are connected to the external element IP. That is, electronic components can be mounted on the wiring substrate 1 via an interposer. On the other hand, conductor pad 122p can be a connection pad for connecting to any substrate, electrical component, or mechanical component (not shown), such as an external motherboard.
[0025] In the illustrated example, a reinforcing material ST is provided on the solder mask layer SR1. The reinforcing material ST is positioned to surround the area where the external element IP is mounted, avoiding the area where the conductor pad 112p is provided, so as not to obstruct the mounting of the component to the surface of the wiring substrate 1. By providing the reinforcing material ST, deformation such as bending and warping of the wiring substrate 1 can be suppressed. By suppressing the deformation of the wiring substrate 1, the mounting of the external element IP to the wiring substrate 1 can be achieved with high reliability.
[0026] The glass plate 100G constituting the core 100 is formed of glass selected from soda lime glass, aluminosilicate glass, and borosilicate glass. The glass plate 100G may also contain magnesium, calcium, manganese, aluminum, lead, iron, chromium, potassium, sulfur, antimony, boron, etc., as additives. In the wiring substrate of this embodiment, the thermal expansion coefficient of the glass plate 100G is relatively low, ranging from 3 ppm / °C to 5 ppm / °C.
[0027] The insulating layer 111 constituting the first laminate 11 and the insulating layer 121 constituting the second laminate 12 are formed using insulating resins such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin. Each insulating layer 111, 121 may contain reinforcing materials (core materials) such as glass fiber and / or inorganic fillers such as silica or alumina. The coefficient of thermal expansion of the insulating layers 111, 121 is, for example, 15 ppm / ℃ or higher and 25 ppm / ℃ or lower.
[0028] The solder mask layers SR1 and SR2 are formed, for example, using photosensitive epoxy resin or polyimide resin. As for the reinforcing material ST, any material that can suppress the deformation of the wiring substrate 1 can be used. Metal materials such as copper alloy, aluminum alloy, and iron alloy can be used, but it is preferable to use a material with high rigidity, such as stainless steel.
[0029] Conductor layers 112, 122, via conductors 113, 123, and through-hole conductors 100t can be formed using any metal such as copper or nickel. For example, conductor layers 112, 122 can be formed from metal foils such as copper foil and / or metal films formed by plating or sputtering. Conductor layers 112, 122, via conductors 113, 123, and through-hole conductors 100t in... Figure 1 For ease of observation, it is simplified to a single-layer structure, but it can have a multi-layer structure with two or more layers. Conductor layers 112, 122, via conductors 113, 123, and through-hole conductors 100t can have a two-layer structure comprising a metal film layer (e.g., electroless copper plating) and a plating film layer (e.g., electroplated copper plating). Each conductor layer 112, 122 of the wiring substrate 1 is patterned to have a prescribed conductor pattern.
[0030] The through-hole conductor 100t constituting the core 100 connects the conductor layer 112 constituting the first stacked portion 11 to the conductor layer 122 constituting the second stacked portion 12. In the illustrated example, the through-hole conductor 100t is connected to the conductor layer 112 via the via conductor 113 by direct connection to the via conductor 113, and is also connected to the conductor layer 122 via the via conductor 123 by direct connection to the via conductor 123.
[0031] The through-hole conductor 100t is a conductor that integrally fills the through-hole 100h formed in the glass plate 100G. In the figure, the through-hole 100h is formed to have approximately the same size in the thickness direction of the glass plate 100G. However, the through-hole 100h (and therefore the through-hole conductor 100t) may also have a shape that tapers in diameter from the first surface 100A side and the second surface 100B side toward the central portion of the thickness of the glass plate 100G.
[0032] For convenience, the term "reduced diameter" is used here, but the opening shape of the through-hole 100h when viewed from above is not necessarily limited to a circle. "Diameter" refers to the straight-line distance between the two farthest points on the outer edge of an object when viewed from above. "Reduced diameter" simply means that the straight-line distance between the two farthest points on the outer edge of the horizontal cross-section of the through-hole 100h is reduced. Furthermore, "viewed from above" refers to observing the object with a line of sight parallel to the thickness direction of the wiring substrate 1 (i.e., the thickness direction of the glass plate 100G).
[0033] As described above, in the wiring substrate of the embodiment, the thermal expansion coefficient of the glass plate 100G is relatively low, ranging from 3 ppm / °C to 5 ppm / °C. When the core 100 includes such a glass plate 100G with a relatively low thermal expansion coefficient, the degree of warping that may occur in the wiring substrate 1 can be reduced, and the thickness of the core 100 (i.e., the thickness of the glass plate 100G) can be relatively thin, ranging from 0.4 mm to 1.2 mm. This achieves reduction in wiring substrate warping and thinning. In such a glass plate 100G with a relatively low thermal expansion coefficient and small thickness, if the distance (arrangement spacing) between adjacent via conductors 100t (through holes 100h) is small, cracks are prone to occur. To address this problem, in the wiring substrate of the embodiment, by setting the arrangement spacing between via conductors (through holes) to a predetermined value or higher, the generation of cracks in the glass plate is suppressed.
[0034] Next, refer to Figure 2 The configuration of the through-hole conductor 100t (through-hole 100h) used to suppress the generation of cracks in the glass plate 100G is described in detail. Figure 2 It shows Figure 1 This is a top view of the first surface 100A, with the structural elements on the upper side of the core 100 of the wiring substrate 1 removed. Therefore, in Figure 2 In this structure, the surface of the glass plate 100G constituting the first surface 100A of the core 100 and the surface of the through-hole conductor 100t are exposed. Furthermore, Figure 1 It is along Figure 2 The diagram shows a cross-sectional view of the wiring substrate 1 when the II line is cut off. Furthermore, the wiring substrate 1 is formed into a rectangular shape with each side having a length of 50 mm or more when viewed from above; therefore, the glass plate 100G also has a rectangular shape with each side having a length of 50 mm or more.
[0035] In the wiring substrate of the embodiment, the shortest distance PT between the centers CT of two adjacent through-hole conductors 100t among the plurality of through-hole conductors 100t included in the core 100 is 200 μm or more and 400 μm or less. By setting the arrangement spacing between the through-hole conductors 100t to the above value, localized stress concentration caused by the difference between the thermal expansion coefficient of the glass material constituting the glass plate 100G and the thermal expansion coefficient of the conductor constituting the through-hole conductor 100t can be avoided. The generation of cracks in the glass plate 100G can be suppressed. Furthermore, here, the "center" of the through-hole conductor 100t refers to the midpoint of the straight line connecting the two furthest points of the outer edge of the through-hole conductor 100t when viewed from above. In addition, the center CT and arrangement spacing PT of the through-hole conductor 100t can also be interchanged with the center CT and arrangement spacing of the through hole 100h.
[0036] It should be noted that the diameter DA of the two surfaces (first surface 100A and second surface 100B) of the through-hole conductor 100t perpendicular to the thickness direction of the glass plate 100G refers to the maximum diameter of the through-hole 100h or the through-hole conductor 100t, for example, 50 μm or more and 150 μm or less. From the viewpoint of suppressing the generation of cracks in the glass plate 100G by suppressing the stress and strain caused by the thermal expansion of the through-hole conductor 100t, the diameter DA of the through-hole conductor 100t is preferably 100 μm or less.
[0037] Furthermore, the shortest distance (i.e., the space between the outer edges of adjacent through-hole conductors 100t on the two surfaces (first surface 100A and second surface 100B) perpendicular to the thickness direction of the glass plate 100G, for example, is 50 μm or more and 150 μm or less. From the viewpoint of effectively dispersing the stress caused by the thermal expansion of the through-hole conductors 100t in the glass plate 100G and suppressing the generation of cracks in the glass plate 100G, the space SP between adjacent through-hole conductors 100t is preferably 100 μm or more.
[0038] Next, to manufacture Figure 1 Taking the case of wiring board 1 as an example, refer to Figures 3A to 3H This illustrates an example of a method for manufacturing a wiring substrate. Furthermore, in... Figures 3A to 3H In, with Figure 1 Similarly, the construction of each conductor layer is shown to be simplified to a single-layer structure.
[0039] First, such as Figure 3AAs shown, a glass plate 100G is prepared. The thermal expansion coefficient of the prepared glass plate 100G is 3 ppm / ℃ or higher and 5 ppm / ℃ or lower. As a glass plate 100G with a thermal expansion coefficient within this range, a plate made of glass selected from soda lime glass, aluminosilicate glass, and borosilicate glass can be prepared, for example. Furthermore, the thickness of the glass plate 100G is 0.4 mm or higher and 1.2 mm or lower. The glass plate 100G has a rectangular shape with each side having a length of 50 mm or more when viewed from above.
[0040] At the location where a through hole 100h should be formed in glass plate 100G (refer to...) Figure 3B The modified portion hp is formed by laser irradiation. Helium-neon lasers, argon-ion lasers, excimer lasers, and various YAG lasers are used as the laser. The modified portion hp is the part of the glass structure that has undergone structural alteration and is easily removed by subsequent etching processes. The shortest distance (pitch) between the centers of two adjacent modified portions hp formed is 200 μm to 400 μm, suppressing the stress and strain that may occur in the glass plate 100G due to the heat effect that may be generated by laser irradiation. This process can suppress the generation of cracks in the glass plate 100G during the formation process of the modified portion hp based on laser irradiation.
[0041] Next, the modified portion hp is removed, for example, by using an etching solution containing an aqueous solution of hydrogen fluoride. Specifically, the modified portion hp is removed by immersing the glass plate 100G to which the modified portion hp is formed in an etching solution, for example, containing an aqueous solution of hydrogen fluoride. The concentration of the aqueous solution of hydrogen fluoride is appropriately adjusted to ensure sufficient etching. Furthermore, from the viewpoint of promoting etching, hydrochloric acid and / or nitric acid can be included in the etching solution, and ultrasonic waves can be propagated in the etching tank during the etching of the glass plate 100G. Figure 3B As shown, through holes 100h are formed in the portion where the modified portion hp has been removed. The diameter of the formed through holes 100h is, for example, 50 μm or more and 150 μm or less. In addition, the shortest distance between two adjacent through holes 100h among the formed plurality of through holes 100h is, for example, 50 μm or more and 150 μm or less.
[0042] Next, as Figure 3CAs shown, the through-hole 100h is filled with a conductive material CM. The conductive material CM is formed to completely fill the interior of the through-hole 100h and completely cover the two surfaces of the glass plate 100G perpendicular to the thickness direction. In the formation of the conductive material CM, firstly, a metal film layer (not shown) is formed on the inner wall surface of the through-hole 100h and on the two surfaces of the glass plate 100G, for example, by chemical plating. Next, by electroplating the metal film layer as a power supply layer, a plating film layer is formed on the metal film layer, forming a through-hole conductor 100t with a double-layer structure of metal film layer and plating film layer (single layer in the figure) within the through-hole 100h. The two surfaces of the glass plate 100G are covered by the conductive material CM with a double-layer structure of metal film layer and plating film layer (single layer in the figure).
[0043] Next, the conductive layer CM covering the two surfaces of the glass plate 100G, perpendicular to the thickness direction, is removed by grinding. For example... Figure 3D As shown, the surfaces of the glass plate 100G and the through-hole conductor 100t are exposed. A core 100 is formed having a first surface 100A and a second surface 100B, which are formed by the surfaces of the glass plate 100G and the through-hole conductor 100t. The removal of the conductor CM layer by polishing can be carried out, for example, by chemical mechanical polishing (CMP).
[0044] Next, as Figure 3E As shown, an insulating layer 111 is stacked on the first surface 100A of the core 100, and then a conductor layer 112 is formed on the insulating layer 111. A via conductor 113 is formed simultaneously with the conductor layer 112. Furthermore, an insulating layer 121 is stacked on the second surface 100B of the core 100, and then a conductor layer 122 is formed on the insulating layer 121. A via conductor 123 is formed simultaneously with the conductor layer 122.
[0045] Insulating layers 111 and 121 are formed, for example, by hot-pressing a film-like insulating resin (e.g., epoxy resin) onto the surfaces (first surface 100A and second surface 100B) of the core 100. The thermal expansion coefficient of the insulating layer is 15 ppm / ℃ or more and 25 ppm / ℃ or less. Through-holes vh are formed in the insulating resin at locations where via conductors 113 and 123 should be formed, for example, by irradiation with a carbon dioxide laser. Conductor layers 112 and 122 and via conductors 113 and 123 are formed by forming a metal film layer (not shown) based on chemical plating or sputtering on the inner surface of the through-holes vh and the upper surface of the insulating layers 111 and 121, and by electroplating a metal film layer using an anti-plating agent with appropriate openings as a power supply layer. That is, conductor layers 112 and 122 and via conductors 113 and 123 are formed using a semi-additive process (SAP).
[0046] Next, as Figure 3F As shown, on the upper side of the first surface 100A of the core 100, the same process as forming the insulating layer 111, conductor layer 112, and via conductor 113 described above is repeated three or more times to form a first laminate 11 containing four or more insulating layers 111 and four or more conductor layers 112. Similarly, on the upper side of the second surface 100B of the core 100, the same process as forming the insulating layer 121, conductor layer 122, and via conductor 123 described above is repeated three or more times to form a second laminate 12 containing four or more insulating layers 121 and four or more conductor layers 122. The outermost conductor layer 112 of the first laminate 11 is formed with a pattern including conductor pads 112p. The outermost conductor layer 122 of the second laminate 12 is formed with a pattern including conductor pads 122p.
[0047] Next, as Figure 3G As shown, a solder resist layer SR1 is formed on the first stacked layer 11, and a solder resist layer SR2 is formed on the second stacked layer 12. The solder resist layers SR1 and SR2 are formed, for example, by forming a resin layer containing a photosensitive epoxy resin or polyimide resin, and by exposure and development using a mask with a suitable opening pattern. The solder resist layers SR1 and SR2 are formed with openings SR1o and SR2o that expose the conductor pads 112p and 122p. On the exposed surfaces of the conductor pads 112p and 122p, a surface protective film (not shown) composed of Au, Ni / Au, Ni / Pd / Au, solder, or a heat-resistant pre-soldering flux can also be formed by chemical plating, solder leveling, or spraying.
[0048] Next, as Figure 3HAs shown, a reinforcing material ST is mounted on the solder mask layer SR1. The reinforcing material ST can be, for example, sheet-like stainless steel, but other metal materials can also be used. The reinforcing material ST is a material whose planar shape is formed along the contour of the area of the mounting component on the wiring substrate 1 by stamping or laser processing of a sheet-like metal material. The sheet-like reinforcing material ST is bonded to the solder mask layer SR1, for example, via a thermosetting adhesive (not shown). After the above processes, the wiring substrate 1 is completed.
[0049] The wiring substrate of the embodiments is not limited to having the structure illustrated in the accompanying drawings and the structure, shape, and material illustrated in this specification. In the wiring substrate 1 described, the first stacking portion 11 and the second stacking portion 12 each include 5 conductor layers and 5 insulating layers, but the number of insulating and conductor layers in the first stacking portion 11 and the second stacking portion 12 is not limited thereto. The first stacking portion 11 and the second stacking portion 12 of the wiring substrate of the embodiments may each include 4 or more conductor layers and 4 or more insulating layers, or they may include 6 or more conductor layers and 6 or more insulating layers. For example, the first stacking portion 11 and the second stacking portion 12 may also have different numbers of insulating and conductor layers.
Claims
1. A wiring substrate comprising: The core comprises a glass plate having a first side and a second side being the opposite side of the first side; and The laminated portions, formed on both sides of the glass plate, are composed of stacked conductor layers and insulating layers. in, The laminated portion consists of four or more conductor layers and four or more insulating layers. The core includes a plurality of through-hole conductors that connect the conductor layer formed in the stacked portion on the first side to the conductor layer formed in the stacked portion on the second side. The glass plate has a thickness of 0.4 mm or more and 1.2 mm or less, and a coefficient of thermal expansion of 3 ppm / ℃ or more and 5 ppm / ℃ or less. The minimum spacing between the plurality of through-hole conductors is 200 μm or more and 400 μm or less.
2. The wiring substrate according to claim 1, wherein, The shortest distance between adjacent through-hole conductors in the plurality of through-hole conductors is 100 μm or more.
3. The wiring substrate according to claim 1, wherein, The diameter of the through-hole conductor is less than 100 μm.
4. The wiring substrate according to claim 1, wherein, The glass plate has a rectangular planar shape. The length of each side of the rectangle is 50mm or more.
5. The wiring substrate according to claim 1, wherein, The thermal expansion coefficient of the insulating layer constituting the laminate portion is 15 ppm / ℃ or more and 25 ppm / ℃ or less.
6. The wiring substrate according to claim 1, wherein, The through-hole conductor is composed of a conductor that completely fills the through-hole penetrating the glass plate.
7. The wiring substrate according to claim 1, wherein, The thickness of the glass plate is 0.6 mm or more and 0.9 mm or less.